./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 11:53:57,892 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 11:53:57,968 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 11:53:57,974 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 11:53:57,975 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 11:53:58,002 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 11:53:58,003 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 11:53:58,004 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 11:53:58,005 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 11:53:58,006 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 11:53:58,007 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 11:53:58,007 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 11:53:58,008 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 11:53:58,009 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 11:53:58,009 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 11:53:58,010 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 11:53:58,010 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 11:53:58,011 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 11:53:58,011 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 11:53:58,012 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 11:53:58,012 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 11:53:58,013 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 11:53:58,014 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 11:53:58,014 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 11:53:58,015 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 11:53:58,015 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 11:53:58,016 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 11:53:58,016 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 11:53:58,017 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 11:53:58,017 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 11:53:58,018 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 11:53:58,018 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 11:53:58,019 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 11:53:58,019 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 11:53:58,020 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 11:53:58,020 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 11:53:58,021 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 11:53:58,022 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 11:53:58,022 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e [2023-11-26 11:53:58,321 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 11:53:58,355 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 11:53:58,359 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 11:53:58,360 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 11:53:58,361 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 11:53:58,362 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2023-11-26 11:54:01,664 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 11:54:02,001 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 11:54:02,001 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2023-11-26 11:54:02,033 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme/data/09fda838b/1eb95a4c81544b6b803114443f0ecd4e/FLAG6dd1b335b [2023-11-26 11:54:02,052 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme/data/09fda838b/1eb95a4c81544b6b803114443f0ecd4e [2023-11-26 11:54:02,060 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 11:54:02,062 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 11:54:02,068 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 11:54:02,068 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 11:54:02,074 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 11:54:02,075 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:54:02" (1/1) ... [2023-11-26 11:54:02,077 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2d9876f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02, skipping insertion in model container [2023-11-26 11:54:02,077 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 11:54:02" (1/1) ... [2023-11-26 11:54:02,152 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 11:54:02,484 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:54:02,514 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 11:54:02,591 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 11:54:02,620 INFO L206 MainTranslator]: Completed translation [2023-11-26 11:54:02,622 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02 WrapperNode [2023-11-26 11:54:02,622 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 11:54:02,624 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 11:54:02,624 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 11:54:02,624 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 11:54:02,633 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02" (1/1) ... [2023-11-26 11:54:02,649 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02" (1/1) ... [2023-11-26 11:54:02,800 INFO L138 Inliner]: procedures = 46, calls = 59, calls flagged for inlining = 54, calls inlined = 183, statements flattened = 2778 [2023-11-26 11:54:02,801 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 11:54:02,802 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 11:54:02,802 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 11:54:02,802 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 11:54:02,814 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02" (1/1) ... [2023-11-26 11:54:02,814 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02" (1/1) ... [2023-11-26 11:54:02,834 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02" (1/1) ... [2023-11-26 11:54:02,873 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 11:54:02,873 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02" (1/1) ... [2023-11-26 11:54:02,874 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02" (1/1) ... [2023-11-26 11:54:02,934 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02" (1/1) ... [2023-11-26 11:54:02,970 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02" (1/1) ... [2023-11-26 11:54:02,975 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02" (1/1) ... [2023-11-26 11:54:02,986 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02" (1/1) ... [2023-11-26 11:54:03,000 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 11:54:03,001 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 11:54:03,001 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 11:54:03,001 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 11:54:03,002 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02" (1/1) ... [2023-11-26 11:54:03,009 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 11:54:03,025 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 11:54:03,040 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 11:54:03,060 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_8a868638-05bb-45e0-8d2e-a68a5acfa087/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 11:54:03,082 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 11:54:03,082 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 11:54:03,083 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 11:54:03,083 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 11:54:03,208 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 11:54:03,211 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 11:54:05,234 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 11:54:05,272 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 11:54:05,273 INFO L309 CfgBuilder]: Removed 12 assume(true) statements. [2023-11-26 11:54:05,275 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:54:05 BoogieIcfgContainer [2023-11-26 11:54:05,275 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 11:54:05,277 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 11:54:05,277 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 11:54:05,281 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 11:54:05,282 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:54:05,282 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 11:54:02" (1/3) ... [2023-11-26 11:54:05,283 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@48491e51 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:54:05, skipping insertion in model container [2023-11-26 11:54:05,284 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:54:05,284 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 11:54:02" (2/3) ... [2023-11-26 11:54:05,284 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@48491e51 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 11:54:05, skipping insertion in model container [2023-11-26 11:54:05,285 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 11:54:05,285 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 11:54:05" (3/3) ... [2023-11-26 11:54:05,286 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-1.c [2023-11-26 11:54:05,384 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 11:54:05,384 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 11:54:05,385 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 11:54:05,385 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 11:54:05,385 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 11:54:05,385 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 11:54:05,385 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 11:54:05,386 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 11:54:05,397 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1187 states, 1186 states have (on average 1.5050590219224282) internal successors, (1785), 1186 states have internal predecessors, (1785), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:05,479 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1056 [2023-11-26 11:54:05,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:05,479 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:05,498 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:05,498 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:05,498 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 11:54:05,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1187 states, 1186 states have (on average 1.5050590219224282) internal successors, (1785), 1186 states have internal predecessors, (1785), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:05,519 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1056 [2023-11-26 11:54:05,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:05,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:05,525 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:05,525 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:05,536 INFO L748 eck$LassoCheckResult]: Stem: 169#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1075#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 887#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1071#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 763#L658true assume !(1 == ~m_i~0);~m_st~0 := 2; 407#L658-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 786#L663-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 726#L668-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 268#L673-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 827#L678-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 633#L683-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1045#L688-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8#L693-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 103#L698-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 336#L703-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1036#L939true assume !(0 == ~M_E~0); 538#L939-2true assume !(0 == ~T1_E~0); 758#L944-1true assume !(0 == ~T2_E~0); 361#L949-1true assume !(0 == ~T3_E~0); 359#L954-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1082#L959-1true assume !(0 == ~T5_E~0); 787#L964-1true assume !(0 == ~T6_E~0); 183#L969-1true assume !(0 == ~T7_E~0); 898#L974-1true assume !(0 == ~T8_E~0); 713#L979-1true assume !(0 == ~T9_E~0); 1108#L984-1true assume !(0 == ~E_M~0); 275#L989-1true assume !(0 == ~E_1~0); 518#L994-1true assume 0 == ~E_2~0;~E_2~0 := 1; 210#L999-1true assume !(0 == ~E_3~0); 676#L1004-1true assume !(0 == ~E_4~0); 37#L1009-1true assume !(0 == ~E_5~0); 206#L1014-1true assume !(0 == ~E_6~0); 639#L1019-1true assume !(0 == ~E_7~0); 952#L1024-1true assume !(0 == ~E_8~0); 166#L1029-1true assume !(0 == ~E_9~0); 213#L1034-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 966#L460true assume 1 == ~m_pc~0; 2#L461true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 603#L471true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 743#is_master_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1040#L1167true assume !(0 != activate_threads_~tmp~1#1); 350#L1167-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 502#L479true assume 1 == ~t1_pc~0; 337#L480true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1054#L490true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 173#L1175true assume !(0 != activate_threads_~tmp___0~0#1); 393#L1175-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93#L498true assume !(1 == ~t2_pc~0); 648#L498-2true is_transmit2_triggered_~__retres1~2#1 := 0; 335#L509true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 677#L1183true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 595#L1183-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1131#L517true assume 1 == ~t3_pc~0; 911#L518true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1077#L528true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 192#L1191true assume !(0 != activate_threads_~tmp___2~0#1); 650#L1191-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 828#L536true assume !(1 == ~t4_pc~0); 1110#L536-2true is_transmit4_triggered_~__retres1~4#1 := 0; 776#L547true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 376#L1199true assume !(0 != activate_threads_~tmp___3~0#1); 1100#L1199-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 569#L555true assume 1 == ~t5_pc~0; 1176#L556true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 709#L566true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 746#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 167#L1207true assume !(0 != activate_threads_~tmp___4~0#1); 107#L1207-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56#L574true assume !(1 == ~t6_pc~0); 641#L574-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1113#L585true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 264#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 672#L1215true assume !(0 != activate_threads_~tmp___5~0#1); 1105#L1215-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 986#L593true assume 1 == ~t7_pc~0; 1152#L594true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 791#L604true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1094#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1093#L1223true assume !(0 != activate_threads_~tmp___6~0#1); 915#L1223-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 273#L612true assume !(1 == ~t8_pc~0); 1034#L612-2true is_transmit8_triggered_~__retres1~8#1 := 0; 901#L623true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 678#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 822#L1231true assume !(0 != activate_threads_~tmp___7~0#1); 450#L1231-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 506#L631true assume 1 == ~t9_pc~0; 461#L632true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52#L642true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 301#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 338#L1239true assume !(0 != activate_threads_~tmp___8~0#1); 1063#L1239-2true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 653#L1047true assume !(1 == ~M_E~0); 23#L1047-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 444#L1052-1true assume !(1 == ~T2_E~0); 15#L1057-1true assume !(1 == ~T3_E~0); 158#L1062-1true assume !(1 == ~T4_E~0); 788#L1067-1true assume !(1 == ~T5_E~0); 352#L1072-1true assume !(1 == ~T6_E~0); 621#L1077-1true assume !(1 == ~T7_E~0); 100#L1082-1true assume !(1 == ~T8_E~0); 426#L1087-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 5#L1092-1true assume !(1 == ~E_M~0); 16#L1097-1true assume !(1 == ~E_1~0); 957#L1102-1true assume !(1 == ~E_2~0); 503#L1107-1true assume !(1 == ~E_3~0); 446#L1112-1true assume !(1 == ~E_4~0); 481#L1117-1true assume !(1 == ~E_5~0); 1165#L1122-1true assume !(1 == ~E_6~0); 389#L1127-1true assume 1 == ~E_7~0;~E_7~0 := 2; 216#L1132-1true assume !(1 == ~E_8~0); 960#L1137-1true assume !(1 == ~E_9~0); 156#L1142-1true assume { :end_inline_reset_delta_events } true; 81#L1428-2true [2023-11-26 11:54:05,540 INFO L750 eck$LassoCheckResult]: Loop: 81#L1428-2true assume !false; 443#L1429true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 490#L914-1true assume false; 686#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 413#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 773#L939-3true assume 0 == ~M_E~0;~M_E~0 := 1; 114#L939-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 141#L944-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 4#L949-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 730#L954-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 364#L959-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 40#L964-3true assume !(0 == ~T6_E~0); 261#L969-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 140#L974-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1068#L979-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 421#L984-3true assume 0 == ~E_M~0;~E_M~0 := 1; 1155#L989-3true assume 0 == ~E_1~0;~E_1~0 := 1; 171#L994-3true assume 0 == ~E_2~0;~E_2~0 := 1; 987#L999-3true assume 0 == ~E_3~0;~E_3~0 := 1; 545#L1004-3true assume !(0 == ~E_4~0); 76#L1009-3true assume 0 == ~E_5~0;~E_5~0 := 1; 627#L1014-3true assume 0 == ~E_6~0;~E_6~0 := 1; 408#L1019-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1124#L1024-3true assume 0 == ~E_8~0;~E_8~0 := 1; 396#L1029-3true assume 0 == ~E_9~0;~E_9~0 := 1; 366#L1034-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 936#L460-33true assume 1 == ~m_pc~0; 390#L461-11true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 558#L471-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 701#is_master_triggered_returnLabel#12true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7#L1167-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 507#L1167-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 186#L479-33true assume !(1 == ~t1_pc~0); 717#L479-35true is_transmit1_triggered_~__retres1~1#1 := 0; 168#L490-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1062#is_transmit1_triggered_returnLabel#12true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 877#L1175-33true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1007#L1175-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 191#L498-33true assume !(1 == ~t2_pc~0); 58#L498-35true is_transmit2_triggered_~__retres1~2#1 := 0; 322#L509-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 646#is_transmit2_triggered_returnLabel#12true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 435#L1183-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 115#L1183-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1016#L517-33true assume !(1 == ~t3_pc~0); 1122#L517-35true is_transmit3_triggered_~__retres1~3#1 := 0; 750#L528-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92#is_transmit3_triggered_returnLabel#12true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 532#L1191-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 673#L1191-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 241#L536-33true assume !(1 == ~t4_pc~0); 1027#L536-35true is_transmit4_triggered_~__retres1~4#1 := 0; 286#L547-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 949#is_transmit4_triggered_returnLabel#12true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 719#L1199-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 829#L1199-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27#L555-33true assume !(1 == ~t5_pc~0); 813#L555-35true is_transmit5_triggered_~__retres1~5#1 := 0; 476#L566-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1012#is_transmit5_triggered_returnLabel#12true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 499#L1207-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1049#L1207-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14#L574-33true assume 1 == ~t6_pc~0; 733#L575-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 857#L585-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 345#is_transmit6_triggered_returnLabel#12true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 582#L1215-33true assume !(0 != activate_threads_~tmp___5~0#1); 331#L1215-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49#L593-33true assume 1 == ~t7_pc~0; 405#L594-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 970#L604-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 771#is_transmit7_triggered_returnLabel#12true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 557#L1223-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 704#L1223-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1130#L612-33true assume 1 == ~t8_pc~0; 934#L613-11true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 863#L623-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 484#is_transmit8_triggered_returnLabel#12true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 620#L1231-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 98#L1231-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1174#L631-33true assume 1 == ~t9_pc~0; 784#L632-11true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 69#L642-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 655#is_transmit9_triggered_returnLabel#12true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 205#L1239-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 129#L1239-35true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 219#L1047-3true assume 1 == ~M_E~0;~M_E~0 := 2; 785#L1047-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1183#L1052-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 684#L1057-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1178#L1062-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 73#L1067-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1041#L1072-3true assume !(1 == ~T6_E~0); 296#L1077-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 196#L1082-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 238#L1087-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 440#L1092-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1188#L1097-3true assume 1 == ~E_1~0;~E_1~0 := 2; 388#L1102-3true assume 1 == ~E_2~0;~E_2~0 := 2; 965#L1107-3true assume 1 == ~E_3~0;~E_3~0 := 2; 738#L1112-3true assume !(1 == ~E_4~0); 193#L1117-3true assume 1 == ~E_5~0;~E_5~0 := 2; 748#L1122-3true assume 1 == ~E_6~0;~E_6~0 := 2; 220#L1127-3true assume 1 == ~E_7~0;~E_7~0 := 2; 517#L1132-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1096#L1137-3true assume 1 == ~E_9~0;~E_9~0 := 2; 493#L1142-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 131#L716-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 501#L768-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 239#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 311#L1447true assume !(0 == start_simulation_~tmp~3#1); 712#L1447-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1154#L716-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 742#L768-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 38#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 209#L1402true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78#L1409true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 429#stop_simulation_returnLabel#1true start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 354#L1460true assume !(0 != start_simulation_~tmp___0~1#1); 81#L1428-2true [2023-11-26 11:54:05,555 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:05,556 INFO L85 PathProgramCache]: Analyzing trace with hash -986421749, now seen corresponding path program 1 times [2023-11-26 11:54:05,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:05,566 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1605139503] [2023-11-26 11:54:05,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:05,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:05,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:05,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:05,947 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:05,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1605139503] [2023-11-26 11:54:05,949 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1605139503] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:05,949 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:05,949 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:05,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197094790] [2023-11-26 11:54:05,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:05,958 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:05,960 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:05,960 INFO L85 PathProgramCache]: Analyzing trace with hash 1305754084, now seen corresponding path program 1 times [2023-11-26 11:54:05,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:05,961 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991364928] [2023-11-26 11:54:05,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:05,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:05,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:06,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:06,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:06,054 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1991364928] [2023-11-26 11:54:06,054 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1991364928] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:06,054 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:06,054 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:54:06,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767381803] [2023-11-26 11:54:06,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:06,056 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:06,057 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:06,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:06,089 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:06,094 INFO L87 Difference]: Start difference. First operand has 1187 states, 1186 states have (on average 1.5050590219224282) internal successors, (1785), 1186 states have internal predecessors, (1785), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:06,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:06,215 INFO L93 Difference]: Finished difference Result 1185 states and 1757 transitions. [2023-11-26 11:54:06,216 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1185 states and 1757 transitions. [2023-11-26 11:54:06,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:06,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1185 states to 1180 states and 1752 transitions. [2023-11-26 11:54:06,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-26 11:54:06,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-26 11:54:06,270 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1752 transitions. [2023-11-26 11:54:06,283 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:06,283 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1752 transitions. [2023-11-26 11:54:06,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1752 transitions. [2023-11-26 11:54:06,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-26 11:54:06,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4847457627118643) internal successors, (1752), 1179 states have internal predecessors, (1752), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:06,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1752 transitions. [2023-11-26 11:54:06,396 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1752 transitions. [2023-11-26 11:54:06,397 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:06,403 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1752 transitions. [2023-11-26 11:54:06,404 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 11:54:06,404 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1752 transitions. [2023-11-26 11:54:06,417 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:06,417 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:06,417 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:06,426 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:06,427 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:06,428 INFO L748 eck$LassoCheckResult]: Stem: 2723#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2724#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3504#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3505#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3439#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 3103#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3104#L663-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3415#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2891#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2892#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3342#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3343#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2395#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2396#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2599#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2993#L939 assume !(0 == ~M_E~0); 3248#L939-2 assume !(0 == ~T1_E~0); 3249#L944-1 assume !(0 == ~T2_E~0); 3031#L949-1 assume !(0 == ~T3_E~0); 3029#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3030#L959-1 assume !(0 == ~T5_E~0); 3451#L964-1 assume !(0 == ~T6_E~0); 2744#L969-1 assume !(0 == ~T7_E~0); 2745#L974-1 assume !(0 == ~T8_E~0); 3400#L979-1 assume !(0 == ~T9_E~0); 3401#L984-1 assume !(0 == ~E_M~0); 2905#L989-1 assume !(0 == ~E_1~0); 2906#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2795#L999-1 assume !(0 == ~E_3~0); 2796#L1004-1 assume !(0 == ~E_4~0); 2463#L1009-1 assume !(0 == ~E_5~0); 2464#L1014-1 assume !(0 == ~E_6~0); 2792#L1019-1 assume !(0 == ~E_7~0); 3347#L1024-1 assume !(0 == ~E_8~0); 2716#L1029-1 assume !(0 == ~E_9~0); 2717#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2801#L460 assume 1 == ~m_pc~0; 2381#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2382#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3312#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3425#L1167 assume !(0 != activate_threads_~tmp~1#1); 3014#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3015#L479 assume 1 == ~t1_pc~0; 2994#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2995#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2465#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2466#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 2729#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2578#L498 assume !(1 == ~t2_pc~0); 2579#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2992#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2895#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2896#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3302#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3303#L517 assume 1 == ~t3_pc~0; 3512#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3513#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2402#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2403#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 2765#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3354#L536 assume !(1 == ~t4_pc~0); 3059#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3058#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2561#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2562#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 3052#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3282#L555 assume 1 == ~t5_pc~0; 3283#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3348#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3398#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2718#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 2602#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2501#L574 assume !(1 == ~t6_pc~0); 2502#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3158#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2885#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2886#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 3371#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3537#L593 assume 1 == ~t7_pc~0; 3538#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2737#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3454#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3554#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 3516#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2900#L612 assume !(1 == ~t8_pc~0); 2901#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3330#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3374#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3375#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 3160#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3161#L631 assume 1 == ~t9_pc~0; 3174#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2493#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2494#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2945#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 2997#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3355#L1047 assume !(1 == ~M_E~0); 2429#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2430#L1052-1 assume !(1 == ~T2_E~0); 2412#L1057-1 assume !(1 == ~T3_E~0); 2413#L1062-1 assume !(1 == ~T4_E~0); 2702#L1067-1 assume !(1 == ~T5_E~0); 3018#L1072-1 assume !(1 == ~T6_E~0); 3019#L1077-1 assume !(1 == ~T7_E~0); 2593#L1082-1 assume !(1 == ~T8_E~0); 2594#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2391#L1092-1 assume !(1 == ~E_M~0); 2392#L1097-1 assume !(1 == ~E_1~0); 2414#L1102-1 assume !(1 == ~E_2~0); 3218#L1107-1 assume !(1 == ~E_3~0); 3156#L1112-1 assume !(1 == ~E_4~0); 3157#L1117-1 assume !(1 == ~E_5~0); 3192#L1122-1 assume !(1 == ~E_6~0); 3074#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2807#L1132-1 assume !(1 == ~E_8~0); 2808#L1137-1 assume !(1 == ~E_9~0); 2699#L1142-1 assume { :end_inline_reset_delta_events } true; 2552#L1428-2 [2023-11-26 11:54:06,430 INFO L750 eck$LassoCheckResult]: Loop: 2552#L1428-2 assume !false; 2553#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2924#L914-1 assume !false; 3152#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3153#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2400#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2401#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2923#L783 assume !(0 != eval_~tmp~0#1); 3372#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3111#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3112#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2617#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2618#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2387#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2388#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3036#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2467#L964-3 assume !(0 == ~T6_E~0); 2468#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2670#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2671#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3123#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3124#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2725#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2726#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3257#L1004-3 assume !(0 == ~E_4~0); 2544#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2545#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3105#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3106#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3084#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3037#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3038#L460-33 assume 1 == ~m_pc~0; 3075#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3076#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3272#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2393#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2394#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2753#L479-33 assume !(1 == ~t1_pc~0); 2754#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2719#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2720#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3492#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3493#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2763#L498-33 assume !(1 == ~t2_pc~0); 2507#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 2508#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2975#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3146#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2619#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2620#L517-33 assume !(1 == ~t3_pc~0); 3546#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3431#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2576#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2577#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3242#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2843#L536-33 assume 1 == ~t4_pc~0; 2844#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2921#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2922#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3406#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3407#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2438#L555-33 assume 1 == ~t5_pc~0; 2439#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3184#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3185#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3214#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3215#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2404#L574-33 assume !(1 == ~t6_pc~0); 2405#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3419#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3006#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3007#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 2985#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2482#L593-33 assume 1 == ~t7_pc~0; 2483#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2949#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3442#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3270#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3271#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3393#L612-33 assume 1 == ~t8_pc~0; 3524#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3485#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3195#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3196#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2587#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2588#L631-33 assume !(1 == ~t9_pc~0); 3221#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2528#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2529#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2787#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2645#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2646#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2811#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3450#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3379#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3380#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2538#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2539#L1072-3 assume !(1 == ~T6_E~0); 2935#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2771#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2772#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2837#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3151#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3070#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3071#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3420#L1112-3 assume !(1 == ~E_4~0); 2766#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2767#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2812#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2813#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3231#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3209#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2647#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2524#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2838#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2839#L1447 assume !(0 == start_simulation_~tmp~3#1); 2955#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3399#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2678#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2461#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 2462#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2546#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2547#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3022#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 2552#L1428-2 [2023-11-26 11:54:06,431 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:06,432 INFO L85 PathProgramCache]: Analyzing trace with hash 1581400585, now seen corresponding path program 1 times [2023-11-26 11:54:06,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:06,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638101422] [2023-11-26 11:54:06,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:06,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:06,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:06,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:06,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:06,618 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1638101422] [2023-11-26 11:54:06,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1638101422] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:06,619 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:06,619 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:06,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1550704425] [2023-11-26 11:54:06,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:06,620 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:06,621 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:06,621 INFO L85 PathProgramCache]: Analyzing trace with hash 1780472913, now seen corresponding path program 1 times [2023-11-26 11:54:06,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:06,621 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852239477] [2023-11-26 11:54:06,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:06,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:06,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:06,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:06,809 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:06,809 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1852239477] [2023-11-26 11:54:06,809 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1852239477] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:06,810 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:06,810 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:06,810 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [236609078] [2023-11-26 11:54:06,810 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:06,811 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:06,811 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:06,811 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:06,812 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:06,812 INFO L87 Difference]: Start difference. First operand 1180 states and 1752 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:06,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:06,849 INFO L93 Difference]: Finished difference Result 1180 states and 1751 transitions. [2023-11-26 11:54:06,849 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1751 transitions. [2023-11-26 11:54:06,860 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:06,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1751 transitions. [2023-11-26 11:54:06,871 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-26 11:54:06,873 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-26 11:54:06,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1751 transitions. [2023-11-26 11:54:06,875 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:06,876 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1751 transitions. [2023-11-26 11:54:06,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1751 transitions. [2023-11-26 11:54:06,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-26 11:54:06,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4838983050847459) internal successors, (1751), 1179 states have internal predecessors, (1751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:06,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1751 transitions. [2023-11-26 11:54:06,910 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1751 transitions. [2023-11-26 11:54:06,911 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:06,913 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1751 transitions. [2023-11-26 11:54:06,913 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 11:54:06,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1751 transitions. [2023-11-26 11:54:06,926 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:06,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:06,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:06,935 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:06,935 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:06,938 INFO L748 eck$LassoCheckResult]: Stem: 5090#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5091#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5871#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5872#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5806#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 5470#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5471#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5782#L668-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5258#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5259#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5709#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5710#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4762#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4763#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4966#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5360#L939 assume !(0 == ~M_E~0); 5615#L939-2 assume !(0 == ~T1_E~0); 5616#L944-1 assume !(0 == ~T2_E~0); 5398#L949-1 assume !(0 == ~T3_E~0); 5396#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5397#L959-1 assume !(0 == ~T5_E~0); 5818#L964-1 assume !(0 == ~T6_E~0); 5111#L969-1 assume !(0 == ~T7_E~0); 5112#L974-1 assume !(0 == ~T8_E~0); 5769#L979-1 assume !(0 == ~T9_E~0); 5770#L984-1 assume !(0 == ~E_M~0); 5272#L989-1 assume !(0 == ~E_1~0); 5273#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5162#L999-1 assume !(0 == ~E_3~0); 5163#L1004-1 assume !(0 == ~E_4~0); 4830#L1009-1 assume !(0 == ~E_5~0); 4831#L1014-1 assume !(0 == ~E_6~0); 5159#L1019-1 assume !(0 == ~E_7~0); 5714#L1024-1 assume !(0 == ~E_8~0); 5083#L1029-1 assume !(0 == ~E_9~0); 5084#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5168#L460 assume 1 == ~m_pc~0; 4751#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4752#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5679#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5792#L1167 assume !(0 != activate_threads_~tmp~1#1); 5381#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5382#L479 assume 1 == ~t1_pc~0; 5361#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5362#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4834#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4835#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 5096#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4945#L498 assume !(1 == ~t2_pc~0); 4946#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5359#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5262#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5263#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5669#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5670#L517 assume 1 == ~t3_pc~0; 5879#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5880#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4769#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4770#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 5132#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5721#L536 assume !(1 == ~t4_pc~0); 5426#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5425#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4931#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4932#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 5419#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5649#L555 assume 1 == ~t5_pc~0; 5650#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5715#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5765#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5085#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 4969#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4868#L574 assume !(1 == ~t6_pc~0); 4869#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5525#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5252#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5253#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 5738#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5904#L593 assume 1 == ~t7_pc~0; 5905#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5104#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5821#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5921#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 5883#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5267#L612 assume !(1 == ~t8_pc~0); 5268#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5697#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5741#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5742#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 5527#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5528#L631 assume 1 == ~t9_pc~0; 5541#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4860#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4861#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5312#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 5364#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5722#L1047 assume !(1 == ~M_E~0); 4796#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4797#L1052-1 assume !(1 == ~T2_E~0); 4779#L1057-1 assume !(1 == ~T3_E~0); 4780#L1062-1 assume !(1 == ~T4_E~0); 5069#L1067-1 assume !(1 == ~T5_E~0); 5385#L1072-1 assume !(1 == ~T6_E~0); 5386#L1077-1 assume !(1 == ~T7_E~0); 4960#L1082-1 assume !(1 == ~T8_E~0); 4961#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4758#L1092-1 assume !(1 == ~E_M~0); 4759#L1097-1 assume !(1 == ~E_1~0); 4781#L1102-1 assume !(1 == ~E_2~0); 5585#L1107-1 assume !(1 == ~E_3~0); 5523#L1112-1 assume !(1 == ~E_4~0); 5524#L1117-1 assume !(1 == ~E_5~0); 5560#L1122-1 assume !(1 == ~E_6~0); 5441#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5174#L1132-1 assume !(1 == ~E_8~0); 5175#L1137-1 assume !(1 == ~E_9~0); 5066#L1142-1 assume { :end_inline_reset_delta_events } true; 4922#L1428-2 [2023-11-26 11:54:06,938 INFO L750 eck$LassoCheckResult]: Loop: 4922#L1428-2 assume !false; 4923#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5291#L914-1 assume !false; 5519#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5520#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4767#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4768#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5290#L783 assume !(0 != eval_~tmp~0#1); 5739#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5479#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5480#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4986#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4987#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4754#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4755#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5403#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4836#L964-3 assume !(0 == ~T6_E~0); 4837#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5037#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5038#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5490#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5491#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5092#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5093#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5624#L1004-3 assume !(0 == ~E_4~0); 4911#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4912#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5472#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5473#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5451#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5407#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5408#L460-33 assume 1 == ~m_pc~0; 5443#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5444#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5639#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4760#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4761#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5120#L479-33 assume !(1 == ~t1_pc~0); 5121#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 5086#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5087#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5859#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5860#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5125#L498-33 assume 1 == ~t2_pc~0; 5126#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4872#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5342#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5513#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4984#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4985#L517-33 assume !(1 == ~t3_pc~0); 5913#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 5798#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4943#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4944#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5609#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5207#L536-33 assume 1 == ~t4_pc~0; 5208#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5288#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5289#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5773#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5774#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4805#L555-33 assume 1 == ~t5_pc~0; 4806#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5551#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5552#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5581#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5582#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4774#L574-33 assume !(1 == ~t6_pc~0); 4775#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 5786#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5373#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5374#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 5352#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4852#L593-33 assume 1 == ~t7_pc~0; 4853#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5317#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5809#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5637#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5638#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5760#L612-33 assume 1 == ~t8_pc~0; 5891#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5852#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5562#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5563#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4954#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4955#L631-33 assume !(1 == ~t9_pc~0); 5588#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 4897#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4898#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5154#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5012#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5013#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5178#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5817#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5746#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5747#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4905#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4906#L1072-3 assume !(1 == ~T6_E~0); 5302#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5138#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5139#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5204#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5518#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5437#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5438#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5787#L1112-3 assume !(1 == ~E_4~0); 5133#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5134#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5179#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5180#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5598#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5576#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5017#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4891#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5205#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 5206#L1447 assume !(0 == start_simulation_~tmp~3#1); 5322#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5766#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5045#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4828#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 4829#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4913#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4914#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5389#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 4922#L1428-2 [2023-11-26 11:54:06,939 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:06,940 INFO L85 PathProgramCache]: Analyzing trace with hash -1066203769, now seen corresponding path program 1 times [2023-11-26 11:54:06,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:06,941 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [64172498] [2023-11-26 11:54:06,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:06,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:06,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:07,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:07,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:07,048 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [64172498] [2023-11-26 11:54:07,049 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [64172498] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:07,050 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:07,050 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:07,050 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [143489598] [2023-11-26 11:54:07,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:07,051 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:07,052 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:07,052 INFO L85 PathProgramCache]: Analyzing trace with hash 320478992, now seen corresponding path program 1 times [2023-11-26 11:54:07,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:07,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92613422] [2023-11-26 11:54:07,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:07,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:07,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:07,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:07,142 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:07,142 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [92613422] [2023-11-26 11:54:07,143 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [92613422] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:07,143 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:07,143 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:07,143 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059227077] [2023-11-26 11:54:07,144 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:07,145 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:07,145 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:07,145 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:07,146 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:07,146 INFO L87 Difference]: Start difference. First operand 1180 states and 1751 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:07,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:07,199 INFO L93 Difference]: Finished difference Result 1180 states and 1750 transitions. [2023-11-26 11:54:07,199 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1750 transitions. [2023-11-26 11:54:07,209 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:07,220 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1750 transitions. [2023-11-26 11:54:07,220 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-26 11:54:07,221 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-26 11:54:07,221 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1750 transitions. [2023-11-26 11:54:07,223 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:07,223 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1750 transitions. [2023-11-26 11:54:07,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1750 transitions. [2023-11-26 11:54:07,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-26 11:54:07,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4830508474576272) internal successors, (1750), 1179 states have internal predecessors, (1750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:07,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1750 transitions. [2023-11-26 11:54:07,252 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1750 transitions. [2023-11-26 11:54:07,252 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:07,254 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1750 transitions. [2023-11-26 11:54:07,255 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 11:54:07,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1750 transitions. [2023-11-26 11:54:07,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:07,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:07,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:07,266 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:07,266 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:07,267 INFO L748 eck$LassoCheckResult]: Stem: 7457#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7458#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 8238#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8239#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8173#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 7839#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7840#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8149#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7627#L673-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7628#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8076#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8077#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7129#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7130#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7333#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7727#L939 assume !(0 == ~M_E~0); 7982#L939-2 assume !(0 == ~T1_E~0); 7983#L944-1 assume !(0 == ~T2_E~0); 7765#L949-1 assume !(0 == ~T3_E~0); 7763#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7764#L959-1 assume !(0 == ~T5_E~0); 8185#L964-1 assume !(0 == ~T6_E~0); 7478#L969-1 assume !(0 == ~T7_E~0); 7479#L974-1 assume !(0 == ~T8_E~0); 8136#L979-1 assume !(0 == ~T9_E~0); 8137#L984-1 assume !(0 == ~E_M~0); 7641#L989-1 assume !(0 == ~E_1~0); 7642#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7529#L999-1 assume !(0 == ~E_3~0); 7530#L1004-1 assume !(0 == ~E_4~0); 7197#L1009-1 assume !(0 == ~E_5~0); 7198#L1014-1 assume !(0 == ~E_6~0); 7526#L1019-1 assume !(0 == ~E_7~0); 8081#L1024-1 assume !(0 == ~E_8~0); 7450#L1029-1 assume !(0 == ~E_9~0); 7451#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7537#L460 assume 1 == ~m_pc~0; 7118#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7119#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8046#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8160#L1167 assume !(0 != activate_threads_~tmp~1#1); 7748#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7749#L479 assume 1 == ~t1_pc~0; 7728#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7729#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7201#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7202#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 7464#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7312#L498 assume !(1 == ~t2_pc~0); 7313#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7726#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7629#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7630#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8036#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8037#L517 assume 1 == ~t3_pc~0; 8247#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8248#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7136#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7137#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 7499#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8088#L536 assume !(1 == ~t4_pc~0); 7793#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7792#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7298#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7299#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 7786#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8018#L555 assume 1 == ~t5_pc~0; 8019#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8082#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8132#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7454#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 7338#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7235#L574 assume !(1 == ~t6_pc~0); 7236#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7892#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7619#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7620#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 8105#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8271#L593 assume 1 == ~t7_pc~0; 8272#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7471#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8190#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8288#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 8250#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7634#L612 assume !(1 == ~t8_pc~0); 7635#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8064#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8110#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8111#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 7894#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7895#L631 assume 1 == ~t9_pc~0; 7908#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7227#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7228#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7679#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 7731#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8089#L1047 assume !(1 == ~M_E~0); 7165#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7166#L1052-1 assume !(1 == ~T2_E~0); 7146#L1057-1 assume !(1 == ~T3_E~0); 7147#L1062-1 assume !(1 == ~T4_E~0); 7436#L1067-1 assume !(1 == ~T5_E~0); 7752#L1072-1 assume !(1 == ~T6_E~0); 7753#L1077-1 assume !(1 == ~T7_E~0); 7327#L1082-1 assume !(1 == ~T8_E~0); 7328#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7125#L1092-1 assume !(1 == ~E_M~0); 7126#L1097-1 assume !(1 == ~E_1~0); 7148#L1102-1 assume !(1 == ~E_2~0); 7952#L1107-1 assume !(1 == ~E_3~0); 7890#L1112-1 assume !(1 == ~E_4~0); 7891#L1117-1 assume !(1 == ~E_5~0); 7927#L1122-1 assume !(1 == ~E_6~0); 7808#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7541#L1132-1 assume !(1 == ~E_8~0); 7542#L1137-1 assume !(1 == ~E_9~0); 7435#L1142-1 assume { :end_inline_reset_delta_events } true; 7289#L1428-2 [2023-11-26 11:54:07,267 INFO L750 eck$LassoCheckResult]: Loop: 7289#L1428-2 assume !false; 7290#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7657#L914-1 assume !false; 7886#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7887#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7134#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7135#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7658#L783 assume !(0 != eval_~tmp~0#1); 8106#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7846#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7847#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7353#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7354#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7121#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7122#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7770#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7203#L964-3 assume !(0 == ~T6_E~0); 7204#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7404#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7405#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7857#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7858#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7459#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7460#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7991#L1004-3 assume !(0 == ~E_4~0); 7278#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7279#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7837#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7838#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7818#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7771#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7772#L460-33 assume 1 == ~m_pc~0; 7809#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7810#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8006#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7127#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7128#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7485#L479-33 assume !(1 == ~t1_pc~0); 7486#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 7452#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7453#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8226#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8227#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7495#L498-33 assume 1 == ~t2_pc~0; 7496#L499-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7242#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7709#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7880#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7351#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7352#L517-33 assume !(1 == ~t3_pc~0); 8280#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 8165#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7310#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7311#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7976#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7577#L536-33 assume 1 == ~t4_pc~0; 7578#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7655#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7656#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8140#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8141#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7172#L555-33 assume 1 == ~t5_pc~0; 7173#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7918#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7919#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7948#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7949#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7143#L574-33 assume !(1 == ~t6_pc~0); 7144#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 8153#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7740#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7741#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 7719#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7221#L593-33 assume 1 == ~t7_pc~0; 7222#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7687#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8177#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8004#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8005#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8127#L612-33 assume 1 == ~t8_pc~0; 8258#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8219#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7929#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7930#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7323#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7324#L631-33 assume !(1 == ~t9_pc~0); 7955#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 7264#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7265#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7523#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7379#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7380#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7545#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8184#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8113#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8114#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7272#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7273#L1072-3 assume !(1 == ~T6_E~0); 7669#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7505#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7506#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7571#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7885#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7804#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7805#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8154#L1112-3 assume !(1 == ~E_4~0); 7500#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7501#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7546#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7547#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7965#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7943#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7384#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7261#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7572#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 7573#L1447 assume !(0 == start_simulation_~tmp~3#1); 7689#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8133#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7412#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7195#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 7196#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7280#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7281#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7756#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 7289#L1428-2 [2023-11-26 11:54:07,268 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:07,268 INFO L85 PathProgramCache]: Analyzing trace with hash 1065146953, now seen corresponding path program 1 times [2023-11-26 11:54:07,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:07,269 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785750869] [2023-11-26 11:54:07,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:07,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:07,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:07,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:07,333 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:07,333 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [785750869] [2023-11-26 11:54:07,333 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [785750869] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:07,334 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:07,334 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:07,338 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1645350826] [2023-11-26 11:54:07,339 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:07,339 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:07,340 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:07,340 INFO L85 PathProgramCache]: Analyzing trace with hash 320478992, now seen corresponding path program 2 times [2023-11-26 11:54:07,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:07,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1387306360] [2023-11-26 11:54:07,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:07,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:07,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:07,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:07,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:07,418 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1387306360] [2023-11-26 11:54:07,418 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1387306360] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:07,418 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:07,418 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:07,419 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1863575066] [2023-11-26 11:54:07,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:07,419 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:07,419 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:07,420 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:07,420 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:07,420 INFO L87 Difference]: Start difference. First operand 1180 states and 1750 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:07,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:07,454 INFO L93 Difference]: Finished difference Result 1180 states and 1749 transitions. [2023-11-26 11:54:07,454 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1749 transitions. [2023-11-26 11:54:07,464 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:07,474 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1749 transitions. [2023-11-26 11:54:07,474 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-26 11:54:07,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-26 11:54:07,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1749 transitions. [2023-11-26 11:54:07,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:07,478 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1749 transitions. [2023-11-26 11:54:07,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1749 transitions. [2023-11-26 11:54:07,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-26 11:54:07,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4822033898305085) internal successors, (1749), 1179 states have internal predecessors, (1749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:07,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1749 transitions. [2023-11-26 11:54:07,511 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1749 transitions. [2023-11-26 11:54:07,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:07,513 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1749 transitions. [2023-11-26 11:54:07,513 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 11:54:07,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1749 transitions. [2023-11-26 11:54:07,520 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:07,520 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:07,521 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:07,524 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:07,524 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:07,525 INFO L748 eck$LassoCheckResult]: Stem: 9822#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 9823#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 10605#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10606#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10540#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 10204#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10205#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10514#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9992#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9993#L678-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10441#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10442#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9496#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9497#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9700#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10094#L939 assume !(0 == ~M_E~0); 10349#L939-2 assume !(0 == ~T1_E~0); 10350#L944-1 assume !(0 == ~T2_E~0); 10132#L949-1 assume !(0 == ~T3_E~0); 10130#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10131#L959-1 assume !(0 == ~T5_E~0); 10552#L964-1 assume !(0 == ~T6_E~0); 9845#L969-1 assume !(0 == ~T7_E~0); 9846#L974-1 assume !(0 == ~T8_E~0); 10501#L979-1 assume !(0 == ~T9_E~0); 10502#L984-1 assume !(0 == ~E_M~0); 10006#L989-1 assume !(0 == ~E_1~0); 10007#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 9896#L999-1 assume !(0 == ~E_3~0); 9897#L1004-1 assume !(0 == ~E_4~0); 9562#L1009-1 assume !(0 == ~E_5~0); 9563#L1014-1 assume !(0 == ~E_6~0); 9891#L1019-1 assume !(0 == ~E_7~0); 10448#L1024-1 assume !(0 == ~E_8~0); 9817#L1029-1 assume !(0 == ~E_9~0); 9818#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9902#L460 assume 1 == ~m_pc~0; 9482#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9483#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10413#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10526#L1167 assume !(0 != activate_threads_~tmp~1#1); 10115#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10116#L479 assume 1 == ~t1_pc~0; 10095#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10096#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9566#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9567#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 9830#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9679#L498 assume !(1 == ~t2_pc~0); 9680#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10093#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9996#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9997#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10403#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10404#L517 assume 1 == ~t3_pc~0; 10611#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10612#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9503#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9504#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 9866#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10453#L536 assume !(1 == ~t4_pc~0); 10160#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10159#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9660#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9661#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 10153#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10381#L555 assume 1 == ~t5_pc~0; 10382#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10449#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10499#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9819#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 9703#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9602#L574 assume !(1 == ~t6_pc~0); 9603#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10259#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9986#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9987#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 10470#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10638#L593 assume 1 == ~t7_pc~0; 10639#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9838#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10555#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10655#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 10617#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10001#L612 assume !(1 == ~t8_pc~0); 10002#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10431#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10475#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10476#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 10261#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10262#L631 assume 1 == ~t9_pc~0; 10275#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9594#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9595#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10046#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 10098#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10456#L1047 assume !(1 == ~M_E~0); 9530#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9531#L1052-1 assume !(1 == ~T2_E~0); 9513#L1057-1 assume !(1 == ~T3_E~0); 9514#L1062-1 assume !(1 == ~T4_E~0); 9803#L1067-1 assume !(1 == ~T5_E~0); 10119#L1072-1 assume !(1 == ~T6_E~0); 10120#L1077-1 assume !(1 == ~T7_E~0); 9694#L1082-1 assume !(1 == ~T8_E~0); 9695#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9490#L1092-1 assume !(1 == ~E_M~0); 9491#L1097-1 assume !(1 == ~E_1~0); 9515#L1102-1 assume !(1 == ~E_2~0); 10319#L1107-1 assume !(1 == ~E_3~0); 10257#L1112-1 assume !(1 == ~E_4~0); 10258#L1117-1 assume !(1 == ~E_5~0); 10293#L1122-1 assume !(1 == ~E_6~0); 10175#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9906#L1132-1 assume !(1 == ~E_8~0); 9907#L1137-1 assume !(1 == ~E_9~0); 9800#L1142-1 assume { :end_inline_reset_delta_events } true; 9653#L1428-2 [2023-11-26 11:54:07,525 INFO L750 eck$LassoCheckResult]: Loop: 9653#L1428-2 assume !false; 9654#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10025#L914-1 assume !false; 10253#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10254#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9501#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9502#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10024#L783 assume !(0 != eval_~tmp~0#1); 10473#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10212#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10213#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9718#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9719#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9488#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9489#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10136#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9568#L964-3 assume !(0 == ~T6_E~0); 9569#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9771#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9772#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10224#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10225#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9826#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9827#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10358#L1004-3 assume !(0 == ~E_4~0); 9645#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9646#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10206#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10207#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10185#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10138#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10139#L460-33 assume 1 == ~m_pc~0; 10176#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10177#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10373#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9494#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9495#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9852#L479-33 assume !(1 == ~t1_pc~0); 9853#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 9820#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9821#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10593#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10594#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9864#L498-33 assume !(1 == ~t2_pc~0); 9608#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 9609#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10076#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10247#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9720#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9721#L517-33 assume !(1 == ~t3_pc~0); 10647#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 10532#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9677#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9678#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10343#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9944#L536-33 assume 1 == ~t4_pc~0; 9945#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10022#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10023#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10507#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10508#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9539#L555-33 assume 1 == ~t5_pc~0; 9540#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10285#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10286#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10315#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10316#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9510#L574-33 assume !(1 == ~t6_pc~0); 9511#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 10520#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10107#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10108#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 10086#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9588#L593-33 assume 1 == ~t7_pc~0; 9589#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10054#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10544#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10371#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10372#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10495#L612-33 assume 1 == ~t8_pc~0; 10625#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10586#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10296#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10297#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9690#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9691#L631-33 assume !(1 == ~t9_pc~0); 10322#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 9631#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9632#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9890#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9746#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9747#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9912#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10551#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10480#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10481#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9639#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9640#L1072-3 assume !(1 == ~T6_E~0); 10036#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9872#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9873#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9938#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10252#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10173#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10174#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10521#L1112-3 assume !(1 == ~E_4~0); 9867#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9868#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9913#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9914#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10332#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10310#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9751#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9628#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9939#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 9940#L1447 assume !(0 == start_simulation_~tmp~3#1); 10056#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10500#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9779#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9564#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 9565#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9647#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9648#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 10123#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 9653#L1428-2 [2023-11-26 11:54:07,526 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:07,526 INFO L85 PathProgramCache]: Analyzing trace with hash 2103731527, now seen corresponding path program 1 times [2023-11-26 11:54:07,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:07,526 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540346549] [2023-11-26 11:54:07,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:07,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:07,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:07,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:07,595 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:07,595 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [540346549] [2023-11-26 11:54:07,595 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [540346549] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:07,596 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:07,596 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:07,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [606171794] [2023-11-26 11:54:07,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:07,596 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:07,597 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:07,597 INFO L85 PathProgramCache]: Analyzing trace with hash 1780472913, now seen corresponding path program 2 times [2023-11-26 11:54:07,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:07,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431234983] [2023-11-26 11:54:07,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:07,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:07,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:07,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:07,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:07,674 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431234983] [2023-11-26 11:54:07,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [431234983] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:07,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:07,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:07,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288190488] [2023-11-26 11:54:07,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:07,675 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:07,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:07,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:07,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:07,676 INFO L87 Difference]: Start difference. First operand 1180 states and 1749 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:07,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:07,711 INFO L93 Difference]: Finished difference Result 1180 states and 1748 transitions. [2023-11-26 11:54:07,712 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1748 transitions. [2023-11-26 11:54:07,721 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:07,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1748 transitions. [2023-11-26 11:54:07,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-26 11:54:07,733 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-26 11:54:07,733 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1748 transitions. [2023-11-26 11:54:07,736 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:07,736 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1748 transitions. [2023-11-26 11:54:07,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1748 transitions. [2023-11-26 11:54:07,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-26 11:54:07,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4813559322033898) internal successors, (1748), 1179 states have internal predecessors, (1748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:07,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1748 transitions. [2023-11-26 11:54:07,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1748 transitions. [2023-11-26 11:54:07,765 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:07,768 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1748 transitions. [2023-11-26 11:54:07,768 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 11:54:07,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1748 transitions. [2023-11-26 11:54:07,776 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:07,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:07,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:07,778 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:07,778 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:07,779 INFO L748 eck$LassoCheckResult]: Stem: 12189#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12190#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12973#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12907#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 12571#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12572#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12881#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12359#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12360#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12808#L683-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12809#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11863#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11864#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12067#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12461#L939 assume !(0 == ~M_E~0); 12716#L939-2 assume !(0 == ~T1_E~0); 12717#L944-1 assume !(0 == ~T2_E~0); 12499#L949-1 assume !(0 == ~T3_E~0); 12497#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12498#L959-1 assume !(0 == ~T5_E~0); 12919#L964-1 assume !(0 == ~T6_E~0); 12212#L969-1 assume !(0 == ~T7_E~0); 12213#L974-1 assume !(0 == ~T8_E~0); 12868#L979-1 assume !(0 == ~T9_E~0); 12869#L984-1 assume !(0 == ~E_M~0); 12373#L989-1 assume !(0 == ~E_1~0); 12374#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12263#L999-1 assume !(0 == ~E_3~0); 12264#L1004-1 assume !(0 == ~E_4~0); 11929#L1009-1 assume !(0 == ~E_5~0); 11930#L1014-1 assume !(0 == ~E_6~0); 12258#L1019-1 assume !(0 == ~E_7~0); 12815#L1024-1 assume !(0 == ~E_8~0); 12184#L1029-1 assume !(0 == ~E_9~0); 12185#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12269#L460 assume 1 == ~m_pc~0; 11849#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11850#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12780#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12893#L1167 assume !(0 != activate_threads_~tmp~1#1); 12482#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12483#L479 assume 1 == ~t1_pc~0; 12462#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12463#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11933#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11934#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 12197#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12046#L498 assume !(1 == ~t2_pc~0); 12047#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12460#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12363#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12364#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12770#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12771#L517 assume 1 == ~t3_pc~0; 12978#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12979#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11870#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11871#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 12233#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12820#L536 assume !(1 == ~t4_pc~0); 12527#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12526#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12027#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12028#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 12520#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12748#L555 assume 1 == ~t5_pc~0; 12749#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12816#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12866#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12186#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 12070#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11969#L574 assume !(1 == ~t6_pc~0); 11970#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12626#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12353#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12354#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 12837#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13005#L593 assume 1 == ~t7_pc~0; 13006#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12205#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12922#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13022#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 12984#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12368#L612 assume !(1 == ~t8_pc~0); 12369#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12798#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12842#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12843#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 12628#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12629#L631 assume 1 == ~t9_pc~0; 12642#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11961#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11962#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12413#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 12465#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12823#L1047 assume !(1 == ~M_E~0); 11897#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11898#L1052-1 assume !(1 == ~T2_E~0); 11880#L1057-1 assume !(1 == ~T3_E~0); 11881#L1062-1 assume !(1 == ~T4_E~0); 12170#L1067-1 assume !(1 == ~T5_E~0); 12486#L1072-1 assume !(1 == ~T6_E~0); 12487#L1077-1 assume !(1 == ~T7_E~0); 12061#L1082-1 assume !(1 == ~T8_E~0); 12062#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11857#L1092-1 assume !(1 == ~E_M~0); 11858#L1097-1 assume !(1 == ~E_1~0); 11882#L1102-1 assume !(1 == ~E_2~0); 12686#L1107-1 assume !(1 == ~E_3~0); 12624#L1112-1 assume !(1 == ~E_4~0); 12625#L1117-1 assume !(1 == ~E_5~0); 12660#L1122-1 assume !(1 == ~E_6~0); 12542#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12273#L1132-1 assume !(1 == ~E_8~0); 12274#L1137-1 assume !(1 == ~E_9~0); 12167#L1142-1 assume { :end_inline_reset_delta_events } true; 12020#L1428-2 [2023-11-26 11:54:07,779 INFO L750 eck$LassoCheckResult]: Loop: 12020#L1428-2 assume !false; 12021#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12392#L914-1 assume !false; 12620#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12621#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11868#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11869#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12391#L783 assume !(0 != eval_~tmp~0#1); 12840#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12579#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12580#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12085#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12086#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11855#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11856#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12503#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11935#L964-3 assume !(0 == ~T6_E~0); 11936#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12138#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12139#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12591#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12592#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12193#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12194#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12725#L1004-3 assume !(0 == ~E_4~0); 12012#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12013#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12573#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12574#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12552#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12505#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12506#L460-33 assume !(1 == ~m_pc~0); 12545#L460-35 is_master_triggered_~__retres1~0#1 := 0; 12544#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12740#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11861#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11862#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12219#L479-33 assume !(1 == ~t1_pc~0); 12220#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 12187#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12188#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12960#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12961#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12231#L498-33 assume !(1 == ~t2_pc~0); 11975#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 11976#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12443#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12614#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12087#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12088#L517-33 assume !(1 == ~t3_pc~0); 13014#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 12899#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12044#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12045#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12710#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12311#L536-33 assume 1 == ~t4_pc~0; 12312#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12389#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12390#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12874#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12875#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11906#L555-33 assume 1 == ~t5_pc~0; 11907#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12652#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12653#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12682#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12683#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11877#L574-33 assume !(1 == ~t6_pc~0); 11878#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 12887#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12474#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12475#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 12453#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11955#L593-33 assume 1 == ~t7_pc~0; 11956#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12421#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12911#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12738#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12739#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12862#L612-33 assume 1 == ~t8_pc~0; 12992#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12953#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12663#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12664#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12057#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12058#L631-33 assume !(1 == ~t9_pc~0); 12689#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 11998#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11999#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12257#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12113#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12114#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12279#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12918#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12847#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12848#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12006#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12007#L1072-3 assume !(1 == ~T6_E~0); 12403#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12239#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12240#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12305#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12619#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12540#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12541#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12888#L1112-3 assume !(1 == ~E_4~0); 12234#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12235#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12280#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12281#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12699#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12677#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12118#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11995#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12306#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 12307#L1447 assume !(0 == start_simulation_~tmp~3#1); 12423#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12867#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12146#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11931#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 11932#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12014#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12015#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 12490#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 12020#L1428-2 [2023-11-26 11:54:07,780 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:07,780 INFO L85 PathProgramCache]: Analyzing trace with hash -218070391, now seen corresponding path program 1 times [2023-11-26 11:54:07,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:07,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624069373] [2023-11-26 11:54:07,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:07,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:07,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:07,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:07,859 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:07,859 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624069373] [2023-11-26 11:54:07,864 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [624069373] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:07,864 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:07,865 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:07,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1394951036] [2023-11-26 11:54:07,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:07,865 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:07,866 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:07,866 INFO L85 PathProgramCache]: Analyzing trace with hash -1397309422, now seen corresponding path program 1 times [2023-11-26 11:54:07,866 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:07,866 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807011047] [2023-11-26 11:54:07,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:07,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:07,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:07,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:07,935 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:07,935 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807011047] [2023-11-26 11:54:07,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1807011047] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:07,936 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:07,936 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:07,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [608829228] [2023-11-26 11:54:07,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:07,937 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:07,937 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:07,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:07,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:07,938 INFO L87 Difference]: Start difference. First operand 1180 states and 1748 transitions. cyclomatic complexity: 569 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:07,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:07,970 INFO L93 Difference]: Finished difference Result 1180 states and 1747 transitions. [2023-11-26 11:54:07,970 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1747 transitions. [2023-11-26 11:54:07,980 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:07,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1747 transitions. [2023-11-26 11:54:07,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-26 11:54:07,991 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-26 11:54:07,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1747 transitions. [2023-11-26 11:54:07,993 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:07,993 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1747 transitions. [2023-11-26 11:54:07,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1747 transitions. [2023-11-26 11:54:08,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-26 11:54:08,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.480508474576271) internal successors, (1747), 1179 states have internal predecessors, (1747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:08,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1747 transitions. [2023-11-26 11:54:08,022 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1747 transitions. [2023-11-26 11:54:08,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:08,025 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1747 transitions. [2023-11-26 11:54:08,025 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 11:54:08,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1747 transitions. [2023-11-26 11:54:08,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:08,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:08,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:08,035 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:08,035 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:08,036 INFO L748 eck$LassoCheckResult]: Stem: 14556#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 14557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 15339#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15340#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15274#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 14938#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14939#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15248#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14726#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14727#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15175#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15176#L688-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14230#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14231#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14434#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14828#L939 assume !(0 == ~M_E~0); 15083#L939-2 assume !(0 == ~T1_E~0); 15084#L944-1 assume !(0 == ~T2_E~0); 14866#L949-1 assume !(0 == ~T3_E~0); 14864#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14865#L959-1 assume !(0 == ~T5_E~0); 15286#L964-1 assume !(0 == ~T6_E~0); 14579#L969-1 assume !(0 == ~T7_E~0); 14580#L974-1 assume !(0 == ~T8_E~0); 15235#L979-1 assume !(0 == ~T9_E~0); 15236#L984-1 assume !(0 == ~E_M~0); 14740#L989-1 assume !(0 == ~E_1~0); 14741#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 14630#L999-1 assume !(0 == ~E_3~0); 14631#L1004-1 assume !(0 == ~E_4~0); 14296#L1009-1 assume !(0 == ~E_5~0); 14297#L1014-1 assume !(0 == ~E_6~0); 14625#L1019-1 assume !(0 == ~E_7~0); 15182#L1024-1 assume !(0 == ~E_8~0); 14551#L1029-1 assume !(0 == ~E_9~0); 14552#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14636#L460 assume 1 == ~m_pc~0; 14216#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14217#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15147#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15260#L1167 assume !(0 != activate_threads_~tmp~1#1); 14849#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14850#L479 assume 1 == ~t1_pc~0; 14829#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14830#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14300#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14301#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 14564#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14413#L498 assume !(1 == ~t2_pc~0); 14414#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14827#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14730#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14731#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15137#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15138#L517 assume 1 == ~t3_pc~0; 15345#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15346#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14237#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14238#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 14600#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15187#L536 assume !(1 == ~t4_pc~0); 14894#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14893#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14394#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14395#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 14887#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15115#L555 assume 1 == ~t5_pc~0; 15116#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15183#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15233#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14553#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 14437#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14336#L574 assume !(1 == ~t6_pc~0); 14337#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14993#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14720#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14721#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 15204#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15372#L593 assume 1 == ~t7_pc~0; 15373#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14572#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15289#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15389#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 15351#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14735#L612 assume !(1 == ~t8_pc~0); 14736#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 15165#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15209#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15210#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 14995#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14996#L631 assume 1 == ~t9_pc~0; 15009#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14328#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14329#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14780#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 14832#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15190#L1047 assume !(1 == ~M_E~0); 14264#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14265#L1052-1 assume !(1 == ~T2_E~0); 14247#L1057-1 assume !(1 == ~T3_E~0); 14248#L1062-1 assume !(1 == ~T4_E~0); 14537#L1067-1 assume !(1 == ~T5_E~0); 14853#L1072-1 assume !(1 == ~T6_E~0); 14854#L1077-1 assume !(1 == ~T7_E~0); 14428#L1082-1 assume !(1 == ~T8_E~0); 14429#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14224#L1092-1 assume !(1 == ~E_M~0); 14225#L1097-1 assume !(1 == ~E_1~0); 14249#L1102-1 assume !(1 == ~E_2~0); 15053#L1107-1 assume !(1 == ~E_3~0); 14991#L1112-1 assume !(1 == ~E_4~0); 14992#L1117-1 assume !(1 == ~E_5~0); 15027#L1122-1 assume !(1 == ~E_6~0); 14909#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14640#L1132-1 assume !(1 == ~E_8~0); 14641#L1137-1 assume !(1 == ~E_9~0); 14534#L1142-1 assume { :end_inline_reset_delta_events } true; 14387#L1428-2 [2023-11-26 11:54:08,036 INFO L750 eck$LassoCheckResult]: Loop: 14387#L1428-2 assume !false; 14388#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14759#L914-1 assume !false; 14987#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14988#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14235#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14236#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14758#L783 assume !(0 != eval_~tmp~0#1); 15207#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14946#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14947#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14452#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14453#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14222#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14223#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14870#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14302#L964-3 assume !(0 == ~T6_E~0); 14303#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14505#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14506#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14958#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14959#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14560#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14561#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15092#L1004-3 assume !(0 == ~E_4~0); 14379#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14380#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14940#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14941#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14919#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14872#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14873#L460-33 assume !(1 == ~m_pc~0); 14912#L460-35 is_master_triggered_~__retres1~0#1 := 0; 14911#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15107#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14228#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14229#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14586#L479-33 assume !(1 == ~t1_pc~0); 14587#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 14554#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14555#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15327#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15328#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14598#L498-33 assume !(1 == ~t2_pc~0); 14342#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 14343#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14810#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14981#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14454#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14455#L517-33 assume !(1 == ~t3_pc~0); 15381#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 15266#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14411#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14412#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15077#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14678#L536-33 assume 1 == ~t4_pc~0; 14679#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14756#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14757#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15241#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15242#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14273#L555-33 assume 1 == ~t5_pc~0; 14274#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15019#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15020#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15049#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15050#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14244#L574-33 assume !(1 == ~t6_pc~0); 14245#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 15254#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14841#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14842#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 14820#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14322#L593-33 assume 1 == ~t7_pc~0; 14323#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14788#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15278#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15105#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15106#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15229#L612-33 assume !(1 == ~t8_pc~0); 15360#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 15320#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15030#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15031#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14424#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14425#L631-33 assume !(1 == ~t9_pc~0); 15056#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 14365#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14366#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14624#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14480#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14481#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14646#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15285#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15214#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15215#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14373#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14374#L1072-3 assume !(1 == ~T6_E~0); 14770#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14606#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14607#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14672#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14986#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14907#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14908#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15255#L1112-3 assume !(1 == ~E_4~0); 14601#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14602#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14647#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14648#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15066#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15044#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14485#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14362#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14673#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 14674#L1447 assume !(0 == start_simulation_~tmp~3#1); 14790#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15234#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14513#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14298#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 14299#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14381#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14382#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 14857#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 14387#L1428-2 [2023-11-26 11:54:08,037 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:08,037 INFO L85 PathProgramCache]: Analyzing trace with hash 1923790087, now seen corresponding path program 1 times [2023-11-26 11:54:08,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:08,037 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589995923] [2023-11-26 11:54:08,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:08,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:08,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:08,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:08,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:08,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [589995923] [2023-11-26 11:54:08,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [589995923] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:08,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:08,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:08,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732070845] [2023-11-26 11:54:08,091 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:08,091 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:08,091 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:08,091 INFO L85 PathProgramCache]: Analyzing trace with hash 2024180179, now seen corresponding path program 1 times [2023-11-26 11:54:08,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:08,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1306339933] [2023-11-26 11:54:08,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:08,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:08,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:08,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:08,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:08,153 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1306339933] [2023-11-26 11:54:08,153 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1306339933] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:08,154 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:08,154 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:08,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [892906870] [2023-11-26 11:54:08,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:08,154 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:08,155 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:08,155 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:08,155 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:08,155 INFO L87 Difference]: Start difference. First operand 1180 states and 1747 transitions. cyclomatic complexity: 568 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:08,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:08,188 INFO L93 Difference]: Finished difference Result 1180 states and 1746 transitions. [2023-11-26 11:54:08,188 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1746 transitions. [2023-11-26 11:54:08,198 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:08,208 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1746 transitions. [2023-11-26 11:54:08,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-26 11:54:08,210 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-26 11:54:08,210 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1746 transitions. [2023-11-26 11:54:08,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:08,212 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1746 transitions. [2023-11-26 11:54:08,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1746 transitions. [2023-11-26 11:54:08,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-26 11:54:08,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.4796610169491526) internal successors, (1746), 1179 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:08,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1746 transitions. [2023-11-26 11:54:08,240 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1746 transitions. [2023-11-26 11:54:08,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:08,242 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1746 transitions. [2023-11-26 11:54:08,242 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 11:54:08,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1746 transitions. [2023-11-26 11:54:08,251 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:08,251 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:08,251 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:08,253 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:08,254 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:08,261 INFO L748 eck$LassoCheckResult]: Stem: 16923#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 16924#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17706#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17707#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17641#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 17305#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17306#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17617#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17093#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17094#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17544#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17545#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16597#L693-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16598#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16801#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17195#L939 assume !(0 == ~M_E~0); 17450#L939-2 assume !(0 == ~T1_E~0); 17451#L944-1 assume !(0 == ~T2_E~0); 17233#L949-1 assume !(0 == ~T3_E~0); 17231#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17232#L959-1 assume !(0 == ~T5_E~0); 17653#L964-1 assume !(0 == ~T6_E~0); 16946#L969-1 assume !(0 == ~T7_E~0); 16947#L974-1 assume !(0 == ~T8_E~0); 17602#L979-1 assume !(0 == ~T9_E~0); 17603#L984-1 assume !(0 == ~E_M~0); 17107#L989-1 assume !(0 == ~E_1~0); 17108#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 16997#L999-1 assume !(0 == ~E_3~0); 16998#L1004-1 assume !(0 == ~E_4~0); 16665#L1009-1 assume !(0 == ~E_5~0); 16666#L1014-1 assume !(0 == ~E_6~0); 16994#L1019-1 assume !(0 == ~E_7~0); 17549#L1024-1 assume !(0 == ~E_8~0); 16918#L1029-1 assume !(0 == ~E_9~0); 16919#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17003#L460 assume 1 == ~m_pc~0; 16583#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16584#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17514#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17627#L1167 assume !(0 != activate_threads_~tmp~1#1); 17216#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17217#L479 assume 1 == ~t1_pc~0; 17196#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17197#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16667#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16668#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 16931#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16780#L498 assume !(1 == ~t2_pc~0); 16781#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17194#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17097#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17098#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17504#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17505#L517 assume 1 == ~t3_pc~0; 17714#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17715#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16604#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16605#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 16967#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17554#L536 assume !(1 == ~t4_pc~0); 17261#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17260#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16761#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16762#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 17254#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17484#L555 assume 1 == ~t5_pc~0; 17485#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17550#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17600#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16920#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 16804#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16703#L574 assume !(1 == ~t6_pc~0); 16704#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17360#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17087#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17088#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 17571#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17739#L593 assume 1 == ~t7_pc~0; 17740#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16939#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17656#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17756#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 17718#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17102#L612 assume !(1 == ~t8_pc~0); 17103#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17532#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17576#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17577#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 17362#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17363#L631 assume 1 == ~t9_pc~0; 17376#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16695#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16696#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17147#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 17199#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17557#L1047 assume !(1 == ~M_E~0); 16631#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16632#L1052-1 assume !(1 == ~T2_E~0); 16614#L1057-1 assume !(1 == ~T3_E~0); 16615#L1062-1 assume !(1 == ~T4_E~0); 16904#L1067-1 assume !(1 == ~T5_E~0); 17220#L1072-1 assume !(1 == ~T6_E~0); 17221#L1077-1 assume !(1 == ~T7_E~0); 16795#L1082-1 assume !(1 == ~T8_E~0); 16796#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16591#L1092-1 assume !(1 == ~E_M~0); 16592#L1097-1 assume !(1 == ~E_1~0); 16616#L1102-1 assume !(1 == ~E_2~0); 17420#L1107-1 assume !(1 == ~E_3~0); 17358#L1112-1 assume !(1 == ~E_4~0); 17359#L1117-1 assume !(1 == ~E_5~0); 17394#L1122-1 assume !(1 == ~E_6~0); 17276#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17007#L1132-1 assume !(1 == ~E_8~0); 17008#L1137-1 assume !(1 == ~E_9~0); 16901#L1142-1 assume { :end_inline_reset_delta_events } true; 16754#L1428-2 [2023-11-26 11:54:08,261 INFO L750 eck$LassoCheckResult]: Loop: 16754#L1428-2 assume !false; 16755#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17126#L914-1 assume !false; 17354#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17355#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16602#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16603#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17125#L783 assume !(0 != eval_~tmp~0#1); 17574#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17313#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17314#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16819#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16820#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16589#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16590#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17237#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16669#L964-3 assume !(0 == ~T6_E~0); 16670#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16872#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16873#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17325#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17326#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16927#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16928#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17459#L1004-3 assume !(0 == ~E_4~0); 16746#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16747#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17307#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17308#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17286#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17239#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17240#L460-33 assume 1 == ~m_pc~0; 17277#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17278#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17474#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16595#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16596#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16955#L479-33 assume !(1 == ~t1_pc~0); 16956#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16921#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16922#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17694#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17695#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16965#L498-33 assume !(1 == ~t2_pc~0); 16709#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 16710#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17177#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17348#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16821#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16822#L517-33 assume !(1 == ~t3_pc~0); 17748#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 17633#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16778#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16779#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17444#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17045#L536-33 assume 1 == ~t4_pc~0; 17046#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17123#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17124#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17608#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17609#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16640#L555-33 assume 1 == ~t5_pc~0; 16641#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17386#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17387#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17416#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17417#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16611#L574-33 assume !(1 == ~t6_pc~0); 16612#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 17621#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17208#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17209#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 17187#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16689#L593-33 assume 1 == ~t7_pc~0; 16690#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17156#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17644#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17472#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17473#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17595#L612-33 assume 1 == ~t8_pc~0; 17726#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17687#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17397#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17398#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16786#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16787#L631-33 assume 1 == ~t9_pc~0; 17651#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16730#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16731#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16989#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16847#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16848#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17013#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17652#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17581#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17582#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16740#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16741#L1072-3 assume !(1 == ~T6_E~0); 17137#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16973#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16974#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17039#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17353#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17272#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17273#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17622#L1112-3 assume !(1 == ~E_4~0); 16968#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16969#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17014#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17015#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17433#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17411#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16849#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16726#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17040#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 17041#L1447 assume !(0 == start_simulation_~tmp~3#1); 17157#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17601#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16880#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16663#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 16664#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16748#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16749#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 17224#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 16754#L1428-2 [2023-11-26 11:54:08,262 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:08,262 INFO L85 PathProgramCache]: Analyzing trace with hash -1747895607, now seen corresponding path program 1 times [2023-11-26 11:54:08,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:08,263 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386138650] [2023-11-26 11:54:08,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:08,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:08,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:08,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:08,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:08,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1386138650] [2023-11-26 11:54:08,311 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1386138650] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:08,312 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:08,312 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:08,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [511822136] [2023-11-26 11:54:08,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:08,312 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:08,313 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:08,313 INFO L85 PathProgramCache]: Analyzing trace with hash -1557566000, now seen corresponding path program 1 times [2023-11-26 11:54:08,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:08,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1509111056] [2023-11-26 11:54:08,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:08,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:08,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:08,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:08,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:08,408 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1509111056] [2023-11-26 11:54:08,410 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1509111056] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:08,410 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:08,411 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:08,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942915227] [2023-11-26 11:54:08,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:08,411 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:08,411 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:08,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:08,412 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:08,412 INFO L87 Difference]: Start difference. First operand 1180 states and 1746 transitions. cyclomatic complexity: 567 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:08,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:08,445 INFO L93 Difference]: Finished difference Result 1180 states and 1745 transitions. [2023-11-26 11:54:08,445 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1745 transitions. [2023-11-26 11:54:08,453 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:08,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1745 transitions. [2023-11-26 11:54:08,463 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2023-11-26 11:54:08,468 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2023-11-26 11:54:08,468 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1745 transitions. [2023-11-26 11:54:08,470 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:08,470 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1745 transitions. [2023-11-26 11:54:08,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1745 transitions. [2023-11-26 11:54:08,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1180. [2023-11-26 11:54:08,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1180 states, 1180 states have (on average 1.478813559322034) internal successors, (1745), 1179 states have internal predecessors, (1745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:08,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1180 states to 1180 states and 1745 transitions. [2023-11-26 11:54:08,500 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1180 states and 1745 transitions. [2023-11-26 11:54:08,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:08,503 INFO L428 stractBuchiCegarLoop]: Abstraction has 1180 states and 1745 transitions. [2023-11-26 11:54:08,503 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 11:54:08,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1180 states and 1745 transitions. [2023-11-26 11:54:08,508 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1053 [2023-11-26 11:54:08,509 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:08,509 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:08,511 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:08,511 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:08,511 INFO L748 eck$LassoCheckResult]: Stem: 19292#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19293#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 20073#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20074#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20008#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 19672#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19673#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19984#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19460#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19461#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19911#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19912#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18964#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18965#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19168#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19562#L939 assume !(0 == ~M_E~0); 19817#L939-2 assume !(0 == ~T1_E~0); 19818#L944-1 assume !(0 == ~T2_E~0); 19600#L949-1 assume !(0 == ~T3_E~0); 19598#L954-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19599#L959-1 assume !(0 == ~T5_E~0); 20020#L964-1 assume !(0 == ~T6_E~0); 19313#L969-1 assume !(0 == ~T7_E~0); 19314#L974-1 assume !(0 == ~T8_E~0); 19971#L979-1 assume !(0 == ~T9_E~0); 19972#L984-1 assume !(0 == ~E_M~0); 19474#L989-1 assume !(0 == ~E_1~0); 19475#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 19364#L999-1 assume !(0 == ~E_3~0); 19365#L1004-1 assume !(0 == ~E_4~0); 19032#L1009-1 assume !(0 == ~E_5~0); 19033#L1014-1 assume !(0 == ~E_6~0); 19361#L1019-1 assume !(0 == ~E_7~0); 19916#L1024-1 assume !(0 == ~E_8~0); 19285#L1029-1 assume !(0 == ~E_9~0); 19286#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19370#L460 assume 1 == ~m_pc~0; 18953#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18954#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19881#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19994#L1167 assume !(0 != activate_threads_~tmp~1#1); 19583#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19584#L479 assume 1 == ~t1_pc~0; 19563#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19564#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19034#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19035#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 19298#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19147#L498 assume !(1 == ~t2_pc~0); 19148#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19561#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19464#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19465#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19871#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19872#L517 assume 1 == ~t3_pc~0; 20081#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20082#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18971#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18972#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 19334#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19923#L536 assume !(1 == ~t4_pc~0); 19628#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19627#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19133#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19134#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 19621#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19851#L555 assume 1 == ~t5_pc~0; 19852#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19917#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19967#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19287#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 19171#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19070#L574 assume !(1 == ~t6_pc~0); 19071#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19727#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19454#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19455#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 19940#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20106#L593 assume 1 == ~t7_pc~0; 20107#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19306#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20023#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20123#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 20085#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19469#L612 assume !(1 == ~t8_pc~0); 19470#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19899#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19943#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19944#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 19729#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19730#L631 assume 1 == ~t9_pc~0; 19743#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19062#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19063#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19514#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 19566#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19924#L1047 assume !(1 == ~M_E~0); 18998#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18999#L1052-1 assume !(1 == ~T2_E~0); 18981#L1057-1 assume !(1 == ~T3_E~0); 18982#L1062-1 assume !(1 == ~T4_E~0); 19271#L1067-1 assume !(1 == ~T5_E~0); 19587#L1072-1 assume !(1 == ~T6_E~0); 19588#L1077-1 assume !(1 == ~T7_E~0); 19162#L1082-1 assume !(1 == ~T8_E~0); 19163#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18960#L1092-1 assume !(1 == ~E_M~0); 18961#L1097-1 assume !(1 == ~E_1~0); 18983#L1102-1 assume !(1 == ~E_2~0); 19787#L1107-1 assume !(1 == ~E_3~0); 19725#L1112-1 assume !(1 == ~E_4~0); 19726#L1117-1 assume !(1 == ~E_5~0); 19761#L1122-1 assume !(1 == ~E_6~0); 19643#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19376#L1132-1 assume !(1 == ~E_8~0); 19377#L1137-1 assume !(1 == ~E_9~0); 19268#L1142-1 assume { :end_inline_reset_delta_events } true; 19121#L1428-2 [2023-11-26 11:54:08,512 INFO L750 eck$LassoCheckResult]: Loop: 19121#L1428-2 assume !false; 19122#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19493#L914-1 assume !false; 19721#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19722#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 18969#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 18970#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19492#L783 assume !(0 != eval_~tmp~0#1); 19941#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19681#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19682#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19186#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19187#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18956#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18957#L954-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19605#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19036#L964-3 assume !(0 == ~T6_E~0); 19037#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19239#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19240#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19692#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19693#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19294#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19295#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19826#L1004-3 assume !(0 == ~E_4~0); 19113#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19114#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19674#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19675#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19653#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19606#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19607#L460-33 assume 1 == ~m_pc~0; 19645#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19646#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19841#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18962#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18963#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19322#L479-33 assume !(1 == ~t1_pc~0); 19323#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 19288#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19289#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20061#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20062#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19332#L498-33 assume !(1 == ~t2_pc~0); 19076#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 19077#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19544#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19715#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19188#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19189#L517-33 assume !(1 == ~t3_pc~0); 20115#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 20000#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19145#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19146#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19811#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19409#L536-33 assume 1 == ~t4_pc~0; 19410#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19490#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19491#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19975#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19976#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19004#L555-33 assume 1 == ~t5_pc~0; 19005#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19753#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19754#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19783#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19784#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18976#L574-33 assume !(1 == ~t6_pc~0); 18977#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 19988#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19575#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19576#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 19554#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19054#L593-33 assume !(1 == ~t7_pc~0); 19056#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 19519#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20011#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19839#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19840#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19962#L612-33 assume 1 == ~t8_pc~0; 20093#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20054#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19764#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19765#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19156#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19157#L631-33 assume 1 == ~t9_pc~0; 20018#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19099#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19100#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19356#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19214#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19215#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19380#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20019#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19948#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19949#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19107#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19108#L1072-3 assume !(1 == ~T6_E~0); 19504#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19340#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19341#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19406#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19720#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19639#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19640#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19989#L1112-3 assume !(1 == ~E_4~0); 19335#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19336#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19381#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19382#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19800#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19778#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19216#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19093#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19407#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 19408#L1447 assume !(0 == start_simulation_~tmp~3#1); 19524#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19968#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19247#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19030#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 19031#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19115#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19116#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 19591#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 19121#L1428-2 [2023-11-26 11:54:08,512 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:08,513 INFO L85 PathProgramCache]: Analyzing trace with hash -1866337081, now seen corresponding path program 1 times [2023-11-26 11:54:08,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:08,513 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [571963962] [2023-11-26 11:54:08,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:08,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:08,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:08,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:08,612 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:08,612 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [571963962] [2023-11-26 11:54:08,612 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [571963962] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:08,612 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:08,612 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:08,613 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [878530136] [2023-11-26 11:54:08,613 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:08,613 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:08,614 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:08,614 INFO L85 PathProgramCache]: Analyzing trace with hash 636560081, now seen corresponding path program 1 times [2023-11-26 11:54:08,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:08,614 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288455453] [2023-11-26 11:54:08,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:08,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:08,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:08,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:08,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:08,674 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1288455453] [2023-11-26 11:54:08,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1288455453] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:08,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:08,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:08,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2110344303] [2023-11-26 11:54:08,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:08,675 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:08,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:08,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:54:08,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:54:08,676 INFO L87 Difference]: Start difference. First operand 1180 states and 1745 transitions. cyclomatic complexity: 566 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:08,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:08,858 INFO L93 Difference]: Finished difference Result 2161 states and 3183 transitions. [2023-11-26 11:54:08,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2161 states and 3183 transitions. [2023-11-26 11:54:08,873 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2014 [2023-11-26 11:54:08,892 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2161 states to 2161 states and 3183 transitions. [2023-11-26 11:54:08,892 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2161 [2023-11-26 11:54:08,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2161 [2023-11-26 11:54:08,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2161 states and 3183 transitions. [2023-11-26 11:54:08,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:08,900 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2161 states and 3183 transitions. [2023-11-26 11:54:08,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2161 states and 3183 transitions. [2023-11-26 11:54:08,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2161 to 2161. [2023-11-26 11:54:08,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2161 states, 2161 states have (on average 1.4729291994447016) internal successors, (3183), 2160 states have internal predecessors, (3183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:08,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2161 states to 2161 states and 3183 transitions. [2023-11-26 11:54:08,960 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2161 states and 3183 transitions. [2023-11-26 11:54:08,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:54:08,962 INFO L428 stractBuchiCegarLoop]: Abstraction has 2161 states and 3183 transitions. [2023-11-26 11:54:08,963 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 11:54:08,963 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2161 states and 3183 transitions. [2023-11-26 11:54:08,973 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2014 [2023-11-26 11:54:08,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:08,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:08,975 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:08,976 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:08,976 INFO L748 eck$LassoCheckResult]: Stem: 22644#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 22645#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 23494#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23495#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23416#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 23036#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23037#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23387#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22819#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22820#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23300#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23301#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22315#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22316#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22519#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22921#L939 assume !(0 == ~M_E~0); 23190#L939-2 assume !(0 == ~T1_E~0); 23191#L944-1 assume !(0 == ~T2_E~0); 22959#L949-1 assume !(0 == ~T3_E~0); 22957#L954-1 assume !(0 == ~T4_E~0); 22958#L959-1 assume !(0 == ~T5_E~0); 23432#L964-1 assume !(0 == ~T6_E~0); 22665#L969-1 assume !(0 == ~T7_E~0); 22666#L974-1 assume !(0 == ~T8_E~0); 23372#L979-1 assume !(0 == ~T9_E~0); 23373#L984-1 assume !(0 == ~E_M~0); 22833#L989-1 assume !(0 == ~E_1~0); 22834#L994-1 assume 0 == ~E_2~0;~E_2~0 := 1; 22716#L999-1 assume !(0 == ~E_3~0); 22717#L1004-1 assume !(0 == ~E_4~0); 22383#L1009-1 assume !(0 == ~E_5~0); 22384#L1014-1 assume !(0 == ~E_6~0); 22713#L1019-1 assume !(0 == ~E_7~0); 23305#L1024-1 assume !(0 == ~E_8~0); 22637#L1029-1 assume !(0 == ~E_9~0); 22638#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22724#L460 assume 1 == ~m_pc~0; 22304#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22305#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23266#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23400#L1167 assume !(0 != activate_threads_~tmp~1#1); 22942#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22943#L479 assume 1 == ~t1_pc~0; 22922#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22923#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22387#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22388#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 22651#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22498#L498 assume !(1 == ~t2_pc~0); 22499#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22920#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22821#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22822#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23255#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23256#L517 assume 1 == ~t3_pc~0; 23506#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23507#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22322#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22323#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 22686#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23315#L536 assume !(1 == ~t4_pc~0); 22988#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22987#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22484#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22485#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 22981#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23233#L555 assume 1 == ~t5_pc~0; 23234#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23306#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23368#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22641#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 22524#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22421#L574 assume !(1 == ~t6_pc~0); 22422#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23089#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22809#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22810#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 23335#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23539#L593 assume 1 == ~t7_pc~0; 23540#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22658#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23437#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23565#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 23510#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22826#L612 assume !(1 == ~t8_pc~0); 22827#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23285#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23341#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23342#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 23091#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23092#L631 assume 1 == ~t9_pc~0; 23106#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22413#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22414#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22872#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 22925#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23317#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 22351#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22352#L1052-1 assume !(1 == ~T2_E~0); 22332#L1057-1 assume !(1 == ~T3_E~0); 22333#L1062-1 assume !(1 == ~T4_E~0); 22623#L1067-1 assume !(1 == ~T5_E~0); 22946#L1072-1 assume !(1 == ~T6_E~0); 22947#L1077-1 assume !(1 == ~T7_E~0); 22513#L1082-1 assume !(1 == ~T8_E~0); 22514#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22311#L1092-1 assume !(1 == ~E_M~0); 22312#L1097-1 assume !(1 == ~E_1~0); 22334#L1102-1 assume !(1 == ~E_2~0); 23158#L1107-1 assume !(1 == ~E_3~0); 23087#L1112-1 assume !(1 == ~E_4~0); 23088#L1117-1 assume !(1 == ~E_5~0); 23605#L1122-1 assume !(1 == ~E_6~0); 23603#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23602#L1132-1 assume !(1 == ~E_8~0); 23601#L1137-1 assume !(1 == ~E_9~0); 23600#L1142-1 assume { :end_inline_reset_delta_events } true; 23595#L1428-2 [2023-11-26 11:54:08,976 INFO L750 eck$LassoCheckResult]: Loop: 23595#L1428-2 assume !false; 23592#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23148#L914-1 assume !false; 23083#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23084#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23581#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23580#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23336#L783 assume !(0 != eval_~tmp~0#1); 23337#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23043#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23044#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22539#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22540#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22307#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22308#L954-3 assume !(0 == ~T4_E~0); 22965#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22389#L964-3 assume !(0 == ~T6_E~0); 22390#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22591#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22592#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23054#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23055#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22646#L994-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22647#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23201#L1004-3 assume !(0 == ~E_4~0); 22464#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22465#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23034#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23035#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23015#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22966#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22967#L460-33 assume 1 == ~m_pc~0; 23005#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23006#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23220#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22313#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22314#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22672#L479-33 assume !(1 == ~t1_pc~0); 22673#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 23375#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24388#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24387#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24386#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24385#L498-33 assume !(1 == ~t2_pc~0); 24384#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 24382#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24381#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24380#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24379#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24378#L517-33 assume !(1 == ~t3_pc~0); 24376#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 24375#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24374#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24373#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24372#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24371#L536-33 assume 1 == ~t4_pc~0; 24369#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24368#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24367#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24366#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24365#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24364#L555-33 assume !(1 == ~t5_pc~0); 24362#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 24361#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24360#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24359#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24358#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24357#L574-33 assume 1 == ~t6_pc~0; 24355#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24354#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24353#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24352#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 24351#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24350#L593-33 assume 1 == ~t7_pc~0; 24348#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24347#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24346#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24345#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24344#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24343#L612-33 assume !(1 == ~t8_pc~0); 24341#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 24340#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24339#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24338#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24337#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24336#L631-33 assume 1 == ~t9_pc~0; 24334#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24333#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24332#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24331#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24330#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24329#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22732#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24328#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24327#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24326#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23578#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24325#L1072-3 assume !(1 == ~T6_E~0); 24324#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22692#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22693#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22759#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23082#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23000#L1102-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23001#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23394#L1112-3 assume !(1 == ~E_4~0); 22687#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22688#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22734#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22735#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23171#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23149#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22571#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22444#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22761#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 22762#L1447 assume !(0 == start_simulation_~tmp~3#1); 22882#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23369#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23649#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23646#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 23644#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23611#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23610#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23599#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 23595#L1428-2 [2023-11-26 11:54:08,977 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:08,977 INFO L85 PathProgramCache]: Analyzing trace with hash 99525123, now seen corresponding path program 1 times [2023-11-26 11:54:08,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:08,977 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [154469438] [2023-11-26 11:54:08,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:08,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:08,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:09,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:09,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:09,087 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [154469438] [2023-11-26 11:54:09,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [154469438] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:09,087 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:09,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:54:09,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [850665300] [2023-11-26 11:54:09,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:09,088 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:09,089 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:09,089 INFO L85 PathProgramCache]: Analyzing trace with hash 69234191, now seen corresponding path program 1 times [2023-11-26 11:54:09,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:09,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1363197822] [2023-11-26 11:54:09,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:09,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:09,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:09,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:09,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:09,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1363197822] [2023-11-26 11:54:09,158 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1363197822] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:09,158 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:09,158 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:09,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [671218099] [2023-11-26 11:54:09,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:09,159 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:09,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:09,160 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:09,160 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:09,160 INFO L87 Difference]: Start difference. First operand 2161 states and 3183 transitions. cyclomatic complexity: 1024 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:09,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:09,249 INFO L93 Difference]: Finished difference Result 2161 states and 3153 transitions. [2023-11-26 11:54:09,250 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2161 states and 3153 transitions. [2023-11-26 11:54:09,266 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2014 [2023-11-26 11:54:09,286 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2161 states to 2161 states and 3153 transitions. [2023-11-26 11:54:09,286 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2161 [2023-11-26 11:54:09,289 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2161 [2023-11-26 11:54:09,289 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2161 states and 3153 transitions. [2023-11-26 11:54:09,293 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:09,293 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2161 states and 3153 transitions. [2023-11-26 11:54:09,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2161 states and 3153 transitions. [2023-11-26 11:54:09,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2161 to 2161. [2023-11-26 11:54:09,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2161 states, 2161 states have (on average 1.4590467376214715) internal successors, (3153), 2160 states have internal predecessors, (3153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:09,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2161 states to 2161 states and 3153 transitions. [2023-11-26 11:54:09,359 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2161 states and 3153 transitions. [2023-11-26 11:54:09,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:09,360 INFO L428 stractBuchiCegarLoop]: Abstraction has 2161 states and 3153 transitions. [2023-11-26 11:54:09,360 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 11:54:09,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2161 states and 3153 transitions. [2023-11-26 11:54:09,370 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2014 [2023-11-26 11:54:09,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:09,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:09,373 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:09,373 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:09,373 INFO L748 eck$LassoCheckResult]: Stem: 26973#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 26974#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 27800#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27801#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27732#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 27365#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27366#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27705#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27145#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27146#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27624#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27625#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26644#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 26645#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26847#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27249#L939 assume !(0 == ~M_E~0); 27524#L939-2 assume !(0 == ~T1_E~0); 27525#L944-1 assume !(0 == ~T2_E~0); 27287#L949-1 assume !(0 == ~T3_E~0); 27285#L954-1 assume !(0 == ~T4_E~0); 27286#L959-1 assume !(0 == ~T5_E~0); 27746#L964-1 assume !(0 == ~T6_E~0); 26994#L969-1 assume !(0 == ~T7_E~0); 26995#L974-1 assume !(0 == ~T8_E~0); 27691#L979-1 assume !(0 == ~T9_E~0); 27692#L984-1 assume !(0 == ~E_M~0); 27159#L989-1 assume !(0 == ~E_1~0); 27160#L994-1 assume !(0 == ~E_2~0); 27046#L999-1 assume !(0 == ~E_3~0); 27047#L1004-1 assume !(0 == ~E_4~0); 26712#L1009-1 assume !(0 == ~E_5~0); 26713#L1014-1 assume !(0 == ~E_6~0); 27043#L1019-1 assume !(0 == ~E_7~0); 27629#L1024-1 assume !(0 == ~E_8~0); 26966#L1029-1 assume !(0 == ~E_9~0); 26967#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27055#L460 assume 1 == ~m_pc~0; 26633#L461 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26634#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27590#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27718#L1167 assume !(0 != activate_threads_~tmp~1#1); 27270#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27271#L479 assume 1 == ~t1_pc~0; 27250#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27251#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26718#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26719#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 26981#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26826#L498 assume !(1 == ~t2_pc~0); 26827#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27248#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27147#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27148#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27579#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27580#L517 assume 1 == ~t3_pc~0; 27809#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27810#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26651#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26652#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 27015#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27638#L536 assume !(1 == ~t4_pc~0); 27315#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27314#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26812#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26813#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 27309#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27560#L555 assume 1 == ~t5_pc~0; 27561#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27630#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27687#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26970#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 26852#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26750#L574 assume !(1 == ~t6_pc~0); 26751#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27421#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27137#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27138#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 27657#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27839#L593 assume 1 == ~t7_pc~0; 27840#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26987#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27751#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27858#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 27813#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27152#L612 assume !(1 == ~t8_pc~0); 27153#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27610#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27663#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27664#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 27423#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27424#L631 assume 1 == ~t9_pc~0; 27437#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26742#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26743#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27199#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 27253#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27639#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 27640#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28107#L1052-1 assume !(1 == ~T2_E~0); 28106#L1057-1 assume !(1 == ~T3_E~0); 28105#L1062-1 assume !(1 == ~T4_E~0); 26951#L1067-1 assume !(1 == ~T5_E~0); 28104#L1072-1 assume !(1 == ~T6_E~0); 28103#L1077-1 assume !(1 == ~T7_E~0); 28102#L1082-1 assume !(1 == ~T8_E~0); 28101#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28100#L1092-1 assume !(1 == ~E_M~0); 28099#L1097-1 assume !(1 == ~E_1~0); 28098#L1102-1 assume !(1 == ~E_2~0); 28097#L1107-1 assume !(1 == ~E_3~0); 27419#L1112-1 assume !(1 == ~E_4~0); 27420#L1117-1 assume !(1 == ~E_5~0); 27459#L1122-1 assume !(1 == ~E_6~0); 27332#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27333#L1132-1 assume !(1 == ~E_8~0); 27886#L1137-1 assume !(1 == ~E_9~0); 26948#L1142-1 assume { :end_inline_reset_delta_events } true; 26800#L1428-2 [2023-11-26 11:54:09,374 INFO L750 eck$LassoCheckResult]: Loop: 26800#L1428-2 assume !false; 26801#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27475#L914-1 assume !false; 27476#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27614#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26649#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26650#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 27658#L783 assume !(0 != eval_~tmp~0#1); 27659#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27371#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27372#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27869#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28576#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28575#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28574#L954-3 assume !(0 == ~T4_E~0); 28573#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28572#L964-3 assume !(0 == ~T6_E~0); 28571#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28570#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28569#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28568#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28567#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28566#L994-3 assume !(0 == ~E_2~0); 28565#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28564#L1004-3 assume !(0 == ~E_4~0); 28563#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28562#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28561#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28560#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28559#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28558#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28557#L460-33 assume 1 == ~m_pc~0; 28555#L461-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28554#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28553#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28552#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28551#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28550#L479-33 assume !(1 == ~t1_pc~0); 28548#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 28547#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28546#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28545#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28544#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28543#L498-33 assume !(1 == ~t2_pc~0); 28541#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 28540#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28539#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28538#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28537#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28536#L517-33 assume !(1 == ~t3_pc~0); 28534#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 28533#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28532#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28531#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28530#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28529#L536-33 assume !(1 == ~t4_pc~0); 28528#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 28526#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28525#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28524#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28523#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28522#L555-33 assume !(1 == ~t5_pc~0); 28520#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 28519#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28518#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28517#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28516#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28515#L574-33 assume 1 == ~t6_pc~0; 28513#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28512#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28511#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28510#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 28509#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28508#L593-33 assume 1 == ~t7_pc~0; 28506#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28505#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28504#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28503#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28502#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28501#L612-33 assume !(1 == ~t8_pc~0); 28499#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 28498#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28497#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28496#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28495#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28494#L631-33 assume 1 == ~t9_pc~0; 28492#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28491#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28490#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28489#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26893#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26894#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27062#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27745#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27666#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27667#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26786#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26787#L1072-3 assume !(1 == ~T6_E~0); 27189#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27021#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27022#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27088#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27413#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27330#L1102-3 assume !(1 == ~E_2~0); 27331#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27711#L1112-3 assume !(1 == ~E_4~0); 27016#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27017#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27063#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27064#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27506#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27859#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 26898#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26775#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27089#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 27090#L1447 assume !(0 == start_simulation_~tmp~3#1); 27210#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27688#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26926#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26710#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 26711#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26794#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26795#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 27278#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 26800#L1428-2 [2023-11-26 11:54:09,374 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:09,374 INFO L85 PathProgramCache]: Analyzing trace with hash 1976588353, now seen corresponding path program 1 times [2023-11-26 11:54:09,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:09,375 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689088937] [2023-11-26 11:54:09,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:09,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:09,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:09,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:09,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:09,444 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1689088937] [2023-11-26 11:54:09,444 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1689088937] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:09,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:09,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:54:09,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8782480] [2023-11-26 11:54:09,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:09,445 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:09,446 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:09,446 INFO L85 PathProgramCache]: Analyzing trace with hash -237143792, now seen corresponding path program 1 times [2023-11-26 11:54:09,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:09,446 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [606964093] [2023-11-26 11:54:09,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:09,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:09,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:09,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:09,539 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:09,539 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [606964093] [2023-11-26 11:54:09,539 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [606964093] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:09,539 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:09,540 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:54:09,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1808208172] [2023-11-26 11:54:09,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:09,540 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:09,540 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:09,541 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:09,543 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:09,543 INFO L87 Difference]: Start difference. First operand 2161 states and 3153 transitions. cyclomatic complexity: 994 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:09,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:09,680 INFO L93 Difference]: Finished difference Result 4147 states and 5996 transitions. [2023-11-26 11:54:09,680 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4147 states and 5996 transitions. [2023-11-26 11:54:09,705 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3997 [2023-11-26 11:54:09,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4147 states to 4147 states and 5996 transitions. [2023-11-26 11:54:09,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4147 [2023-11-26 11:54:09,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4147 [2023-11-26 11:54:09,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4147 states and 5996 transitions. [2023-11-26 11:54:09,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:09,758 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4147 states and 5996 transitions. [2023-11-26 11:54:09,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4147 states and 5996 transitions. [2023-11-26 11:54:09,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4147 to 4009. [2023-11-26 11:54:09,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4009 states, 4009 states have (on average 1.4477425791968073) internal successors, (5804), 4008 states have internal predecessors, (5804), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:09,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4009 states to 4009 states and 5804 transitions. [2023-11-26 11:54:09,931 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4009 states and 5804 transitions. [2023-11-26 11:54:09,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:09,932 INFO L428 stractBuchiCegarLoop]: Abstraction has 4009 states and 5804 transitions. [2023-11-26 11:54:09,932 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 11:54:09,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4009 states and 5804 transitions. [2023-11-26 11:54:09,951 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3859 [2023-11-26 11:54:09,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:09,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:09,953 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:09,953 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:09,954 INFO L748 eck$LassoCheckResult]: Stem: 33286#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 33287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 34134#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34135#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34052#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 33676#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33677#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34023#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33459#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33460#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33940#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33941#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32958#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32959#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33163#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33563#L939 assume !(0 == ~M_E~0); 33833#L939-2 assume !(0 == ~T1_E~0); 33834#L944-1 assume !(0 == ~T2_E~0); 33600#L949-1 assume !(0 == ~T3_E~0); 33598#L954-1 assume !(0 == ~T4_E~0); 33599#L959-1 assume !(0 == ~T5_E~0); 34067#L964-1 assume !(0 == ~T6_E~0); 33309#L969-1 assume !(0 == ~T7_E~0); 33310#L974-1 assume !(0 == ~T8_E~0); 34007#L979-1 assume !(0 == ~T9_E~0); 34008#L984-1 assume !(0 == ~E_M~0); 33473#L989-1 assume !(0 == ~E_1~0); 33474#L994-1 assume !(0 == ~E_2~0); 33358#L999-1 assume !(0 == ~E_3~0); 33359#L1004-1 assume !(0 == ~E_4~0); 33027#L1009-1 assume !(0 == ~E_5~0); 33028#L1014-1 assume !(0 == ~E_6~0); 33353#L1019-1 assume !(0 == ~E_7~0); 33945#L1024-1 assume !(0 == ~E_8~0); 33281#L1029-1 assume !(0 == ~E_9~0); 33282#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33364#L460 assume !(1 == ~m_pc~0); 34180#L460-2 is_master_triggered_~__retres1~0#1 := 0; 33905#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33906#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 34036#L1167 assume !(0 != activate_threads_~tmp~1#1); 33583#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33584#L479 assume 1 == ~t1_pc~0; 33564#L480 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33565#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33029#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33030#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 33294#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33141#L498 assume !(1 == ~t2_pc~0); 33142#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33562#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33463#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33464#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33892#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33893#L517 assume 1 == ~t3_pc~0; 34149#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34150#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32965#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32966#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 33330#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33950#L536 assume !(1 == ~t4_pc~0); 33628#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33627#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33122#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33123#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 33621#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33869#L555 assume 1 == ~t5_pc~0; 33870#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33946#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34004#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33283#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 33166#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33065#L574 assume !(1 == ~t6_pc~0); 33066#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33732#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33453#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33454#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 33971#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34189#L593 assume 1 == ~t7_pc~0; 34190#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33302#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34070#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34224#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 34153#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33468#L612 assume !(1 == ~t8_pc~0); 33469#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33925#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33976#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33977#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 33734#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33735#L631 assume 1 == ~t9_pc~0; 33750#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33057#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33058#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33514#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 33567#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33953#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 32992#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32993#L1052-1 assume !(1 == ~T2_E~0); 32975#L1057-1 assume !(1 == ~T3_E~0); 32976#L1062-1 assume !(1 == ~T4_E~0); 33267#L1067-1 assume !(1 == ~T5_E~0); 33587#L1072-1 assume !(1 == ~T6_E~0); 33588#L1077-1 assume !(1 == ~T7_E~0); 33156#L1082-1 assume !(1 == ~T8_E~0); 33157#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32952#L1092-1 assume !(1 == ~E_M~0); 32953#L1097-1 assume !(1 == ~E_1~0); 32977#L1102-1 assume !(1 == ~E_2~0); 33798#L1107-1 assume !(1 == ~E_3~0); 33730#L1112-1 assume !(1 == ~E_4~0); 33731#L1117-1 assume !(1 == ~E_5~0); 33771#L1122-1 assume !(1 == ~E_6~0); 34948#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34941#L1132-1 assume !(1 == ~E_8~0); 34934#L1137-1 assume !(1 == ~E_9~0); 34929#L1142-1 assume { :end_inline_reset_delta_events } true; 34923#L1428-2 [2023-11-26 11:54:09,954 INFO L750 eck$LassoCheckResult]: Loop: 34923#L1428-2 assume !false; 34919#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34918#L914-1 assume !false; 34917#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 34915#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 34906#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 34905#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34903#L783 assume !(0 != eval_~tmp~0#1); 34902#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34900#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34897#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34898#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36800#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36799#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36798#L954-3 assume !(0 == ~T4_E~0); 36797#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36796#L964-3 assume !(0 == ~T6_E~0); 36795#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33234#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33235#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34220#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36781#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36772#L994-3 assume !(0 == ~E_2~0); 36771#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36770#L1004-3 assume !(0 == ~E_4~0); 36769#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36768#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36767#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36766#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36765#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36764#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36763#L460-33 assume !(1 == ~m_pc~0); 36762#L460-35 is_master_triggered_~__retres1~0#1 := 0; 36761#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33997#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32956#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32957#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33318#L479-33 assume !(1 == ~t1_pc~0); 33319#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 33284#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33285#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34218#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35608#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35607#L498-33 assume !(1 == ~t2_pc~0); 35444#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 35443#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35442#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35441#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35440#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35438#L517-33 assume !(1 == ~t3_pc~0); 35435#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 35433#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35374#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35368#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35334#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35328#L536-33 assume 1 == ~t4_pc~0; 35321#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35318#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35316#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35314#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35305#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35302#L555-33 assume !(1 == ~t5_pc~0); 35298#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 35295#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35293#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35291#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35289#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35287#L574-33 assume 1 == ~t6_pc~0; 35284#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35283#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35282#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35281#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 35276#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35275#L593-33 assume 1 == ~t7_pc~0; 35272#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35270#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35268#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35266#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35264#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35263#L612-33 assume !(1 == ~t8_pc~0); 35258#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 35256#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35254#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35252#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35247#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34249#L631-33 assume 1 == ~t9_pc~0; 34065#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33802#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35216#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35213#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35211#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35209#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33374#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35206#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35203#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34250#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33101#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33102#L1072-3 assume !(1 == ~T6_E~0); 35194#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35193#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35192#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35191#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35190#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35189#L1102-3 assume !(1 == ~E_2~0); 35188#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35187#L1112-3 assume !(1 == ~E_4~0); 35186#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35185#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35184#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35183#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35182#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35181#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 35176#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 35170#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 35169#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 35138#L1447 assume !(0 == start_simulation_~tmp~3#1); 35137#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 34993#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 34986#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 34955#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 34947#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34940#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34933#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 34928#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 34923#L1428-2 [2023-11-26 11:54:09,955 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:09,955 INFO L85 PathProgramCache]: Analyzing trace with hash -858385022, now seen corresponding path program 1 times [2023-11-26 11:54:09,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:09,955 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130542035] [2023-11-26 11:54:09,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:09,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:09,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:10,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:10,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:10,020 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1130542035] [2023-11-26 11:54:10,020 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1130542035] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:10,020 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:10,021 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:54:10,022 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [305579531] [2023-11-26 11:54:10,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:10,022 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:10,023 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:10,023 INFO L85 PathProgramCache]: Analyzing trace with hash -257587696, now seen corresponding path program 1 times [2023-11-26 11:54:10,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:10,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163887469] [2023-11-26 11:54:10,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:10,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:10,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:10,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:10,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:10,080 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [163887469] [2023-11-26 11:54:10,080 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [163887469] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:10,080 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:10,080 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:10,080 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564378513] [2023-11-26 11:54:10,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:10,081 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:10,081 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:10,082 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:10,082 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:10,082 INFO L87 Difference]: Start difference. First operand 4009 states and 5804 transitions. cyclomatic complexity: 1799 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:10,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:10,217 INFO L93 Difference]: Finished difference Result 7541 states and 10846 transitions. [2023-11-26 11:54:10,218 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7541 states and 10846 transitions. [2023-11-26 11:54:10,261 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7380 [2023-11-26 11:54:10,314 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7541 states to 7541 states and 10846 transitions. [2023-11-26 11:54:10,315 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7541 [2023-11-26 11:54:10,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7541 [2023-11-26 11:54:10,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7541 states and 10846 transitions. [2023-11-26 11:54:10,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:10,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7541 states and 10846 transitions. [2023-11-26 11:54:10,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7541 states and 10846 transitions. [2023-11-26 11:54:10,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7541 to 7533. [2023-11-26 11:54:10,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7533 states, 7533 states have (on average 1.4387362272666933) internal successors, (10838), 7532 states have internal predecessors, (10838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:10,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7533 states to 7533 states and 10838 transitions. [2023-11-26 11:54:10,541 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7533 states and 10838 transitions. [2023-11-26 11:54:10,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:10,542 INFO L428 stractBuchiCegarLoop]: Abstraction has 7533 states and 10838 transitions. [2023-11-26 11:54:10,542 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 11:54:10,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7533 states and 10838 transitions. [2023-11-26 11:54:10,621 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7372 [2023-11-26 11:54:10,621 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:10,622 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:10,624 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:10,624 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:10,625 INFO L748 eck$LassoCheckResult]: Stem: 44843#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 44844#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 45679#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45680#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45600#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 45224#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45225#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45570#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45015#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45016#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45483#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45484#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44515#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44516#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44718#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45119#L939 assume !(0 == ~M_E~0); 45381#L939-2 assume !(0 == ~T1_E~0); 45382#L944-1 assume !(0 == ~T2_E~0); 45154#L949-1 assume !(0 == ~T3_E~0); 45152#L954-1 assume !(0 == ~T4_E~0); 45153#L959-1 assume !(0 == ~T5_E~0); 45617#L964-1 assume !(0 == ~T6_E~0); 44866#L969-1 assume !(0 == ~T7_E~0); 44867#L974-1 assume !(0 == ~T8_E~0); 45555#L979-1 assume !(0 == ~T9_E~0); 45556#L984-1 assume !(0 == ~E_M~0); 45029#L989-1 assume !(0 == ~E_1~0); 45030#L994-1 assume !(0 == ~E_2~0); 44918#L999-1 assume !(0 == ~E_3~0); 44919#L1004-1 assume !(0 == ~E_4~0); 44581#L1009-1 assume !(0 == ~E_5~0); 44582#L1014-1 assume !(0 == ~E_6~0); 44913#L1019-1 assume !(0 == ~E_7~0); 45490#L1024-1 assume !(0 == ~E_8~0); 44838#L1029-1 assume !(0 == ~E_9~0); 44839#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44924#L460 assume !(1 == ~m_pc~0); 45716#L460-2 is_master_triggered_~__retres1~0#1 := 0; 45453#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45454#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45583#L1167 assume !(0 != activate_threads_~tmp~1#1); 45137#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45138#L479 assume !(1 == ~t1_pc~0); 45297#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45298#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44585#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44586#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 44851#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44697#L498 assume !(1 == ~t2_pc~0); 44698#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45118#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45019#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45020#L1183 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45440#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45441#L517 assume 1 == ~t3_pc~0; 45689#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45690#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44522#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44523#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 44888#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45496#L536 assume !(1 == ~t4_pc~0); 45182#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 45181#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44678#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44679#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 45175#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45416#L555 assume 1 == ~t5_pc~0; 45417#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45491#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45553#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44840#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 44721#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44621#L574 assume !(1 == ~t6_pc~0); 44622#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 45279#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45009#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45010#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 45516#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45724#L593 assume 1 == ~t7_pc~0; 45725#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44859#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45620#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45755#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 45695#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45024#L612 assume !(1 == ~t8_pc~0); 45025#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 45473#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45521#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45522#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 45281#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45282#L631 assume 1 == ~t9_pc~0; 45295#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44613#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44614#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45071#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 45120#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45499#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 45500#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46914#L1052-1 assume !(1 == ~T2_E~0); 46913#L1057-1 assume !(1 == ~T3_E~0); 46912#L1062-1 assume !(1 == ~T4_E~0); 44823#L1067-1 assume !(1 == ~T5_E~0); 46911#L1072-1 assume !(1 == ~T6_E~0); 46910#L1077-1 assume !(1 == ~T7_E~0); 46909#L1082-1 assume !(1 == ~T8_E~0); 46908#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46907#L1092-1 assume !(1 == ~E_M~0); 46906#L1097-1 assume !(1 == ~E_1~0); 46905#L1102-1 assume !(1 == ~E_2~0); 46904#L1107-1 assume !(1 == ~E_3~0); 46903#L1112-1 assume !(1 == ~E_4~0); 46902#L1117-1 assume !(1 == ~E_5~0); 46901#L1122-1 assume !(1 == ~E_6~0); 46900#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46899#L1132-1 assume !(1 == ~E_8~0); 46898#L1137-1 assume !(1 == ~E_9~0); 44819#L1142-1 assume { :end_inline_reset_delta_events } true; 44820#L1428-2 [2023-11-26 11:54:10,625 INFO L750 eck$LassoCheckResult]: Loop: 44820#L1428-2 assume !false; 46606#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46602#L914-1 assume !false; 46598#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 46580#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 46570#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 46568#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 46564#L783 assume !(0 != eval_~tmp~0#1); 46562#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46560#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46557#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46558#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47877#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47876#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47875#L954-3 assume !(0 == ~T4_E~0); 47874#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47873#L964-3 assume !(0 == ~T6_E~0); 47872#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47871#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47870#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47869#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47868#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47867#L994-3 assume !(0 == ~E_2~0); 47866#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47865#L1004-3 assume !(0 == ~E_4~0); 47864#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47863#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47862#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47861#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47860#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47859#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47858#L460-33 assume !(1 == ~m_pc~0); 47857#L460-35 is_master_triggered_~__retres1~0#1 := 0; 47856#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47855#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47854#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47853#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47852#L479-33 assume !(1 == ~t1_pc~0); 47851#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 47850#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47849#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47848#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47847#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46475#L498-33 assume !(1 == ~t2_pc~0); 46343#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 46332#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46320#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46311#L1183-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46310#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46309#L517-33 assume !(1 == ~t3_pc~0); 46307#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 46306#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46305#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46304#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46303#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46302#L536-33 assume 1 == ~t4_pc~0; 46300#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46299#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46298#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46297#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46296#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46295#L555-33 assume !(1 == ~t5_pc~0); 46293#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 46292#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46291#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46290#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46289#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46286#L574-33 assume 1 == ~t6_pc~0; 46281#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46282#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47814#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46270#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 46267#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46264#L593-33 assume 1 == ~t7_pc~0; 46260#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46257#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46254#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46250#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46247#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46245#L612-33 assume !(1 == ~t8_pc~0); 46242#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 46240#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46237#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46233#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46230#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46228#L631-33 assume 1 == ~t9_pc~0; 46225#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46223#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46220#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46216#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46213#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46211#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46209#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46206#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46207#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47780#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46199#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47776#L1072-3 assume !(1 == ~T6_E~0); 47774#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47772#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47770#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47768#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47765#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47763#L1102-3 assume !(1 == ~E_2~0); 47761#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47759#L1112-3 assume !(1 == ~E_4~0); 47757#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47755#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47752#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47750#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47748#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47746#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 46144#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 46139#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 45828#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 45829#L1447 assume !(0 == start_simulation_~tmp~3#1); 47536#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 46890#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 46883#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 46880#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 46878#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46876#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46874#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 46872#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 44820#L1428-2 [2023-11-26 11:54:10,626 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:10,626 INFO L85 PathProgramCache]: Analyzing trace with hash -717285501, now seen corresponding path program 1 times [2023-11-26 11:54:10,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:10,627 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [555517611] [2023-11-26 11:54:10,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:10,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:10,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:10,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:10,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:10,725 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [555517611] [2023-11-26 11:54:10,726 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [555517611] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:10,726 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:10,726 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:54:10,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1120178644] [2023-11-26 11:54:10,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:10,727 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:10,728 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:10,728 INFO L85 PathProgramCache]: Analyzing trace with hash -257587696, now seen corresponding path program 2 times [2023-11-26 11:54:10,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:10,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295718288] [2023-11-26 11:54:10,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:10,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:10,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:10,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:10,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:10,784 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295718288] [2023-11-26 11:54:10,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [295718288] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:10,784 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:10,785 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:10,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2097455392] [2023-11-26 11:54:10,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:10,786 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:10,786 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:10,787 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 11:54:10,787 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 11:54:10,788 INFO L87 Difference]: Start difference. First operand 7533 states and 10838 transitions. cyclomatic complexity: 3313 Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:11,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:11,072 INFO L93 Difference]: Finished difference Result 9025 states and 12901 transitions. [2023-11-26 11:54:11,072 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9025 states and 12901 transitions. [2023-11-26 11:54:11,123 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8860 [2023-11-26 11:54:11,159 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9025 states to 9025 states and 12901 transitions. [2023-11-26 11:54:11,159 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9025 [2023-11-26 11:54:11,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9025 [2023-11-26 11:54:11,170 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9025 states and 12901 transitions. [2023-11-26 11:54:11,181 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:11,181 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9025 states and 12901 transitions. [2023-11-26 11:54:11,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9025 states and 12901 transitions. [2023-11-26 11:54:11,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9025 to 7545. [2023-11-26 11:54:11,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7545 states, 7545 states have (on average 1.4273028495692512) internal successors, (10769), 7544 states have internal predecessors, (10769), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:11,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7545 states to 7545 states and 10769 transitions. [2023-11-26 11:54:11,414 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7545 states and 10769 transitions. [2023-11-26 11:54:11,415 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 11:54:11,416 INFO L428 stractBuchiCegarLoop]: Abstraction has 7545 states and 10769 transitions. [2023-11-26 11:54:11,416 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 11:54:11,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7545 states and 10769 transitions. [2023-11-26 11:54:11,447 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7384 [2023-11-26 11:54:11,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:11,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:11,449 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:11,450 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:11,450 INFO L748 eck$LassoCheckResult]: Stem: 61426#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 61427#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 62550#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 62551#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62389#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 61866#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 61867#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62335#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61621#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 61622#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62209#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62210#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 61086#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 61087#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 61294#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61740#L939 assume !(0 == ~M_E~0); 62061#L939-2 assume !(0 == ~T1_E~0); 62062#L944-1 assume !(0 == ~T2_E~0); 61779#L949-1 assume !(0 == ~T3_E~0); 61777#L954-1 assume !(0 == ~T4_E~0); 61778#L959-1 assume !(0 == ~T5_E~0); 62418#L964-1 assume !(0 == ~T6_E~0); 61455#L969-1 assume !(0 == ~T7_E~0); 61456#L974-1 assume !(0 == ~T8_E~0); 62317#L979-1 assume !(0 == ~T9_E~0); 62318#L984-1 assume !(0 == ~E_M~0); 61635#L989-1 assume !(0 == ~E_1~0); 61636#L994-1 assume !(0 == ~E_2~0); 61511#L999-1 assume !(0 == ~E_3~0); 61512#L1004-1 assume !(0 == ~E_4~0); 61152#L1009-1 assume !(0 == ~E_5~0); 61153#L1014-1 assume !(0 == ~E_6~0); 61504#L1019-1 assume !(0 == ~E_7~0); 62219#L1024-1 assume !(0 == ~E_8~0); 61421#L1029-1 assume !(0 == ~E_9~0); 61422#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61518#L460 assume !(1 == ~m_pc~0); 62622#L460-2 is_master_triggered_~__retres1~0#1 := 0; 62164#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62165#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 62358#L1167 assume !(0 != activate_threads_~tmp~1#1); 61760#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61761#L479 assume !(1 == ~t1_pc~0); 61957#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61958#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61156#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 61157#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 61434#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61271#L498 assume !(1 == ~t2_pc~0); 61272#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 61739#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61625#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 61626#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 62149#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62150#L517 assume 1 == ~t3_pc~0; 62573#L518 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62574#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61093#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61094#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 61477#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62231#L536 assume !(1 == ~t4_pc~0); 61812#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 61811#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61251#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61252#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 61805#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62110#L555 assume 1 == ~t5_pc~0; 62111#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62220#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62313#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61423#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 61297#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61194#L574 assume !(1 == ~t6_pc~0); 61195#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 61935#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61613#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61614#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 62262#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62640#L593 assume 1 == ~t7_pc~0; 62641#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61444#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62421#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62734#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 62580#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61630#L612 assume !(1 == ~t8_pc~0); 61631#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 62193#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62269#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62270#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 61938#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61939#L631 assume 1 == ~t9_pc~0; 61955#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 61185#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61186#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61683#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 61741#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62236#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 62237#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61929#L1052-1 assume !(1 == ~T2_E~0); 61103#L1057-1 assume !(1 == ~T3_E~0); 61104#L1062-1 assume !(1 == ~T4_E~0); 61405#L1067-1 assume !(1 == ~T5_E~0); 61764#L1072-1 assume !(1 == ~T6_E~0); 61765#L1077-1 assume !(1 == ~T7_E~0); 61287#L1082-1 assume !(1 == ~T8_E~0); 61288#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 61080#L1092-1 assume !(1 == ~E_M~0); 61081#L1097-1 assume !(1 == ~E_1~0); 61105#L1102-1 assume !(1 == ~E_2~0); 62015#L1107-1 assume !(1 == ~E_3~0); 61933#L1112-1 assume !(1 == ~E_4~0); 61934#L1117-1 assume !(1 == ~E_5~0); 61983#L1122-1 assume !(1 == ~E_6~0); 61831#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 61523#L1132-1 assume !(1 == ~E_8~0); 61524#L1137-1 assume !(1 == ~E_9~0); 62621#L1142-1 assume { :end_inline_reset_delta_events } true; 64507#L1428-2 [2023-11-26 11:54:11,451 INFO L750 eck$LassoCheckResult]: Loop: 64507#L1428-2 assume !false; 64499#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64493#L914-1 assume !false; 64489#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 64442#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 64428#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 64423#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 64416#L783 assume !(0 != eval_~tmp~0#1); 64417#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65820#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65818#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65816#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65814#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 65812#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 63267#L954-3 assume !(0 == ~T4_E~0); 63268#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 63261#L964-3 assume !(0 == ~T6_E~0); 63262#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 63255#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 63256#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 63249#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 63250#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 63243#L994-3 assume !(0 == ~E_2~0); 63244#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 63237#L1004-3 assume !(0 == ~E_4~0); 63238#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 63231#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 63232#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 63225#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 63226#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 63219#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63220#L460-33 assume !(1 == ~m_pc~0); 63213#L460-35 is_master_triggered_~__retres1~0#1 := 0; 63214#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63207#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63208#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 63200#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63201#L479-33 assume !(1 == ~t1_pc~0); 63194#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 63195#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63188#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 63189#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 63182#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63183#L498-33 assume !(1 == ~t2_pc~0); 65228#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 65227#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65226#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63163#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 63160#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63155#L517-33 assume !(1 == ~t3_pc~0); 63156#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 65217#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65215#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65212#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 65210#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65208#L536-33 assume 1 == ~t4_pc~0; 65205#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65203#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65201#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65199#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65196#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65194#L555-33 assume !(1 == ~t5_pc~0); 65191#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 65189#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65187#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65185#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65182#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65180#L574-33 assume 1 == ~t6_pc~0; 65177#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65175#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65173#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65171#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 65168#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65166#L593-33 assume 1 == ~t7_pc~0; 65163#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65161#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65159#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65157#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 65154#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65152#L612-33 assume !(1 == ~t8_pc~0); 65149#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 65147#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65145#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65143#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 65140#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65138#L631-33 assume !(1 == ~t9_pc~0); 65136#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 65133#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65131#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65129#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 65128#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65125#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 61529#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65122#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65120#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65118#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62814#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 65114#L1072-3 assume !(1 == ~T6_E~0); 65111#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65109#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65107#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65105#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65103#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65101#L1102-3 assume !(1 == ~E_2~0); 65098#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65077#L1112-3 assume !(1 == ~E_4~0); 65073#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65069#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 65066#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65061#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65058#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65056#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 64782#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 64775#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 64773#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 64733#L1447 assume !(0 == start_simulation_~tmp~3#1); 64731#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 64715#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 64708#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 64706#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 64704#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 64702#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64700#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 64518#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 64507#L1428-2 [2023-11-26 11:54:11,452 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:11,452 INFO L85 PathProgramCache]: Analyzing trace with hash 1891501957, now seen corresponding path program 1 times [2023-11-26 11:54:11,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:11,453 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1956336998] [2023-11-26 11:54:11,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:11,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:11,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:11,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:11,525 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:11,526 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1956336998] [2023-11-26 11:54:11,526 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1956336998] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:11,526 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:11,526 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:54:11,527 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012934609] [2023-11-26 11:54:11,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:11,527 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:11,527 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:11,528 INFO L85 PathProgramCache]: Analyzing trace with hash -1187450477, now seen corresponding path program 1 times [2023-11-26 11:54:11,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:11,528 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1695059130] [2023-11-26 11:54:11,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:11,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:11,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:11,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:11,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:11,583 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1695059130] [2023-11-26 11:54:11,583 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1695059130] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:11,583 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:11,583 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:11,583 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1374542983] [2023-11-26 11:54:11,584 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:11,584 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:11,584 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:11,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:11,585 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:11,585 INFO L87 Difference]: Start difference. First operand 7545 states and 10769 transitions. cyclomatic complexity: 3232 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:11,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:11,827 INFO L93 Difference]: Finished difference Result 14284 states and 20274 transitions. [2023-11-26 11:54:11,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14284 states and 20274 transitions. [2023-11-26 11:54:11,918 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14100 [2023-11-26 11:54:11,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14284 states to 14284 states and 20274 transitions. [2023-11-26 11:54:11,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14284 [2023-11-26 11:54:12,000 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14284 [2023-11-26 11:54:12,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14284 states and 20274 transitions. [2023-11-26 11:54:12,017 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:12,017 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14284 states and 20274 transitions. [2023-11-26 11:54:12,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14284 states and 20274 transitions. [2023-11-26 11:54:12,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14284 to 14268. [2023-11-26 11:54:12,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14268 states, 14268 states have (on average 1.41982057751612) internal successors, (20258), 14267 states have internal predecessors, (20258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:12,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14268 states to 14268 states and 20258 transitions. [2023-11-26 11:54:12,387 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14268 states and 20258 transitions. [2023-11-26 11:54:12,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:12,389 INFO L428 stractBuchiCegarLoop]: Abstraction has 14268 states and 20258 transitions. [2023-11-26 11:54:12,389 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 11:54:12,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14268 states and 20258 transitions. [2023-11-26 11:54:12,459 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14084 [2023-11-26 11:54:12,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:12,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:12,462 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:12,462 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:12,463 INFO L748 eck$LassoCheckResult]: Stem: 83252#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 83253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 84110#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 84111#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84024#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 83639#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83640#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83992#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 83426#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 83427#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 83904#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 83905#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 82922#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 82923#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 83125#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 83529#L939 assume !(0 == ~M_E~0); 83800#L939-2 assume !(0 == ~T1_E~0); 83801#L944-1 assume !(0 == ~T2_E~0); 83566#L949-1 assume !(0 == ~T3_E~0); 83564#L954-1 assume !(0 == ~T4_E~0); 83565#L959-1 assume !(0 == ~T5_E~0); 84041#L964-1 assume !(0 == ~T6_E~0); 83277#L969-1 assume !(0 == ~T7_E~0); 83278#L974-1 assume !(0 == ~T8_E~0); 83978#L979-1 assume !(0 == ~T9_E~0); 83979#L984-1 assume !(0 == ~E_M~0); 83440#L989-1 assume !(0 == ~E_1~0); 83441#L994-1 assume !(0 == ~E_2~0); 83327#L999-1 assume !(0 == ~E_3~0); 83328#L1004-1 assume !(0 == ~E_4~0); 82988#L1009-1 assume !(0 == ~E_5~0); 82989#L1014-1 assume !(0 == ~E_6~0); 83322#L1019-1 assume !(0 == ~E_7~0); 83913#L1024-1 assume !(0 == ~E_8~0); 83247#L1029-1 assume !(0 == ~E_9~0); 83248#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83333#L460 assume !(1 == ~m_pc~0); 84157#L460-2 is_master_triggered_~__retres1~0#1 := 0; 83872#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83873#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 84009#L1167 assume !(0 != activate_threads_~tmp~1#1); 83549#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83550#L479 assume !(1 == ~t1_pc~0); 83715#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 83716#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82992#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 82993#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 83260#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83103#L498 assume !(1 == ~t2_pc~0); 83104#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 83528#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83430#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 83431#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 83860#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83861#L517 assume !(1 == ~t3_pc~0); 84202#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 84203#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82929#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 82930#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 83299#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83918#L536 assume !(1 == ~t4_pc~0); 83594#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 83593#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83084#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83085#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 83586#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83832#L555 assume 1 == ~t5_pc~0; 83833#L556 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83914#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83976#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 83249#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 83130#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83028#L574 assume !(1 == ~t6_pc~0); 83029#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 83696#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83419#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83420#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 83939#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 84165#L593 assume 1 == ~t7_pc~0; 84166#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 83268#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84044#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84207#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 84128#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 83435#L612 assume !(1 == ~t8_pc~0); 83436#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 83893#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83944#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 83945#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 83699#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83700#L631 assume 1 == ~t9_pc~0; 83713#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 83020#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 83021#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 83480#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 83530#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83921#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 83922#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87302#L1052-1 assume !(1 == ~T2_E~0); 87300#L1057-1 assume !(1 == ~T3_E~0); 87297#L1062-1 assume !(1 == ~T4_E~0); 83232#L1067-1 assume !(1 == ~T5_E~0); 87294#L1072-1 assume !(1 == ~T6_E~0); 87292#L1077-1 assume !(1 == ~T7_E~0); 87290#L1082-1 assume !(1 == ~T8_E~0); 87288#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 87285#L1092-1 assume !(1 == ~E_M~0); 87283#L1097-1 assume !(1 == ~E_1~0); 87281#L1102-1 assume !(1 == ~E_2~0); 87279#L1107-1 assume !(1 == ~E_3~0); 87277#L1112-1 assume !(1 == ~E_4~0); 87275#L1117-1 assume !(1 == ~E_5~0); 87272#L1122-1 assume !(1 == ~E_6~0); 83610#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 83611#L1132-1 assume !(1 == ~E_8~0); 84156#L1137-1 assume !(1 == ~E_9~0); 83228#L1142-1 assume { :end_inline_reset_delta_events } true; 83229#L1428-2 [2023-11-26 11:54:12,464 INFO L750 eck$LassoCheckResult]: Loop: 83229#L1428-2 assume !false; 92235#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 92229#L914-1 assume !false; 92224#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 92083#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 92066#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 92060#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 92053#L783 assume !(0 != eval_~tmp~0#1); 92054#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94234#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 94231#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 94229#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 94227#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 94225#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 94223#L954-3 assume !(0 == ~T4_E~0); 94221#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 94218#L964-3 assume !(0 == ~T6_E~0); 94215#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 94213#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 94211#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 94209#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 94206#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 94189#L994-3 assume !(0 == ~E_2~0); 94188#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 94186#L1004-3 assume !(0 == ~E_4~0); 94184#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 94181#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 94179#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 94177#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 94169#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 94166#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94164#L460-33 assume !(1 == ~m_pc~0); 94162#L460-35 is_master_triggered_~__retres1~0#1 := 0; 94160#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94158#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 94150#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 94148#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94146#L479-33 assume !(1 == ~t1_pc~0); 94144#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 94141#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94138#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 94137#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 94134#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94132#L498-33 assume !(1 == ~t2_pc~0); 94129#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 94121#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94079#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94077#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 94072#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94071#L517-33 assume !(1 == ~t3_pc~0); 94070#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 94069#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94068#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 94067#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 94066#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94065#L536-33 assume !(1 == ~t4_pc~0); 94064#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 94062#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94061#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 94060#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 84064#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82962#L555-33 assume 1 == ~t5_pc~0; 82963#L556-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83730#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83731#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 83761#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 83762#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82933#L574-33 assume 1 == ~t6_pc~0; 82935#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 84000#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83539#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83540#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 83521#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83011#L593-33 assume !(1 == ~t7_pc~0); 83013#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 83487#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84028#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 83821#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 83822#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 83972#L612-33 assume !(1 == ~t8_pc~0); 84145#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 84088#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83741#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 83742#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 83114#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83115#L631-33 assume 1 == ~t9_pc~0; 84039#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 83055#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 83056#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 83321#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 83175#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83176#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 83344#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 84040#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83952#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83953#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83063#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 83064#L1072-3 assume !(1 == ~T6_E~0); 83470#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 83305#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 83306#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 83371#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 83690#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 83608#L1102-3 assume !(1 == ~E_2~0); 83609#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 84004#L1112-3 assume !(1 == ~E_4~0); 83300#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 83301#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 83345#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 83346#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 83779#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 83755#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 83180#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 83052#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 83372#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 83373#L1447 assume !(0 == start_simulation_~tmp~3#1); 83490#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 92494#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 92315#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 92311#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 92309#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 92305#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 92276#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 92254#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 83229#L1428-2 [2023-11-26 11:54:12,465 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:12,465 INFO L85 PathProgramCache]: Analyzing trace with hash -1826536698, now seen corresponding path program 1 times [2023-11-26 11:54:12,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:12,466 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278392387] [2023-11-26 11:54:12,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:12,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:12,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:12,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:12,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:12,624 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1278392387] [2023-11-26 11:54:12,624 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1278392387] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:12,624 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:12,624 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:54:12,624 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [713219460] [2023-11-26 11:54:12,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:12,625 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:12,625 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:12,625 INFO L85 PathProgramCache]: Analyzing trace with hash -1770663085, now seen corresponding path program 1 times [2023-11-26 11:54:12,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:12,626 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1582653092] [2023-11-26 11:54:12,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:12,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:12,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:12,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:12,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:12,701 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1582653092] [2023-11-26 11:54:12,701 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1582653092] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:12,701 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:12,701 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:54:12,701 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [173345413] [2023-11-26 11:54:12,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:12,702 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:12,702 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:12,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:12,703 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:12,703 INFO L87 Difference]: Start difference. First operand 14268 states and 20258 transitions. cyclomatic complexity: 6006 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:12,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:12,946 INFO L93 Difference]: Finished difference Result 27103 states and 38299 transitions. [2023-11-26 11:54:12,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27103 states and 38299 transitions. [2023-11-26 11:54:13,085 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26848 [2023-11-26 11:54:13,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27103 states to 27103 states and 38299 transitions. [2023-11-26 11:54:13,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27103 [2023-11-26 11:54:13,229 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27103 [2023-11-26 11:54:13,229 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27103 states and 38299 transitions. [2023-11-26 11:54:13,256 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:13,256 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27103 states and 38299 transitions. [2023-11-26 11:54:13,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27103 states and 38299 transitions. [2023-11-26 11:54:14,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27103 to 27071. [2023-11-26 11:54:14,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27071 states, 27071 states have (on average 1.4135791067932475) internal successors, (38267), 27070 states have internal predecessors, (38267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:14,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27071 states to 27071 states and 38267 transitions. [2023-11-26 11:54:14,161 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27071 states and 38267 transitions. [2023-11-26 11:54:14,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:14,162 INFO L428 stractBuchiCegarLoop]: Abstraction has 27071 states and 38267 transitions. [2023-11-26 11:54:14,162 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 11:54:14,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27071 states and 38267 transitions. [2023-11-26 11:54:14,378 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26816 [2023-11-26 11:54:14,391 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:14,391 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:14,394 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:14,394 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:14,395 INFO L748 eck$LassoCheckResult]: Stem: 124629#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 124630#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 125504#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 125505#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 125409#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 125026#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 125027#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 125380#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 124811#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 124812#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 125288#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 125289#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 124302#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 124303#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 124507#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 124916#L939 assume !(0 == ~M_E~0); 125188#L939-2 assume !(0 == ~T1_E~0); 125189#L944-1 assume !(0 == ~T2_E~0); 124950#L949-1 assume !(0 == ~T3_E~0); 124948#L954-1 assume !(0 == ~T4_E~0); 124949#L959-1 assume !(0 == ~T5_E~0); 125428#L964-1 assume !(0 == ~T6_E~0); 124655#L969-1 assume !(0 == ~T7_E~0); 124656#L974-1 assume !(0 == ~T8_E~0); 125362#L979-1 assume !(0 == ~T9_E~0); 125363#L984-1 assume !(0 == ~E_M~0); 124825#L989-1 assume !(0 == ~E_1~0); 124826#L994-1 assume !(0 == ~E_2~0); 124707#L999-1 assume !(0 == ~E_3~0); 124708#L1004-1 assume !(0 == ~E_4~0); 124367#L1009-1 assume !(0 == ~E_5~0); 124368#L1014-1 assume !(0 == ~E_6~0); 124702#L1019-1 assume !(0 == ~E_7~0); 125298#L1024-1 assume !(0 == ~E_8~0); 124624#L1029-1 assume !(0 == ~E_9~0); 124625#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124713#L460 assume !(1 == ~m_pc~0); 125548#L460-2 is_master_triggered_~__retres1~0#1 := 0; 125259#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 125260#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 125393#L1167 assume !(0 != activate_threads_~tmp~1#1); 124933#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 124934#L479 assume !(1 == ~t1_pc~0); 125106#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 125107#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 124371#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 124372#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 124637#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 124485#L498 assume !(1 == ~t2_pc~0); 124486#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 124915#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 124815#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 124816#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 125249#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 125250#L517 assume !(1 == ~t3_pc~0); 125590#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 125591#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 124309#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 124310#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 124676#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 125305#L536 assume !(1 == ~t4_pc~0); 124978#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 124977#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 124465#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 124466#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 124970#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 125223#L555 assume !(1 == ~t5_pc~0); 125224#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 125299#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 125360#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 124626#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 124510#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124408#L574 assume !(1 == ~t6_pc~0); 124409#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 125086#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 124804#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 124805#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 125327#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 125558#L593 assume 1 == ~t7_pc~0; 125559#L594 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 124646#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125431#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 125597#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 125520#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 124820#L612 assume !(1 == ~t8_pc~0); 124821#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 125278#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 125332#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 125333#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 125089#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 125090#L631 assume 1 == ~t9_pc~0; 125104#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 124399#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 124400#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 124867#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 124917#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 125309#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 124336#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 124337#L1052-1 assume !(1 == ~T2_E~0); 124319#L1057-1 assume !(1 == ~T3_E~0); 124320#L1062-1 assume !(1 == ~T4_E~0); 124610#L1067-1 assume !(1 == ~T5_E~0); 124937#L1072-1 assume !(1 == ~T6_E~0); 124938#L1077-1 assume !(1 == ~T7_E~0); 124500#L1082-1 assume !(1 == ~T8_E~0); 124501#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 124296#L1092-1 assume !(1 == ~E_M~0); 124297#L1097-1 assume !(1 == ~E_1~0); 124321#L1102-1 assume !(1 == ~E_2~0); 125543#L1107-1 assume !(1 == ~E_3~0); 144519#L1112-1 assume !(1 == ~E_4~0); 125129#L1117-1 assume !(1 == ~E_5~0); 125130#L1122-1 assume !(1 == ~E_6~0); 124995#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 124996#L1132-1 assume !(1 == ~E_8~0); 144509#L1137-1 assume !(1 == ~E_9~0); 124606#L1142-1 assume { :end_inline_reset_delta_events } true; 124607#L1428-2 [2023-11-26 11:54:14,396 INFO L750 eck$LassoCheckResult]: Loop: 124607#L1428-2 assume !false; 145853#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 145851#L914-1 assume !false; 145850#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 145835#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 145823#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 145819#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 140010#L783 assume !(0 != eval_~tmp~0#1); 140011#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 146461#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 146460#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 146459#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 146457#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 146454#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 146452#L954-3 assume !(0 == ~T4_E~0); 146450#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 146448#L964-3 assume !(0 == ~T6_E~0); 146446#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 146444#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 146442#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 146440#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 146438#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 146436#L994-3 assume !(0 == ~E_2~0); 146434#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 146431#L1004-3 assume !(0 == ~E_4~0); 146429#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 146427#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 146425#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 146423#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 146421#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 146419#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 146417#L460-33 assume !(1 == ~m_pc~0); 146415#L460-35 is_master_triggered_~__retres1~0#1 := 0; 146413#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 146411#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 146409#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 146407#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 146404#L479-33 assume !(1 == ~t1_pc~0); 146402#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 146400#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 146398#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 146396#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 146394#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 146392#L498-33 assume !(1 == ~t2_pc~0); 146389#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 146387#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 146385#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 146383#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 146381#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 146378#L517-33 assume !(1 == ~t3_pc~0); 146376#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 146374#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 146372#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 146370#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 146368#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 146365#L536-33 assume 1 == ~t4_pc~0; 146362#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 146360#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 146358#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 146356#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 146354#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 146351#L555-33 assume !(1 == ~t5_pc~0); 146349#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 146347#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 146345#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 146343#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 146341#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 146338#L574-33 assume !(1 == ~t6_pc~0); 146336#L574-35 is_transmit6_triggered_~__retres1~6#1 := 0; 146333#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 146331#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 146329#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 146325#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 146323#L593-33 assume 1 == ~t7_pc~0; 146320#L594-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 146319#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 146316#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 146315#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 146314#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 146313#L612-33 assume !(1 == ~t8_pc~0); 146311#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 146310#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 146309#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 146308#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 146307#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 146306#L631-33 assume 1 == ~t9_pc~0; 146304#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 146303#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 146302#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 146301#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 146300#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 146299#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 145130#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 146298#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 146297#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 146296#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 145121#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 146294#L1072-3 assume !(1 == ~T6_E~0); 146291#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 146289#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 146287#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 146285#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 146283#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 146281#L1102-3 assume !(1 == ~E_2~0); 146279#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 146277#L1112-3 assume !(1 == ~E_4~0); 146275#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 146273#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 146271#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 146268#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 146266#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 146264#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 146252#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 146245#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 146243#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 146207#L1447 assume !(0 == start_simulation_~tmp~3#1); 146205#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 146193#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 146186#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 146184#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 146181#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 146179#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 146177#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 146175#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 124607#L1428-2 [2023-11-26 11:54:14,397 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:14,397 INFO L85 PathProgramCache]: Analyzing trace with hash 367589383, now seen corresponding path program 1 times [2023-11-26 11:54:14,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:14,397 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2133355867] [2023-11-26 11:54:14,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:14,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:14,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:14,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:14,609 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:14,609 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2133355867] [2023-11-26 11:54:14,610 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2133355867] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:14,610 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:14,610 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:14,610 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [899286408] [2023-11-26 11:54:14,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:14,611 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:14,611 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:14,612 INFO L85 PathProgramCache]: Analyzing trace with hash 9745235, now seen corresponding path program 1 times [2023-11-26 11:54:14,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:14,612 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005043311] [2023-11-26 11:54:14,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:14,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:14,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:14,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:14,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:14,682 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1005043311] [2023-11-26 11:54:14,682 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1005043311] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:14,683 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:14,683 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:14,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [597581986] [2023-11-26 11:54:14,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:14,684 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:14,684 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:14,684 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:54:14,684 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:54:14,685 INFO L87 Difference]: Start difference. First operand 27071 states and 38267 transitions. cyclomatic complexity: 11228 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:15,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:15,684 INFO L93 Difference]: Finished difference Result 63666 states and 89420 transitions. [2023-11-26 11:54:15,684 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63666 states and 89420 transitions. [2023-11-26 11:54:16,180 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 63140 [2023-11-26 11:54:16,552 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63666 states to 63666 states and 89420 transitions. [2023-11-26 11:54:16,553 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63666 [2023-11-26 11:54:16,605 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63666 [2023-11-26 11:54:16,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63666 states and 89420 transitions. [2023-11-26 11:54:16,653 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:16,654 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63666 states and 89420 transitions. [2023-11-26 11:54:16,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63666 states and 89420 transitions. [2023-11-26 11:54:17,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63666 to 51390. [2023-11-26 11:54:17,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51390 states, 51390 states have (on average 1.4080560420315236) internal successors, (72360), 51389 states have internal predecessors, (72360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:18,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51390 states to 51390 states and 72360 transitions. [2023-11-26 11:54:18,082 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51390 states and 72360 transitions. [2023-11-26 11:54:18,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:54:18,084 INFO L428 stractBuchiCegarLoop]: Abstraction has 51390 states and 72360 transitions. [2023-11-26 11:54:18,084 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 11:54:18,084 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51390 states and 72360 transitions. [2023-11-26 11:54:18,256 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 51024 [2023-11-26 11:54:18,257 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:18,257 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:18,259 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:18,260 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:18,260 INFO L748 eck$LassoCheckResult]: Stem: 215377#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 215378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 216280#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 216281#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 216183#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 215778#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 215779#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 216153#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 215556#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 215557#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 216061#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 216062#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 215048#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 215049#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 215250#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 215663#L939 assume !(0 == ~M_E~0); 215945#L939-2 assume !(0 == ~T1_E~0); 215946#L944-1 assume !(0 == ~T2_E~0); 215701#L949-1 assume !(0 == ~T3_E~0); 215699#L954-1 assume !(0 == ~T4_E~0); 215700#L959-1 assume !(0 == ~T5_E~0); 216202#L964-1 assume !(0 == ~T6_E~0); 215404#L969-1 assume !(0 == ~T7_E~0); 215405#L974-1 assume !(0 == ~T8_E~0); 216135#L979-1 assume !(0 == ~T9_E~0); 216136#L984-1 assume !(0 == ~E_M~0); 215570#L989-1 assume !(0 == ~E_1~0); 215571#L994-1 assume !(0 == ~E_2~0); 215452#L999-1 assume !(0 == ~E_3~0); 215453#L1004-1 assume !(0 == ~E_4~0); 215114#L1009-1 assume !(0 == ~E_5~0); 215115#L1014-1 assume !(0 == ~E_6~0); 215447#L1019-1 assume !(0 == ~E_7~0); 216070#L1024-1 assume !(0 == ~E_8~0); 215372#L1029-1 assume !(0 == ~E_9~0); 215373#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 215459#L460 assume !(1 == ~m_pc~0); 216339#L460-2 is_master_triggered_~__retres1~0#1 := 0; 216026#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 216027#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 216166#L1167 assume !(0 != activate_threads_~tmp~1#1); 215683#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 215684#L479 assume !(1 == ~t1_pc~0); 215858#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 215859#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 215118#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 215119#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 215385#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 215229#L498 assume !(1 == ~t2_pc~0); 215230#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 215662#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 215560#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 215561#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 216014#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216015#L517 assume !(1 == ~t3_pc~0); 216388#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 216389#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 215055#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 215056#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 215424#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 216078#L536 assume !(1 == ~t4_pc~0); 215731#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 215730#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 215211#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 215212#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 215721#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 215984#L555 assume !(1 == ~t5_pc~0); 215985#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 216071#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216132#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 215374#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 215255#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 215154#L574 assume !(1 == ~t6_pc~0); 215155#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 215840#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 215549#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 215550#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 216099#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 216348#L593 assume !(1 == ~t7_pc~0); 215392#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 215393#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 216207#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 216395#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 216300#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 215565#L612 assume !(1 == ~t8_pc~0); 215566#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 216046#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 216104#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 216105#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 215842#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 215843#L631 assume 1 == ~t9_pc~0; 215856#L632 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 215145#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 215146#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 215610#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 215664#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 216082#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 216083#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 215835#L1052-1 assume !(1 == ~T2_E~0); 215836#L1057-1 assume !(1 == ~T3_E~0); 215357#L1062-1 assume !(1 == ~T4_E~0); 215358#L1067-1 assume !(1 == ~T5_E~0); 215687#L1072-1 assume !(1 == ~T6_E~0); 215688#L1077-1 assume !(1 == ~T7_E~0); 215244#L1082-1 assume !(1 == ~T8_E~0); 215245#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 215042#L1092-1 assume !(1 == ~E_M~0); 215043#L1097-1 assume !(1 == ~E_1~0); 216332#L1102-1 assume !(1 == ~E_2~0); 216333#L1107-1 assume !(1 == ~E_3~0); 215838#L1112-1 assume !(1 == ~E_4~0); 215839#L1117-1 assume !(1 == ~E_5~0); 216418#L1122-1 assume !(1 == ~E_6~0); 216419#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 215464#L1132-1 assume !(1 == ~E_8~0); 215465#L1137-1 assume !(1 == ~E_9~0); 215353#L1142-1 assume { :end_inline_reset_delta_events } true; 215354#L1428-2 [2023-11-26 11:54:18,261 INFO L750 eck$LassoCheckResult]: Loop: 215354#L1428-2 assume !false; 264051#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 264029#L914-1 assume !false; 263781#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 254318#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 254309#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 254306#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 254303#L783 assume !(0 != eval_~tmp~0#1); 254304#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 265350#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 265349#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 265333#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 265311#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 265310#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 265309#L954-3 assume !(0 == ~T4_E~0); 265308#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 265307#L964-3 assume !(0 == ~T6_E~0); 265306#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 265305#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 265303#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 265235#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 265124#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 264876#L994-3 assume !(0 == ~E_2~0); 264875#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 264874#L1004-3 assume !(0 == ~E_4~0); 264873#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 264872#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 264871#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 264870#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 264869#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 264867#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216317#L460-33 assume !(1 == ~m_pc~0); 215998#L460-35 is_master_triggered_~__retres1~0#1 := 0; 215973#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 215974#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 215046#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 215047#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 215408#L479-33 assume !(1 == ~t1_pc~0); 215409#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 265799#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 265797#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 265794#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 265791#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 265787#L498-33 assume !(1 == ~t2_pc~0); 265774#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 215642#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 215643#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 216077#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 265481#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 265480#L517-33 assume !(1 == ~t3_pc~0); 265479#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 265478#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 265477#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 265476#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 265475#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 265474#L536-33 assume 1 == ~t4_pc~0; 265472#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 265471#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 265470#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 265469#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 265467#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 265465#L555-33 assume !(1 == ~t5_pc~0); 265463#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 265460#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 265458#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 265456#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 265454#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 265452#L574-33 assume 1 == ~t6_pc~0; 265449#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 265447#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 265445#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 265443#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 265441#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 265439#L593-33 assume !(1 == ~t7_pc~0); 240970#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 265436#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 265433#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 265431#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 265429#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 265427#L612-33 assume !(1 == ~t8_pc~0); 265424#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 265422#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 265419#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 265417#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 265415#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 265413#L631-33 assume 1 == ~t9_pc~0; 265410#L632-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 265408#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 265405#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 265403#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 265401#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 265399#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 256759#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 265351#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 216112#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 216113#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 256746#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 216369#L1072-3 assume !(1 == ~T6_E~0); 215600#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 215430#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 215431#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 215498#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 215832#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 215745#L1102-3 assume !(1 == ~E_2~0); 215746#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 216161#L1112-3 assume !(1 == ~E_4~0); 215425#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 215426#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 215471#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 215472#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 215924#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 215900#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 215304#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 215178#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 215499#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 215500#L1447 assume !(0 == start_simulation_~tmp~3#1); 215623#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 264767#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 264760#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 264759#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 264758#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 264242#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 264241#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 264240#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 215354#L1428-2 [2023-11-26 11:54:18,262 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:18,262 INFO L85 PathProgramCache]: Analyzing trace with hash -589339000, now seen corresponding path program 1 times [2023-11-26 11:54:18,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:18,262 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499587053] [2023-11-26 11:54:18,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:18,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:18,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:18,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:18,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:18,537 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [499587053] [2023-11-26 11:54:18,537 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [499587053] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:18,537 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:18,537 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:54:18,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [711791387] [2023-11-26 11:54:18,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:18,538 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:18,538 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:18,539 INFO L85 PathProgramCache]: Analyzing trace with hash 1963603987, now seen corresponding path program 1 times [2023-11-26 11:54:18,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:18,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [812593435] [2023-11-26 11:54:18,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:18,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:18,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:18,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:18,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:18,592 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [812593435] [2023-11-26 11:54:18,592 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [812593435] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:18,593 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:18,593 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:18,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1445787094] [2023-11-26 11:54:18,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:18,594 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:18,594 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:18,594 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:18,594 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:18,595 INFO L87 Difference]: Start difference. First operand 51390 states and 72360 transitions. cyclomatic complexity: 21002 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:19,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:19,322 INFO L93 Difference]: Finished difference Result 97613 states and 136917 transitions. [2023-11-26 11:54:19,322 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97613 states and 136917 transitions. [2023-11-26 11:54:19,870 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 96896 [2023-11-26 11:54:20,295 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97613 states to 97613 states and 136917 transitions. [2023-11-26 11:54:20,296 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97613 [2023-11-26 11:54:20,388 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97613 [2023-11-26 11:54:20,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97613 states and 136917 transitions. [2023-11-26 11:54:20,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:20,871 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97613 states and 136917 transitions. [2023-11-26 11:54:20,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97613 states and 136917 transitions. [2023-11-26 11:54:22,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97613 to 97485. [2023-11-26 11:54:22,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97485 states, 97485 states have (on average 1.4031799764066266) internal successors, (136789), 97484 states have internal predecessors, (136789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:22,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97485 states to 97485 states and 136789 transitions. [2023-11-26 11:54:22,370 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97485 states and 136789 transitions. [2023-11-26 11:54:22,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:22,371 INFO L428 stractBuchiCegarLoop]: Abstraction has 97485 states and 136789 transitions. [2023-11-26 11:54:22,371 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 11:54:22,371 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97485 states and 136789 transitions. [2023-11-26 11:54:23,015 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 96768 [2023-11-26 11:54:23,015 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:23,015 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:23,018 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:23,018 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:23,019 INFO L748 eck$LassoCheckResult]: Stem: 364385#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 364386#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 365302#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 365303#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 365199#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 364786#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 364787#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 365168#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 364562#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 364563#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 365068#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 365069#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 364058#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 364059#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 364260#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 364668#L939 assume !(0 == ~M_E~0); 364954#L939-2 assume !(0 == ~T1_E~0); 364955#L944-1 assume !(0 == ~T2_E~0); 364707#L949-1 assume !(0 == ~T3_E~0); 364703#L954-1 assume !(0 == ~T4_E~0); 364704#L959-1 assume !(0 == ~T5_E~0); 365219#L964-1 assume !(0 == ~T6_E~0); 364411#L969-1 assume !(0 == ~T7_E~0); 364412#L974-1 assume !(0 == ~T8_E~0); 365149#L979-1 assume !(0 == ~T9_E~0); 365150#L984-1 assume !(0 == ~E_M~0); 364576#L989-1 assume !(0 == ~E_1~0); 364577#L994-1 assume !(0 == ~E_2~0); 364463#L999-1 assume !(0 == ~E_3~0); 364464#L1004-1 assume !(0 == ~E_4~0); 364123#L1009-1 assume !(0 == ~E_5~0); 364124#L1014-1 assume !(0 == ~E_6~0); 364458#L1019-1 assume !(0 == ~E_7~0); 365076#L1024-1 assume !(0 == ~E_8~0); 364380#L1029-1 assume !(0 == ~E_9~0); 364381#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 364470#L460 assume !(1 == ~m_pc~0); 365356#L460-2 is_master_triggered_~__retres1~0#1 := 0; 365036#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 365037#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 365182#L1167 assume !(0 != activate_threads_~tmp~1#1); 364688#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 364689#L479 assume !(1 == ~t1_pc~0); 364864#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 364865#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 364127#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 364128#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 364393#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 364239#L498 assume !(1 == ~t2_pc~0); 364240#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 364667#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 364566#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 364567#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 365025#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 365026#L517 assume !(1 == ~t3_pc~0); 365420#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 365421#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 364065#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 364066#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 364431#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 365084#L536 assume !(1 == ~t4_pc~0); 364735#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 364734#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 364220#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 364221#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 364727#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 364997#L555 assume !(1 == ~t5_pc~0); 364998#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 365077#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 365147#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 364382#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 364265#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 364162#L574 assume !(1 == ~t6_pc~0); 364163#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 364847#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 364556#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 364557#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 365108#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 365370#L593 assume !(1 == ~t7_pc~0); 364400#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 364401#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 365222#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 365429#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 365323#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 364571#L612 assume !(1 == ~t8_pc~0); 364572#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 365057#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 365113#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 365114#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 364849#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 364850#L631 assume !(1 == ~t9_pc~0); 364919#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 364154#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 364155#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 364617#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 364669#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 365087#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 364092#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 364093#L1052-1 assume !(1 == ~T2_E~0); 364075#L1057-1 assume !(1 == ~T3_E~0); 364076#L1062-1 assume !(1 == ~T4_E~0); 364365#L1067-1 assume !(1 == ~T5_E~0); 364692#L1072-1 assume !(1 == ~T6_E~0); 364693#L1077-1 assume !(1 == ~T7_E~0); 364254#L1082-1 assume !(1 == ~T8_E~0); 364255#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 364052#L1092-1 assume !(1 == ~E_M~0); 364053#L1097-1 assume !(1 == ~E_1~0); 364077#L1102-1 assume !(1 == ~E_2~0); 364913#L1107-1 assume !(1 == ~E_3~0); 364845#L1112-1 assume !(1 == ~E_4~0); 364846#L1117-1 assume !(1 == ~E_5~0); 364885#L1122-1 assume !(1 == ~E_6~0); 364751#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 364475#L1132-1 assume !(1 == ~E_8~0); 364476#L1137-1 assume !(1 == ~E_9~0); 364361#L1142-1 assume { :end_inline_reset_delta_events } true; 364362#L1428-2 [2023-11-26 11:54:23,019 INFO L750 eck$LassoCheckResult]: Loop: 364362#L1428-2 assume !false; 414895#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 414893#L914-1 assume !false; 414891#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 406279#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 406269#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 406268#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 406265#L783 assume !(0 != eval_~tmp~0#1); 406266#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 415270#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 415268#L939-3 assume 0 == ~M_E~0;~M_E~0 := 1; 415266#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 415263#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 415261#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 415259#L954-3 assume !(0 == ~T4_E~0); 415257#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 415255#L964-3 assume !(0 == ~T6_E~0); 415251#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 415249#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 415247#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 415245#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 415242#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 415240#L994-3 assume !(0 == ~E_2~0); 415238#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 415235#L1004-3 assume !(0 == ~E_4~0); 415233#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 415231#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 415229#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 415227#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 415225#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 415222#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 415220#L460-33 assume !(1 == ~m_pc~0); 415218#L460-35 is_master_triggered_~__retres1~0#1 := 0; 415216#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 415214#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 415212#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 415209#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 415207#L479-33 assume !(1 == ~t1_pc~0); 415205#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 415203#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 415201#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 415199#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 415196#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 415194#L498-33 assume !(1 == ~t2_pc~0); 415191#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 415189#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 415187#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 415184#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 415183#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 415180#L517-33 assume !(1 == ~t3_pc~0); 415178#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 415176#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 415174#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 415172#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 415170#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 415167#L536-33 assume 1 == ~t4_pc~0; 415164#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 415162#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 415160#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 415158#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 415156#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 415154#L555-33 assume !(1 == ~t5_pc~0); 415152#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 415150#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 415148#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 415146#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 415145#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 415144#L574-33 assume 1 == ~t6_pc~0; 415142#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 415141#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 415140#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 415139#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 415138#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 415137#L593-33 assume !(1 == ~t7_pc~0); 406818#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 415136#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 415135#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 415134#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 415133#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 415132#L612-33 assume !(1 == ~t8_pc~0); 415130#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 415129#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 415127#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 415125#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 415123#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 415121#L631-33 assume !(1 == ~t9_pc~0); 415119#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 415117#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 415115#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 415113#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 415111#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 415109#L1047-3 assume 1 == ~M_E~0;~M_E~0 := 2; 413655#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 415106#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 415103#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 415101#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 413645#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 415098#L1072-3 assume !(1 == ~T6_E~0); 415096#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 415094#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 415092#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 415090#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 415088#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 415086#L1102-3 assume !(1 == ~E_2~0); 415084#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 415082#L1112-3 assume !(1 == ~E_4~0); 415080#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 415077#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 415075#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 415073#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 415071#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 415069#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 415057#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 415049#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 415047#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 414966#L1447 assume !(0 == start_simulation_~tmp~3#1); 414964#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 414952#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 414945#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 414943#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 414941#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 414939#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 414937#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 414934#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 364362#L1428-2 [2023-11-26 11:54:23,020 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:23,021 INFO L85 PathProgramCache]: Analyzing trace with hash 2033110665, now seen corresponding path program 1 times [2023-11-26 11:54:23,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:23,021 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94146607] [2023-11-26 11:54:23,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:23,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:23,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:23,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:23,099 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:23,099 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94146607] [2023-11-26 11:54:23,099 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [94146607] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:23,099 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:23,099 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:54:23,100 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1583041877] [2023-11-26 11:54:23,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:23,100 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:23,101 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:23,101 INFO L85 PathProgramCache]: Analyzing trace with hash 1006675604, now seen corresponding path program 1 times [2023-11-26 11:54:23,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:23,101 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1329964804] [2023-11-26 11:54:23,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:23,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:23,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:23,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:23,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:23,153 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1329964804] [2023-11-26 11:54:23,153 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1329964804] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:23,153 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:23,154 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:23,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1596157068] [2023-11-26 11:54:23,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:23,154 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:23,155 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:23,155 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:23,155 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:23,155 INFO L87 Difference]: Start difference. First operand 97485 states and 136789 transitions. cyclomatic complexity: 39368 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:23,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:23,704 INFO L93 Difference]: Finished difference Result 144585 states and 203180 transitions. [2023-11-26 11:54:23,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144585 states and 203180 transitions. [2023-11-26 11:54:24,897 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 143584 [2023-11-26 11:54:25,454 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144585 states to 144585 states and 203180 transitions. [2023-11-26 11:54:25,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144585 [2023-11-26 11:54:25,542 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144585 [2023-11-26 11:54:25,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144585 states and 203180 transitions. [2023-11-26 11:54:25,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:25,716 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144585 states and 203180 transitions. [2023-11-26 11:54:25,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144585 states and 203180 transitions. [2023-11-26 11:54:27,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144585 to 98745. [2023-11-26 11:54:27,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98745 states, 98745 states have (on average 1.4088612081624385) internal successors, (139118), 98744 states have internal predecessors, (139118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:27,643 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98745 states to 98745 states and 139118 transitions. [2023-11-26 11:54:27,643 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98745 states and 139118 transitions. [2023-11-26 11:54:27,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:27,644 INFO L428 stractBuchiCegarLoop]: Abstraction has 98745 states and 139118 transitions. [2023-11-26 11:54:27,644 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 11:54:27,644 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98745 states and 139118 transitions. [2023-11-26 11:54:28,464 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98048 [2023-11-26 11:54:28,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:28,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:28,467 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:28,467 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:28,467 INFO L748 eck$LassoCheckResult]: Stem: 606461#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 606462#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 607339#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 607340#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 607245#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 606860#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 606861#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 607218#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 606636#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 606637#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 607128#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 607129#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 606135#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 606136#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 606335#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 606743#L939 assume !(0 == ~M_E~0); 607021#L939-2 assume !(0 == ~T1_E~0); 607022#L944-1 assume !(0 == ~T2_E~0); 606782#L949-1 assume !(0 == ~T3_E~0); 606778#L954-1 assume !(0 == ~T4_E~0); 606779#L959-1 assume !(0 == ~T5_E~0); 607264#L964-1 assume !(0 == ~T6_E~0); 606484#L969-1 assume !(0 == ~T7_E~0); 606485#L974-1 assume !(0 == ~T8_E~0); 607201#L979-1 assume !(0 == ~T9_E~0); 607202#L984-1 assume !(0 == ~E_M~0); 606650#L989-1 assume !(0 == ~E_1~0); 606651#L994-1 assume !(0 == ~E_2~0); 606533#L999-1 assume !(0 == ~E_3~0); 606534#L1004-1 assume !(0 == ~E_4~0); 606202#L1009-1 assume !(0 == ~E_5~0); 606203#L1014-1 assume !(0 == ~E_6~0); 606530#L1019-1 assume !(0 == ~E_7~0); 607134#L1024-1 assume !(0 == ~E_8~0); 606454#L1029-1 assume !(0 == ~E_9~0); 606455#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 606543#L460 assume !(1 == ~m_pc~0); 607380#L460-2 is_master_triggered_~__retres1~0#1 := 0; 607094#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 607095#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 607231#L1167 assume !(0 != activate_threads_~tmp~1#1); 606763#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 606764#L479 assume !(1 == ~t1_pc~0); 606933#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 606934#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 606208#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 606209#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 606469#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 606313#L498 assume !(1 == ~t2_pc~0); 606314#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 606742#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 606638#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 606639#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 607083#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 607084#L517 assume !(1 == ~t3_pc~0); 607423#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 607424#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 606142#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 606143#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 606503#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 607143#L536 assume !(1 == ~t4_pc~0); 606811#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 606810#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 606299#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 606300#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 606804#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 607062#L555 assume !(1 == ~t5_pc~0); 607063#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 607135#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 607195#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 606458#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 606342#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 606239#L574 assume !(1 == ~t6_pc~0); 606240#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 606915#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 606627#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 606628#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 607161#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 607388#L593 assume !(1 == ~t7_pc~0); 606474#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 606475#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 607269#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 607430#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 607355#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 606643#L612 assume !(1 == ~t8_pc~0); 606644#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 607116#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 607166#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 607167#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 606917#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 606918#L631 assume !(1 == ~t9_pc~0); 606989#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 606231#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 606232#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 606688#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 606744#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 607144#L1047 assume !(1 == ~M_E~0); 606171#L1047-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 606172#L1052-1 assume !(1 == ~T2_E~0); 606152#L1057-1 assume !(1 == ~T3_E~0); 606153#L1062-1 assume !(1 == ~T4_E~0); 606440#L1067-1 assume !(1 == ~T5_E~0); 606767#L1072-1 assume !(1 == ~T6_E~0); 606768#L1077-1 assume !(1 == ~T7_E~0); 606328#L1082-1 assume !(1 == ~T8_E~0); 606329#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 606131#L1092-1 assume !(1 == ~E_M~0); 606132#L1097-1 assume !(1 == ~E_1~0); 606154#L1102-1 assume !(1 == ~E_2~0); 606984#L1107-1 assume !(1 == ~E_3~0); 606913#L1112-1 assume !(1 == ~E_4~0); 606914#L1117-1 assume !(1 == ~E_5~0); 606956#L1122-1 assume !(1 == ~E_6~0); 606827#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 606546#L1132-1 assume !(1 == ~E_8~0); 606547#L1137-1 assume !(1 == ~E_9~0); 606438#L1142-1 assume { :end_inline_reset_delta_events } true; 606439#L1428-2 [2023-11-26 11:54:28,468 INFO L750 eck$LassoCheckResult]: Loop: 606439#L1428-2 assume !false; 637830#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 637828#L914-1 assume !false; 637826#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 637584#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 637568#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 637559#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 637553#L783 assume !(0 != eval_~tmp~0#1); 637554#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 653807#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 653804#L939-3 assume !(0 == ~M_E~0); 653801#L939-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 653796#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 653791#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 653786#L954-3 assume !(0 == ~T4_E~0); 653781#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 653776#L964-3 assume !(0 == ~T6_E~0); 653771#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 653766#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 653761#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 653756#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 653751#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 653746#L994-3 assume !(0 == ~E_2~0); 653742#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 653738#L1004-3 assume !(0 == ~E_4~0); 653734#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 653730#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 653725#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 653720#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 653715#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 653710#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 653705#L460-33 assume !(1 == ~m_pc~0); 653700#L460-35 is_master_triggered_~__retres1~0#1 := 0; 653695#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 653690#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 653685#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 653680#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 653675#L479-33 assume !(1 == ~t1_pc~0); 653670#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 653665#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 653660#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 653653#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 653648#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 653642#L498-33 assume !(1 == ~t2_pc~0); 653636#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 653631#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 653624#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 653619#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 653614#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 653609#L517-33 assume !(1 == ~t3_pc~0); 653604#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 653599#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 653594#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 653589#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 653584#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 653579#L536-33 assume !(1 == ~t4_pc~0); 653573#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 653567#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 653562#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 653555#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 653550#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 653544#L555-33 assume !(1 == ~t5_pc~0); 653539#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 653534#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 653529#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 653524#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 653519#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 653514#L574-33 assume 1 == ~t6_pc~0; 653505#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 653499#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 653493#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 653485#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 653479#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 653457#L593-33 assume !(1 == ~t7_pc~0); 653451#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 653446#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 653441#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 653435#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 653430#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 653425#L612-33 assume 1 == ~t8_pc~0; 653419#L613-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 653413#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 653408#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 653402#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 653397#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 653392#L631-33 assume !(1 == ~t9_pc~0); 653386#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 653381#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 653377#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 653374#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 653370#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 653365#L1047-3 assume !(1 == ~M_E~0); 615859#L1047-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 653357#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 653352#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 653348#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 653343#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 653337#L1072-3 assume !(1 == ~T6_E~0); 653331#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 653324#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 653318#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 653312#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 653306#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 653301#L1102-3 assume !(1 == ~E_2~0); 653296#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 653291#L1112-3 assume !(1 == ~E_4~0); 653286#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 653281#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 653276#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 653273#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 653270#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 653268#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 652766#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 652760#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 652749#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 616015#L1447 assume !(0 == start_simulation_~tmp~3#1); 616016#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 637856#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 637849#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 637846#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 637844#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 637842#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 637840#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 637838#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 606439#L1428-2 [2023-11-26 11:54:28,469 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:28,469 INFO L85 PathProgramCache]: Analyzing trace with hash -1839154805, now seen corresponding path program 1 times [2023-11-26 11:54:28,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:28,469 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535571114] [2023-11-26 11:54:28,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:28,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:28,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:28,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:28,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:28,536 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535571114] [2023-11-26 11:54:28,536 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535571114] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:28,536 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:28,536 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 11:54:28,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1833781000] [2023-11-26 11:54:28,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:28,537 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:28,537 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:28,538 INFO L85 PathProgramCache]: Analyzing trace with hash 652314580, now seen corresponding path program 1 times [2023-11-26 11:54:28,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:28,538 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907887830] [2023-11-26 11:54:28,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:28,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:28,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:28,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:28,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:28,610 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1907887830] [2023-11-26 11:54:28,610 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1907887830] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:28,610 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:28,610 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:54:28,610 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [167694958] [2023-11-26 11:54:28,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:28,611 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:28,611 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:28,612 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 11:54:28,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 11:54:28,612 INFO L87 Difference]: Start difference. First operand 98745 states and 139118 transitions. cyclomatic complexity: 40405 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:28,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:28,966 INFO L93 Difference]: Finished difference Result 98745 states and 138732 transitions. [2023-11-26 11:54:28,967 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98745 states and 138732 transitions. [2023-11-26 11:54:29,315 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98048 [2023-11-26 11:54:30,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98745 states to 98745 states and 138732 transitions. [2023-11-26 11:54:30,222 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 98745 [2023-11-26 11:54:30,283 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 98745 [2023-11-26 11:54:30,283 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98745 states and 138732 transitions. [2023-11-26 11:54:30,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:30,378 INFO L218 hiAutomatonCegarLoop]: Abstraction has 98745 states and 138732 transitions. [2023-11-26 11:54:30,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98745 states and 138732 transitions. [2023-11-26 11:54:31,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98745 to 98745. [2023-11-26 11:54:31,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98745 states, 98745 states have (on average 1.4049521494759227) internal successors, (138732), 98744 states have internal predecessors, (138732), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:32,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98745 states to 98745 states and 138732 transitions. [2023-11-26 11:54:32,108 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98745 states and 138732 transitions. [2023-11-26 11:54:32,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 11:54:32,109 INFO L428 stractBuchiCegarLoop]: Abstraction has 98745 states and 138732 transitions. [2023-11-26 11:54:32,110 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-26 11:54:32,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98745 states and 138732 transitions. [2023-11-26 11:54:32,395 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98048 [2023-11-26 11:54:32,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:32,396 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:32,398 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:32,399 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:32,399 INFO L748 eck$LassoCheckResult]: Stem: 803966#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 803967#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 804873#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 804874#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 804774#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 804368#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 804369#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 804740#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 804147#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 804148#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 804649#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 804650#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 803634#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 803635#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 803839#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 804254#L939 assume !(0 == ~M_E~0); 804536#L939-2 assume !(0 == ~T1_E~0); 804537#L944-1 assume !(0 == ~T2_E~0); 804291#L949-1 assume !(0 == ~T3_E~0); 804289#L954-1 assume !(0 == ~T4_E~0); 804290#L959-1 assume !(0 == ~T5_E~0); 804790#L964-1 assume !(0 == ~T6_E~0); 803990#L969-1 assume !(0 == ~T7_E~0); 803991#L974-1 assume !(0 == ~T8_E~0); 804726#L979-1 assume !(0 == ~T9_E~0); 804727#L984-1 assume !(0 == ~E_M~0); 804161#L989-1 assume !(0 == ~E_1~0); 804162#L994-1 assume !(0 == ~E_2~0); 804040#L999-1 assume !(0 == ~E_3~0); 804041#L1004-1 assume !(0 == ~E_4~0); 803700#L1009-1 assume !(0 == ~E_5~0); 803701#L1014-1 assume !(0 == ~E_6~0); 804036#L1019-1 assume !(0 == ~E_7~0); 804657#L1024-1 assume !(0 == ~E_8~0); 803959#L1029-1 assume !(0 == ~E_9~0); 803960#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 804049#L460 assume !(1 == ~m_pc~0); 804918#L460-2 is_master_triggered_~__retres1~0#1 := 0; 804617#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 804618#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 804756#L1167 assume !(0 != activate_threads_~tmp~1#1); 804274#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 804275#L479 assume !(1 == ~t1_pc~0); 804446#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 804447#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 803708#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 803709#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 803975#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 803818#L498 assume !(1 == ~t2_pc~0); 803819#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 804253#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 804149#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 804150#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 804606#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 804607#L517 assume !(1 == ~t3_pc~0); 804969#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 804970#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 803641#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 803642#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 804011#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 804667#L536 assume !(1 == ~t4_pc~0); 804321#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 804320#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 803803#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 803804#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 804315#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 804578#L555 assume !(1 == ~t5_pc~0); 804579#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 804658#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 804721#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 803963#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 803844#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 803740#L574 assume !(1 == ~t6_pc~0); 803741#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 804425#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 804137#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 804138#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 804685#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 804925#L593 assume !(1 == ~t7_pc~0); 803980#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 803981#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 804795#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 804975#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 804888#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 804154#L612 assume !(1 == ~t8_pc~0); 804155#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 804637#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 804690#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 804691#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 804427#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 804428#L631 assume !(1 == ~t9_pc~0); 804503#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 803731#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 803732#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 804200#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 804255#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 804668#L1047 assume !(1 == ~M_E~0); 803670#L1047-2 assume !(1 == ~T1_E~0); 803671#L1052-1 assume !(1 == ~T2_E~0); 803651#L1057-1 assume !(1 == ~T3_E~0); 803652#L1062-1 assume !(1 == ~T4_E~0); 803945#L1067-1 assume !(1 == ~T5_E~0); 804278#L1072-1 assume !(1 == ~T6_E~0); 804279#L1077-1 assume !(1 == ~T7_E~0); 803833#L1082-1 assume !(1 == ~T8_E~0); 803834#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 803630#L1092-1 assume !(1 == ~E_M~0); 803631#L1097-1 assume !(1 == ~E_1~0); 803653#L1102-1 assume !(1 == ~E_2~0); 804498#L1107-1 assume !(1 == ~E_3~0); 804423#L1112-1 assume !(1 == ~E_4~0); 804424#L1117-1 assume !(1 == ~E_5~0); 804468#L1122-1 assume !(1 == ~E_6~0); 804337#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 804052#L1132-1 assume !(1 == ~E_8~0); 804053#L1137-1 assume !(1 == ~E_9~0); 803943#L1142-1 assume { :end_inline_reset_delta_events } true; 803944#L1428-2 [2023-11-26 11:54:32,400 INFO L750 eck$LassoCheckResult]: Loop: 803944#L1428-2 assume !false; 831271#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 831270#L914-1 assume !false; 831269#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 831264#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 831254#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 831252#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 831249#L783 assume !(0 != eval_~tmp~0#1); 831250#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 831682#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 831680#L939-3 assume !(0 == ~M_E~0); 831679#L939-5 assume !(0 == ~T1_E~0); 831678#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 831677#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 831676#L954-3 assume !(0 == ~T4_E~0); 831675#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 831674#L964-3 assume !(0 == ~T6_E~0); 831673#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 831672#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 831671#L979-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 831670#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 831669#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 831667#L994-3 assume !(0 == ~E_2~0); 831665#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 831663#L1004-3 assume !(0 == ~E_4~0); 831661#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 831659#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 831657#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 831655#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 831653#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 831651#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 831649#L460-33 assume !(1 == ~m_pc~0); 831647#L460-35 is_master_triggered_~__retres1~0#1 := 0; 831645#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 831643#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 831641#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 831639#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 831637#L479-33 assume !(1 == ~t1_pc~0); 831635#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 831633#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 831631#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 831630#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 831629#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 831628#L498-33 assume !(1 == ~t2_pc~0); 831626#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 831625#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 831624#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 831623#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 831612#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 831610#L517-33 assume !(1 == ~t3_pc~0); 831608#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 831605#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 831604#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 831602#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 831600#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 831598#L536-33 assume !(1 == ~t4_pc~0); 831596#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 831593#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 831591#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 831589#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 831587#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 831585#L555-33 assume !(1 == ~t5_pc~0); 831583#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 831581#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 831579#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 831576#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 831574#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 831572#L574-33 assume 1 == ~t6_pc~0; 831569#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 831567#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 831565#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 831563#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 831561#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 831559#L593-33 assume !(1 == ~t7_pc~0); 831052#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 831556#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 831554#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 831552#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 831549#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 831547#L612-33 assume !(1 == ~t8_pc~0); 831544#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 831542#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 831540#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 831538#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 831536#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 831534#L631-33 assume !(1 == ~t9_pc~0); 831532#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 831530#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 831528#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 831526#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 831523#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 831521#L1047-3 assume !(1 == ~M_E~0); 831517#L1047-5 assume !(1 == ~T1_E~0); 831515#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 831513#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 831511#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 831510#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 831508#L1072-3 assume !(1 == ~T6_E~0); 831506#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 831504#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 831502#L1087-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 831500#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 831497#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 831495#L1102-3 assume !(1 == ~E_2~0); 831493#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 831491#L1112-3 assume !(1 == ~E_4~0); 831489#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 831487#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 831485#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 831483#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 831481#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 831479#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 831466#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 831459#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 831457#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 831431#L1447 assume !(0 == start_simulation_~tmp~3#1); 831429#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 831417#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 831411#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 831410#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 831408#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 831407#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 831406#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 831405#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 803944#L1428-2 [2023-11-26 11:54:32,401 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:32,401 INFO L85 PathProgramCache]: Analyzing trace with hash 1638164041, now seen corresponding path program 1 times [2023-11-26 11:54:32,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:32,402 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807245416] [2023-11-26 11:54:32,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:32,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:32,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:32,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:32,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:32,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [807245416] [2023-11-26 11:54:32,501 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [807245416] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:32,501 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:32,502 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:32,502 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1710385607] [2023-11-26 11:54:32,502 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:32,502 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:32,503 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:32,503 INFO L85 PathProgramCache]: Analyzing trace with hash 1780741461, now seen corresponding path program 1 times [2023-11-26 11:54:32,503 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:32,503 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313465414] [2023-11-26 11:54:32,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:32,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:32,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:32,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:32,591 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:32,592 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1313465414] [2023-11-26 11:54:32,592 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1313465414] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:32,592 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:32,592 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:54:32,592 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [381139983] [2023-11-26 11:54:32,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:32,593 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:32,593 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:32,594 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:54:32,594 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:54:32,594 INFO L87 Difference]: Start difference. First operand 98745 states and 138732 transitions. cyclomatic complexity: 40019 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:33,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:33,348 INFO L93 Difference]: Finished difference Result 155929 states and 218773 transitions. [2023-11-26 11:54:33,348 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155929 states and 218773 transitions. [2023-11-26 11:54:34,699 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 154848 [2023-11-26 11:54:35,053 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 155929 states to 155929 states and 218773 transitions. [2023-11-26 11:54:35,053 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 155929 [2023-11-26 11:54:35,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 155929 [2023-11-26 11:54:35,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 155929 states and 218773 transitions. [2023-11-26 11:54:35,150 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:35,150 INFO L218 hiAutomatonCegarLoop]: Abstraction has 155929 states and 218773 transitions. [2023-11-26 11:54:35,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155929 states and 218773 transitions. [2023-11-26 11:54:36,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155929 to 110094. [2023-11-26 11:54:36,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110094 states, 110094 states have (on average 1.4070975711664577) internal successors, (154913), 110093 states have internal predecessors, (154913), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:36,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110094 states to 110094 states and 154913 transitions. [2023-11-26 11:54:36,780 INFO L240 hiAutomatonCegarLoop]: Abstraction has 110094 states and 154913 transitions. [2023-11-26 11:54:36,783 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:54:36,783 INFO L428 stractBuchiCegarLoop]: Abstraction has 110094 states and 154913 transitions. [2023-11-26 11:54:36,783 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-26 11:54:36,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110094 states and 154913 transitions. [2023-11-26 11:54:37,092 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 109312 [2023-11-26 11:54:37,092 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:37,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:37,102 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:37,102 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:37,103 INFO L748 eck$LassoCheckResult]: Stem: 1058648#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1058649#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1059577#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1059578#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1059474#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1059057#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1059058#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1059442#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1058826#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1058827#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1059342#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1059343#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1058320#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1058321#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1058521#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1058940#L939 assume !(0 == ~M_E~0); 1059227#L939-2 assume !(0 == ~T1_E~0); 1059228#L944-1 assume !(0 == ~T2_E~0); 1058978#L949-1 assume !(0 == ~T3_E~0); 1058976#L954-1 assume !(0 == ~T4_E~0); 1058977#L959-1 assume !(0 == ~T5_E~0); 1059493#L964-1 assume !(0 == ~T6_E~0); 1058672#L969-1 assume !(0 == ~T7_E~0); 1058673#L974-1 assume !(0 == ~T8_E~0); 1059426#L979-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1059427#L984-1 assume !(0 == ~E_M~0); 1058841#L989-1 assume !(0 == ~E_1~0); 1058842#L994-1 assume !(0 == ~E_2~0); 1058724#L999-1 assume !(0 == ~E_3~0); 1058725#L1004-1 assume !(0 == ~E_4~0); 1058386#L1009-1 assume !(0 == ~E_5~0); 1058387#L1014-1 assume !(0 == ~E_6~0); 1058721#L1019-1 assume !(0 == ~E_7~0); 1059737#L1024-1 assume !(0 == ~E_8~0); 1058641#L1029-1 assume !(0 == ~E_9~0); 1058642#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1058730#L460 assume !(1 == ~m_pc~0); 1059625#L460-2 is_master_triggered_~__retres1~0#1 := 0; 1059309#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1059310#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1059659#L1167 assume !(0 != activate_threads_~tmp~1#1); 1059660#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1059734#L479 assume !(1 == ~t1_pc~0); 1059733#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1059667#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1059668#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1058654#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 1058655#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1058500#L498 assume !(1 == ~t2_pc~0); 1058501#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1058938#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1058939#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1059390#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 1059391#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1059700#L517 assume !(1 == ~t3_pc~0); 1059701#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1059681#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1059682#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1058693#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 1058694#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1059731#L536 assume !(1 == ~t4_pc~0); 1059009#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1059008#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1058486#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1058487#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 1059691#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1059692#L555 assume !(1 == ~t5_pc~0); 1059352#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1059353#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1059460#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1059461#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 1059730#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1059729#L574 assume !(1 == ~t6_pc~0); 1059115#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1059116#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1058818#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1058819#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 1059694#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1059635#L593 assume !(1 == ~t7_pc~0); 1059636#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1059727#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1059688#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1059689#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 1059726#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1058836#L612 assume !(1 == ~t8_pc~0); 1058837#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1059725#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1059392#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1059393#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 1059118#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1059119#L631 assume !(1 == ~t9_pc~0); 1059190#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1059721#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1058884#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1058885#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 1059672#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1059673#L1047 assume !(1 == ~M_E~0); 1058354#L1047-2 assume !(1 == ~T1_E~0); 1058355#L1052-1 assume !(1 == ~T2_E~0); 1058337#L1057-1 assume !(1 == ~T3_E~0); 1058338#L1062-1 assume !(1 == ~T4_E~0); 1059718#L1067-1 assume !(1 == ~T5_E~0); 1058965#L1072-1 assume !(1 == ~T6_E~0); 1058966#L1077-1 assume !(1 == ~T7_E~0); 1059717#L1082-1 assume !(1 == ~T8_E~0); 1059716#L1087-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1058316#L1092-1 assume !(1 == ~E_M~0); 1058317#L1097-1 assume !(1 == ~E_1~0); 1058339#L1102-1 assume !(1 == ~E_2~0); 1059186#L1107-1 assume !(1 == ~E_3~0); 1059112#L1112-1 assume !(1 == ~E_4~0); 1059113#L1117-1 assume !(1 == ~E_5~0); 1059158#L1122-1 assume !(1 == ~E_6~0); 1059025#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1058737#L1132-1 assume !(1 == ~E_8~0); 1058738#L1137-1 assume !(1 == ~E_9~0); 1058621#L1142-1 assume { :end_inline_reset_delta_events } true; 1058622#L1428-2 [2023-11-26 11:54:37,103 INFO L750 eck$LassoCheckResult]: Loop: 1058622#L1428-2 assume !false; 1122418#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1122416#L914-1 assume !false; 1122413#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1122407#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1122397#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1122395#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1122392#L783 assume !(0 != eval_~tmp~0#1); 1122393#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1126197#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1126195#L939-3 assume !(0 == ~M_E~0); 1126193#L939-5 assume !(0 == ~T1_E~0); 1126191#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1126189#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1126187#L954-3 assume !(0 == ~T4_E~0); 1126185#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1126183#L964-3 assume !(0 == ~T6_E~0); 1126182#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1126181#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1126179#L979-3 assume !(0 == ~T9_E~0); 1126178#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1126177#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1126176#L994-3 assume !(0 == ~E_2~0); 1126175#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1126174#L1004-3 assume !(0 == ~E_4~0); 1126173#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1126172#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1126171#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1126170#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1126169#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1126168#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1126167#L460-33 assume !(1 == ~m_pc~0); 1126165#L460-35 is_master_triggered_~__retres1~0#1 := 0; 1126163#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1126161#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1126158#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1126156#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1126154#L479-33 assume !(1 == ~t1_pc~0); 1126152#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1126150#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1126148#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1126145#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1126143#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1126141#L498-33 assume !(1 == ~t2_pc~0); 1126138#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1126136#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1126133#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1126131#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 1126129#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1126127#L517-33 assume !(1 == ~t3_pc~0); 1126125#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1126123#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1126121#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1126119#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1126117#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1126115#L536-33 assume !(1 == ~t4_pc~0); 1126113#L536-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1126110#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1126108#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1126105#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1126103#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1126101#L555-33 assume !(1 == ~t5_pc~0); 1126099#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1126097#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1126095#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1126092#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1126090#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1126088#L574-33 assume 1 == ~t6_pc~0; 1126085#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1126083#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1126081#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1126078#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 1126076#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1126074#L593-33 assume !(1 == ~t7_pc~0); 1105635#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1126071#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1126069#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1126066#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1126064#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1126062#L612-33 assume !(1 == ~t8_pc~0); 1126059#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1126057#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1126055#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1126052#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1126050#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1126048#L631-33 assume !(1 == ~t9_pc~0); 1126046#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1126044#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1126042#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1126040#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1126038#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1126036#L1047-3 assume !(1 == ~M_E~0); 1083146#L1047-5 assume !(1 == ~T1_E~0); 1126033#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1126032#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1126031#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1126029#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1126028#L1072-3 assume !(1 == ~T6_E~0); 1126025#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1126023#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1126021#L1087-3 assume !(1 == ~T9_E~0); 1125685#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1125682#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1125680#L1102-3 assume !(1 == ~E_2~0); 1125678#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1125676#L1112-3 assume !(1 == ~E_4~0); 1125674#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1125672#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1125669#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1125667#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1125665#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1125663#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1125377#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1125371#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1125244#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1082837#L1447 assume !(0 == start_simulation_~tmp~3#1); 1082838#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1122496#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1122489#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1122487#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1122485#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1122483#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1122480#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1122478#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1058622#L1428-2 [2023-11-26 11:54:37,104 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:37,104 INFO L85 PathProgramCache]: Analyzing trace with hash -1773294265, now seen corresponding path program 1 times [2023-11-26 11:54:37,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:37,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019124123] [2023-11-26 11:54:37,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:37,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:37,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:37,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:37,168 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:37,168 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019124123] [2023-11-26 11:54:37,168 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2019124123] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:37,168 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:37,168 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:37,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [851108439] [2023-11-26 11:54:37,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:37,169 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:37,169 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:37,169 INFO L85 PathProgramCache]: Analyzing trace with hash 1765169429, now seen corresponding path program 1 times [2023-11-26 11:54:37,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:37,170 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [531453142] [2023-11-26 11:54:37,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:37,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:37,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:37,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:37,235 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:37,235 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [531453142] [2023-11-26 11:54:37,235 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [531453142] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:37,236 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:37,236 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 11:54:37,236 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1447553049] [2023-11-26 11:54:37,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:37,236 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:37,237 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:37,237 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:54:37,237 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:54:37,237 INFO L87 Difference]: Start difference. First operand 110094 states and 154913 transitions. cyclomatic complexity: 44851 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:38,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:38,411 INFO L93 Difference]: Finished difference Result 144569 states and 202122 transitions. [2023-11-26 11:54:38,412 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144569 states and 202122 transitions. [2023-11-26 11:54:39,019 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 143584 [2023-11-26 11:54:39,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144569 states to 144569 states and 202122 transitions. [2023-11-26 11:54:39,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144569 [2023-11-26 11:54:39,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144569 [2023-11-26 11:54:39,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144569 states and 202122 transitions. [2023-11-26 11:54:39,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 11:54:39,572 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144569 states and 202122 transitions. [2023-11-26 11:54:40,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144569 states and 202122 transitions. [2023-11-26 11:54:41,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144569 to 98745. [2023-11-26 11:54:41,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98745 states, 98745 states have (on average 1.4010430907894071) internal successors, (138346), 98744 states have internal predecessors, (138346), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:41,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98745 states to 98745 states and 138346 transitions. [2023-11-26 11:54:41,632 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98745 states and 138346 transitions. [2023-11-26 11:54:41,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 11:54:41,633 INFO L428 stractBuchiCegarLoop]: Abstraction has 98745 states and 138346 transitions. [2023-11-26 11:54:41,633 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-26 11:54:41,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98745 states and 138346 transitions. [2023-11-26 11:54:41,965 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 98048 [2023-11-26 11:54:41,966 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 11:54:41,966 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 11:54:41,969 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:41,969 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 11:54:41,970 INFO L748 eck$LassoCheckResult]: Stem: 1313322#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1313323#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1314222#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1314223#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1314129#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1313722#L658-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1313723#L663-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1314098#L668-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1313499#L673-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1313500#L678-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1314003#L683-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1314004#L688-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1312995#L693-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1312996#L698-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1313196#L703-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1313609#L939 assume !(0 == ~M_E~0); 1313887#L939-2 assume !(0 == ~T1_E~0); 1313888#L944-1 assume !(0 == ~T2_E~0); 1313649#L949-1 assume !(0 == ~T3_E~0); 1313645#L954-1 assume !(0 == ~T4_E~0); 1313646#L959-1 assume !(0 == ~T5_E~0); 1314152#L964-1 assume !(0 == ~T6_E~0); 1313349#L969-1 assume !(0 == ~T7_E~0); 1313350#L974-1 assume !(0 == ~T8_E~0); 1314081#L979-1 assume !(0 == ~T9_E~0); 1314082#L984-1 assume !(0 == ~E_M~0); 1313513#L989-1 assume !(0 == ~E_1~0); 1313514#L994-1 assume !(0 == ~E_2~0); 1313399#L999-1 assume !(0 == ~E_3~0); 1313400#L1004-1 assume !(0 == ~E_4~0); 1313061#L1009-1 assume !(0 == ~E_5~0); 1313062#L1014-1 assume !(0 == ~E_6~0); 1313395#L1019-1 assume !(0 == ~E_7~0); 1314012#L1024-1 assume !(0 == ~E_8~0); 1313317#L1029-1 assume !(0 == ~E_9~0); 1313318#L1034-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1313406#L460 assume !(1 == ~m_pc~0); 1314274#L460-2 is_master_triggered_~__retres1~0#1 := 0; 1313968#L471 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1313969#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1314111#L1167 assume !(0 != activate_threads_~tmp~1#1); 1313630#L1167-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1313631#L479 assume !(1 == ~t1_pc~0); 1313797#L479-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1313798#L490 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1313065#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1313066#L1175 assume !(0 != activate_threads_~tmp___0~0#1); 1313330#L1175-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1313175#L498 assume !(1 == ~t2_pc~0); 1313176#L498-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1313608#L509 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1313503#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1313504#L1183 assume !(0 != activate_threads_~tmp___1~0#1); 1313956#L1183-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1313957#L517 assume !(1 == ~t3_pc~0); 1314324#L517-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1314325#L528 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1313002#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1313003#L1191 assume !(0 != activate_threads_~tmp___2~0#1); 1313369#L1191-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1314021#L536 assume !(1 == ~t4_pc~0); 1313677#L536-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1313676#L547 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1313156#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1313157#L1199 assume !(0 != activate_threads_~tmp___3~0#1); 1313669#L1199-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1313929#L555 assume !(1 == ~t5_pc~0); 1313930#L555-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1314013#L566 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1314079#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1313319#L1207 assume !(0 != activate_threads_~tmp___4~0#1); 1313201#L1207-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1313100#L574 assume !(1 == ~t6_pc~0); 1313101#L574-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1313780#L585 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1313493#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1313494#L1215 assume !(0 != activate_threads_~tmp___5~0#1); 1314039#L1215-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1314286#L593 assume !(1 == ~t7_pc~0); 1313338#L593-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1313339#L604 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1314155#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1314332#L1223 assume !(0 != activate_threads_~tmp___6~0#1); 1314240#L1223-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1313508#L612 assume !(1 == ~t8_pc~0); 1313509#L612-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1313992#L623 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1314045#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1314046#L1231 assume !(0 != activate_threads_~tmp___7~0#1); 1313782#L1231-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1313783#L631 assume !(1 == ~t9_pc~0); 1313853#L631-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1313092#L642 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1313093#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1313554#L1239 assume !(0 != activate_threads_~tmp___8~0#1); 1313610#L1239-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1314024#L1047 assume !(1 == ~M_E~0); 1313029#L1047-2 assume !(1 == ~T1_E~0); 1313030#L1052-1 assume !(1 == ~T2_E~0); 1313012#L1057-1 assume !(1 == ~T3_E~0); 1313013#L1062-1 assume !(1 == ~T4_E~0); 1313303#L1067-1 assume !(1 == ~T5_E~0); 1313634#L1072-1 assume !(1 == ~T6_E~0); 1313635#L1077-1 assume !(1 == ~T7_E~0); 1313190#L1082-1 assume !(1 == ~T8_E~0); 1313191#L1087-1 assume !(1 == ~T9_E~0); 1312989#L1092-1 assume !(1 == ~E_M~0); 1312990#L1097-1 assume !(1 == ~E_1~0); 1313014#L1102-1 assume !(1 == ~E_2~0); 1313848#L1107-1 assume !(1 == ~E_3~0); 1313778#L1112-1 assume !(1 == ~E_4~0); 1313779#L1117-1 assume !(1 == ~E_5~0); 1313820#L1122-1 assume !(1 == ~E_6~0); 1313693#L1127-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1313411#L1132-1 assume !(1 == ~E_8~0); 1313412#L1137-1 assume !(1 == ~E_9~0); 1313299#L1142-1 assume { :end_inline_reset_delta_events } true; 1313300#L1428-2 [2023-11-26 11:54:41,970 INFO L750 eck$LassoCheckResult]: Loop: 1313300#L1428-2 assume !false; 1343934#L1429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1343932#L914-1 assume !false; 1343930#L779 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1343924#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1343914#L768 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1343912#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1343910#L783 assume !(0 != eval_~tmp~0#1); 1343911#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1359183#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1359179#L939-3 assume !(0 == ~M_E~0); 1359175#L939-5 assume !(0 == ~T1_E~0); 1359172#L944-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1359169#L949-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1359165#L954-3 assume !(0 == ~T4_E~0); 1359161#L959-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1359157#L964-3 assume !(0 == ~T6_E~0); 1359153#L969-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1359149#L974-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1359146#L979-3 assume !(0 == ~T9_E~0); 1359143#L984-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1359140#L989-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1359136#L994-3 assume !(0 == ~E_2~0); 1359132#L999-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1359128#L1004-3 assume !(0 == ~E_4~0); 1359124#L1009-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1359120#L1014-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1359116#L1019-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1359112#L1024-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1359108#L1029-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1359104#L1034-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1359100#L460-33 assume !(1 == ~m_pc~0); 1359096#L460-35 is_master_triggered_~__retres1~0#1 := 0; 1359092#L471-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1359088#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1359084#L1167-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1359080#L1167-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1359076#L479-33 assume !(1 == ~t1_pc~0); 1359072#L479-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1359068#L490-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1359064#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1359060#L1175-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1359056#L1175-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1359050#L498-33 assume !(1 == ~t2_pc~0); 1359045#L498-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1359041#L509-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1359037#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1359033#L1183-33 assume !(0 != activate_threads_~tmp___1~0#1); 1359028#L1183-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1359024#L517-33 assume !(1 == ~t3_pc~0); 1359020#L517-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1359015#L528-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1359011#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1359007#L1191-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1359003#L1191-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1358999#L536-33 assume 1 == ~t4_pc~0; 1358992#L537-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1358988#L547-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1358984#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1358980#L1199-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1358976#L1199-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1358971#L555-33 assume !(1 == ~t5_pc~0); 1358967#L555-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1358963#L566-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1358959#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1358955#L1207-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1358951#L1207-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1358947#L574-33 assume 1 == ~t6_pc~0; 1358941#L575-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1358936#L585-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1358932#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1358928#L1215-33 assume !(0 != activate_threads_~tmp___5~0#1); 1358924#L1215-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1358767#L593-33 assume !(1 == ~t7_pc~0); 1358761#L593-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1358755#L604-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1358749#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1358742#L1223-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1358734#L1223-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1358728#L612-33 assume !(1 == ~t8_pc~0); 1358721#L612-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1358715#L623-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1358709#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1358702#L1231-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1358696#L1231-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1358690#L631-33 assume !(1 == ~t9_pc~0); 1358684#L631-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1358677#L642-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1358671#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1358664#L1239-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1358660#L1239-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1358654#L1047-3 assume !(1 == ~M_E~0); 1332205#L1047-5 assume !(1 == ~T1_E~0); 1358643#L1052-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1358637#L1057-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1358632#L1062-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1358626#L1067-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1358619#L1072-3 assume !(1 == ~T6_E~0); 1358612#L1077-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1358606#L1082-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1358600#L1087-3 assume !(1 == ~T9_E~0); 1358594#L1092-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1358589#L1097-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1358584#L1102-3 assume !(1 == ~E_2~0); 1358579#L1107-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1358574#L1112-3 assume !(1 == ~E_4~0); 1358570#L1117-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1358566#L1122-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1358562#L1127-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1358558#L1132-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1358555#L1137-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1358551#L1142-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1358276#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1358260#L768-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1358095#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1332268#L1447 assume !(0 == start_simulation_~tmp~3#1); 1332269#L1447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1344074#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1344067#L768-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1344065#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1344063#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1344061#L1409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1344059#stop_simulation_returnLabel#1 start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1344057#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1313300#L1428-2 [2023-11-26 11:54:41,971 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:41,971 INFO L85 PathProgramCache]: Analyzing trace with hash 1896329479, now seen corresponding path program 1 times [2023-11-26 11:54:41,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:41,972 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511123433] [2023-11-26 11:54:41,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:41,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:41,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:42,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:42,808 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:42,810 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1511123433] [2023-11-26 11:54:42,810 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1511123433] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:42,810 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:42,810 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:42,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378309197] [2023-11-26 11:54:42,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:42,811 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 11:54:42,812 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 11:54:42,812 INFO L85 PathProgramCache]: Analyzing trace with hash 627540564, now seen corresponding path program 1 times [2023-11-26 11:54:42,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 11:54:42,812 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [660277008] [2023-11-26 11:54:42,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 11:54:42,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 11:54:42,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 11:54:42,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 11:54:42,903 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 11:54:42,904 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [660277008] [2023-11-26 11:54:42,904 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [660277008] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 11:54:42,904 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 11:54:42,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 11:54:42,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1315353196] [2023-11-26 11:54:42,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 11:54:42,905 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 11:54:42,905 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 11:54:42,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 11:54:42,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 11:54:42,906 INFO L87 Difference]: Start difference. First operand 98745 states and 138346 transitions. cyclomatic complexity: 39633 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 11:54:43,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 11:54:43,512 INFO L93 Difference]: Finished difference Result 152689 states and 213107 transitions. [2023-11-26 11:54:43,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 152689 states and 213107 transitions.