./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 10:46:45,367 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 10:46:45,485 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 10:46:45,490 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 10:46:45,490 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 10:46:45,543 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 10:46:45,544 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 10:46:45,545 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 10:46:45,546 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 10:46:45,553 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 10:46:45,554 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 10:46:45,555 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 10:46:45,555 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 10:46:45,557 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 10:46:45,558 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 10:46:45,558 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 10:46:45,558 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 10:46:45,559 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 10:46:45,559 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 10:46:45,560 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 10:46:45,560 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 10:46:45,561 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 10:46:45,561 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 10:46:45,562 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 10:46:45,562 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 10:46:45,562 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 10:46:45,563 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 10:46:45,563 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 10:46:45,563 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 10:46:45,564 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 10:46:45,576 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 10:46:45,576 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 10:46:45,577 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 10:46:45,577 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 10:46:45,577 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 10:46:45,577 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 10:46:45,578 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 10:46:45,578 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 10:46:45,579 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b [2023-11-26 10:46:45,917 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 10:46:45,951 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 10:46:45,954 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 10:46:45,955 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 10:46:45,956 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 10:46:45,957 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2023-11-26 10:46:49,223 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 10:46:49,565 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 10:46:49,569 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2023-11-26 10:46:49,592 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme/data/5502935d5/7ab92895bb0548e19259697a727342de/FLAG589479778 [2023-11-26 10:46:49,612 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme/data/5502935d5/7ab92895bb0548e19259697a727342de [2023-11-26 10:46:49,620 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 10:46:49,622 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 10:46:49,624 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 10:46:49,624 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 10:46:49,630 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 10:46:49,633 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:46:49" (1/1) ... [2023-11-26 10:46:49,634 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@163918c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:49, skipping insertion in model container [2023-11-26 10:46:49,634 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:46:49" (1/1) ... [2023-11-26 10:46:49,706 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 10:46:50,046 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:46:50,072 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 10:46:50,152 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:46:50,177 INFO L206 MainTranslator]: Completed translation [2023-11-26 10:46:50,177 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:50 WrapperNode [2023-11-26 10:46:50,178 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 10:46:50,179 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 10:46:50,179 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 10:46:50,179 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 10:46:50,188 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:50" (1/1) ... [2023-11-26 10:46:50,202 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:50" (1/1) ... [2023-11-26 10:46:50,332 INFO L138 Inliner]: procedures = 48, calls = 63, calls flagged for inlining = 58, calls inlined = 212, statements flattened = 3223 [2023-11-26 10:46:50,347 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 10:46:50,348 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 10:46:50,348 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 10:46:50,349 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 10:46:50,361 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:50" (1/1) ... [2023-11-26 10:46:50,362 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:50" (1/1) ... [2023-11-26 10:46:50,373 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:50" (1/1) ... [2023-11-26 10:46:50,415 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 10:46:50,416 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:50" (1/1) ... [2023-11-26 10:46:50,416 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:50" (1/1) ... [2023-11-26 10:46:50,493 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:50" (1/1) ... [2023-11-26 10:46:50,549 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:50" (1/1) ... [2023-11-26 10:46:50,561 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:50" (1/1) ... [2023-11-26 10:46:50,575 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:50" (1/1) ... [2023-11-26 10:46:50,593 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 10:46:50,596 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 10:46:50,596 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 10:46:50,596 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 10:46:50,597 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:50" (1/1) ... [2023-11-26 10:46:50,604 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 10:46:50,618 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:46:50,636 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 10:46:50,642 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_15da2bc5-f398-4135-b49e-6e6e4c473537/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 10:46:50,680 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 10:46:50,680 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 10:46:50,680 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 10:46:50,681 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 10:46:50,862 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 10:46:50,869 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 10:46:52,973 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 10:46:53,017 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 10:46:53,017 INFO L309 CfgBuilder]: Removed 13 assume(true) statements. [2023-11-26 10:46:53,019 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:46:53 BoogieIcfgContainer [2023-11-26 10:46:53,020 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 10:46:53,021 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 10:46:53,021 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 10:46:53,025 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 10:46:53,026 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:46:53,026 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 10:46:49" (1/3) ... [2023-11-26 10:46:53,027 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@68f0b452 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:46:53, skipping insertion in model container [2023-11-26 10:46:53,027 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:46:53,029 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:46:50" (2/3) ... [2023-11-26 10:46:53,031 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@68f0b452 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:46:53, skipping insertion in model container [2023-11-26 10:46:53,032 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:46:53,032 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:46:53" (3/3) ... [2023-11-26 10:46:53,033 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-1.c [2023-11-26 10:46:53,124 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 10:46:53,124 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 10:46:53,125 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 10:46:53,125 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 10:46:53,125 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 10:46:53,125 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 10:46:53,125 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 10:46:53,126 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 10:46:53,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1387 states, 1386 states have (on average 1.5021645021645023) internal successors, (2082), 1386 states have internal predecessors, (2082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:53,221 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1244 [2023-11-26 10:46:53,221 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:46:53,222 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:46:53,241 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:53,242 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:53,242 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 10:46:53,246 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1387 states, 1386 states have (on average 1.5021645021645023) internal successors, (2082), 1386 states have internal predecessors, (2082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:53,267 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1244 [2023-11-26 10:46:53,268 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:46:53,268 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:46:53,274 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:53,275 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:53,286 INFO L748 eck$LassoCheckResult]: Stem: 205#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1274#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1023#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1268#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1171#L731true assume !(1 == ~m_i~0);~m_st~0 := 2; 1034#L731-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 940#L736-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1010#L741-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1328#L746-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 169#L751-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 229#L756-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 850#L761-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 386#L766-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 335#L771-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 170#L776-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10#L781-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54#L1036true assume !(0 == ~M_E~0); 1043#L1036-2true assume !(0 == ~T1_E~0); 620#L1041-1true assume !(0 == ~T2_E~0); 982#L1046-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 193#L1051-1true assume !(0 == ~T4_E~0); 759#L1056-1true assume !(0 == ~T5_E~0); 814#L1061-1true assume !(0 == ~T6_E~0); 137#L1066-1true assume !(0 == ~T7_E~0); 1166#L1071-1true assume !(0 == ~T8_E~0); 739#L1076-1true assume !(0 == ~T9_E~0); 83#L1081-1true assume !(0 == ~T10_E~0); 300#L1086-1true assume 0 == ~E_M~0;~E_M~0 := 1; 1183#L1091-1true assume !(0 == ~E_1~0); 1045#L1096-1true assume !(0 == ~E_2~0); 1278#L1101-1true assume !(0 == ~E_3~0); 344#L1106-1true assume !(0 == ~E_4~0); 559#L1111-1true assume !(0 == ~E_5~0); 462#L1116-1true assume !(0 == ~E_6~0); 1105#L1121-1true assume !(0 == ~E_7~0); 338#L1126-1true assume 0 == ~E_8~0;~E_8~0 := 1; 539#L1131-1true assume !(0 == ~E_9~0); 629#L1136-1true assume !(0 == ~E_10~0); 905#L1141-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 799#L514true assume 1 == ~m_pc~0; 749#L515true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 348#L525true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 877#is_master_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1117#L1285true assume !(0 != activate_threads_~tmp~1#1); 1204#L1285-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 145#L533true assume !(1 == ~t1_pc~0); 1059#L533-2true is_transmit1_triggered_~__retres1~1#1 := 0; 506#L544true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 919#L1293true assume !(0 != activate_threads_~tmp___0~0#1); 653#L1293-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 909#L552true assume 1 == ~t2_pc~0; 269#L553true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 941#L563true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 340#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 986#L1301true assume !(0 != activate_threads_~tmp___1~0#1); 357#L1301-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 518#L571true assume 1 == ~t3_pc~0; 503#L572true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 691#L582true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 660#L1309true assume !(0 != activate_threads_~tmp___2~0#1); 465#L1309-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48#L590true assume !(1 == ~t4_pc~0); 517#L590-2true is_transmit4_triggered_~__retres1~4#1 := 0; 1300#L601true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1129#L1317true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 676#L1317-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 463#L609true assume 1 == ~t5_pc~0; 1290#L610true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1114#L620true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 881#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1388#L1325true assume !(0 != activate_threads_~tmp___4~0#1); 457#L1325-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1287#L628true assume !(1 == ~t6_pc~0); 540#L628-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1264#L639true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 324#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1194#L1333true assume !(0 != activate_threads_~tmp___5~0#1); 715#L1333-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 859#L647true assume 1 == ~t7_pc~0; 345#L648true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 896#L658true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1294#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 346#L1341true assume !(0 != activate_threads_~tmp___6~0#1); 1257#L1341-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1230#L666true assume !(1 == ~t8_pc~0); 797#L666-2true is_transmit8_triggered_~__retres1~8#1 := 0; 356#L677true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 800#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 482#L1349true assume !(0 != activate_threads_~tmp___7~0#1); 298#L1349-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1147#L685true assume 1 == ~t9_pc~0; 1310#L686true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 920#L696true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 381#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 316#L1357true assume !(0 != activate_threads_~tmp___8~0#1); 1017#L1357-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 599#L704true assume !(1 == ~t10_pc~0); 1102#L704-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1052#L715true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 495#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 71#L1365true assume !(0 != activate_threads_~tmp___9~0#1); 197#L1365-2true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 704#L1154true assume !(1 == ~M_E~0); 1190#L1154-2true assume !(1 == ~T1_E~0); 182#L1159-1true assume !(1 == ~T2_E~0); 1320#L1164-1true assume !(1 == ~T3_E~0); 480#L1169-1true assume !(1 == ~T4_E~0); 382#L1174-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 253#L1179-1true assume !(1 == ~T6_E~0); 174#L1184-1true assume !(1 == ~T7_E~0); 217#L1189-1true assume !(1 == ~T8_E~0); 289#L1194-1true assume !(1 == ~T9_E~0); 1368#L1199-1true assume !(1 == ~T10_E~0); 263#L1204-1true assume !(1 == ~E_M~0); 1225#L1209-1true assume !(1 == ~E_1~0); 672#L1214-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1318#L1219-1true assume !(1 == ~E_3~0); 1200#L1224-1true assume !(1 == ~E_4~0); 500#L1229-1true assume !(1 == ~E_5~0); 117#L1234-1true assume !(1 == ~E_6~0); 786#L1239-1true assume !(1 == ~E_7~0); 143#L1244-1true assume !(1 == ~E_8~0); 836#L1249-1true assume !(1 == ~E_9~0); 747#L1254-1true assume 1 == ~E_10~0;~E_10~0 := 2; 68#L1259-1true assume { :end_inline_reset_delta_events } true; 1179#L1565-2true [2023-11-26 10:46:53,290 INFO L750 eck$LassoCheckResult]: Loop: 1179#L1565-2true assume !false; 680#L1566true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1073#L1011-1true assume false; 811#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 512#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 754#L1036-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1080#L1036-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1316#L1041-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 844#L1046-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1201#L1051-3true assume !(0 == ~T4_E~0); 755#L1056-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 191#L1061-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 192#L1066-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1333#L1071-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1083#L1076-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 65#L1081-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1247#L1086-3true assume 0 == ~E_M~0;~E_M~0 := 1; 88#L1091-3true assume !(0 == ~E_1~0); 1157#L1096-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1012#L1101-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1079#L1106-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1134#L1111-3true assume 0 == ~E_5~0;~E_5~0 := 1; 998#L1116-3true assume 0 == ~E_6~0;~E_6~0 := 1; 609#L1121-3true assume 0 == ~E_7~0;~E_7~0 := 1; 944#L1126-3true assume 0 == ~E_8~0;~E_8~0 := 1; 870#L1131-3true assume !(0 == ~E_9~0); 1311#L1136-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1284#L1141-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 613#L514-36true assume 1 == ~m_pc~0; 1362#L515-12true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 283#L525-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1026#is_master_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 651#L1285-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 221#L1285-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 400#L533-36true assume !(1 == ~t1_pc~0); 751#L533-38true is_transmit1_triggered_~__retres1~1#1 := 0; 969#L544-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1024#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 690#L1293-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 516#L1293-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1377#L552-36true assume !(1 == ~t2_pc~0); 1349#L552-38true is_transmit2_triggered_~__retres1~2#1 := 0; 558#L563-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 857#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1188#L1301-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 203#L1301-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 847#L571-36true assume !(1 == ~t3_pc~0); 975#L571-38true is_transmit3_triggered_~__retres1~3#1 := 0; 254#L582-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 378#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 842#L1309-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 887#L1309-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 238#L590-36true assume 1 == ~t4_pc~0; 705#L591-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1027#L601-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 525#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1323#L1317-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 807#L1317-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1070#L609-36true assume !(1 == ~t5_pc~0); 1340#L609-38true is_transmit5_triggered_~__retres1~5#1 := 0; 520#L620-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 978#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 876#L1325-36true assume !(0 != activate_threads_~tmp___4~0#1); 580#L1325-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 435#L628-36true assume !(1 == ~t6_pc~0); 1144#L628-38true is_transmit6_triggered_~__retres1~6#1 := 0; 1148#L639-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 364#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 760#L1333-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 614#L1333-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1111#L647-36true assume !(1 == ~t7_pc~0); 678#L647-38true is_transmit7_triggered_~__retres1~7#1 := 0; 77#L658-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 948#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85#L1341-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 706#L1341-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 779#L666-36true assume 1 == ~t8_pc~0; 181#L667-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1209#L677-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 604#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1222#L1349-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 268#L1349-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 595#L685-36true assume !(1 == ~t9_pc~0); 132#L685-38true is_transmit9_triggered_~__retres1~9#1 := 0; 888#L696-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 403#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1277#L1357-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 354#L1357-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 363#L704-36true assume !(1 == ~t10_pc~0); 266#L704-38true is_transmit10_triggered_~__retres1~10#1 := 0; 1163#L715-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 305#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 732#L1365-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 139#L1365-38true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1361#L1154-3true assume 1 == ~M_E~0;~M_E~0 := 2; 981#L1154-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 769#L1159-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1335#L1164-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1107#L1169-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 309#L1174-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1196#L1179-3true assume !(1 == ~T6_E~0); 923#L1184-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 78#L1189-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 929#L1194-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 274#L1199-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1371#L1204-3true assume 1 == ~E_M~0;~E_M~0 := 2; 497#L1209-3true assume 1 == ~E_1~0;~E_1~0 := 2; 17#L1214-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1021#L1219-3true assume !(1 == ~E_3~0); 658#L1224-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1382#L1229-3true assume 1 == ~E_5~0;~E_5~0 := 2; 679#L1234-3true assume 1 == ~E_6~0;~E_6~0 := 2; 144#L1239-3true assume 1 == ~E_7~0;~E_7~0 := 2; 535#L1244-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1086#L1249-3true assume 1 == ~E_9~0;~E_9~0 := 2; 999#L1254-3true assume 1 == ~E_10~0;~E_10~0 := 2; 664#L1259-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 763#L794-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1296#L851-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 297#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 618#L1584true assume !(0 == start_simulation_~tmp~3#1); 643#L1584-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 150#L794-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 943#L851-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 32#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 342#L1539true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 987#L1546true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 528#stop_simulation_returnLabel#1true start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1174#L1597true assume !(0 != start_simulation_~tmp___0~1#1); 1179#L1565-2true [2023-11-26 10:46:53,298 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:53,298 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2023-11-26 10:46:53,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:53,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296751889] [2023-11-26 10:46:53,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:53,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:53,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:53,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:53,804 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:53,805 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296751889] [2023-11-26 10:46:53,806 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1296751889] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:53,806 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:53,806 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:53,808 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [506246186] [2023-11-26 10:46:53,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:53,815 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:46:53,817 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:53,817 INFO L85 PathProgramCache]: Analyzing trace with hash 1329563516, now seen corresponding path program 1 times [2023-11-26 10:46:53,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:53,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018541911] [2023-11-26 10:46:53,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:53,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:53,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:53,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:53,931 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:53,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018541911] [2023-11-26 10:46:53,932 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2018541911] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:53,932 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:53,932 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:46:53,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1343404770] [2023-11-26 10:46:53,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:53,934 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:46:53,940 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:46:53,991 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:46:53,991 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:46:53,996 INFO L87 Difference]: Start difference. First operand has 1387 states, 1386 states have (on average 1.5021645021645023) internal successors, (2082), 1386 states have internal predecessors, (2082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:54,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:46:54,092 INFO L93 Difference]: Finished difference Result 1383 states and 2049 transitions. [2023-11-26 10:46:54,094 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1383 states and 2049 transitions. [2023-11-26 10:46:54,110 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:54,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1383 states to 1377 states and 2043 transitions. [2023-11-26 10:46:54,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-26 10:46:54,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-26 10:46:54,133 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2043 transitions. [2023-11-26 10:46:54,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:46:54,142 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2043 transitions. [2023-11-26 10:46:54,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2043 transitions. [2023-11-26 10:46:54,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-26 10:46:54,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4836601307189543) internal successors, (2043), 1376 states have internal predecessors, (2043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:54,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2043 transitions. [2023-11-26 10:46:54,244 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2043 transitions. [2023-11-26 10:46:54,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:46:54,251 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2043 transitions. [2023-11-26 10:46:54,252 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 10:46:54,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2043 transitions. [2023-11-26 10:46:54,266 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:54,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:46:54,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:46:54,277 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:54,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:54,279 INFO L748 eck$LassoCheckResult]: Stem: 3197#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3198#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4074#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4075#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4137#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4078#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4038#L736-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4039#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4067#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3136#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3137#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3242#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3487#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3413#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3138#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2797#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2798#L1036 assume !(0 == ~M_E~0); 2895#L1036-2 assume !(0 == ~T1_E~0); 3800#L1041-1 assume !(0 == ~T2_E~0); 3801#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3172#L1051-1 assume !(0 == ~T4_E~0); 3173#L1056-1 assume !(0 == ~T5_E~0); 3929#L1061-1 assume !(0 == ~T6_E~0); 3067#L1066-1 assume !(0 == ~T7_E~0); 3068#L1071-1 assume !(0 == ~T8_E~0); 3911#L1076-1 assume !(0 == ~T9_E~0); 2957#L1081-1 assume !(0 == ~T10_E~0); 2958#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3358#L1091-1 assume !(0 == ~E_1~0); 4086#L1096-1 assume !(0 == ~E_2~0); 4087#L1101-1 assume !(0 == ~E_3~0); 3426#L1106-1 assume !(0 == ~E_4~0); 3427#L1111-1 assume !(0 == ~E_5~0); 3591#L1116-1 assume !(0 == ~E_6~0); 3592#L1121-1 assume !(0 == ~E_7~0); 3417#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3418#L1131-1 assume !(0 == ~E_9~0); 3693#L1136-1 assume !(0 == ~E_10~0); 3808#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3957#L514 assume 1 == ~m_pc~0; 3922#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3435#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3436#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4009#L1285 assume !(0 != activate_threads_~tmp~1#1); 4122#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3086#L533 assume !(1 == ~t1_pc~0); 3087#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3606#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2852#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2853#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3829#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3830#L552 assume 1 == ~t2_pc~0; 3307#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3308#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3421#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3422#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3453#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3454#L571 assume 1 == ~t3_pc~0; 3646#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3647#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2795#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2796#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3596#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2881#L590 assume !(1 == ~t4_pc~0); 2882#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3654#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2975#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2976#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3857#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3593#L609 assume 1 == ~t5_pc~0; 3594#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4119#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4011#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4012#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3585#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3586#L628 assume !(1 == ~t6_pc~0); 3518#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3517#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3395#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3396#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3891#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3892#L647 assume 1 == ~t7_pc~0; 3428#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3429#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4020#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3433#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3434#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4148#L666 assume !(1 == ~t8_pc~0); 3219#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3220#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3447#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3618#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3356#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3357#L685 assume 1 == ~t9_pc~0; 4127#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4028#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3481#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3385#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3386#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3771#L704 assume !(1 == ~t10_pc~0); 3375#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3374#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3636#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2929#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 2930#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3181#L1154 assume !(1 == ~M_E~0); 3879#L1154-2 assume !(1 == ~T1_E~0); 3155#L1159-1 assume !(1 == ~T2_E~0); 3156#L1164-1 assume !(1 == ~T3_E~0); 3615#L1169-1 assume !(1 == ~T4_E~0); 3482#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3286#L1179-1 assume !(1 == ~T6_E~0); 3140#L1184-1 assume !(1 == ~T7_E~0); 3141#L1189-1 assume !(1 == ~T8_E~0); 3217#L1194-1 assume !(1 == ~T9_E~0); 3344#L1199-1 assume !(1 == ~T10_E~0); 3298#L1204-1 assume !(1 == ~E_M~0); 3299#L1209-1 assume !(1 == ~E_1~0); 3852#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3853#L1219-1 assume !(1 == ~E_3~0); 4141#L1224-1 assume !(1 == ~E_4~0); 3640#L1229-1 assume !(1 == ~E_5~0); 3024#L1234-1 assume !(1 == ~E_6~0); 3025#L1239-1 assume !(1 == ~E_7~0); 3082#L1244-1 assume !(1 == ~E_8~0); 3083#L1249-1 assume !(1 == ~E_9~0); 3920#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2924#L1259-1 assume { :end_inline_reset_delta_events } true; 2925#L1565-2 [2023-11-26 10:46:54,283 INFO L750 eck$LassoCheckResult]: Loop: 2925#L1565-2 assume !false; 3858#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3624#L1011-1 assume !false; 3587#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3360#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3123#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3460#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3152#L866 assume !(0 != eval_~tmp~0#1); 3154#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3657#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3658#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3924#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4103#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3985#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3986#L1051-3 assume !(0 == ~T4_E~0); 3925#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3169#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3170#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3171#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4105#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2916#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2917#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2971#L1091-3 assume !(0 == ~E_1~0); 2972#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4069#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4070#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4102#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4061#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3786#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3787#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4000#L1131-3 assume !(0 == ~E_9~0); 4001#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4153#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3789#L514-36 assume !(1 == ~m_pc~0); 3498#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3333#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3334#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3828#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3226#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3227#L533-36 assume 1 == ~t1_pc~0; 3507#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3603#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4051#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3866#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3663#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3664#L552-36 assume 1 == ~t2_pc~0; 3221#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3222#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3722#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3993#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3193#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3194#L571-36 assume 1 == ~t3_pc~0; 3581#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3284#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3285#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3477#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3984#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3253#L590-36 assume 1 == ~t4_pc~0; 3254#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3880#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3673#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3674#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3963#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3964#L609-36 assume 1 == ~t5_pc~0; 3841#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3666#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3667#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4008#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 3750#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3557#L628-36 assume 1 == ~t6_pc~0; 3405#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3406#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3456#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3457#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3791#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3792#L647-36 assume 1 == ~t7_pc~0; 3715#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2943#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2944#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2961#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2962#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3881#L666-36 assume 1 == ~t8_pc~0; 3149#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3150#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3779#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3780#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3304#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3305#L685-36 assume 1 == ~t9_pc~0; 3766#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3056#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3511#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3512#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3444#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3445#L704-36 assume 1 == ~t10_pc~0; 3043#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3044#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3365#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3366#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3071#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3072#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4055#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3938#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3939#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4116#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3371#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3372#L1179-3 assume !(1 == ~T6_E~0); 4030#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2945#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2946#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3315#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3316#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3635#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2813#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2814#L1219-3 assume !(1 == ~E_3~0); 3835#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3836#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3856#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3084#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3085#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3686#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4062#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3839#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3840#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2893#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3353#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3354#L1584 assume !(0 == start_simulation_~tmp~3#1); 3797#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3098#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2793#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2845#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2846#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3423#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3679#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3680#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 2925#L1565-2 [2023-11-26 10:46:54,286 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:54,286 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2023-11-26 10:46:54,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:54,287 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111451139] [2023-11-26 10:46:54,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:54,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:54,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:54,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:54,437 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:54,437 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111451139] [2023-11-26 10:46:54,438 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2111451139] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:54,438 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:54,438 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:54,438 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1444839675] [2023-11-26 10:46:54,439 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:54,440 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:46:54,442 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:54,442 INFO L85 PathProgramCache]: Analyzing trace with hash 642940402, now seen corresponding path program 1 times [2023-11-26 10:46:54,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:54,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737376212] [2023-11-26 10:46:54,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:54,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:54,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:54,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:54,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:54,581 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [737376212] [2023-11-26 10:46:54,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [737376212] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:54,582 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:54,582 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:54,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [91541051] [2023-11-26 10:46:54,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:54,583 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:46:54,584 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:46:54,584 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:46:54,584 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:46:54,585 INFO L87 Difference]: Start difference. First operand 1377 states and 2043 transitions. cyclomatic complexity: 667 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:54,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:46:54,623 INFO L93 Difference]: Finished difference Result 1377 states and 2042 transitions. [2023-11-26 10:46:54,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2042 transitions. [2023-11-26 10:46:54,637 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:54,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2042 transitions. [2023-11-26 10:46:54,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-26 10:46:54,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-26 10:46:54,653 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2042 transitions. [2023-11-26 10:46:54,655 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:46:54,656 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2042 transitions. [2023-11-26 10:46:54,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2042 transitions. [2023-11-26 10:46:54,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-26 10:46:54,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4829339143064633) internal successors, (2042), 1376 states have internal predecessors, (2042), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:54,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2042 transitions. [2023-11-26 10:46:54,755 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2042 transitions. [2023-11-26 10:46:54,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:46:54,758 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2042 transitions. [2023-11-26 10:46:54,758 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 10:46:54,758 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2042 transitions. [2023-11-26 10:46:54,775 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:54,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:46:54,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:46:54,782 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:54,782 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:54,783 INFO L748 eck$LassoCheckResult]: Stem: 5958#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5959#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6835#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6836#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6898#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 6839#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6799#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6800#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6828#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5895#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5896#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6003#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6248#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6174#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5897#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5558#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5559#L1036 assume !(0 == ~M_E~0); 5656#L1036-2 assume !(0 == ~T1_E~0); 6561#L1041-1 assume !(0 == ~T2_E~0); 6562#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5933#L1051-1 assume !(0 == ~T4_E~0); 5934#L1056-1 assume !(0 == ~T5_E~0); 6690#L1061-1 assume !(0 == ~T6_E~0); 5828#L1066-1 assume !(0 == ~T7_E~0); 5829#L1071-1 assume !(0 == ~T8_E~0); 6672#L1076-1 assume !(0 == ~T9_E~0); 5718#L1081-1 assume !(0 == ~T10_E~0); 5719#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6119#L1091-1 assume !(0 == ~E_1~0); 6846#L1096-1 assume !(0 == ~E_2~0); 6847#L1101-1 assume !(0 == ~E_3~0); 6187#L1106-1 assume !(0 == ~E_4~0); 6188#L1111-1 assume !(0 == ~E_5~0); 6352#L1116-1 assume !(0 == ~E_6~0); 6353#L1121-1 assume !(0 == ~E_7~0); 6178#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 6179#L1131-1 assume !(0 == ~E_9~0); 6454#L1136-1 assume !(0 == ~E_10~0); 6569#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6718#L514 assume 1 == ~m_pc~0; 6683#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6196#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6197#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6770#L1285 assume !(0 != activate_threads_~tmp~1#1); 6882#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5847#L533 assume !(1 == ~t1_pc~0); 5848#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6367#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5611#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5612#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 6590#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6591#L552 assume 1 == ~t2_pc~0; 6067#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6068#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6182#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6183#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 6209#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6210#L571 assume 1 == ~t3_pc~0; 6405#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6406#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5556#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5557#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 6357#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5642#L590 assume !(1 == ~t4_pc~0); 5643#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6415#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5736#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5737#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6617#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6354#L609 assume 1 == ~t5_pc~0; 6355#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6880#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6772#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6773#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 6346#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6347#L628 assume !(1 == ~t6_pc~0); 6279#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6278#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6155#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6156#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 6652#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6653#L647 assume 1 == ~t7_pc~0; 6189#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6190#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6781#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6192#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 6193#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6909#L666 assume !(1 == ~t8_pc~0); 5980#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5981#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6208#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6378#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 6116#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6117#L685 assume 1 == ~t9_pc~0; 6888#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6789#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6242#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6146#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 6147#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6532#L704 assume !(1 == ~t10_pc~0); 6136#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6135#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6396#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5690#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 5691#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5942#L1154 assume !(1 == ~M_E~0); 6640#L1154-2 assume !(1 == ~T1_E~0); 5916#L1159-1 assume !(1 == ~T2_E~0); 5917#L1164-1 assume !(1 == ~T3_E~0); 6376#L1169-1 assume !(1 == ~T4_E~0); 6243#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6045#L1179-1 assume !(1 == ~T6_E~0); 5901#L1184-1 assume !(1 == ~T7_E~0); 5902#L1189-1 assume !(1 == ~T8_E~0); 5978#L1194-1 assume !(1 == ~T9_E~0); 6103#L1199-1 assume !(1 == ~T10_E~0); 6057#L1204-1 assume !(1 == ~E_M~0); 6058#L1209-1 assume !(1 == ~E_1~0); 6611#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6612#L1219-1 assume !(1 == ~E_3~0); 6902#L1224-1 assume !(1 == ~E_4~0); 6400#L1229-1 assume !(1 == ~E_5~0); 5785#L1234-1 assume !(1 == ~E_6~0); 5786#L1239-1 assume !(1 == ~E_7~0); 5843#L1244-1 assume !(1 == ~E_8~0); 5844#L1249-1 assume !(1 == ~E_9~0); 6681#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 5685#L1259-1 assume { :end_inline_reset_delta_events } true; 5686#L1565-2 [2023-11-26 10:46:54,784 INFO L750 eck$LassoCheckResult]: Loop: 5686#L1565-2 assume !false; 6619#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6384#L1011-1 assume !false; 6348#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6121#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5884#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6221#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5908#L866 assume !(0 != eval_~tmp~0#1); 5910#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6417#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6418#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6685#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6864#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6746#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6747#L1051-3 assume !(0 == ~T4_E~0); 6686#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5930#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5931#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5932#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6866#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5677#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5678#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5728#L1091-3 assume !(0 == ~E_1~0); 5729#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6830#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6831#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6863#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6822#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6547#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6548#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6761#L1131-3 assume !(0 == ~E_9~0); 6762#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6914#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6550#L514-36 assume !(1 == ~m_pc~0); 6259#L514-38 is_master_triggered_~__retres1~0#1 := 0; 6094#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6095#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6589#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5987#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5988#L533-36 assume 1 == ~t1_pc~0; 6268#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6361#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6812#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6627#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6424#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6425#L552-36 assume !(1 == ~t2_pc~0); 5984#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5983#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6483#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6754#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5954#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5955#L571-36 assume 1 == ~t3_pc~0; 6342#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6046#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6047#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6238#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6745#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6017#L590-36 assume 1 == ~t4_pc~0; 6018#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6641#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6434#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6435#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6724#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6725#L609-36 assume 1 == ~t5_pc~0; 6602#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6427#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6428#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6769#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 6511#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6318#L628-36 assume 1 == ~t6_pc~0; 6166#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6167#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6217#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6218#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6552#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6553#L647-36 assume 1 == ~t7_pc~0; 6476#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5704#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5705#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5722#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5723#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6642#L666-36 assume 1 == ~t8_pc~0; 5913#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5914#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6540#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6541#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6065#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6066#L685-36 assume !(1 == ~t9_pc~0); 5816#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 5817#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6272#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6273#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6205#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6206#L704-36 assume 1 == ~t10_pc~0; 5804#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5805#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6126#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6127#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5832#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5833#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6816#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6699#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6700#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6877#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6132#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6133#L1179-3 assume !(1 == ~T6_E~0); 6791#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5706#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5707#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6076#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6077#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6397#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5574#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5575#L1219-3 assume !(1 == ~E_3~0); 6596#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6597#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6618#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5845#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5846#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6451#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6823#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6600#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6601#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5654#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6114#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6115#L1584 assume !(0 == start_simulation_~tmp~3#1); 6558#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5859#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5554#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5606#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 5607#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6185#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6440#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6441#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 5686#L1565-2 [2023-11-26 10:46:54,785 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:54,785 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2023-11-26 10:46:54,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:54,786 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101160012] [2023-11-26 10:46:54,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:54,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:54,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:54,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:54,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:54,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101160012] [2023-11-26 10:46:54,897 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2101160012] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:54,898 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:54,899 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:54,899 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1925817101] [2023-11-26 10:46:54,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:54,900 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:46:54,900 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:54,901 INFO L85 PathProgramCache]: Analyzing trace with hash 1657784244, now seen corresponding path program 1 times [2023-11-26 10:46:54,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:54,901 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561737634] [2023-11-26 10:46:54,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:54,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:54,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:55,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:55,027 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:55,028 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [561737634] [2023-11-26 10:46:55,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [561737634] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:55,028 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:55,029 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:55,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1536107169] [2023-11-26 10:46:55,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:55,030 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:46:55,030 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:46:55,031 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:46:55,031 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:46:55,031 INFO L87 Difference]: Start difference. First operand 1377 states and 2042 transitions. cyclomatic complexity: 666 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:55,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:46:55,078 INFO L93 Difference]: Finished difference Result 1377 states and 2041 transitions. [2023-11-26 10:46:55,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2041 transitions. [2023-11-26 10:46:55,092 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:55,106 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2041 transitions. [2023-11-26 10:46:55,106 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-26 10:46:55,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-26 10:46:55,108 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2041 transitions. [2023-11-26 10:46:55,111 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:46:55,111 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2041 transitions. [2023-11-26 10:46:55,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2041 transitions. [2023-11-26 10:46:55,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-26 10:46:55,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4822076978939724) internal successors, (2041), 1376 states have internal predecessors, (2041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:55,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2041 transitions. [2023-11-26 10:46:55,146 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2041 transitions. [2023-11-26 10:46:55,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:46:55,148 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2041 transitions. [2023-11-26 10:46:55,149 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 10:46:55,149 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2041 transitions. [2023-11-26 10:46:55,158 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:55,158 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:46:55,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:46:55,162 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:55,163 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:55,163 INFO L748 eck$LassoCheckResult]: Stem: 8719#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 8720#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9596#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9597#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9659#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 9600#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9560#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9561#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9589#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8656#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8657#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8764#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9009#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8935#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8658#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8319#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8320#L1036 assume !(0 == ~M_E~0); 8417#L1036-2 assume !(0 == ~T1_E~0); 9322#L1041-1 assume !(0 == ~T2_E~0); 9323#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8694#L1051-1 assume !(0 == ~T4_E~0); 8695#L1056-1 assume !(0 == ~T5_E~0); 9451#L1061-1 assume !(0 == ~T6_E~0); 8589#L1066-1 assume !(0 == ~T7_E~0); 8590#L1071-1 assume !(0 == ~T8_E~0); 9433#L1076-1 assume !(0 == ~T9_E~0); 8479#L1081-1 assume !(0 == ~T10_E~0); 8480#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8880#L1091-1 assume !(0 == ~E_1~0); 9607#L1096-1 assume !(0 == ~E_2~0); 9608#L1101-1 assume !(0 == ~E_3~0); 8948#L1106-1 assume !(0 == ~E_4~0); 8949#L1111-1 assume !(0 == ~E_5~0); 9113#L1116-1 assume !(0 == ~E_6~0); 9114#L1121-1 assume !(0 == ~E_7~0); 8939#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8940#L1131-1 assume !(0 == ~E_9~0); 9215#L1136-1 assume !(0 == ~E_10~0); 9330#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9479#L514 assume 1 == ~m_pc~0; 9444#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8957#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8958#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9531#L1285 assume !(0 != activate_threads_~tmp~1#1); 9643#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8608#L533 assume !(1 == ~t1_pc~0); 8609#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9128#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8372#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8373#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 9351#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9352#L552 assume 1 == ~t2_pc~0; 8828#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8829#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8943#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8944#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 8970#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8971#L571 assume 1 == ~t3_pc~0; 9166#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9167#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8317#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8318#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 9118#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8403#L590 assume !(1 == ~t4_pc~0); 8404#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9176#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8497#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8498#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9378#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9115#L609 assume 1 == ~t5_pc~0; 9116#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9641#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9533#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9534#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 9107#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9108#L628 assume !(1 == ~t6_pc~0); 9040#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9039#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8916#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8917#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 9413#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9414#L647 assume 1 == ~t7_pc~0; 8950#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8951#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9542#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8953#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 8954#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9670#L666 assume !(1 == ~t8_pc~0); 8741#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8742#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8969#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9139#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 8877#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8878#L685 assume 1 == ~t9_pc~0; 9649#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9550#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9003#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8907#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 8908#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9293#L704 assume !(1 == ~t10_pc~0); 8897#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8896#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9157#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8451#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 8452#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8703#L1154 assume !(1 == ~M_E~0); 9401#L1154-2 assume !(1 == ~T1_E~0); 8677#L1159-1 assume !(1 == ~T2_E~0); 8678#L1164-1 assume !(1 == ~T3_E~0); 9137#L1169-1 assume !(1 == ~T4_E~0); 9004#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8806#L1179-1 assume !(1 == ~T6_E~0); 8662#L1184-1 assume !(1 == ~T7_E~0); 8663#L1189-1 assume !(1 == ~T8_E~0); 8739#L1194-1 assume !(1 == ~T9_E~0); 8864#L1199-1 assume !(1 == ~T10_E~0); 8818#L1204-1 assume !(1 == ~E_M~0); 8819#L1209-1 assume !(1 == ~E_1~0); 9372#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9373#L1219-1 assume !(1 == ~E_3~0); 9663#L1224-1 assume !(1 == ~E_4~0); 9161#L1229-1 assume !(1 == ~E_5~0); 8546#L1234-1 assume !(1 == ~E_6~0); 8547#L1239-1 assume !(1 == ~E_7~0); 8604#L1244-1 assume !(1 == ~E_8~0); 8605#L1249-1 assume !(1 == ~E_9~0); 9442#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 8446#L1259-1 assume { :end_inline_reset_delta_events } true; 8447#L1565-2 [2023-11-26 10:46:55,164 INFO L750 eck$LassoCheckResult]: Loop: 8447#L1565-2 assume !false; 9380#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9146#L1011-1 assume !false; 9109#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8882#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8645#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8982#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8669#L866 assume !(0 != eval_~tmp~0#1); 8671#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9178#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9179#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9446#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9625#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9507#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9508#L1051-3 assume !(0 == ~T4_E~0); 9447#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8691#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8692#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8693#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9627#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8438#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8439#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8489#L1091-3 assume !(0 == ~E_1~0); 8490#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9591#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9592#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9624#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9583#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9308#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9309#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9522#L1131-3 assume !(0 == ~E_9~0); 9523#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9675#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9311#L514-36 assume 1 == ~m_pc~0; 9312#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8855#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8856#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9350#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8748#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8749#L533-36 assume 1 == ~t1_pc~0; 9029#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9122#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9573#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9388#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9185#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9186#L552-36 assume 1 == ~t2_pc~0; 8743#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8744#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9244#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9515#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8715#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8716#L571-36 assume !(1 == ~t3_pc~0); 9104#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 8807#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8808#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8999#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9506#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8778#L590-36 assume 1 == ~t4_pc~0; 8779#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9402#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9196#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9197#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9485#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9486#L609-36 assume 1 == ~t5_pc~0; 9363#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9188#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9189#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9530#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 9272#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9079#L628-36 assume !(1 == ~t6_pc~0); 8929#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 8928#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8978#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8979#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9313#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9314#L647-36 assume 1 == ~t7_pc~0; 9237#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8465#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8466#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8483#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8484#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9403#L666-36 assume 1 == ~t8_pc~0; 8674#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8675#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9301#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9302#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8826#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8827#L685-36 assume !(1 == ~t9_pc~0); 8577#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 8578#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9033#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9034#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8966#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8967#L704-36 assume 1 == ~t10_pc~0; 8565#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8566#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8887#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8888#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8593#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8594#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9577#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9460#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9461#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9638#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8893#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8894#L1179-3 assume !(1 == ~T6_E~0); 9552#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8467#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8468#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8837#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8838#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9158#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8338#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8339#L1219-3 assume !(1 == ~E_3~0); 9357#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9358#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9379#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8606#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8607#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9212#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9584#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9361#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9362#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8415#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8875#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 8876#L1584 assume !(0 == start_simulation_~tmp~3#1); 9319#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8620#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8315#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8367#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 8368#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8946#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9201#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9202#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 8447#L1565-2 [2023-11-26 10:46:55,165 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:55,166 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2023-11-26 10:46:55,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:55,167 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1420663731] [2023-11-26 10:46:55,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:55,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:55,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:55,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:55,226 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:55,226 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1420663731] [2023-11-26 10:46:55,227 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1420663731] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:55,227 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:55,227 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:55,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [15382119] [2023-11-26 10:46:55,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:55,233 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:46:55,233 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:55,233 INFO L85 PathProgramCache]: Analyzing trace with hash -1243014924, now seen corresponding path program 1 times [2023-11-26 10:46:55,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:55,234 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886124821] [2023-11-26 10:46:55,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:55,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:55,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:55,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:55,337 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:55,337 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886124821] [2023-11-26 10:46:55,338 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [886124821] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:55,338 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:55,338 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:55,338 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82034946] [2023-11-26 10:46:55,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:55,339 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:46:55,339 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:46:55,340 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:46:55,340 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:46:55,340 INFO L87 Difference]: Start difference. First operand 1377 states and 2041 transitions. cyclomatic complexity: 665 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:55,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:46:55,376 INFO L93 Difference]: Finished difference Result 1377 states and 2040 transitions. [2023-11-26 10:46:55,376 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2040 transitions. [2023-11-26 10:46:55,389 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:55,401 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2040 transitions. [2023-11-26 10:46:55,401 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-26 10:46:55,403 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-26 10:46:55,403 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2040 transitions. [2023-11-26 10:46:55,405 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:46:55,405 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2023-11-26 10:46:55,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2040 transitions. [2023-11-26 10:46:55,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-26 10:46:55,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4814814814814814) internal successors, (2040), 1376 states have internal predecessors, (2040), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:55,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2040 transitions. [2023-11-26 10:46:55,444 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2023-11-26 10:46:55,444 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:46:55,446 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2023-11-26 10:46:55,446 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 10:46:55,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2040 transitions. [2023-11-26 10:46:55,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:55,456 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:46:55,456 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:46:55,460 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:55,461 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:55,461 INFO L748 eck$LassoCheckResult]: Stem: 11480#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 11481#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 12357#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12358#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12420#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 12361#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12321#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12322#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12350#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11419#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11420#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11525#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11770#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11696#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11421#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11080#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11081#L1036 assume !(0 == ~M_E~0); 11178#L1036-2 assume !(0 == ~T1_E~0); 12083#L1041-1 assume !(0 == ~T2_E~0); 12084#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11455#L1051-1 assume !(0 == ~T4_E~0); 11456#L1056-1 assume !(0 == ~T5_E~0); 12212#L1061-1 assume !(0 == ~T6_E~0); 11350#L1066-1 assume !(0 == ~T7_E~0); 11351#L1071-1 assume !(0 == ~T8_E~0); 12194#L1076-1 assume !(0 == ~T9_E~0); 11240#L1081-1 assume !(0 == ~T10_E~0); 11241#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 11641#L1091-1 assume !(0 == ~E_1~0); 12369#L1096-1 assume !(0 == ~E_2~0); 12370#L1101-1 assume !(0 == ~E_3~0); 11709#L1106-1 assume !(0 == ~E_4~0); 11710#L1111-1 assume !(0 == ~E_5~0); 11874#L1116-1 assume !(0 == ~E_6~0); 11875#L1121-1 assume !(0 == ~E_7~0); 11700#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11701#L1131-1 assume !(0 == ~E_9~0); 11976#L1136-1 assume !(0 == ~E_10~0); 12091#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12240#L514 assume 1 == ~m_pc~0; 12205#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11718#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11719#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12293#L1285 assume !(0 != activate_threads_~tmp~1#1); 12405#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11369#L533 assume !(1 == ~t1_pc~0); 11370#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11889#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11136#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 12112#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12113#L552 assume 1 == ~t2_pc~0; 11590#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11591#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11704#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11705#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 11736#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11737#L571 assume 1 == ~t3_pc~0; 11929#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11930#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11078#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11079#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 11879#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11164#L590 assume !(1 == ~t4_pc~0); 11165#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11938#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11258#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11259#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12140#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11876#L609 assume 1 == ~t5_pc~0; 11877#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12402#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12294#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12295#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 11868#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11869#L628 assume !(1 == ~t6_pc~0); 11801#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11800#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11678#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11679#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 12174#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12175#L647 assume 1 == ~t7_pc~0; 11711#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11712#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12303#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11716#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 11717#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12431#L666 assume !(1 == ~t8_pc~0); 11502#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11503#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11730#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11901#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 11639#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11640#L685 assume 1 == ~t9_pc~0; 12410#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12311#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11764#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11668#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 11669#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12054#L704 assume !(1 == ~t10_pc~0); 11658#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11657#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11919#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11212#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 11213#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11464#L1154 assume !(1 == ~M_E~0); 12162#L1154-2 assume !(1 == ~T1_E~0); 11438#L1159-1 assume !(1 == ~T2_E~0); 11439#L1164-1 assume !(1 == ~T3_E~0); 11898#L1169-1 assume !(1 == ~T4_E~0); 11765#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11569#L1179-1 assume !(1 == ~T6_E~0); 11423#L1184-1 assume !(1 == ~T7_E~0); 11424#L1189-1 assume !(1 == ~T8_E~0); 11500#L1194-1 assume !(1 == ~T9_E~0); 11627#L1199-1 assume !(1 == ~T10_E~0); 11581#L1204-1 assume !(1 == ~E_M~0); 11582#L1209-1 assume !(1 == ~E_1~0); 12135#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12136#L1219-1 assume !(1 == ~E_3~0); 12424#L1224-1 assume !(1 == ~E_4~0); 11923#L1229-1 assume !(1 == ~E_5~0); 11307#L1234-1 assume !(1 == ~E_6~0); 11308#L1239-1 assume !(1 == ~E_7~0); 11365#L1244-1 assume !(1 == ~E_8~0); 11366#L1249-1 assume !(1 == ~E_9~0); 12203#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 11207#L1259-1 assume { :end_inline_reset_delta_events } true; 11208#L1565-2 [2023-11-26 10:46:55,462 INFO L750 eck$LassoCheckResult]: Loop: 11208#L1565-2 assume !false; 12141#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11907#L1011-1 assume !false; 11870#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11646#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11406#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11743#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11435#L866 assume !(0 != eval_~tmp~0#1); 11437#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11940#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11941#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12207#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12386#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12268#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12269#L1051-3 assume !(0 == ~T4_E~0); 12208#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11452#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11453#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11454#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12388#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11199#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11200#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11254#L1091-3 assume !(0 == ~E_1~0); 11255#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12352#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12353#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12385#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12344#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12069#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12070#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12283#L1131-3 assume !(0 == ~E_9~0); 12284#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12436#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12072#L514-36 assume !(1 == ~m_pc~0); 11781#L514-38 is_master_triggered_~__retres1~0#1 := 0; 11616#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11617#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12111#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11509#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11510#L533-36 assume 1 == ~t1_pc~0; 11789#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11883#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12334#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12149#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11946#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11947#L552-36 assume 1 == ~t2_pc~0; 11504#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11505#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12005#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12276#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11476#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11477#L571-36 assume 1 == ~t3_pc~0; 11864#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11567#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11568#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11760#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12267#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11539#L590-36 assume 1 == ~t4_pc~0; 11540#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12163#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11956#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11957#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12246#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12247#L609-36 assume 1 == ~t5_pc~0; 12124#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11949#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11950#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12291#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 12033#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11840#L628-36 assume 1 == ~t6_pc~0; 11688#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11689#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11739#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11740#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12074#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12075#L647-36 assume 1 == ~t7_pc~0; 11998#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11226#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11227#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11244#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11245#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12164#L666-36 assume 1 == ~t8_pc~0; 11432#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11433#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12062#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12063#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11587#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11588#L685-36 assume 1 == ~t9_pc~0; 12049#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11339#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11794#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11795#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11727#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11728#L704-36 assume !(1 == ~t10_pc~0); 11328#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 11327#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11648#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11649#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11354#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11355#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12338#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12221#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12222#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12399#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11654#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11655#L1179-3 assume !(1 == ~T6_E~0); 12313#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11228#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11229#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11598#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11599#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11918#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11096#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11097#L1219-3 assume !(1 == ~E_3~0); 12118#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12119#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12139#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11367#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11368#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11969#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12345#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12122#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12123#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11176#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11636#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 11637#L1584 assume !(0 == start_simulation_~tmp~3#1); 12080#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11381#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11076#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11128#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 11129#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11707#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11962#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 11963#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 11208#L1565-2 [2023-11-26 10:46:55,463 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:55,464 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2023-11-26 10:46:55,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:55,464 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1547161474] [2023-11-26 10:46:55,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:55,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:55,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:55,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:55,527 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:55,527 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1547161474] [2023-11-26 10:46:55,527 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1547161474] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:55,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:55,528 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:55,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083588414] [2023-11-26 10:46:55,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:55,529 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:46:55,529 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:55,529 INFO L85 PathProgramCache]: Analyzing trace with hash 157765683, now seen corresponding path program 1 times [2023-11-26 10:46:55,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:55,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1643570229] [2023-11-26 10:46:55,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:55,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:55,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:55,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:55,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:55,661 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1643570229] [2023-11-26 10:46:55,661 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1643570229] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:55,662 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:55,662 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:55,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1061522376] [2023-11-26 10:46:55,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:55,663 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:46:55,663 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:46:55,663 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:46:55,664 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:46:55,664 INFO L87 Difference]: Start difference. First operand 1377 states and 2040 transitions. cyclomatic complexity: 664 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:55,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:46:55,706 INFO L93 Difference]: Finished difference Result 1377 states and 2039 transitions. [2023-11-26 10:46:55,706 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2039 transitions. [2023-11-26 10:46:55,719 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:55,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2039 transitions. [2023-11-26 10:46:55,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-26 10:46:55,733 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-26 10:46:55,733 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2039 transitions. [2023-11-26 10:46:55,737 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:46:55,737 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2039 transitions. [2023-11-26 10:46:55,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2039 transitions. [2023-11-26 10:46:55,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-26 10:46:55,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4807552650689906) internal successors, (2039), 1376 states have internal predecessors, (2039), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:55,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2039 transitions. [2023-11-26 10:46:55,768 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2039 transitions. [2023-11-26 10:46:55,768 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:46:55,770 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2039 transitions. [2023-11-26 10:46:55,771 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 10:46:55,771 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2039 transitions. [2023-11-26 10:46:55,780 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:55,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:46:55,780 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:46:55,782 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:55,783 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:55,783 INFO L748 eck$LassoCheckResult]: Stem: 14241#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 15118#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15119#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15181#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 15122#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15082#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15083#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15111#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14178#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14179#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14286#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14531#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14457#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14180#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13841#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13842#L1036 assume !(0 == ~M_E~0); 13939#L1036-2 assume !(0 == ~T1_E~0); 14844#L1041-1 assume !(0 == ~T2_E~0); 14845#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14216#L1051-1 assume !(0 == ~T4_E~0); 14217#L1056-1 assume !(0 == ~T5_E~0); 14973#L1061-1 assume !(0 == ~T6_E~0); 14111#L1066-1 assume !(0 == ~T7_E~0); 14112#L1071-1 assume !(0 == ~T8_E~0); 14955#L1076-1 assume !(0 == ~T9_E~0); 14001#L1081-1 assume !(0 == ~T10_E~0); 14002#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14402#L1091-1 assume !(0 == ~E_1~0); 15129#L1096-1 assume !(0 == ~E_2~0); 15130#L1101-1 assume !(0 == ~E_3~0); 14470#L1106-1 assume !(0 == ~E_4~0); 14471#L1111-1 assume !(0 == ~E_5~0); 14635#L1116-1 assume !(0 == ~E_6~0); 14636#L1121-1 assume !(0 == ~E_7~0); 14461#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14462#L1131-1 assume !(0 == ~E_9~0); 14737#L1136-1 assume !(0 == ~E_10~0); 14852#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15001#L514 assume 1 == ~m_pc~0; 14966#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14479#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14480#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15053#L1285 assume !(0 != activate_threads_~tmp~1#1); 15165#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14130#L533 assume !(1 == ~t1_pc~0); 14131#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14650#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13894#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13895#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 14873#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14874#L552 assume 1 == ~t2_pc~0; 14350#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14351#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14465#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14466#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 14492#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14493#L571 assume 1 == ~t3_pc~0; 14688#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14689#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13839#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13840#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 14640#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13925#L590 assume !(1 == ~t4_pc~0); 13926#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14698#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14019#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14020#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14900#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14637#L609 assume 1 == ~t5_pc~0; 14638#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15163#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15055#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15056#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 14629#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14630#L628 assume !(1 == ~t6_pc~0); 14562#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14561#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14438#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14439#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 14935#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14936#L647 assume 1 == ~t7_pc~0; 14472#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14473#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15064#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14475#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 14476#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15192#L666 assume !(1 == ~t8_pc~0); 14263#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14264#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14491#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14661#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 14399#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14400#L685 assume 1 == ~t9_pc~0; 15171#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15072#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14525#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14429#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 14430#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14815#L704 assume !(1 == ~t10_pc~0); 14419#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14418#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14679#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13973#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 13974#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14225#L1154 assume !(1 == ~M_E~0); 14923#L1154-2 assume !(1 == ~T1_E~0); 14199#L1159-1 assume !(1 == ~T2_E~0); 14200#L1164-1 assume !(1 == ~T3_E~0); 14659#L1169-1 assume !(1 == ~T4_E~0); 14526#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14328#L1179-1 assume !(1 == ~T6_E~0); 14184#L1184-1 assume !(1 == ~T7_E~0); 14185#L1189-1 assume !(1 == ~T8_E~0); 14261#L1194-1 assume !(1 == ~T9_E~0); 14386#L1199-1 assume !(1 == ~T10_E~0); 14340#L1204-1 assume !(1 == ~E_M~0); 14341#L1209-1 assume !(1 == ~E_1~0); 14894#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14895#L1219-1 assume !(1 == ~E_3~0); 15185#L1224-1 assume !(1 == ~E_4~0); 14683#L1229-1 assume !(1 == ~E_5~0); 14068#L1234-1 assume !(1 == ~E_6~0); 14069#L1239-1 assume !(1 == ~E_7~0); 14126#L1244-1 assume !(1 == ~E_8~0); 14127#L1249-1 assume !(1 == ~E_9~0); 14964#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13968#L1259-1 assume { :end_inline_reset_delta_events } true; 13969#L1565-2 [2023-11-26 10:46:55,784 INFO L750 eck$LassoCheckResult]: Loop: 13969#L1565-2 assume !false; 14902#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14667#L1011-1 assume !false; 14631#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14404#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14167#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14504#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14191#L866 assume !(0 != eval_~tmp~0#1); 14193#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14700#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14701#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14968#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15147#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15029#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15030#L1051-3 assume !(0 == ~T4_E~0); 14969#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14213#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14214#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14215#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15149#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13960#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13961#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14011#L1091-3 assume !(0 == ~E_1~0); 14012#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15113#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15114#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15146#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15105#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14830#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14831#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15044#L1131-3 assume !(0 == ~E_9~0); 15045#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15197#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14833#L514-36 assume 1 == ~m_pc~0; 14834#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14377#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14378#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14872#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14270#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14271#L533-36 assume 1 == ~t1_pc~0; 14551#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14644#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15095#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14910#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14707#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14708#L552-36 assume 1 == ~t2_pc~0; 14265#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14266#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14766#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15037#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14237#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14238#L571-36 assume 1 == ~t3_pc~0; 14625#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14329#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14330#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14521#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15028#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14300#L590-36 assume 1 == ~t4_pc~0; 14301#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14924#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14717#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14718#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15007#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15008#L609-36 assume 1 == ~t5_pc~0; 14885#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14710#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14711#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15052#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 14794#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14601#L628-36 assume 1 == ~t6_pc~0; 14449#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14450#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14500#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14501#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14835#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14836#L647-36 assume 1 == ~t7_pc~0; 14759#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13987#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13988#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14005#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14006#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14925#L666-36 assume 1 == ~t8_pc~0; 14196#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14197#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14823#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14824#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14348#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14349#L685-36 assume !(1 == ~t9_pc~0); 14099#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 14100#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14555#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14556#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14488#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14489#L704-36 assume 1 == ~t10_pc~0; 14087#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14088#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14409#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14410#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14115#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14116#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15099#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14982#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14983#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15160#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14415#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14416#L1179-3 assume !(1 == ~T6_E~0); 15074#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13989#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13990#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14359#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14360#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14680#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13857#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13858#L1219-3 assume !(1 == ~E_3~0); 14879#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14880#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14901#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14128#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14129#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14734#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15106#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14883#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14884#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13937#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14397#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14398#L1584 assume !(0 == start_simulation_~tmp~3#1); 14841#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14142#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13837#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13889#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 13890#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14468#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14723#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 14724#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 13969#L1565-2 [2023-11-26 10:46:55,785 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:55,785 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2023-11-26 10:46:55,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:55,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650347301] [2023-11-26 10:46:55,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:55,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:55,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:55,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:55,848 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:55,848 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1650347301] [2023-11-26 10:46:55,853 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1650347301] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:55,853 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:55,854 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:55,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [599791482] [2023-11-26 10:46:55,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:55,854 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:46:55,855 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:55,855 INFO L85 PathProgramCache]: Analyzing trace with hash -220510030, now seen corresponding path program 1 times [2023-11-26 10:46:55,855 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:55,856 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575423101] [2023-11-26 10:46:55,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:55,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:55,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:55,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:55,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:55,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [575423101] [2023-11-26 10:46:55,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [575423101] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:55,951 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:55,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:55,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639511166] [2023-11-26 10:46:55,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:55,952 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:46:55,952 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:46:55,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:46:55,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:46:55,953 INFO L87 Difference]: Start difference. First operand 1377 states and 2039 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:55,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:46:55,991 INFO L93 Difference]: Finished difference Result 1377 states and 2038 transitions. [2023-11-26 10:46:55,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2038 transitions. [2023-11-26 10:46:56,005 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:56,017 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2038 transitions. [2023-11-26 10:46:56,018 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-26 10:46:56,019 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-26 10:46:56,020 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2038 transitions. [2023-11-26 10:46:56,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:46:56,022 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2038 transitions. [2023-11-26 10:46:56,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2038 transitions. [2023-11-26 10:46:56,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-26 10:46:56,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4800290486564995) internal successors, (2038), 1376 states have internal predecessors, (2038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:56,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2038 transitions. [2023-11-26 10:46:56,058 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2038 transitions. [2023-11-26 10:46:56,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:46:56,060 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2038 transitions. [2023-11-26 10:46:56,063 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 10:46:56,063 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2038 transitions. [2023-11-26 10:46:56,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:56,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:46:56,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:46:56,077 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:56,077 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:56,078 INFO L748 eck$LassoCheckResult]: Stem: 17002#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 17003#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 17879#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17880#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17942#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 17883#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17843#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17844#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17872#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16939#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16940#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17047#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17292#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17218#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16941#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16602#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16603#L1036 assume !(0 == ~M_E~0); 16700#L1036-2 assume !(0 == ~T1_E~0); 17605#L1041-1 assume !(0 == ~T2_E~0); 17606#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16977#L1051-1 assume !(0 == ~T4_E~0); 16978#L1056-1 assume !(0 == ~T5_E~0); 17734#L1061-1 assume !(0 == ~T6_E~0); 16872#L1066-1 assume !(0 == ~T7_E~0); 16873#L1071-1 assume !(0 == ~T8_E~0); 17716#L1076-1 assume !(0 == ~T9_E~0); 16762#L1081-1 assume !(0 == ~T10_E~0); 16763#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 17163#L1091-1 assume !(0 == ~E_1~0); 17890#L1096-1 assume !(0 == ~E_2~0); 17891#L1101-1 assume !(0 == ~E_3~0); 17231#L1106-1 assume !(0 == ~E_4~0); 17232#L1111-1 assume !(0 == ~E_5~0); 17396#L1116-1 assume !(0 == ~E_6~0); 17397#L1121-1 assume !(0 == ~E_7~0); 17222#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 17223#L1131-1 assume !(0 == ~E_9~0); 17498#L1136-1 assume !(0 == ~E_10~0); 17613#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17762#L514 assume 1 == ~m_pc~0; 17727#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17240#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17241#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17814#L1285 assume !(0 != activate_threads_~tmp~1#1); 17926#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16891#L533 assume !(1 == ~t1_pc~0); 16892#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17411#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16655#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16656#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 17634#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17635#L552 assume 1 == ~t2_pc~0; 17111#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17112#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17226#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17227#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 17253#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17254#L571 assume 1 == ~t3_pc~0; 17449#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17450#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16600#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16601#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 17401#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16686#L590 assume !(1 == ~t4_pc~0); 16687#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17459#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16780#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16781#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17662#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17398#L609 assume 1 == ~t5_pc~0; 17399#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17924#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17816#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17817#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 17390#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17391#L628 assume !(1 == ~t6_pc~0); 17323#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17322#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17199#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17200#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 17696#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17697#L647 assume 1 == ~t7_pc~0; 17233#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17234#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17825#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17236#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 17237#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17953#L666 assume !(1 == ~t8_pc~0); 17024#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17025#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17252#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17422#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 17160#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17161#L685 assume 1 == ~t9_pc~0; 17932#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17833#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17286#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17190#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 17191#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17576#L704 assume !(1 == ~t10_pc~0); 17180#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17179#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17441#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16734#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 16735#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16986#L1154 assume !(1 == ~M_E~0); 17684#L1154-2 assume !(1 == ~T1_E~0); 16960#L1159-1 assume !(1 == ~T2_E~0); 16961#L1164-1 assume !(1 == ~T3_E~0); 17420#L1169-1 assume !(1 == ~T4_E~0); 17287#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17089#L1179-1 assume !(1 == ~T6_E~0); 16945#L1184-1 assume !(1 == ~T7_E~0); 16946#L1189-1 assume !(1 == ~T8_E~0); 17022#L1194-1 assume !(1 == ~T9_E~0); 17147#L1199-1 assume !(1 == ~T10_E~0); 17101#L1204-1 assume !(1 == ~E_M~0); 17102#L1209-1 assume !(1 == ~E_1~0); 17655#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17656#L1219-1 assume !(1 == ~E_3~0); 17946#L1224-1 assume !(1 == ~E_4~0); 17444#L1229-1 assume !(1 == ~E_5~0); 16829#L1234-1 assume !(1 == ~E_6~0); 16830#L1239-1 assume !(1 == ~E_7~0); 16887#L1244-1 assume !(1 == ~E_8~0); 16888#L1249-1 assume !(1 == ~E_9~0); 17725#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16729#L1259-1 assume { :end_inline_reset_delta_events } true; 16730#L1565-2 [2023-11-26 10:46:56,079 INFO L750 eck$LassoCheckResult]: Loop: 16730#L1565-2 assume !false; 17663#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17429#L1011-1 assume !false; 17392#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17165#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16928#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17265#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16952#L866 assume !(0 != eval_~tmp~0#1); 16954#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17461#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17462#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17729#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17908#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17790#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17791#L1051-3 assume !(0 == ~T4_E~0); 17730#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16974#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16975#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16976#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17910#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16721#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16722#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16772#L1091-3 assume !(0 == ~E_1~0); 16773#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17874#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17875#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17907#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17866#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17591#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17592#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17805#L1131-3 assume !(0 == ~E_9~0); 17806#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17958#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17594#L514-36 assume !(1 == ~m_pc~0); 17303#L514-38 is_master_triggered_~__retres1~0#1 := 0; 17138#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17139#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17633#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17031#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17032#L533-36 assume 1 == ~t1_pc~0; 17312#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17405#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17856#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17671#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17468#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17469#L552-36 assume 1 == ~t2_pc~0; 17026#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17027#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17527#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17798#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16998#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16999#L571-36 assume 1 == ~t3_pc~0; 17386#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17090#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17091#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17282#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17789#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17061#L590-36 assume 1 == ~t4_pc~0; 17062#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17685#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17479#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17480#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17768#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17769#L609-36 assume 1 == ~t5_pc~0; 17646#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17471#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17472#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17813#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 17555#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17362#L628-36 assume 1 == ~t6_pc~0; 17210#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17211#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17261#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17262#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17596#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17597#L647-36 assume 1 == ~t7_pc~0; 17520#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16750#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16751#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16766#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16767#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17686#L666-36 assume 1 == ~t8_pc~0; 16957#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16958#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17584#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17585#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17109#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17110#L685-36 assume 1 == ~t9_pc~0; 17570#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16859#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17314#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17315#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17249#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17250#L704-36 assume 1 == ~t10_pc~0; 16848#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16849#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17170#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17171#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16874#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16875#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17860#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17743#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17744#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17921#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17176#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17177#L1179-3 assume !(1 == ~T6_E~0); 17835#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16748#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16749#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17120#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17121#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17440#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16618#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16619#L1219-3 assume !(1 == ~E_3~0); 17640#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17641#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17661#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16889#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16890#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17491#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17867#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17644#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17645#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16698#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17158#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17159#L1584 assume !(0 == start_simulation_~tmp~3#1); 17602#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16903#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16598#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16650#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 16651#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17228#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17484#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 17485#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 16730#L1565-2 [2023-11-26 10:46:56,079 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:56,080 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2023-11-26 10:46:56,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:56,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1171452778] [2023-11-26 10:46:56,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:56,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:56,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:56,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:56,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:56,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1171452778] [2023-11-26 10:46:56,156 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1171452778] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:56,156 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:56,156 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:56,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [120689241] [2023-11-26 10:46:56,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:56,157 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:46:56,157 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:56,158 INFO L85 PathProgramCache]: Analyzing trace with hash 642940402, now seen corresponding path program 2 times [2023-11-26 10:46:56,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:56,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189002963] [2023-11-26 10:46:56,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:56,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:56,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:56,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:56,264 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:56,265 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189002963] [2023-11-26 10:46:56,265 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1189002963] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:56,265 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:56,265 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:56,265 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1474079193] [2023-11-26 10:46:56,266 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:56,266 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:46:56,266 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:46:56,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:46:56,267 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:46:56,267 INFO L87 Difference]: Start difference. First operand 1377 states and 2038 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:56,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:46:56,307 INFO L93 Difference]: Finished difference Result 1377 states and 2037 transitions. [2023-11-26 10:46:56,307 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2037 transitions. [2023-11-26 10:46:56,319 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:56,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2037 transitions. [2023-11-26 10:46:56,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-26 10:46:56,334 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-26 10:46:56,335 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2037 transitions. [2023-11-26 10:46:56,337 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:46:56,337 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2037 transitions. [2023-11-26 10:46:56,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2037 transitions. [2023-11-26 10:46:56,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-26 10:46:56,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4793028322440087) internal successors, (2037), 1376 states have internal predecessors, (2037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:56,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2037 transitions. [2023-11-26 10:46:56,373 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2037 transitions. [2023-11-26 10:46:56,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:46:56,376 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2037 transitions. [2023-11-26 10:46:56,376 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 10:46:56,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2037 transitions. [2023-11-26 10:46:56,386 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:56,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:46:56,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:46:56,390 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:56,390 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:56,390 INFO L748 eck$LassoCheckResult]: Stem: 19763#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 19764#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 20640#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20641#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20703#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 20644#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20604#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20605#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20633#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19702#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19703#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19808#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20053#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19979#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19704#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19363#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19364#L1036 assume !(0 == ~M_E~0); 19461#L1036-2 assume !(0 == ~T1_E~0); 20366#L1041-1 assume !(0 == ~T2_E~0); 20367#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19738#L1051-1 assume !(0 == ~T4_E~0); 19739#L1056-1 assume !(0 == ~T5_E~0); 20495#L1061-1 assume !(0 == ~T6_E~0); 19633#L1066-1 assume !(0 == ~T7_E~0); 19634#L1071-1 assume !(0 == ~T8_E~0); 20477#L1076-1 assume !(0 == ~T9_E~0); 19523#L1081-1 assume !(0 == ~T10_E~0); 19524#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 19924#L1091-1 assume !(0 == ~E_1~0); 20652#L1096-1 assume !(0 == ~E_2~0); 20653#L1101-1 assume !(0 == ~E_3~0); 19992#L1106-1 assume !(0 == ~E_4~0); 19993#L1111-1 assume !(0 == ~E_5~0); 20157#L1116-1 assume !(0 == ~E_6~0); 20158#L1121-1 assume !(0 == ~E_7~0); 19983#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19984#L1131-1 assume !(0 == ~E_9~0); 20259#L1136-1 assume !(0 == ~E_10~0); 20374#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20523#L514 assume 1 == ~m_pc~0; 20488#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20001#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20002#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20576#L1285 assume !(0 != activate_threads_~tmp~1#1); 20688#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19655#L533 assume !(1 == ~t1_pc~0); 19656#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20172#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19418#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19419#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 20395#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20396#L552 assume 1 == ~t2_pc~0; 19873#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19874#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19987#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19988#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 20019#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20020#L571 assume 1 == ~t3_pc~0; 20212#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20213#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19361#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19362#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 20162#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19447#L590 assume !(1 == ~t4_pc~0); 19448#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20221#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19541#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19542#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20423#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20159#L609 assume 1 == ~t5_pc~0; 20160#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20685#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20577#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20578#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 20151#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20152#L628 assume !(1 == ~t6_pc~0); 20084#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 20083#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19963#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19964#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 20457#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20458#L647 assume 1 == ~t7_pc~0; 19994#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19995#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20586#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19999#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 20000#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20714#L666 assume !(1 == ~t8_pc~0); 19785#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19786#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20013#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20184#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 19922#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19923#L685 assume 1 == ~t9_pc~0; 20693#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20594#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20047#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19951#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 19952#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20337#L704 assume !(1 == ~t10_pc~0); 19941#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19940#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20202#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19495#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 19496#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19747#L1154 assume !(1 == ~M_E~0); 20445#L1154-2 assume !(1 == ~T1_E~0); 19721#L1159-1 assume !(1 == ~T2_E~0); 19722#L1164-1 assume !(1 == ~T3_E~0); 20181#L1169-1 assume !(1 == ~T4_E~0); 20048#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19852#L1179-1 assume !(1 == ~T6_E~0); 19706#L1184-1 assume !(1 == ~T7_E~0); 19707#L1189-1 assume !(1 == ~T8_E~0); 19783#L1194-1 assume !(1 == ~T9_E~0); 19910#L1199-1 assume !(1 == ~T10_E~0); 19864#L1204-1 assume !(1 == ~E_M~0); 19865#L1209-1 assume !(1 == ~E_1~0); 20418#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20419#L1219-1 assume !(1 == ~E_3~0); 20707#L1224-1 assume !(1 == ~E_4~0); 20206#L1229-1 assume !(1 == ~E_5~0); 19590#L1234-1 assume !(1 == ~E_6~0); 19591#L1239-1 assume !(1 == ~E_7~0); 19648#L1244-1 assume !(1 == ~E_8~0); 19649#L1249-1 assume !(1 == ~E_9~0); 20486#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19490#L1259-1 assume { :end_inline_reset_delta_events } true; 19491#L1565-2 [2023-11-26 10:46:56,391 INFO L750 eck$LassoCheckResult]: Loop: 19491#L1565-2 assume !false; 20424#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20190#L1011-1 assume !false; 20153#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19929#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19689#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20026#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19718#L866 assume !(0 != eval_~tmp~0#1); 19720#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20223#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20224#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20490#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20670#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20551#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20552#L1051-3 assume !(0 == ~T4_E~0); 20491#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19735#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19736#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19737#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20671#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19482#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19483#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19537#L1091-3 assume !(0 == ~E_1~0); 19538#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20635#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20636#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20668#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20627#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20352#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20353#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20566#L1131-3 assume !(0 == ~E_9~0); 20567#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20719#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20354#L514-36 assume 1 == ~m_pc~0; 20355#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19899#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19900#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20394#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19792#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19793#L533-36 assume 1 == ~t1_pc~0; 20072#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20166#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20617#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20432#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20229#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20230#L552-36 assume 1 == ~t2_pc~0; 19787#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19788#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20288#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20559#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19759#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19760#L571-36 assume 1 == ~t3_pc~0; 20147#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19850#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19851#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20043#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20550#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19822#L590-36 assume !(1 == ~t4_pc~0); 19824#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 20446#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20239#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20240#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20529#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20530#L609-36 assume 1 == ~t5_pc~0; 20407#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20232#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20233#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20574#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 20316#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20123#L628-36 assume 1 == ~t6_pc~0; 19971#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19972#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20022#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20023#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20357#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20358#L647-36 assume 1 == ~t7_pc~0; 20281#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19509#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19510#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19527#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19528#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20447#L666-36 assume 1 == ~t8_pc~0; 19715#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19716#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20345#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20346#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19870#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19871#L685-36 assume !(1 == ~t9_pc~0); 19621#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 19622#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20077#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20078#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20010#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20011#L704-36 assume 1 == ~t10_pc~0; 19609#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19610#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19931#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19932#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19637#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19638#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20621#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20504#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20505#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20682#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19937#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19938#L1179-3 assume !(1 == ~T6_E~0); 20596#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19511#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19512#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19881#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19882#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20201#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19379#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19380#L1219-3 assume !(1 == ~E_3~0); 20401#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20402#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20422#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19650#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19651#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20252#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20628#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20405#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20406#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19459#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19919#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 19920#L1584 assume !(0 == start_simulation_~tmp~3#1); 20363#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19664#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19359#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19411#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 19412#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19990#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20245#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 20246#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 19491#L1565-2 [2023-11-26 10:46:56,392 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:56,392 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2023-11-26 10:46:56,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:56,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333430052] [2023-11-26 10:46:56,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:56,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:56,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:56,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:56,453 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:56,454 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333430052] [2023-11-26 10:46:56,454 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333430052] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:56,454 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:56,454 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:56,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [966074025] [2023-11-26 10:46:56,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:56,459 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:46:56,460 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:56,460 INFO L85 PathProgramCache]: Analyzing trace with hash -2062823821, now seen corresponding path program 1 times [2023-11-26 10:46:56,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:56,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317774154] [2023-11-26 10:46:56,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:56,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:56,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:56,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:56,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:56,580 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317774154] [2023-11-26 10:46:56,580 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317774154] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:56,581 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:56,581 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:56,581 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1838349561] [2023-11-26 10:46:56,581 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:56,582 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:46:56,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:46:56,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:46:56,583 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:46:56,583 INFO L87 Difference]: Start difference. First operand 1377 states and 2037 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:56,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:46:56,630 INFO L93 Difference]: Finished difference Result 1377 states and 2036 transitions. [2023-11-26 10:46:56,631 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2036 transitions. [2023-11-26 10:46:56,643 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:56,657 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2036 transitions. [2023-11-26 10:46:56,657 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-26 10:46:56,659 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-26 10:46:56,659 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2036 transitions. [2023-11-26 10:46:56,662 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:46:56,662 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2036 transitions. [2023-11-26 10:46:56,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2036 transitions. [2023-11-26 10:46:56,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-26 10:46:56,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.478576615831518) internal successors, (2036), 1376 states have internal predecessors, (2036), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:56,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2036 transitions. [2023-11-26 10:46:56,699 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2036 transitions. [2023-11-26 10:46:56,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:46:56,701 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2036 transitions. [2023-11-26 10:46:56,701 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 10:46:56,701 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2036 transitions. [2023-11-26 10:46:56,709 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:56,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:46:56,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:46:56,712 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:56,713 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:56,713 INFO L748 eck$LassoCheckResult]: Stem: 22524#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 23401#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23402#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23464#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 23405#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23365#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23366#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23394#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22461#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22462#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22569#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22814#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22740#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22463#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22124#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22125#L1036 assume !(0 == ~M_E~0); 22222#L1036-2 assume !(0 == ~T1_E~0); 23127#L1041-1 assume !(0 == ~T2_E~0); 23128#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22499#L1051-1 assume !(0 == ~T4_E~0); 22500#L1056-1 assume !(0 == ~T5_E~0); 23256#L1061-1 assume !(0 == ~T6_E~0); 22394#L1066-1 assume !(0 == ~T7_E~0); 22395#L1071-1 assume !(0 == ~T8_E~0); 23238#L1076-1 assume !(0 == ~T9_E~0); 22284#L1081-1 assume !(0 == ~T10_E~0); 22285#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 22685#L1091-1 assume !(0 == ~E_1~0); 23412#L1096-1 assume !(0 == ~E_2~0); 23413#L1101-1 assume !(0 == ~E_3~0); 22753#L1106-1 assume !(0 == ~E_4~0); 22754#L1111-1 assume !(0 == ~E_5~0); 22918#L1116-1 assume !(0 == ~E_6~0); 22919#L1121-1 assume !(0 == ~E_7~0); 22744#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 22745#L1131-1 assume !(0 == ~E_9~0); 23020#L1136-1 assume !(0 == ~E_10~0); 23135#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23284#L514 assume 1 == ~m_pc~0; 23249#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22762#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22763#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23336#L1285 assume !(0 != activate_threads_~tmp~1#1); 23448#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22413#L533 assume !(1 == ~t1_pc~0); 22414#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22933#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22177#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22178#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 23156#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23157#L552 assume 1 == ~t2_pc~0; 22633#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22634#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22748#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22749#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 22775#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22776#L571 assume 1 == ~t3_pc~0; 22971#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22972#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22122#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22123#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 22923#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22208#L590 assume !(1 == ~t4_pc~0); 22209#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22981#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22302#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22303#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23183#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22920#L609 assume 1 == ~t5_pc~0; 22921#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23446#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23338#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23339#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 22912#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22913#L628 assume !(1 == ~t6_pc~0); 22845#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22844#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22721#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22722#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 23218#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23219#L647 assume 1 == ~t7_pc~0; 22755#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22756#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23347#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22758#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 22759#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23475#L666 assume !(1 == ~t8_pc~0); 22546#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22547#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22774#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22944#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 22682#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22683#L685 assume 1 == ~t9_pc~0; 23454#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23355#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22808#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22712#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 22713#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23098#L704 assume !(1 == ~t10_pc~0); 22702#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22701#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22962#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22256#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 22257#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22508#L1154 assume !(1 == ~M_E~0); 23206#L1154-2 assume !(1 == ~T1_E~0); 22482#L1159-1 assume !(1 == ~T2_E~0); 22483#L1164-1 assume !(1 == ~T3_E~0); 22942#L1169-1 assume !(1 == ~T4_E~0); 22809#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22611#L1179-1 assume !(1 == ~T6_E~0); 22467#L1184-1 assume !(1 == ~T7_E~0); 22468#L1189-1 assume !(1 == ~T8_E~0); 22544#L1194-1 assume !(1 == ~T9_E~0); 22669#L1199-1 assume !(1 == ~T10_E~0); 22623#L1204-1 assume !(1 == ~E_M~0); 22624#L1209-1 assume !(1 == ~E_1~0); 23177#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 23178#L1219-1 assume !(1 == ~E_3~0); 23468#L1224-1 assume !(1 == ~E_4~0); 22966#L1229-1 assume !(1 == ~E_5~0); 22351#L1234-1 assume !(1 == ~E_6~0); 22352#L1239-1 assume !(1 == ~E_7~0); 22409#L1244-1 assume !(1 == ~E_8~0); 22410#L1249-1 assume !(1 == ~E_9~0); 23247#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22251#L1259-1 assume { :end_inline_reset_delta_events } true; 22252#L1565-2 [2023-11-26 10:46:56,714 INFO L750 eck$LassoCheckResult]: Loop: 22252#L1565-2 assume !false; 23185#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22950#L1011-1 assume !false; 22914#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22687#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22450#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22787#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22474#L866 assume !(0 != eval_~tmp~0#1); 22476#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22983#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22984#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23251#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23430#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23312#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23313#L1051-3 assume !(0 == ~T4_E~0); 23252#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22496#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22497#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22498#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23432#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22243#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22244#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22294#L1091-3 assume !(0 == ~E_1~0); 22295#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23396#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23397#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23429#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23388#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23113#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23114#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23327#L1131-3 assume !(0 == ~E_9~0); 23328#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23480#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23116#L514-36 assume !(1 == ~m_pc~0); 22825#L514-38 is_master_triggered_~__retres1~0#1 := 0; 22660#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22661#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23155#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22553#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22554#L533-36 assume 1 == ~t1_pc~0; 22834#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22927#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23378#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23193#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22990#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22991#L552-36 assume 1 == ~t2_pc~0; 22548#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22549#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23049#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23320#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22520#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22521#L571-36 assume 1 == ~t3_pc~0; 22908#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22612#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22613#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22804#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23311#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22583#L590-36 assume 1 == ~t4_pc~0; 22584#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23207#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23000#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23001#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23290#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23291#L609-36 assume 1 == ~t5_pc~0; 23168#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22993#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22994#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23335#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 23077#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22884#L628-36 assume 1 == ~t6_pc~0; 22732#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22733#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22783#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22784#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23118#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23119#L647-36 assume 1 == ~t7_pc~0; 23042#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22270#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22271#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22288#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22289#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23208#L666-36 assume !(1 == ~t8_pc~0); 22481#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 22480#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23106#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23107#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22631#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22632#L685-36 assume 1 == ~t9_pc~0; 23093#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22383#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22838#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22839#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22771#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22772#L704-36 assume 1 == ~t10_pc~0; 22370#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22371#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22692#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22693#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22398#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22399#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23382#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23265#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23266#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23443#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22698#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22699#L1179-3 assume !(1 == ~T6_E~0); 23357#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22272#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22273#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22642#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22643#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22963#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22140#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22141#L1219-3 assume !(1 == ~E_3~0); 23162#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23163#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23184#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22411#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22412#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23017#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23389#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23166#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23167#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22220#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22680#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 22681#L1584 assume !(0 == start_simulation_~tmp~3#1); 23124#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22425#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22120#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22172#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 22173#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22751#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23006#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 23007#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 22252#L1565-2 [2023-11-26 10:46:56,715 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:56,715 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2023-11-26 10:46:56,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:56,716 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1503228684] [2023-11-26 10:46:56,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:56,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:56,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:56,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:56,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:56,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1503228684] [2023-11-26 10:46:56,781 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1503228684] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:56,781 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:56,781 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:56,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1875222304] [2023-11-26 10:46:56,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:56,782 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:46:56,783 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:56,783 INFO L85 PathProgramCache]: Analyzing trace with hash 369161907, now seen corresponding path program 1 times [2023-11-26 10:46:56,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:56,784 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522039237] [2023-11-26 10:46:56,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:56,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:56,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:56,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:56,873 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:56,873 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522039237] [2023-11-26 10:46:56,874 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [522039237] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:56,874 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:56,874 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:56,874 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [437501545] [2023-11-26 10:46:56,875 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:56,875 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:46:56,875 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:46:56,876 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:46:56,876 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:46:56,876 INFO L87 Difference]: Start difference. First operand 1377 states and 2036 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:56,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:46:56,922 INFO L93 Difference]: Finished difference Result 1377 states and 2035 transitions. [2023-11-26 10:46:56,922 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2035 transitions. [2023-11-26 10:46:56,934 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:56,948 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2035 transitions. [2023-11-26 10:46:56,948 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-26 10:46:56,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-26 10:46:56,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2035 transitions. [2023-11-26 10:46:56,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:46:56,954 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2035 transitions. [2023-11-26 10:46:56,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2035 transitions. [2023-11-26 10:46:56,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-26 10:46:56,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4778503994190269) internal successors, (2035), 1376 states have internal predecessors, (2035), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:56,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2035 transitions. [2023-11-26 10:46:56,995 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2035 transitions. [2023-11-26 10:46:56,996 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:46:56,997 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2035 transitions. [2023-11-26 10:46:56,997 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 10:46:56,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2035 transitions. [2023-11-26 10:46:57,006 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-26 10:46:57,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:46:57,007 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:46:57,010 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:57,010 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:57,011 INFO L748 eck$LassoCheckResult]: Stem: 25285#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 26162#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26163#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26225#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 26166#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26126#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26127#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26155#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25222#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25223#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25330#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25575#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25501#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25224#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 24885#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24886#L1036 assume !(0 == ~M_E~0); 24983#L1036-2 assume !(0 == ~T1_E~0); 25888#L1041-1 assume !(0 == ~T2_E~0); 25889#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25260#L1051-1 assume !(0 == ~T4_E~0); 25261#L1056-1 assume !(0 == ~T5_E~0); 26017#L1061-1 assume !(0 == ~T6_E~0); 25155#L1066-1 assume !(0 == ~T7_E~0); 25156#L1071-1 assume !(0 == ~T8_E~0); 25999#L1076-1 assume !(0 == ~T9_E~0); 25045#L1081-1 assume !(0 == ~T10_E~0); 25046#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 25446#L1091-1 assume !(0 == ~E_1~0); 26173#L1096-1 assume !(0 == ~E_2~0); 26174#L1101-1 assume !(0 == ~E_3~0); 25514#L1106-1 assume !(0 == ~E_4~0); 25515#L1111-1 assume !(0 == ~E_5~0); 25679#L1116-1 assume !(0 == ~E_6~0); 25680#L1121-1 assume !(0 == ~E_7~0); 25505#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25506#L1131-1 assume !(0 == ~E_9~0); 25781#L1136-1 assume !(0 == ~E_10~0); 25896#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26045#L514 assume 1 == ~m_pc~0; 26010#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25523#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25524#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26097#L1285 assume !(0 != activate_threads_~tmp~1#1); 26209#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25174#L533 assume !(1 == ~t1_pc~0); 25175#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25694#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24938#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24939#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 25917#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25918#L552 assume 1 == ~t2_pc~0; 25394#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25395#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25509#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25510#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 25539#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25540#L571 assume 1 == ~t3_pc~0; 25732#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25733#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24883#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24884#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 25684#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24969#L590 assume !(1 == ~t4_pc~0); 24970#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25742#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25063#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25064#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25945#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25681#L609 assume 1 == ~t5_pc~0; 25682#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26207#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26099#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26100#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 25673#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25674#L628 assume !(1 == ~t6_pc~0); 25606#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25605#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25482#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25483#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 25979#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25980#L647 assume 1 == ~t7_pc~0; 25516#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25517#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26108#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25519#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 25520#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26236#L666 assume !(1 == ~t8_pc~0); 25307#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25308#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25535#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25705#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 25443#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25444#L685 assume 1 == ~t9_pc~0; 26215#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26116#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25569#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25473#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 25474#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25859#L704 assume !(1 == ~t10_pc~0); 25463#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25462#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25724#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25017#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 25018#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25269#L1154 assume !(1 == ~M_E~0); 25967#L1154-2 assume !(1 == ~T1_E~0); 25243#L1159-1 assume !(1 == ~T2_E~0); 25244#L1164-1 assume !(1 == ~T3_E~0); 25703#L1169-1 assume !(1 == ~T4_E~0); 25570#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25372#L1179-1 assume !(1 == ~T6_E~0); 25228#L1184-1 assume !(1 == ~T7_E~0); 25229#L1189-1 assume !(1 == ~T8_E~0); 25305#L1194-1 assume !(1 == ~T9_E~0); 25430#L1199-1 assume !(1 == ~T10_E~0); 25384#L1204-1 assume !(1 == ~E_M~0); 25385#L1209-1 assume !(1 == ~E_1~0); 25940#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25941#L1219-1 assume !(1 == ~E_3~0); 26229#L1224-1 assume !(1 == ~E_4~0); 25727#L1229-1 assume !(1 == ~E_5~0); 25112#L1234-1 assume !(1 == ~E_6~0); 25113#L1239-1 assume !(1 == ~E_7~0); 25170#L1244-1 assume !(1 == ~E_8~0); 25171#L1249-1 assume !(1 == ~E_9~0); 26008#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 25012#L1259-1 assume { :end_inline_reset_delta_events } true; 25013#L1565-2 [2023-11-26 10:46:57,012 INFO L750 eck$LassoCheckResult]: Loop: 25013#L1565-2 assume !false; 25946#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25712#L1011-1 assume !false; 25675#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25448#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 25211#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25548#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25238#L866 assume !(0 != eval_~tmp~0#1); 25240#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25744#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25745#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26012#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26191#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26073#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26074#L1051-3 assume !(0 == ~T4_E~0); 26013#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25257#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25258#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25259#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26193#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25004#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25005#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25055#L1091-3 assume !(0 == ~E_1~0); 25056#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26157#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26158#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26190#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26149#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25874#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25875#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26088#L1131-3 assume !(0 == ~E_9~0); 26089#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26241#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25877#L514-36 assume !(1 == ~m_pc~0); 25586#L514-38 is_master_triggered_~__retres1~0#1 := 0; 25421#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25422#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25916#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25314#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25315#L533-36 assume 1 == ~t1_pc~0; 25595#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25688#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26139#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25954#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25751#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25752#L552-36 assume 1 == ~t2_pc~0; 25309#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25310#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25810#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26081#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25281#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25282#L571-36 assume 1 == ~t3_pc~0; 25669#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25373#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25374#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25565#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26072#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25346#L590-36 assume 1 == ~t4_pc~0; 25347#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25968#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25762#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25763#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26051#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26052#L609-36 assume 1 == ~t5_pc~0; 25929#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25754#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25755#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26096#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 25838#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25645#L628-36 assume 1 == ~t6_pc~0; 25493#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25494#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25544#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25545#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25879#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25880#L647-36 assume 1 == ~t7_pc~0; 25803#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25031#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25032#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25049#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25050#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25969#L666-36 assume 1 == ~t8_pc~0; 25235#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25236#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25867#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25868#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25392#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25393#L685-36 assume !(1 == ~t9_pc~0); 25141#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 25142#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25598#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25599#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25532#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25533#L704-36 assume 1 == ~t10_pc~0; 25131#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25132#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25453#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25454#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25157#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25158#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26143#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26026#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26027#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26204#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25459#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25460#L1179-3 assume !(1 == ~T6_E~0); 26118#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25033#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25034#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25403#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25404#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25723#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24901#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24902#L1219-3 assume !(1 == ~E_3~0); 25923#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25924#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25944#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25172#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25173#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25774#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 26150#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25927#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25928#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24981#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25441#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25442#L1584 assume !(0 == start_simulation_~tmp~3#1); 25885#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25186#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24881#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24933#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 24934#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25511#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25767#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25768#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 25013#L1565-2 [2023-11-26 10:46:57,013 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:57,013 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2023-11-26 10:46:57,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:57,014 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230923358] [2023-11-26 10:46:57,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:57,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:57,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:57,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:57,137 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:57,137 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230923358] [2023-11-26 10:46:57,137 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1230923358] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:57,137 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:57,137 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:57,138 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127575864] [2023-11-26 10:46:57,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:57,139 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:46:57,140 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:57,140 INFO L85 PathProgramCache]: Analyzing trace with hash -1250501773, now seen corresponding path program 1 times [2023-11-26 10:46:57,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:57,141 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [168565609] [2023-11-26 10:46:57,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:57,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:57,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:57,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:57,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:57,232 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [168565609] [2023-11-26 10:46:57,232 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [168565609] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:57,232 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:57,233 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:57,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1487925604] [2023-11-26 10:46:57,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:57,233 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:46:57,234 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:46:57,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:46:57,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:46:57,235 INFO L87 Difference]: Start difference. First operand 1377 states and 2035 transitions. cyclomatic complexity: 659 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:57,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:46:57,457 INFO L93 Difference]: Finished difference Result 2536 states and 3734 transitions. [2023-11-26 10:46:57,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2536 states and 3734 transitions. [2023-11-26 10:46:57,478 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2375 [2023-11-26 10:46:57,503 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2536 states to 2536 states and 3734 transitions. [2023-11-26 10:46:57,503 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2536 [2023-11-26 10:46:57,506 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2536 [2023-11-26 10:46:57,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2536 states and 3734 transitions. [2023-11-26 10:46:57,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:46:57,511 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2536 states and 3734 transitions. [2023-11-26 10:46:57,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2536 states and 3734 transitions. [2023-11-26 10:46:57,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2536 to 2536. [2023-11-26 10:46:57,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2536 states, 2536 states have (on average 1.472397476340694) internal successors, (3734), 2535 states have internal predecessors, (3734), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:57,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2536 states to 2536 states and 3734 transitions. [2023-11-26 10:46:57,574 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2536 states and 3734 transitions. [2023-11-26 10:46:57,575 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:46:57,575 INFO L428 stractBuchiCegarLoop]: Abstraction has 2536 states and 3734 transitions. [2023-11-26 10:46:57,576 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 10:46:57,576 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2536 states and 3734 transitions. [2023-11-26 10:46:57,589 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2375 [2023-11-26 10:46:57,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:46:57,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:46:57,593 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:57,593 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:57,593 INFO L748 eck$LassoCheckResult]: Stem: 29208#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 29209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 30090#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30091#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30162#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 30094#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30054#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30055#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30083#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29145#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29146#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29253#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29499#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29424#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29147#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 28808#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28809#L1036 assume !(0 == ~M_E~0); 28906#L1036-2 assume !(0 == ~T1_E~0); 29813#L1041-1 assume !(0 == ~T2_E~0); 29814#L1046-1 assume !(0 == ~T3_E~0); 29183#L1051-1 assume !(0 == ~T4_E~0); 29184#L1056-1 assume !(0 == ~T5_E~0); 29944#L1061-1 assume !(0 == ~T6_E~0); 29078#L1066-1 assume !(0 == ~T7_E~0); 29079#L1071-1 assume !(0 == ~T8_E~0); 29926#L1076-1 assume !(0 == ~T9_E~0); 28968#L1081-1 assume !(0 == ~T10_E~0); 28969#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 29369#L1091-1 assume !(0 == ~E_1~0); 30101#L1096-1 assume !(0 == ~E_2~0); 30102#L1101-1 assume !(0 == ~E_3~0); 29437#L1106-1 assume !(0 == ~E_4~0); 29438#L1111-1 assume !(0 == ~E_5~0); 29604#L1116-1 assume !(0 == ~E_6~0); 29605#L1121-1 assume !(0 == ~E_7~0); 29428#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 29429#L1131-1 assume !(0 == ~E_9~0); 29706#L1136-1 assume !(0 == ~E_10~0); 29821#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29972#L514 assume 1 == ~m_pc~0; 29937#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29446#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29447#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30024#L1285 assume !(0 != activate_threads_~tmp~1#1); 30141#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29097#L533 assume !(1 == ~t1_pc~0); 29098#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29619#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28861#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28862#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 29842#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29843#L552 assume 1 == ~t2_pc~0; 29317#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29318#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29432#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29433#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 29459#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29460#L571 assume 1 == ~t3_pc~0; 29657#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29658#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28806#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28807#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 29609#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28892#L590 assume !(1 == ~t4_pc~0); 28893#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29667#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28986#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28987#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29869#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29606#L609 assume 1 == ~t5_pc~0; 29607#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30139#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30026#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30027#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 29598#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29599#L628 assume !(1 == ~t6_pc~0); 29531#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29530#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29405#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29406#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 29906#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29907#L647 assume 1 == ~t7_pc~0; 29439#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29440#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30036#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29442#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 29443#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30176#L666 assume !(1 == ~t8_pc~0); 29230#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29231#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29458#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29630#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 29366#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29367#L685 assume 1 == ~t9_pc~0; 30150#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30044#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29493#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29396#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 29397#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29784#L704 assume !(1 == ~t10_pc~0); 29386#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29385#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29648#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28940#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 28941#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29192#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 29893#L1154-2 assume !(1 == ~T1_E~0); 31020#L1159-1 assume !(1 == ~T2_E~0); 31018#L1164-1 assume !(1 == ~T3_E~0); 30184#L1169-1 assume !(1 == ~T4_E~0); 31015#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31013#L1179-1 assume !(1 == ~T6_E~0); 31010#L1184-1 assume !(1 == ~T7_E~0); 31008#L1189-1 assume !(1 == ~T8_E~0); 31006#L1194-1 assume !(1 == ~T9_E~0); 31004#L1199-1 assume !(1 == ~T10_E~0); 30276#L1204-1 assume !(1 == ~E_M~0); 30264#L1209-1 assume !(1 == ~E_1~0); 30262#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30260#L1219-1 assume !(1 == ~E_3~0); 30258#L1224-1 assume !(1 == ~E_4~0); 30256#L1229-1 assume !(1 == ~E_5~0); 30253#L1234-1 assume !(1 == ~E_6~0); 30251#L1239-1 assume !(1 == ~E_7~0); 30249#L1244-1 assume !(1 == ~E_8~0); 30248#L1249-1 assume !(1 == ~E_9~0); 30231#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30222#L1259-1 assume { :end_inline_reset_delta_events } true; 30215#L1565-2 [2023-11-26 10:46:57,594 INFO L750 eck$LassoCheckResult]: Loop: 30215#L1565-2 assume !false; 30211#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30207#L1011-1 assume !false; 30206#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30205#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30194#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30193#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30191#L866 assume !(0 != eval_~tmp~0#1); 30190#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30189#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30188#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30120#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30121#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30000#L1046-3 assume !(0 == ~T3_E~0); 30001#L1051-3 assume !(0 == ~T4_E~0); 29940#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29180#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29181#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29182#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30123#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28927#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28928#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28978#L1091-3 assume !(0 == ~E_1~0); 28979#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31000#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30998#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30996#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30994#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30992#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30989#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30987#L1131-3 assume !(0 == ~E_9~0); 30985#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30983#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30981#L514-36 assume !(1 == ~m_pc~0); 30978#L514-38 is_master_triggered_~__retres1~0#1 := 0; 30975#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30973#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30971#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30969#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30967#L533-36 assume 1 == ~t1_pc~0; 30964#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30961#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30959#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30957#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30955#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30953#L552-36 assume !(1 == ~t2_pc~0); 30950#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 30947#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30945#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30943#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30941#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30939#L571-36 assume 1 == ~t3_pc~0; 30936#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30933#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30931#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30929#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30927#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30925#L590-36 assume !(1 == ~t4_pc~0); 30922#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 30919#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30917#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30915#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30914#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30913#L609-36 assume !(1 == ~t5_pc~0); 30912#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 30910#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30909#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30908#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 30907#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30906#L628-36 assume 1 == ~t6_pc~0; 30904#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30903#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30902#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30901#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30900#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30899#L647-36 assume 1 == ~t7_pc~0; 30897#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30896#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30895#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30894#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30893#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30892#L666-36 assume 1 == ~t8_pc~0; 30889#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30887#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30885#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30883#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30880#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30878#L685-36 assume !(1 == ~t9_pc~0); 30875#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 30873#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30871#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30869#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30866#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30864#L704-36 assume 1 == ~t10_pc~0; 30861#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30859#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30857#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30855#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30852#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30850#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30187#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30847#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30845#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30185#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30841#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30839#L1179-3 assume !(1 == ~T6_E~0); 30837#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30835#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30833#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30831#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30828#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30827#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30826#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30825#L1219-3 assume !(1 == ~E_3~0); 30824#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30823#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30822#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30821#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30820#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30819#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30818#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30817#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30719#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30717#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30715#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30671#L1584 assume !(0 == start_simulation_~tmp~3#1); 30181#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30274#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30263#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30261#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 30259#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30257#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30232#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 30223#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 30215#L1565-2 [2023-11-26 10:46:57,596 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:57,596 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2023-11-26 10:46:57,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:57,596 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1788060061] [2023-11-26 10:46:57,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:57,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:57,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:57,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:57,694 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:57,694 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1788060061] [2023-11-26 10:46:57,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1788060061] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:57,695 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:57,695 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:57,695 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [161266655] [2023-11-26 10:46:57,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:57,696 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:46:57,697 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:57,697 INFO L85 PathProgramCache]: Analyzing trace with hash -1651803656, now seen corresponding path program 1 times [2023-11-26 10:46:57,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:57,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1734972495] [2023-11-26 10:46:57,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:57,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:57,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:57,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:57,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:57,821 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1734972495] [2023-11-26 10:46:57,822 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1734972495] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:57,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:57,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:57,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114124774] [2023-11-26 10:46:57,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:57,823 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:46:57,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:46:57,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:46:57,824 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:46:57,824 INFO L87 Difference]: Start difference. First operand 2536 states and 3734 transitions. cyclomatic complexity: 1200 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:58,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:46:58,068 INFO L93 Difference]: Finished difference Result 4684 states and 6883 transitions. [2023-11-26 10:46:58,068 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4684 states and 6883 transitions. [2023-11-26 10:46:58,103 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4491 [2023-11-26 10:46:58,143 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4684 states to 4684 states and 6883 transitions. [2023-11-26 10:46:58,143 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4684 [2023-11-26 10:46:58,149 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4684 [2023-11-26 10:46:58,149 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4684 states and 6883 transitions. [2023-11-26 10:46:58,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:46:58,156 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4684 states and 6883 transitions. [2023-11-26 10:46:58,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4684 states and 6883 transitions. [2023-11-26 10:46:58,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4684 to 4682. [2023-11-26 10:46:58,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4682 states, 4682 states have (on average 1.4696710807347289) internal successors, (6881), 4681 states have internal predecessors, (6881), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:58,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4682 states to 4682 states and 6881 transitions. [2023-11-26 10:46:58,283 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4682 states and 6881 transitions. [2023-11-26 10:46:58,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:46:58,284 INFO L428 stractBuchiCegarLoop]: Abstraction has 4682 states and 6881 transitions. [2023-11-26 10:46:58,285 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 10:46:58,285 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4682 states and 6881 transitions. [2023-11-26 10:46:58,310 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4491 [2023-11-26 10:46:58,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:46:58,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:46:58,313 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:58,313 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:58,314 INFO L748 eck$LassoCheckResult]: Stem: 36439#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36440#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 37389#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37390#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37463#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 37393#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37341#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37342#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37381#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36377#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36378#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36485#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36742#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36664#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36379#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36038#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36039#L1036 assume !(0 == ~M_E~0); 36136#L1036-2 assume !(0 == ~T1_E~0); 37070#L1041-1 assume !(0 == ~T2_E~0); 37071#L1046-1 assume !(0 == ~T3_E~0); 36414#L1051-1 assume !(0 == ~T4_E~0); 36415#L1056-1 assume !(0 == ~T5_E~0); 37209#L1061-1 assume !(0 == ~T6_E~0); 36308#L1066-1 assume !(0 == ~T7_E~0); 36309#L1071-1 assume !(0 == ~T8_E~0); 37190#L1076-1 assume !(0 == ~T9_E~0); 36198#L1081-1 assume !(0 == ~T10_E~0); 36199#L1086-1 assume !(0 == ~E_M~0); 36608#L1091-1 assume !(0 == ~E_1~0); 37401#L1096-1 assume !(0 == ~E_2~0); 37402#L1101-1 assume !(0 == ~E_3~0); 36677#L1106-1 assume !(0 == ~E_4~0); 36678#L1111-1 assume !(0 == ~E_5~0); 36854#L1116-1 assume !(0 == ~E_6~0); 36855#L1121-1 assume !(0 == ~E_7~0); 36668#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36669#L1131-1 assume !(0 == ~E_9~0); 36960#L1136-1 assume !(0 == ~E_10~0); 37078#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37245#L514 assume 1 == ~m_pc~0; 37201#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36686#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36687#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37305#L1285 assume !(0 != activate_threads_~tmp~1#1); 37447#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36330#L533 assume !(1 == ~t1_pc~0); 36331#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36869#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36093#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36094#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 37099#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37100#L552 assume 1 == ~t2_pc~0; 36556#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36557#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36672#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36673#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 36706#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36707#L571 assume 1 == ~t3_pc~0; 36913#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36914#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36036#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36037#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 36859#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36122#L590 assume !(1 == ~t4_pc~0); 36123#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36922#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36216#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36217#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37131#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36856#L609 assume 1 == ~t5_pc~0; 36857#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37442#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37306#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37307#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 36848#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36849#L628 assume !(1 == ~t6_pc~0); 36776#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36775#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36648#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36649#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 37168#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37169#L647 assume 1 == ~t7_pc~0; 36679#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36680#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37315#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36684#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 36685#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37484#L666 assume !(1 == ~t8_pc~0); 36462#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36463#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36698#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36883#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 36606#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36607#L685 assume 1 == ~t9_pc~0; 37450#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37330#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36735#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36635#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 36636#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37040#L704 assume !(1 == ~t10_pc~0); 36625#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36624#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36903#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36170#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 36171#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36423#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 37154#L1154-2 assume !(1 == ~T1_E~0); 37470#L1159-1 assume !(1 == ~T2_E~0); 37496#L1164-1 assume !(1 == ~T3_E~0); 36879#L1169-1 assume !(1 == ~T4_E~0); 36880#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36532#L1179-1 assume !(1 == ~T6_E~0); 36533#L1184-1 assume !(1 == ~T7_E~0); 36459#L1189-1 assume !(1 == ~T8_E~0); 36460#L1194-1 assume !(1 == ~T9_E~0); 37507#L1199-1 assume !(1 == ~T10_E~0); 37508#L1204-1 assume !(1 == ~E_M~0); 37580#L1209-1 assume !(1 == ~E_1~0); 37577#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 37575#L1219-1 assume !(1 == ~E_3~0); 37573#L1224-1 assume !(1 == ~E_4~0); 37571#L1229-1 assume !(1 == ~E_5~0); 37569#L1234-1 assume !(1 == ~E_6~0); 37565#L1239-1 assume !(1 == ~E_7~0); 37563#L1244-1 assume !(1 == ~E_8~0); 37561#L1249-1 assume !(1 == ~E_9~0); 37558#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 37548#L1259-1 assume { :end_inline_reset_delta_events } true; 37541#L1565-2 [2023-11-26 10:46:58,315 INFO L750 eck$LassoCheckResult]: Loop: 37541#L1565-2 assume !false; 37535#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37531#L1011-1 assume !false; 37530#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37529#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37518#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37517#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37515#L866 assume !(0 != eval_~tmp~0#1); 37514#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37513#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37512#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37425#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37426#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37495#L1046-3 assume !(0 == ~T3_E~0); 39886#L1051-3 assume !(0 == ~T4_E~0); 37204#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36411#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36412#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36413#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37427#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36157#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36158#L1086-3 assume !(0 == ~E_M~0); 36212#L1091-3 assume !(0 == ~E_1~0); 36213#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37383#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37384#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37423#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37373#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37055#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37056#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37294#L1131-3 assume !(0 == ~E_9~0); 37295#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37492#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37057#L514-36 assume 1 == ~m_pc~0; 37058#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36582#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36583#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37098#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36469#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36470#L533-36 assume 1 == ~t1_pc~0; 36762#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36863#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37357#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37141#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36930#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36931#L552-36 assume 1 == ~t2_pc~0; 36464#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36465#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36989#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37286#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36435#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36436#L571-36 assume 1 == ~t3_pc~0; 36844#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36530#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36531#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36731#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37277#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36499#L590-36 assume 1 == ~t4_pc~0; 36500#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37156#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36940#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36941#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37251#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37252#L609-36 assume !(1 == ~t5_pc~0); 37418#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 39832#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39831#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39830#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 39829#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39828#L628-36 assume 1 == ~t6_pc~0; 36656#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36657#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36709#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36710#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37060#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37061#L647-36 assume 1 == ~t7_pc~0; 36982#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36184#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36185#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36202#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36203#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37157#L666-36 assume 1 == ~t8_pc~0; 36391#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36392#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37048#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37049#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36553#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36554#L685-36 assume !(1 == ~t9_pc~0); 36296#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 36297#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36769#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36770#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38589#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38586#L704-36 assume 1 == ~t10_pc~0; 38579#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38570#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36615#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36616#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38562#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38557#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37361#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37362#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38548#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38544#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38540#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38534#L1179-3 assume !(1 == ~T6_E~0); 38530#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38526#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38522#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36564#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36565#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38506#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38503#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38500#L1219-3 assume !(1 == ~E_3~0); 38497#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38494#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38491#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38485#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38480#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38476#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38472#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 38468#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 38065#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 38052#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 38041#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 38029#L1584 assume !(0 == start_simulation_~tmp~3#1); 37491#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37619#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37607#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37605#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 37603#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37599#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37596#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 37549#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 37541#L1565-2 [2023-11-26 10:46:58,316 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:58,316 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2023-11-26 10:46:58,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:58,317 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121301249] [2023-11-26 10:46:58,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:58,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:58,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:58,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:58,431 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:58,432 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2121301249] [2023-11-26 10:46:58,432 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2121301249] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:58,432 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:58,432 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:58,432 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1624495823] [2023-11-26 10:46:58,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:58,433 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:46:58,433 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:58,434 INFO L85 PathProgramCache]: Analyzing trace with hash 39360823, now seen corresponding path program 1 times [2023-11-26 10:46:58,434 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:58,434 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117232657] [2023-11-26 10:46:58,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:58,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:58,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:58,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:58,512 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:58,512 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1117232657] [2023-11-26 10:46:58,513 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1117232657] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:58,513 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:58,513 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:58,513 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [792637205] [2023-11-26 10:46:58,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:58,514 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:46:58,514 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:46:58,514 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:46:58,515 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:46:58,515 INFO L87 Difference]: Start difference. First operand 4682 states and 6881 transitions. cyclomatic complexity: 2203 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:58,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:46:58,785 INFO L93 Difference]: Finished difference Result 8780 states and 12872 transitions. [2023-11-26 10:46:58,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8780 states and 12872 transitions. [2023-11-26 10:46:58,842 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8565 [2023-11-26 10:46:58,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8780 states to 8780 states and 12872 transitions. [2023-11-26 10:46:58,898 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8780 [2023-11-26 10:46:58,908 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8780 [2023-11-26 10:46:58,908 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8780 states and 12872 transitions. [2023-11-26 10:46:58,922 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:46:58,922 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8780 states and 12872 transitions. [2023-11-26 10:46:58,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8780 states and 12872 transitions. [2023-11-26 10:46:59,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8780 to 8776. [2023-11-26 10:46:59,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8776 states, 8776 states have (on average 1.466271649954421) internal successors, (12868), 8775 states have internal predecessors, (12868), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:59,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8776 states to 8776 states and 12868 transitions. [2023-11-26 10:46:59,255 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8776 states and 12868 transitions. [2023-11-26 10:46:59,256 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:46:59,257 INFO L428 stractBuchiCegarLoop]: Abstraction has 8776 states and 12868 transitions. [2023-11-26 10:46:59,258 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 10:46:59,258 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8776 states and 12868 transitions. [2023-11-26 10:46:59,304 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8565 [2023-11-26 10:46:59,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:46:59,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:46:59,307 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:59,307 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:46:59,308 INFO L748 eck$LassoCheckResult]: Stem: 49914#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 49915#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 50857#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50858#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50935#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 50861#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50816#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50817#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50848#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49849#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49850#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49960#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50216#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50137#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49851#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49510#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49511#L1036 assume !(0 == ~M_E~0); 49608#L1036-2 assume !(0 == ~T1_E~0); 50544#L1041-1 assume !(0 == ~T2_E~0); 50545#L1046-1 assume !(0 == ~T3_E~0); 49889#L1051-1 assume !(0 == ~T4_E~0); 49890#L1056-1 assume !(0 == ~T5_E~0); 50691#L1061-1 assume !(0 == ~T6_E~0); 49780#L1066-1 assume !(0 == ~T7_E~0); 49781#L1071-1 assume !(0 == ~T8_E~0); 50673#L1076-1 assume !(0 == ~T9_E~0); 49670#L1081-1 assume !(0 == ~T10_E~0); 49671#L1086-1 assume !(0 == ~E_M~0); 50080#L1091-1 assume !(0 == ~E_1~0); 50869#L1096-1 assume !(0 == ~E_2~0); 50870#L1101-1 assume !(0 == ~E_3~0); 50150#L1106-1 assume !(0 == ~E_4~0); 50151#L1111-1 assume !(0 == ~E_5~0); 50327#L1116-1 assume !(0 == ~E_6~0); 50328#L1121-1 assume !(0 == ~E_7~0); 50141#L1126-1 assume !(0 == ~E_8~0); 50142#L1131-1 assume !(0 == ~E_9~0); 50436#L1136-1 assume !(0 == ~E_10~0); 50553#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50724#L514 assume 1 == ~m_pc~0; 50684#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 50159#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50160#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50780#L1285 assume !(0 != activate_threads_~tmp~1#1); 50911#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49800#L533 assume !(1 == ~t1_pc~0); 49801#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50342#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49563#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49564#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 50576#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50577#L552 assume 1 == ~t2_pc~0; 50026#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50027#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50145#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50146#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 50172#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50173#L571 assume 1 == ~t3_pc~0; 50386#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50387#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49508#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49509#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 50332#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49594#L590 assume !(1 == ~t4_pc~0); 49595#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 50396#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49688#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49689#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50608#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50329#L609 assume 1 == ~t5_pc~0; 50330#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50909#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50784#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50785#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 50321#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50322#L628 assume !(1 == ~t6_pc~0); 50252#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50251#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50118#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50119#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 50650#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50651#L647 assume 1 == ~t7_pc~0; 50152#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50153#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50794#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50155#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 50156#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50952#L666 assume !(1 == ~t8_pc~0); 49937#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49938#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50171#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50355#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 50077#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50078#L685 assume 1 == ~t9_pc~0; 50920#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50804#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50209#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50107#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 50108#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50515#L704 assume !(1 == ~t10_pc~0); 50097#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50096#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50376#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49642#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 49643#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49898#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 50637#L1154-2 assume !(1 == ~T1_E~0); 50938#L1159-1 assume !(1 == ~T2_E~0); 50967#L1164-1 assume !(1 == ~T3_E~0); 50352#L1169-1 assume !(1 == ~T4_E~0); 50353#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50002#L1179-1 assume !(1 == ~T6_E~0); 50003#L1184-1 assume !(1 == ~T7_E~0); 49934#L1189-1 assume !(1 == ~T8_E~0); 49935#L1194-1 assume !(1 == ~T9_E~0); 50981#L1199-1 assume !(1 == ~T10_E~0); 50982#L1204-1 assume !(1 == ~E_M~0); 51061#L1209-1 assume !(1 == ~E_1~0); 51057#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 51054#L1219-1 assume !(1 == ~E_3~0); 51051#L1224-1 assume !(1 == ~E_4~0); 51048#L1229-1 assume !(1 == ~E_5~0); 51045#L1234-1 assume !(1 == ~E_6~0); 51041#L1239-1 assume !(1 == ~E_7~0); 51038#L1244-1 assume !(1 == ~E_8~0); 51034#L1249-1 assume !(1 == ~E_9~0); 51031#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 51022#L1259-1 assume { :end_inline_reset_delta_events } true; 51015#L1565-2 [2023-11-26 10:46:59,308 INFO L750 eck$LassoCheckResult]: Loop: 51015#L1565-2 assume !false; 51009#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51005#L1011-1 assume !false; 51004#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51003#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50992#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50991#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 50989#L866 assume !(0 != eval_~tmp~0#1); 50988#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50987#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50985#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50986#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53502#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53500#L1046-3 assume !(0 == ~T3_E~0); 53498#L1051-3 assume !(0 == ~T4_E~0); 53496#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53494#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53491#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53489#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53487#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53485#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53483#L1086-3 assume !(0 == ~E_M~0); 53481#L1091-3 assume !(0 == ~E_1~0); 53478#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53476#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53474#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53472#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53470#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53468#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53465#L1126-3 assume !(0 == ~E_8~0); 53463#L1131-3 assume !(0 == ~E_9~0); 53461#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53459#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53158#L514-36 assume !(1 == ~m_pc~0); 53154#L514-38 is_master_triggered_~__retres1~0#1 := 0; 53152#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53150#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53148#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53146#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53143#L533-36 assume 1 == ~t1_pc~0; 53139#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53136#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53134#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53132#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53130#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53128#L552-36 assume !(1 == ~t2_pc~0); 53125#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 53124#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53121#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53119#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53117#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53115#L571-36 assume 1 == ~t3_pc~0; 53112#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53110#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53107#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53105#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53103#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53101#L590-36 assume !(1 == ~t4_pc~0); 53098#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 53096#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53095#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53093#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53090#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53089#L609-36 assume 1 == ~t5_pc~0; 53086#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53084#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53082#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52624#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 52620#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52618#L628-36 assume 1 == ~t6_pc~0; 52615#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52614#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52613#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52610#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 52608#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52606#L647-36 assume 1 == ~t7_pc~0; 52604#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52197#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52194#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52192#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52190#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52188#L666-36 assume 1 == ~t8_pc~0; 52185#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52183#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52180#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52178#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52176#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52174#L685-36 assume !(1 == ~t9_pc~0); 52168#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 52166#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52164#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52162#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52160#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52158#L704-36 assume 1 == ~t10_pc~0; 52154#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52152#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52150#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52148#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 52146#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52144#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50978#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52141#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52140#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50971#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52085#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52079#L1179-3 assume !(1 == ~T6_E~0); 52069#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 52063#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52057#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52051#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52045#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 52038#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51436#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51434#L1219-3 assume !(1 == ~E_3~0); 51177#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51175#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51166#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51160#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51155#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 51149#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51145#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51137#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51121#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51118#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51115#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 51112#L1584 assume !(0 == start_simulation_~tmp~3#1); 50962#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51107#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51096#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51093#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 51091#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51089#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51087#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 51023#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 51015#L1565-2 [2023-11-26 10:46:59,309 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:59,309 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2023-11-26 10:46:59,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:59,310 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310485122] [2023-11-26 10:46:59,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:59,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:59,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:59,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:59,400 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:59,400 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310485122] [2023-11-26 10:46:59,401 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [310485122] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:59,401 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:59,401 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:46:59,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1467497512] [2023-11-26 10:46:59,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:59,403 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:46:59,403 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:46:59,403 INFO L85 PathProgramCache]: Analyzing trace with hash -2145863301, now seen corresponding path program 1 times [2023-11-26 10:46:59,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:46:59,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2071345899] [2023-11-26 10:46:59,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:46:59,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:46:59,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:46:59,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:46:59,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:46:59,473 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2071345899] [2023-11-26 10:46:59,473 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2071345899] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:46:59,474 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:46:59,474 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:46:59,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [59395643] [2023-11-26 10:46:59,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:46:59,475 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:46:59,475 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:46:59,476 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:46:59,476 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:46:59,477 INFO L87 Difference]: Start difference. First operand 8776 states and 12868 transitions. cyclomatic complexity: 4100 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:46:59,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:46:59,785 INFO L93 Difference]: Finished difference Result 17195 states and 25019 transitions. [2023-11-26 10:46:59,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17195 states and 25019 transitions. [2023-11-26 10:46:59,879 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16969 [2023-11-26 10:46:59,948 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17195 states to 17195 states and 25019 transitions. [2023-11-26 10:46:59,948 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17195 [2023-11-26 10:46:59,964 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17195 [2023-11-26 10:46:59,964 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17195 states and 25019 transitions. [2023-11-26 10:46:59,981 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:46:59,981 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17195 states and 25019 transitions. [2023-11-26 10:47:00,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17195 states and 25019 transitions. [2023-11-26 10:47:00,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17195 to 16587. [2023-11-26 10:47:00,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16587 states, 16587 states have (on average 1.4567432326520768) internal successors, (24163), 16586 states have internal predecessors, (24163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:00,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16587 states to 16587 states and 24163 transitions. [2023-11-26 10:47:00,522 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16587 states and 24163 transitions. [2023-11-26 10:47:00,522 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:47:00,523 INFO L428 stractBuchiCegarLoop]: Abstraction has 16587 states and 24163 transitions. [2023-11-26 10:47:00,523 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 10:47:00,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16587 states and 24163 transitions. [2023-11-26 10:47:00,592 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16361 [2023-11-26 10:47:00,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:00,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:00,595 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:00,595 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:00,596 INFO L748 eck$LassoCheckResult]: Stem: 75899#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 75900#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 76948#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76949#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77050#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 76953#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76883#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76884#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76939#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75831#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75832#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75946#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76206#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76128#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75833#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 75488#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75489#L1036 assume !(0 == ~M_E~0); 75586#L1036-2 assume !(0 == ~T1_E~0); 76558#L1041-1 assume !(0 == ~T2_E~0); 76559#L1046-1 assume !(0 == ~T3_E~0); 75873#L1051-1 assume !(0 == ~T4_E~0); 75874#L1056-1 assume !(0 == ~T5_E~0); 76719#L1061-1 assume !(0 == ~T6_E~0); 75759#L1066-1 assume !(0 == ~T7_E~0); 75760#L1071-1 assume !(0 == ~T8_E~0); 76700#L1076-1 assume !(0 == ~T9_E~0); 75647#L1081-1 assume !(0 == ~T10_E~0); 75648#L1086-1 assume !(0 == ~E_M~0); 76073#L1091-1 assume !(0 == ~E_1~0); 76962#L1096-1 assume !(0 == ~E_2~0); 76963#L1101-1 assume !(0 == ~E_3~0); 76141#L1106-1 assume !(0 == ~E_4~0); 76142#L1111-1 assume !(0 == ~E_5~0); 76318#L1116-1 assume !(0 == ~E_6~0); 76319#L1121-1 assume !(0 == ~E_7~0); 76132#L1126-1 assume !(0 == ~E_8~0); 76133#L1131-1 assume !(0 == ~E_9~0); 76428#L1136-1 assume !(0 == ~E_10~0); 76574#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76761#L514 assume !(1 == ~m_pc~0); 76762#L514-2 is_master_triggered_~__retres1~0#1 := 0; 76150#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76151#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76844#L1285 assume !(0 != activate_threads_~tmp~1#1); 77022#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75781#L533 assume !(1 == ~t1_pc~0); 75782#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76333#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75543#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75544#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 76600#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76601#L552 assume 1 == ~t2_pc~0; 76017#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76018#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76136#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76137#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 76170#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76171#L571 assume 1 == ~t3_pc~0; 76378#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76379#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75486#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75487#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 76323#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75572#L590 assume !(1 == ~t4_pc~0); 75573#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76387#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75665#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75666#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76637#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76320#L609 assume 1 == ~t5_pc~0; 76321#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77015#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76845#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76846#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 76312#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76313#L628 assume !(1 == ~t6_pc~0); 76240#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76239#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76112#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76113#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 76678#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76679#L647 assume 1 == ~t7_pc~0; 76143#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76144#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76855#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76148#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 76149#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77076#L666 assume !(1 == ~t8_pc~0); 75923#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75924#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76163#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76346#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 76070#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76071#L685 assume 1 == ~t9_pc~0; 77028#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76866#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76200#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76098#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 76099#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76523#L704 assume !(1 == ~t10_pc~0); 76089#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76088#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76367#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 75619#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 75620#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75881#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 76665#L1154-2 assume !(1 == ~T1_E~0); 75852#L1159-1 assume !(1 == ~T2_E~0); 75853#L1164-1 assume !(1 == ~T3_E~0); 76343#L1169-1 assume !(1 == ~T4_E~0); 76201#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75995#L1179-1 assume !(1 == ~T6_E~0); 75837#L1184-1 assume !(1 == ~T7_E~0); 75838#L1189-1 assume !(1 == ~T8_E~0); 75921#L1194-1 assume !(1 == ~T9_E~0); 76056#L1199-1 assume !(1 == ~T10_E~0); 76008#L1204-1 assume !(1 == ~E_M~0); 76009#L1209-1 assume !(1 == ~E_1~0); 91065#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 91063#L1219-1 assume !(1 == ~E_3~0); 91061#L1224-1 assume !(1 == ~E_4~0); 91059#L1229-1 assume !(1 == ~E_5~0); 75716#L1234-1 assume !(1 == ~E_6~0); 75717#L1239-1 assume !(1 == ~E_7~0); 75774#L1244-1 assume !(1 == ~E_8~0); 75775#L1249-1 assume !(1 == ~E_9~0); 76709#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 75616#L1259-1 assume { :end_inline_reset_delta_events } true; 75617#L1565-2 [2023-11-26 10:47:00,596 INFO L750 eck$LassoCheckResult]: Loop: 75617#L1565-2 assume !false; 76638#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76353#L1011-1 assume !false; 76311#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 76074#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 75817#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 76176#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 75847#L866 assume !(0 != eval_~tmp~0#1); 75849#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76388#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76389#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 76988#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76989#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 91875#L1046-3 assume !(0 == ~T3_E~0); 91874#L1051-3 assume !(0 == ~T4_E~0); 91873#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 91871#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 91869#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 91868#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 91867#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 91866#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 77089#L1086-3 assume !(0 == ~E_M~0); 75657#L1091-3 assume !(0 == ~E_1~0); 75658#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 91858#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 91857#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 91856#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 91855#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 91854#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 91853#L1126-3 assume !(0 == ~E_8~0); 91852#L1131-3 assume !(0 == ~E_9~0); 91851#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 91850#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91849#L514-36 assume !(1 == ~m_pc~0); 91848#L514-38 is_master_triggered_~__retres1~0#1 := 0; 91847#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91829#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 91803#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91802#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91801#L533-36 assume 1 == ~t1_pc~0; 91799#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 91798#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91797#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 91796#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 91795#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 91794#L552-36 assume 1 == ~t2_pc~0; 91793#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 91791#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 91790#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78017#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78016#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78015#L571-36 assume 1 == ~t3_pc~0; 78013#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 78012#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78011#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78010#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78009#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78008#L590-36 assume 1 == ~t4_pc~0; 78007#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 78005#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78004#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78003#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78002#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78001#L609-36 assume !(1 == ~t5_pc~0); 78000#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 77998#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77997#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77996#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 77995#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77994#L628-36 assume !(1 == ~t6_pc~0); 77993#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 77991#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77990#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77989#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 77988#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77987#L647-36 assume 1 == ~t7_pc~0; 77985#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 77984#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77983#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77982#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 77981#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77980#L666-36 assume !(1 == ~t8_pc~0); 77979#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 77977#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77976#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77975#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 77974#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77973#L685-36 assume !(1 == ~t9_pc~0); 77971#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 77970#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77969#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77968#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 77967#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77966#L704-36 assume !(1 == ~t10_pc~0); 77965#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 77963#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77962#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77961#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77960#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77959#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 77958#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77957#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77956#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77941#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77940#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77939#L1179-3 assume !(1 == ~T6_E~0); 77938#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77937#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 77936#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 76026#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 76027#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 77133#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77844#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77841#L1219-3 assume !(1 == ~E_3~0); 77839#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77837#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77835#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77833#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 77831#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77828#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 77826#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 77825#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77811#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77810#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77776#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 76554#L1584 assume !(0 == start_simulation_~tmp~3#1); 76555#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77861#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77851#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77850#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 77849#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77848#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77847#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 77049#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 75617#L1565-2 [2023-11-26 10:47:00,597 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:00,597 INFO L85 PathProgramCache]: Analyzing trace with hash -2098669114, now seen corresponding path program 1 times [2023-11-26 10:47:00,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:00,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1919053890] [2023-11-26 10:47:00,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:00,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:00,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:00,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:00,681 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:00,681 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1919053890] [2023-11-26 10:47:00,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1919053890] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:00,682 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:00,682 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:47:00,682 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1849671309] [2023-11-26 10:47:00,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:00,683 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:47:00,684 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:00,684 INFO L85 PathProgramCache]: Analyzing trace with hash -1253499843, now seen corresponding path program 1 times [2023-11-26 10:47:00,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:00,684 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [865481620] [2023-11-26 10:47:00,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:00,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:00,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:00,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:00,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:00,829 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [865481620] [2023-11-26 10:47:00,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [865481620] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:00,829 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:00,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:47:00,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2006678303] [2023-11-26 10:47:00,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:00,830 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:47:00,831 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:47:00,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:47:00,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:47:00,831 INFO L87 Difference]: Start difference. First operand 16587 states and 24163 transitions. cyclomatic complexity: 7592 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:01,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:47:01,077 INFO L93 Difference]: Finished difference Result 31537 states and 45713 transitions. [2023-11-26 10:47:01,077 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31537 states and 45713 transitions. [2023-11-26 10:47:01,245 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31264 [2023-11-26 10:47:01,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31537 states to 31537 states and 45713 transitions. [2023-11-26 10:47:01,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31537 [2023-11-26 10:47:01,549 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31537 [2023-11-26 10:47:01,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31537 states and 45713 transitions. [2023-11-26 10:47:01,578 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:47:01,579 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31537 states and 45713 transitions. [2023-11-26 10:47:01,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31537 states and 45713 transitions. [2023-11-26 10:47:02,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31537 to 31505. [2023-11-26 10:47:02,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31505 states, 31505 states have (on average 1.4499603237581336) internal successors, (45681), 31504 states have internal predecessors, (45681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:02,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31505 states to 31505 states and 45681 transitions. [2023-11-26 10:47:02,201 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31505 states and 45681 transitions. [2023-11-26 10:47:02,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:47:02,203 INFO L428 stractBuchiCegarLoop]: Abstraction has 31505 states and 45681 transitions. [2023-11-26 10:47:02,203 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 10:47:02,203 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31505 states and 45681 transitions. [2023-11-26 10:47:02,471 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31232 [2023-11-26 10:47:02,471 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:02,471 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:02,474 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:02,475 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:02,475 INFO L748 eck$LassoCheckResult]: Stem: 124025#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 124026#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 125050#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 125051#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 125147#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 125061#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 124983#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 124984#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125043#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 123958#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 123959#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 124070#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 124331#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 124253#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 123960#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 123619#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 123620#L1036 assume !(0 == ~M_E~0); 123716#L1036-2 assume !(0 == ~T1_E~0); 124674#L1041-1 assume !(0 == ~T2_E~0); 124675#L1046-1 assume !(0 == ~T3_E~0); 123999#L1051-1 assume !(0 == ~T4_E~0); 124000#L1056-1 assume !(0 == ~T5_E~0); 124827#L1061-1 assume !(0 == ~T6_E~0); 123889#L1066-1 assume !(0 == ~T7_E~0); 123890#L1071-1 assume !(0 == ~T8_E~0); 124809#L1076-1 assume !(0 == ~T9_E~0); 123778#L1081-1 assume !(0 == ~T10_E~0); 123779#L1086-1 assume !(0 == ~E_M~0); 124195#L1091-1 assume !(0 == ~E_1~0); 125071#L1096-1 assume !(0 == ~E_2~0); 125072#L1101-1 assume !(0 == ~E_3~0); 124266#L1106-1 assume !(0 == ~E_4~0); 124267#L1111-1 assume !(0 == ~E_5~0); 124445#L1116-1 assume !(0 == ~E_6~0); 124446#L1121-1 assume !(0 == ~E_7~0); 124257#L1126-1 assume !(0 == ~E_8~0); 124258#L1131-1 assume !(0 == ~E_9~0); 124556#L1136-1 assume !(0 == ~E_10~0); 124687#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124866#L514 assume !(1 == ~m_pc~0); 124867#L514-2 is_master_triggered_~__retres1~0#1 := 0; 124275#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124276#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 124945#L1285 assume !(0 != activate_threads_~tmp~1#1); 125125#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123909#L533 assume !(1 == ~t1_pc~0); 123910#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 124462#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123671#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 123672#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 124712#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 124713#L552 assume !(1 == ~t2_pc~0); 124405#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 124406#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 124261#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 124262#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 124288#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 124289#L571 assume 1 == ~t3_pc~0; 124504#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 124505#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123617#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123618#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 124450#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123702#L590 assume !(1 == ~t4_pc~0); 123703#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 124514#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123796#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 123797#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124743#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124447#L609 assume 1 == ~t5_pc~0; 124448#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 125123#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124947#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 124948#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 124439#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124440#L628 assume !(1 == ~t6_pc~0); 124365#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 124364#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 124234#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 124235#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 124788#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124789#L647 assume 1 == ~t7_pc~0; 124268#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 124269#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 124958#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 124271#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 124272#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 125178#L666 assume !(1 == ~t8_pc~0); 124047#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 124048#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 124287#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 124474#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 124192#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 124193#L685 assume 1 == ~t9_pc~0; 125133#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 124969#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 124323#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 124224#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 124225#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 124643#L704 assume !(1 == ~t10_pc~0); 124214#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 124213#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 124495#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 123750#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 123751#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124009#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 124770#L1154-2 assume !(1 == ~T1_E~0); 123980#L1159-1 assume !(1 == ~T2_E~0); 123981#L1164-1 assume !(1 == ~T3_E~0); 135335#L1169-1 assume !(1 == ~T4_E~0); 135320#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 135312#L1179-1 assume !(1 == ~T6_E~0); 135309#L1184-1 assume !(1 == ~T7_E~0); 135307#L1189-1 assume !(1 == ~T8_E~0); 135305#L1194-1 assume !(1 == ~T9_E~0); 135303#L1199-1 assume !(1 == ~T10_E~0); 135294#L1204-1 assume !(1 == ~E_M~0); 135292#L1209-1 assume !(1 == ~E_1~0); 135289#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 135287#L1219-1 assume !(1 == ~E_3~0); 135285#L1224-1 assume !(1 == ~E_4~0); 135283#L1229-1 assume !(1 == ~E_5~0); 135281#L1234-1 assume !(1 == ~E_6~0); 133289#L1239-1 assume !(1 == ~E_7~0); 132828#L1244-1 assume !(1 == ~E_8~0); 132823#L1249-1 assume !(1 == ~E_9~0); 132775#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 132762#L1259-1 assume { :end_inline_reset_delta_events } true; 132760#L1565-2 [2023-11-26 10:47:02,476 INFO L750 eck$LassoCheckResult]: Loop: 132760#L1565-2 assume !false; 132758#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 132745#L1011-1 assume !false; 132737#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 132664#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 132648#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 132644#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 132641#L866 assume !(0 != eval_~tmp~0#1); 132642#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 136151#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 136149#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 136147#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 136145#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 136143#L1046-3 assume !(0 == ~T3_E~0); 136141#L1051-3 assume !(0 == ~T4_E~0); 136139#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 136137#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 136135#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 136133#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 136131#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 136129#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 136127#L1086-3 assume !(0 == ~E_M~0); 136125#L1091-3 assume !(0 == ~E_1~0); 136123#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 136121#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 136119#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 136117#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 136115#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 136113#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 136111#L1126-3 assume !(0 == ~E_8~0); 136109#L1131-3 assume !(0 == ~E_9~0); 136107#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 136105#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136103#L514-36 assume !(1 == ~m_pc~0); 136101#L514-38 is_master_triggered_~__retres1~0#1 := 0; 136099#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 136097#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 136095#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 136093#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136091#L533-36 assume 1 == ~t1_pc~0; 136088#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 136086#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136083#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 136081#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 136079#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 136077#L552-36 assume !(1 == ~t2_pc~0); 136075#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 136073#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 136071#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 136069#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 136067#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 136065#L571-36 assume 1 == ~t3_pc~0; 136062#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 136060#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136057#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 136055#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 136053#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 136051#L590-36 assume !(1 == ~t4_pc~0); 136048#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 136046#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 136045#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 136042#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 136040#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 136038#L609-36 assume 1 == ~t5_pc~0; 136035#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 136033#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 136031#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 136028#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 136026#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 136024#L628-36 assume !(1 == ~t6_pc~0); 136022#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 136019#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 136017#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 136014#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 136012#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 136010#L647-36 assume 1 == ~t7_pc~0; 136007#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 136005#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 136003#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 136000#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 135998#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 135996#L666-36 assume !(1 == ~t8_pc~0); 135994#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 135209#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 133199#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 133196#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 133194#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 133192#L685-36 assume 1 == ~t9_pc~0; 133190#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 133187#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 133185#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 133182#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 133180#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 133178#L704-36 assume 1 == ~t10_pc~0; 133175#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 133173#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 133171#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 133168#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 133166#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 133164#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 133160#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 133158#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 133156#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 133151#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 133149#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 133147#L1179-3 assume !(1 == ~T6_E~0); 133145#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 133143#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 133141#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 133138#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 133136#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 133132#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 133130#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 133128#L1219-3 assume !(1 == ~E_3~0); 133126#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 133123#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 133121#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 133119#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 133117#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 133113#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 133112#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 133111#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 133100#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 133099#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 133098#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 133097#L1584 assume !(0 == start_simulation_~tmp~3#1); 133095#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 133093#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 133080#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 133078#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 133076#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 132794#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 132791#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 132763#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 132760#L1565-2 [2023-11-26 10:47:02,477 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:02,477 INFO L85 PathProgramCache]: Analyzing trace with hash 353984391, now seen corresponding path program 1 times [2023-11-26 10:47:02,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:02,478 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335773153] [2023-11-26 10:47:02,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:02,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:02,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:02,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:02,656 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:02,656 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1335773153] [2023-11-26 10:47:02,656 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1335773153] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:02,656 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:02,656 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:47:02,656 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [481954983] [2023-11-26 10:47:02,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:02,657 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:47:02,657 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:02,658 INFO L85 PathProgramCache]: Analyzing trace with hash -148556804, now seen corresponding path program 1 times [2023-11-26 10:47:02,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:02,658 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2000802369] [2023-11-26 10:47:02,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:02,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:02,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:02,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:02,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:02,728 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2000802369] [2023-11-26 10:47:02,729 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2000802369] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:02,729 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:02,729 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:47:02,729 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1691076464] [2023-11-26 10:47:02,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:02,730 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:47:02,730 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:47:02,730 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:47:02,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:47:02,731 INFO L87 Difference]: Start difference. First operand 31505 states and 45681 transitions. cyclomatic complexity: 14208 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:03,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:47:03,195 INFO L93 Difference]: Finished difference Result 59948 states and 86522 transitions. [2023-11-26 10:47:03,196 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59948 states and 86522 transitions. [2023-11-26 10:47:03,668 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59580 [2023-11-26 10:47:03,946 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59948 states to 59948 states and 86522 transitions. [2023-11-26 10:47:03,946 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59948 [2023-11-26 10:47:03,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59948 [2023-11-26 10:47:03,990 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59948 states and 86522 transitions. [2023-11-26 10:47:04,140 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:47:04,140 INFO L218 hiAutomatonCegarLoop]: Abstraction has 59948 states and 86522 transitions. [2023-11-26 10:47:04,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59948 states and 86522 transitions. [2023-11-26 10:47:05,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59948 to 59884. [2023-11-26 10:47:05,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59884 states, 59884 states have (on average 1.4437579320018703) internal successors, (86458), 59883 states have internal predecessors, (86458), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:05,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59884 states to 59884 states and 86458 transitions. [2023-11-26 10:47:05,621 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59884 states and 86458 transitions. [2023-11-26 10:47:05,621 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:47:05,622 INFO L428 stractBuchiCegarLoop]: Abstraction has 59884 states and 86458 transitions. [2023-11-26 10:47:05,622 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 10:47:05,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59884 states and 86458 transitions. [2023-11-26 10:47:05,940 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59516 [2023-11-26 10:47:05,940 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:05,940 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:05,943 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:05,943 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:05,944 INFO L748 eck$LassoCheckResult]: Stem: 215482#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 215483#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 216454#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 216455#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 216541#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 216460#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 216403#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 216404#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 216444#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 215416#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 215417#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 215528#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 215781#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 215701#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 215418#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 215079#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 215080#L1036 assume !(0 == ~M_E~0); 215176#L1036-2 assume !(0 == ~T1_E~0); 216115#L1041-1 assume !(0 == ~T2_E~0); 216116#L1046-1 assume !(0 == ~T3_E~0); 215455#L1051-1 assume !(0 == ~T4_E~0); 215456#L1056-1 assume !(0 == ~T5_E~0); 216265#L1061-1 assume !(0 == ~T6_E~0); 215349#L1066-1 assume !(0 == ~T7_E~0); 215350#L1071-1 assume !(0 == ~T8_E~0); 216246#L1076-1 assume !(0 == ~T9_E~0); 215238#L1081-1 assume !(0 == ~T10_E~0); 215239#L1086-1 assume !(0 == ~E_M~0); 215646#L1091-1 assume !(0 == ~E_1~0); 216469#L1096-1 assume !(0 == ~E_2~0); 216470#L1101-1 assume !(0 == ~E_3~0); 215714#L1106-1 assume !(0 == ~E_4~0); 215715#L1111-1 assume !(0 == ~E_5~0); 215895#L1116-1 assume !(0 == ~E_6~0); 215896#L1121-1 assume !(0 == ~E_7~0); 215705#L1126-1 assume !(0 == ~E_8~0); 215706#L1131-1 assume !(0 == ~E_9~0); 216000#L1136-1 assume !(0 == ~E_10~0); 216127#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216299#L514 assume !(1 == ~m_pc~0); 216300#L514-2 is_master_triggered_~__retres1~0#1 := 0; 215723#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 215724#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 216370#L1285 assume !(0 != activate_threads_~tmp~1#1); 216519#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 215369#L533 assume !(1 == ~t1_pc~0); 215370#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 215910#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 215131#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 215132#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 216154#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 216155#L552 assume !(1 == ~t2_pc~0); 215856#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 215857#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 215709#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 215710#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 215736#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 215737#L571 assume !(1 == ~t3_pc~0); 215969#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 216054#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 215077#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 215078#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 215900#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 215162#L590 assume !(1 == ~t4_pc~0); 215163#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 215957#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 215256#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 215257#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 216185#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 215897#L609 assume 1 == ~t5_pc~0; 215898#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 216516#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216372#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 216373#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 215888#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 215889#L628 assume !(1 == ~t6_pc~0); 215815#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 215814#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 215682#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 215683#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 216225#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 216226#L647 assume 1 == ~t7_pc~0; 215716#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 215717#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 216380#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 215719#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 215720#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 216569#L666 assume !(1 == ~t8_pc~0); 215506#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 215507#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 215735#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 215922#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 215643#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 215644#L685 assume 1 == ~t9_pc~0; 216528#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 216389#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 215773#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 215672#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 215673#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 216085#L704 assume !(1 == ~t10_pc~0); 215663#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 215662#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 215941#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 215210#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 215211#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 215464#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 216210#L1154-2 assume !(1 == ~T1_E~0); 215438#L1159-1 assume !(1 == ~T2_E~0); 215439#L1164-1 assume !(1 == ~T3_E~0); 217660#L1169-1 assume !(1 == ~T4_E~0); 217655#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 217650#L1179-1 assume !(1 == ~T6_E~0); 217645#L1184-1 assume !(1 == ~T7_E~0); 217636#L1189-1 assume !(1 == ~T8_E~0); 217629#L1194-1 assume !(1 == ~T9_E~0); 217621#L1199-1 assume !(1 == ~T10_E~0); 217614#L1204-1 assume !(1 == ~E_M~0); 217452#L1209-1 assume !(1 == ~E_1~0); 217450#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 217448#L1219-1 assume !(1 == ~E_3~0); 217446#L1224-1 assume !(1 == ~E_4~0); 217443#L1229-1 assume !(1 == ~E_5~0); 217441#L1234-1 assume !(1 == ~E_6~0); 217304#L1239-1 assume !(1 == ~E_7~0); 217269#L1244-1 assume !(1 == ~E_8~0); 217265#L1249-1 assume !(1 == ~E_9~0); 217253#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 217244#L1259-1 assume { :end_inline_reset_delta_events } true; 217237#L1565-2 [2023-11-26 10:47:05,944 INFO L750 eck$LassoCheckResult]: Loop: 217237#L1565-2 assume !false; 217231#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 217227#L1011-1 assume !false; 217226#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 217225#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 217214#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 217213#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 217211#L866 assume !(0 != eval_~tmp~0#1); 217210#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 217209#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 217206#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 217207#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 220646#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 220644#L1046-3 assume !(0 == ~T3_E~0); 220642#L1051-3 assume !(0 == ~T4_E~0); 220640#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 220638#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 220636#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 220634#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 220632#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 220630#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 220628#L1086-3 assume !(0 == ~E_M~0); 220626#L1091-3 assume !(0 == ~E_1~0); 220624#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 220622#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 220620#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 220618#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 220610#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 220605#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 220600#L1126-3 assume !(0 == ~E_8~0); 220595#L1131-3 assume !(0 == ~E_9~0); 220589#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 220583#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 220577#L514-36 assume !(1 == ~m_pc~0); 220570#L514-38 is_master_triggered_~__retres1~0#1 := 0; 220563#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 220556#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 220549#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 220541#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 220534#L533-36 assume !(1 == ~t1_pc~0); 220526#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 220517#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 220510#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 217134#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 217135#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 220153#L552-36 assume !(1 == ~t2_pc~0); 220151#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 220149#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 220147#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 220145#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 220143#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 220141#L571-36 assume !(1 == ~t3_pc~0); 220140#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 220139#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220138#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 220137#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 220136#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 220135#L590-36 assume 1 == ~t4_pc~0; 220134#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 220131#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 220129#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 220127#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 220125#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 220122#L609-36 assume 1 == ~t5_pc~0; 220119#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 220117#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 220115#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 220113#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 220111#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 220108#L628-36 assume !(1 == ~t6_pc~0); 220106#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 220103#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 220101#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 220099#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 220097#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 220096#L647-36 assume !(1 == ~t7_pc~0); 220095#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 220093#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 220091#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 220089#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 219679#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 219677#L666-36 assume !(1 == ~t8_pc~0); 219675#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 219672#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 219670#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 219667#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 219665#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 219663#L685-36 assume 1 == ~t9_pc~0; 219661#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 219658#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 219656#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 219654#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 219652#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 219650#L704-36 assume !(1 == ~t10_pc~0); 219648#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 219645#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 219643#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 219641#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 219639#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 219637#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 216989#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 219634#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 219632#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 219627#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 219625#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 219623#L1179-3 assume !(1 == ~T6_E~0); 219621#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 219619#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 219617#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 219614#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 219612#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 219608#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 219606#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 218827#L1219-3 assume !(1 == ~E_3~0); 218825#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 218568#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 218566#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 218538#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 218529#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 218520#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 218128#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 218126#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 218067#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 218058#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 218048#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 218038#L1584 assume !(0 == start_simulation_~tmp~3#1); 218033#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 217802#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 217455#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 217306#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 217270#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 217266#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 217254#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 217245#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 217237#L1565-2 [2023-11-26 10:47:05,944 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:05,945 INFO L85 PathProgramCache]: Analyzing trace with hash -1601336824, now seen corresponding path program 1 times [2023-11-26 10:47:05,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:05,945 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319242579] [2023-11-26 10:47:05,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:05,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:05,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:06,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:06,038 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:06,038 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319242579] [2023-11-26 10:47:06,038 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [319242579] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:06,039 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:06,039 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:47:06,039 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1433517748] [2023-11-26 10:47:06,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:06,040 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:47:06,040 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:06,040 INFO L85 PathProgramCache]: Analyzing trace with hash -1349972737, now seen corresponding path program 1 times [2023-11-26 10:47:06,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:06,040 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1975945668] [2023-11-26 10:47:06,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:06,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:06,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:06,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:06,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:06,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1975945668] [2023-11-26 10:47:06,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1975945668] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:06,102 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:06,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:47:06,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [404348944] [2023-11-26 10:47:06,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:06,103 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:47:06,103 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:47:06,104 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 10:47:06,104 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 10:47:06,104 INFO L87 Difference]: Start difference. First operand 59884 states and 86458 transitions. cyclomatic complexity: 26638 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:07,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:47:07,178 INFO L93 Difference]: Finished difference Result 144384 states and 206761 transitions. [2023-11-26 10:47:07,178 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144384 states and 206761 transitions. [2023-11-26 10:47:08,138 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 143672 [2023-11-26 10:47:08,555 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144384 states to 144384 states and 206761 transitions. [2023-11-26 10:47:08,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144384 [2023-11-26 10:47:08,641 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144384 [2023-11-26 10:47:08,641 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144384 states and 206761 transitions. [2023-11-26 10:47:08,766 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:47:08,766 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144384 states and 206761 transitions. [2023-11-26 10:47:08,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144384 states and 206761 transitions. [2023-11-26 10:47:10,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144384 to 61735. [2023-11-26 10:47:10,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61735 states, 61735 states have (on average 1.4304527415566535) internal successors, (88309), 61734 states have internal predecessors, (88309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:10,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61735 states to 61735 states and 88309 transitions. [2023-11-26 10:47:10,792 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61735 states and 88309 transitions. [2023-11-26 10:47:10,793 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 10:47:10,795 INFO L428 stractBuchiCegarLoop]: Abstraction has 61735 states and 88309 transitions. [2023-11-26 10:47:10,795 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 10:47:10,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61735 states and 88309 transitions. [2023-11-26 10:47:10,961 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 61364 [2023-11-26 10:47:10,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:10,961 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:10,963 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:10,964 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:10,964 INFO L748 eck$LassoCheckResult]: Stem: 419770#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 419771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 420839#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 420840#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 420951#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 420847#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 420768#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 420769#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 420829#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 419700#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 419701#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 419820#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 420073#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 419997#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 419702#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 419360#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 419361#L1036 assume !(0 == ~M_E~0); 419459#L1036-2 assume !(0 == ~T1_E~0); 420427#L1041-1 assume !(0 == ~T2_E~0); 420428#L1046-1 assume !(0 == ~T3_E~0); 419742#L1051-1 assume !(0 == ~T4_E~0); 419743#L1056-1 assume !(0 == ~T5_E~0); 420600#L1061-1 assume !(0 == ~T6_E~0); 419631#L1066-1 assume !(0 == ~T7_E~0); 419632#L1071-1 assume !(0 == ~T8_E~0); 420578#L1076-1 assume !(0 == ~T9_E~0); 419521#L1081-1 assume !(0 == ~T10_E~0); 419522#L1086-1 assume !(0 == ~E_M~0); 419940#L1091-1 assume !(0 == ~E_1~0); 420858#L1096-1 assume !(0 == ~E_2~0); 420859#L1101-1 assume !(0 == ~E_3~0); 420010#L1106-1 assume !(0 == ~E_4~0); 420011#L1111-1 assume !(0 == ~E_5~0); 420189#L1116-1 assume !(0 == ~E_6~0); 420190#L1121-1 assume !(0 == ~E_7~0); 420001#L1126-1 assume !(0 == ~E_8~0); 420002#L1131-1 assume !(0 == ~E_9~0); 420302#L1136-1 assume !(0 == ~E_10~0); 420441#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 420639#L514 assume !(1 == ~m_pc~0); 420640#L514-2 is_master_triggered_~__retres1~0#1 := 0; 420019#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 420020#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 420727#L1285 assume !(0 != activate_threads_~tmp~1#1); 420918#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 419650#L533 assume !(1 == ~t1_pc~0); 419651#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 420206#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 419413#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 419414#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 420471#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 420472#L552 assume !(1 == ~t2_pc~0); 420148#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 420149#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 420005#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 420006#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 420033#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 420034#L571 assume !(1 == ~t3_pc~0); 420267#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 420359#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 419358#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 419359#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 420195#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 419445#L590 assume !(1 == ~t4_pc~0); 419446#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 420266#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 421018#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 420924#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 420505#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 420191#L609 assume 1 == ~t5_pc~0; 420192#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 420915#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 420730#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 420731#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 420182#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 420183#L628 assume !(1 == ~t6_pc~0); 420108#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 420107#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 419977#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 419978#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 420553#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 420554#L647 assume 1 == ~t7_pc~0; 420012#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 420013#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 420744#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 420015#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 420016#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 420980#L666 assume !(1 == ~t8_pc~0); 419797#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 419798#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 420032#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 420218#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 419935#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 419936#L685 assume 1 == ~t9_pc~0; 420934#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 420755#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 420067#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 419967#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 419968#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 420394#L704 assume !(1 == ~t10_pc~0); 419958#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 419957#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 420237#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 419493#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 419494#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 419752#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 420537#L1154-2 assume !(1 == ~T1_E~0); 420961#L1159-1 assume !(1 == ~T2_E~0); 421024#L1164-1 assume !(1 == ~T3_E~0); 420216#L1169-1 assume !(1 == ~T4_E~0); 420068#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 419865#L1179-1 assume !(1 == ~T6_E~0); 419708#L1184-1 assume !(1 == ~T7_E~0); 419709#L1189-1 assume !(1 == ~T8_E~0); 419795#L1194-1 assume !(1 == ~T9_E~0); 419921#L1199-1 assume !(1 == ~T10_E~0); 419877#L1204-1 assume !(1 == ~E_M~0); 419878#L1209-1 assume !(1 == ~E_1~0); 420499#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 420500#L1219-1 assume !(1 == ~E_3~0); 420963#L1224-1 assume !(1 == ~E_4~0); 420241#L1229-1 assume !(1 == ~E_5~0); 419588#L1234-1 assume !(1 == ~E_6~0); 419589#L1239-1 assume !(1 == ~E_7~0); 419646#L1244-1 assume !(1 == ~E_8~0); 419647#L1249-1 assume !(1 == ~E_9~0); 420682#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 430620#L1259-1 assume { :end_inline_reset_delta_events } true; 430613#L1565-2 [2023-11-26 10:47:10,965 INFO L750 eck$LassoCheckResult]: Loop: 430613#L1565-2 assume !false; 430607#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 430603#L1011-1 assume !false; 430602#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 430601#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 430590#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 430589#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 430587#L866 assume !(0 != eval_~tmp~0#1); 430588#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 465362#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 465361#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 465360#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 465359#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 465358#L1046-3 assume !(0 == ~T3_E~0); 465357#L1051-3 assume !(0 == ~T4_E~0); 465356#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 465355#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 465354#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 465353#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 465352#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 465351#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 465350#L1086-3 assume !(0 == ~E_M~0); 465349#L1091-3 assume !(0 == ~E_1~0); 465348#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 465347#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 465346#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 465345#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 465344#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 465343#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 465342#L1126-3 assume !(0 == ~E_8~0); 465341#L1131-3 assume !(0 == ~E_9~0); 465340#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 465339#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 465338#L514-36 assume !(1 == ~m_pc~0); 465337#L514-38 is_master_triggered_~__retres1~0#1 := 0; 465336#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 465335#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 465334#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 465333#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 465332#L533-36 assume !(1 == ~t1_pc~0); 465331#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 465329#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 465328#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 465327#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 465326#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 465325#L552-36 assume !(1 == ~t2_pc~0); 465324#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 465323#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 465322#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 465321#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 465320#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 465319#L571-36 assume !(1 == ~t3_pc~0); 465318#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 465317#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 465316#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 465315#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 465314#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 465313#L590-36 assume !(1 == ~t4_pc~0); 465312#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 465310#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 465308#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 465306#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 465303#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 465300#L609-36 assume !(1 == ~t5_pc~0); 465298#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 465295#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 465293#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 465291#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 465289#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 465286#L628-36 assume !(1 == ~t6_pc~0); 465284#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 465281#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 465279#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 465277#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 465275#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 465272#L647-36 assume !(1 == ~t7_pc~0); 465270#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 465267#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 465265#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 465263#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 465261#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 465258#L666-36 assume 1 == ~t8_pc~0; 465255#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 465253#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 465251#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 465249#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 465247#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 465244#L685-36 assume 1 == ~t9_pc~0; 465242#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 465239#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 465237#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 465235#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 465233#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 465219#L704-36 assume !(1 == ~t10_pc~0); 465216#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 465211#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 465203#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 465200#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 419635#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 419636#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 420805#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 420612#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 420613#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 420910#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 419954#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 419955#L1179-3 assume !(1 == ~T6_E~0); 420757#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 419509#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 419510#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 419894#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 419895#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 420238#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 419376#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 419377#L1219-3 assume !(1 == ~E_3~0); 420479#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 420480#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 420506#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 419648#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 419649#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 420299#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 430738#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 430736#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 430703#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 430693#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 430686#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 430677#L1584 assume !(0 == start_simulation_~tmp~3#1); 430671#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 430665#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 430654#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 430652#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 430651#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 430648#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 430629#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 430621#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 430613#L1565-2 [2023-11-26 10:47:10,966 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:10,966 INFO L85 PathProgramCache]: Analyzing trace with hash 360237834, now seen corresponding path program 1 times [2023-11-26 10:47:10,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:10,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780736925] [2023-11-26 10:47:10,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:10,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:10,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:11,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:11,050 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:11,050 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [780736925] [2023-11-26 10:47:11,050 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [780736925] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:11,050 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:11,050 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:47:11,051 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [477337069] [2023-11-26 10:47:11,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:11,051 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:47:11,052 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:11,052 INFO L85 PathProgramCache]: Analyzing trace with hash 1805062786, now seen corresponding path program 1 times [2023-11-26 10:47:11,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:11,052 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106287661] [2023-11-26 10:47:11,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:11,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:11,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:11,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:11,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:11,119 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106287661] [2023-11-26 10:47:11,119 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2106287661] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:11,119 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:11,119 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:47:11,119 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993038732] [2023-11-26 10:47:11,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:11,120 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:47:11,120 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:47:11,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:47:11,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:47:11,121 INFO L87 Difference]: Start difference. First operand 61735 states and 88309 transitions. cyclomatic complexity: 26638 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:11,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:47:11,951 INFO L93 Difference]: Finished difference Result 117490 states and 167414 transitions. [2023-11-26 10:47:11,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117490 states and 167414 transitions. [2023-11-26 10:47:12,468 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 116832 [2023-11-26 10:47:12,958 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117490 states to 117490 states and 167414 transitions. [2023-11-26 10:47:12,959 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117490 [2023-11-26 10:47:13,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117490 [2023-11-26 10:47:13,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117490 states and 167414 transitions. [2023-11-26 10:47:13,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:47:13,141 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117490 states and 167414 transitions. [2023-11-26 10:47:13,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117490 states and 167414 transitions. [2023-11-26 10:47:14,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117490 to 117362. [2023-11-26 10:47:14,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117362 states, 117362 states have (on average 1.4253847071454133) internal successors, (167286), 117361 states have internal predecessors, (167286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:15,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117362 states to 117362 states and 167286 transitions. [2023-11-26 10:47:15,019 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117362 states and 167286 transitions. [2023-11-26 10:47:15,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:47:15,021 INFO L428 stractBuchiCegarLoop]: Abstraction has 117362 states and 167286 transitions. [2023-11-26 10:47:15,021 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 10:47:15,021 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117362 states and 167286 transitions. [2023-11-26 10:47:16,080 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 116704 [2023-11-26 10:47:16,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:16,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:16,084 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:16,084 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:16,085 INFO L748 eck$LassoCheckResult]: Stem: 598996#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 598997#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 599974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 599975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 600074#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 599979#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 599926#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 599927#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 599963#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 598932#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 598933#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 599041#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 599295#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 599217#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 598934#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 598592#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 598593#L1036 assume !(0 == ~M_E~0); 598688#L1036-2 assume !(0 == ~T1_E~0); 599635#L1041-1 assume !(0 == ~T2_E~0); 599636#L1046-1 assume !(0 == ~T3_E~0); 598972#L1051-1 assume !(0 == ~T4_E~0); 598973#L1056-1 assume !(0 == ~T5_E~0); 599782#L1061-1 assume !(0 == ~T6_E~0); 598861#L1066-1 assume !(0 == ~T7_E~0); 598862#L1071-1 assume !(0 == ~T8_E~0); 599761#L1076-1 assume !(0 == ~T9_E~0); 598751#L1081-1 assume !(0 == ~T10_E~0); 598752#L1086-1 assume !(0 == ~E_M~0); 599161#L1091-1 assume !(0 == ~E_1~0); 599989#L1096-1 assume !(0 == ~E_2~0); 599990#L1101-1 assume !(0 == ~E_3~0); 599232#L1106-1 assume !(0 == ~E_4~0); 599233#L1111-1 assume !(0 == ~E_5~0); 599412#L1116-1 assume !(0 == ~E_6~0); 599413#L1121-1 assume !(0 == ~E_7~0); 599221#L1126-1 assume !(0 == ~E_8~0); 599222#L1131-1 assume !(0 == ~E_9~0); 599519#L1136-1 assume !(0 == ~E_10~0); 599644#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 599820#L514 assume !(1 == ~m_pc~0); 599821#L514-2 is_master_triggered_~__retres1~0#1 := 0; 599241#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 599242#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 599886#L1285 assume !(0 != activate_threads_~tmp~1#1); 600048#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 598884#L533 assume !(1 == ~t1_pc~0); 598885#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 599428#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 598647#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 598648#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 599668#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 599669#L552 assume !(1 == ~t2_pc~0); 599369#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 599370#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 599225#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 599226#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 599260#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 599261#L571 assume !(1 == ~t3_pc~0); 599489#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 599573#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 598590#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 598591#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 599416#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 598674#L590 assume !(1 == ~t4_pc~0); 598675#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 599487#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 600132#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 600051#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 599700#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 599414#L609 assume !(1 == ~t5_pc~0); 599415#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 600043#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 599887#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 599888#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 599407#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 599408#L628 assume !(1 == ~t6_pc~0); 599326#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 599325#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 599201#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 599202#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 599737#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 599738#L647 assume 1 == ~t7_pc~0; 599234#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 599235#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 599899#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 599239#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 599240#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 600091#L666 assume !(1 == ~t8_pc~0); 599018#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 599019#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 599253#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 599441#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 599158#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 599159#L685 assume 1 == ~t9_pc~0; 600056#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 599911#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 599288#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 599186#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 599187#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 599605#L704 assume !(1 == ~t10_pc~0); 599177#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 599176#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 599461#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 598723#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 598724#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 598980#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 599723#L1154-2 assume !(1 == ~T1_E~0); 598951#L1159-1 assume !(1 == ~T2_E~0); 598952#L1164-1 assume !(1 == ~T3_E~0); 599437#L1169-1 assume !(1 == ~T4_E~0); 599290#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 599084#L1179-1 assume !(1 == ~T6_E~0); 598936#L1184-1 assume !(1 == ~T7_E~0); 598937#L1189-1 assume !(1 == ~T8_E~0); 599016#L1194-1 assume !(1 == ~T9_E~0); 599144#L1199-1 assume !(1 == ~T10_E~0); 599097#L1204-1 assume !(1 == ~E_M~0); 599098#L1209-1 assume !(1 == ~E_1~0); 600090#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 603588#L1219-1 assume !(1 == ~E_3~0); 603586#L1224-1 assume !(1 == ~E_4~0); 603583#L1229-1 assume !(1 == ~E_5~0); 603581#L1234-1 assume !(1 == ~E_6~0); 603579#L1239-1 assume !(1 == ~E_7~0); 603001#L1244-1 assume !(1 == ~E_8~0); 602270#L1249-1 assume !(1 == ~E_9~0); 602268#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 602000#L1259-1 assume { :end_inline_reset_delta_events } true; 601998#L1565-2 [2023-11-26 10:47:16,086 INFO L750 eck$LassoCheckResult]: Loop: 601998#L1565-2 assume !false; 601996#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 601991#L1011-1 assume !false; 601988#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 601703#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 601691#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 601689#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 601686#L866 assume !(0 != eval_~tmp~0#1); 601687#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 604081#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 604079#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 604077#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 604075#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 604073#L1046-3 assume !(0 == ~T3_E~0); 604071#L1051-3 assume !(0 == ~T4_E~0); 604069#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 604067#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 604065#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 604063#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 604061#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 604059#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 604057#L1086-3 assume !(0 == ~E_M~0); 604055#L1091-3 assume !(0 == ~E_1~0); 604053#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 604051#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 604049#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 604047#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 604045#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 604043#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 604041#L1126-3 assume !(0 == ~E_8~0); 604039#L1131-3 assume !(0 == ~E_9~0); 604037#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 604035#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 604033#L514-36 assume !(1 == ~m_pc~0); 604031#L514-38 is_master_triggered_~__retres1~0#1 := 0; 604029#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 604027#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 604025#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 604023#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 604021#L533-36 assume 1 == ~t1_pc~0; 604017#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 604015#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 604013#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 604011#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 604009#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 604007#L552-36 assume !(1 == ~t2_pc~0); 604005#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 604003#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 604001#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 603999#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 603997#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 603995#L571-36 assume !(1 == ~t3_pc~0); 603993#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 603991#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 603989#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 603987#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 603985#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 603981#L590-36 assume !(1 == ~t4_pc~0); 603977#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 603975#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 603973#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 603970#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 603967#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 603965#L609-36 assume !(1 == ~t5_pc~0); 603963#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 603961#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 603959#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 603957#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 603955#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 603953#L628-36 assume 1 == ~t6_pc~0; 603949#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 603947#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 603945#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 603943#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 603941#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 603939#L647-36 assume 1 == ~t7_pc~0; 603935#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 603933#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 603931#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 603929#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 603927#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 603925#L666-36 assume 1 == ~t8_pc~0; 603921#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 603919#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 603917#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 603915#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 603913#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 603911#L685-36 assume !(1 == ~t9_pc~0); 603907#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 603905#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 603903#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 603901#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 603899#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 603897#L704-36 assume 1 == ~t10_pc~0; 603893#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 603891#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 603889#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 603887#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 603885#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 603883#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 603879#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 603877#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 603876#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 603873#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 603872#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 603871#L1179-3 assume !(1 == ~T6_E~0); 603870#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 603869#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 603868#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 603867#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 603855#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 603851#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 603849#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 603847#L1219-3 assume !(1 == ~E_3~0); 603845#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 603843#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 603841#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 603839#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 603834#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 603831#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 603830#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 603829#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 603616#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 603072#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 603070#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 602409#L1584 assume !(0 == start_simulation_~tmp~3#1); 602406#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 602023#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 602011#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 602009#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 602007#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 602005#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 602003#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 602001#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 601998#L1565-2 [2023-11-26 10:47:16,087 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:16,087 INFO L85 PathProgramCache]: Analyzing trace with hash -671092981, now seen corresponding path program 1 times [2023-11-26 10:47:16,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:16,088 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1471078192] [2023-11-26 10:47:16,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:16,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:16,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:16,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:16,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:16,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1471078192] [2023-11-26 10:47:16,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1471078192] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:16,197 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:16,197 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:47:16,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1903096592] [2023-11-26 10:47:16,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:16,198 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:47:16,199 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:16,199 INFO L85 PathProgramCache]: Analyzing trace with hash 1177559807, now seen corresponding path program 1 times [2023-11-26 10:47:16,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:16,199 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889512050] [2023-11-26 10:47:16,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:16,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:16,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:16,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:16,270 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:16,270 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889512050] [2023-11-26 10:47:16,271 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [889512050] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:16,271 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:16,271 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:47:16,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1266516551] [2023-11-26 10:47:16,271 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:16,272 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:47:16,273 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:47:16,273 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:47:16,273 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:47:16,274 INFO L87 Difference]: Start difference. First operand 117362 states and 167286 transitions. cyclomatic complexity: 50052 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:18,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:47:18,304 INFO L93 Difference]: Finished difference Result 282357 states and 399839 transitions. [2023-11-26 10:47:18,304 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 282357 states and 399839 transitions. [2023-11-26 10:47:19,340 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 280612 [2023-11-26 10:47:20,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 282357 states to 282357 states and 399839 transitions. [2023-11-26 10:47:20,844 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 282357 [2023-11-26 10:47:20,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 282357 [2023-11-26 10:47:20,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 282357 states and 399839 transitions. [2023-11-26 10:47:21,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:47:21,162 INFO L218 hiAutomatonCegarLoop]: Abstraction has 282357 states and 399839 transitions. [2023-11-26 10:47:21,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282357 states and 399839 transitions. [2023-11-26 10:47:24,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282357 to 227905. [2023-11-26 10:47:24,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 227905 states, 227905 states have (on average 1.4191307781751168) internal successors, (323427), 227904 states have internal predecessors, (323427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:25,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227905 states to 227905 states and 323427 transitions. [2023-11-26 10:47:25,308 INFO L240 hiAutomatonCegarLoop]: Abstraction has 227905 states and 323427 transitions. [2023-11-26 10:47:25,309 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:47:25,309 INFO L428 stractBuchiCegarLoop]: Abstraction has 227905 states and 323427 transitions. [2023-11-26 10:47:25,309 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 10:47:25,309 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 227905 states and 323427 transitions. [2023-11-26 10:47:26,733 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 226800 [2023-11-26 10:47:26,733 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:26,733 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:26,735 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:26,740 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:26,740 INFO L748 eck$LassoCheckResult]: Stem: 998721#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 998722#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 999686#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 999687#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 999766#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 999692#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 999635#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 999636#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 999676#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 998654#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 998655#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 998767#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 999016#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 998937#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 998653#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 998321#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 998322#L1036 assume !(0 == ~M_E~0); 998418#L1036-2 assume !(0 == ~T1_E~0); 999344#L1041-1 assume !(0 == ~T2_E~0); 999345#L1046-1 assume !(0 == ~T3_E~0); 998696#L1051-1 assume !(0 == ~T4_E~0); 998697#L1056-1 assume !(0 == ~T5_E~0); 999494#L1061-1 assume !(0 == ~T6_E~0); 998587#L1066-1 assume !(0 == ~T7_E~0); 998588#L1071-1 assume !(0 == ~T8_E~0); 999474#L1076-1 assume !(0 == ~T9_E~0); 998479#L1081-1 assume !(0 == ~T10_E~0); 998480#L1086-1 assume !(0 == ~E_M~0); 998882#L1091-1 assume !(0 == ~E_1~0); 999699#L1096-1 assume !(0 == ~E_2~0); 999700#L1101-1 assume !(0 == ~E_3~0); 998951#L1106-1 assume !(0 == ~E_4~0); 998952#L1111-1 assume !(0 == ~E_5~0); 999127#L1116-1 assume !(0 == ~E_6~0); 999128#L1121-1 assume !(0 == ~E_7~0); 998941#L1126-1 assume !(0 == ~E_8~0); 998942#L1131-1 assume !(0 == ~E_9~0); 999229#L1136-1 assume !(0 == ~E_10~0); 999353#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 999524#L514 assume !(1 == ~m_pc~0); 999525#L514-2 is_master_triggered_~__retres1~0#1 := 0; 998957#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 998958#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 999594#L1285 assume !(0 != activate_threads_~tmp~1#1); 999741#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 998606#L533 assume !(1 == ~t1_pc~0); 998607#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 999142#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 998374#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 998375#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 999375#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 999376#L552 assume !(1 == ~t2_pc~0); 999086#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 999087#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 998945#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 998946#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 998970#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 998971#L571 assume !(1 == ~t3_pc~0); 999200#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 999284#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 998319#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 998320#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 999131#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 998404#L590 assume !(1 == ~t4_pc~0); 998405#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 999199#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 999831#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 999747#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 999407#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 999129#L609 assume !(1 == ~t5_pc~0); 999130#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 999739#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 999596#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 999597#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 999121#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 999122#L628 assume !(1 == ~t6_pc~0); 999047#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 999046#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 998918#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 998919#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 999450#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 999451#L647 assume !(1 == ~t7_pc~0); 999577#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 999613#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 999614#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 998953#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 998954#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 999786#L666 assume !(1 == ~t8_pc~0); 998744#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 998745#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 998969#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 999154#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 998879#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 998880#L685 assume 1 == ~t9_pc~0; 999751#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 999623#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 999008#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 998908#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 998909#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 999314#L704 assume !(1 == ~t10_pc~0); 998900#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 998899#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 999173#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 998452#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 998453#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 998705#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 999435#L1154-2 assume !(1 == ~T1_E~0); 999770#L1159-1 assume !(1 == ~T2_E~0); 999817#L1164-1 assume !(1 == ~T3_E~0); 999818#L1169-1 assume !(1 == ~T4_E~0); 999009#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 999010#L1179-1 assume !(1 == ~T6_E~0); 998661#L1184-1 assume !(1 == ~T7_E~0); 998662#L1189-1 assume !(1 == ~T8_E~0); 998864#L1194-1 assume !(1 == ~T9_E~0); 998865#L1199-1 assume !(1 == ~T10_E~0); 998821#L1204-1 assume !(1 == ~E_M~0); 998822#L1209-1 assume !(1 == ~E_1~0); 999401#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 999402#L1219-1 assume !(1 == ~E_3~0); 999773#L1224-1 assume !(1 == ~E_4~0); 999177#L1229-1 assume !(1 == ~E_5~0); 998546#L1234-1 assume !(1 == ~E_6~0); 998547#L1239-1 assume !(1 == ~E_7~0); 998602#L1244-1 assume !(1 == ~E_8~0); 998603#L1249-1 assume !(1 == ~E_9~0); 999557#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 998447#L1259-1 assume { :end_inline_reset_delta_events } true; 998448#L1565-2 [2023-11-26 10:47:26,741 INFO L750 eck$LassoCheckResult]: Loop: 998448#L1565-2 assume !false; 1047929#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1047907#L1011-1 assume !false; 1047906#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1047464#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1047451#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1047449#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1047446#L866 assume !(0 != eval_~tmp~0#1); 1047447#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1050295#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1050290#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1050284#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1050278#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1050273#L1046-3 assume !(0 == ~T3_E~0); 1050268#L1051-3 assume !(0 == ~T4_E~0); 1050263#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1050257#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1050253#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1050250#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1050248#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1050191#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1050190#L1086-3 assume !(0 == ~E_M~0); 1050189#L1091-3 assume !(0 == ~E_1~0); 1050188#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1050118#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1050112#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1050106#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1050100#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1050092#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1050084#L1126-3 assume !(0 == ~E_8~0); 1050075#L1131-3 assume !(0 == ~E_9~0); 1050067#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1050061#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1050056#L514-36 assume !(1 == ~m_pc~0); 1050050#L514-38 is_master_triggered_~__retres1~0#1 := 0; 1050043#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1050036#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1050030#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1050025#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1050020#L533-36 assume 1 == ~t1_pc~0; 1050013#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1050007#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1050001#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1049995#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1049989#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1049424#L552-36 assume !(1 == ~t2_pc~0); 1049141#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1048251#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1048248#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1048246#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1048244#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1048242#L571-36 assume !(1 == ~t3_pc~0); 1048240#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1048238#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1048236#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1048234#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1048232#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1048230#L590-36 assume 1 == ~t4_pc~0; 1048228#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1048229#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1048278#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1048219#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1048217#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1048215#L609-36 assume !(1 == ~t5_pc~0); 1048213#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1048209#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1048207#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1048205#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 1048203#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1048200#L628-36 assume !(1 == ~t6_pc~0); 1048191#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1048188#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1048186#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1048184#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1048181#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1048179#L647-36 assume !(1 == ~t7_pc~0); 1018204#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1048176#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1048174#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1048172#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1048170#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1048168#L666-36 assume !(1 == ~t8_pc~0); 1048166#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1048162#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1048160#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1048158#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1048156#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1048154#L685-36 assume 1 == ~t9_pc~0; 1048152#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1048150#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1048148#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1048146#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1048144#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1048142#L704-36 assume !(1 == ~t10_pc~0); 1048140#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1048136#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1048134#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1048132#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1048130#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1048128#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1030995#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1048122#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1048120#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1048116#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1048114#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1048112#L1179-3 assume !(1 == ~T6_E~0); 1048110#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1048107#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1048105#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1048103#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1048101#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1031580#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1048098#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1048096#L1219-3 assume !(1 == ~E_3~0); 1048094#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1048092#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1048090#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1048088#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1048086#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1037402#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1048083#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1048081#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1048058#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1048057#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1048056#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1048054#L1584 assume !(0 == start_simulation_~tmp~3#1); 1048051#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1047955#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1047943#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1047941#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1047939#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1047937#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1047935#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1047933#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 998448#L1565-2 [2023-11-26 10:47:26,741 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:26,742 INFO L85 PathProgramCache]: Analyzing trace with hash 1730432140, now seen corresponding path program 1 times [2023-11-26 10:47:26,742 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:26,742 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [211761474] [2023-11-26 10:47:26,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:26,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:26,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:26,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:26,879 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:26,880 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [211761474] [2023-11-26 10:47:26,880 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [211761474] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:26,880 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:26,880 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:47:26,880 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556705688] [2023-11-26 10:47:26,880 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:26,881 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:47:26,881 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:26,881 INFO L85 PathProgramCache]: Analyzing trace with hash 1116749823, now seen corresponding path program 1 times [2023-11-26 10:47:26,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:26,881 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [258966990] [2023-11-26 10:47:26,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:26,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:26,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:26,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:26,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:26,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [258966990] [2023-11-26 10:47:26,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [258966990] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:26,945 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:26,945 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:47:26,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564211649] [2023-11-26 10:47:26,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:26,946 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:47:26,946 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:47:26,947 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:47:26,947 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:47:26,947 INFO L87 Difference]: Start difference. First operand 227905 states and 323427 transitions. cyclomatic complexity: 95650 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:29,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:47:29,227 INFO L93 Difference]: Finished difference Result 432976 states and 612432 transitions. [2023-11-26 10:47:29,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 432976 states and 612432 transitions. [2023-11-26 10:47:32,251 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 430464 [2023-11-26 10:47:33,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 432976 states to 432976 states and 612432 transitions. [2023-11-26 10:47:33,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 432976 [2023-11-26 10:47:33,619 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 432976 [2023-11-26 10:47:33,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 432976 states and 612432 transitions. [2023-11-26 10:47:33,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:47:33,816 INFO L218 hiAutomatonCegarLoop]: Abstraction has 432976 states and 612432 transitions.