./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.13.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.13.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 10:47:49,764 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 10:47:49,837 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 10:47:49,843 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 10:47:49,843 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 10:47:49,872 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 10:47:49,872 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 10:47:49,873 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 10:47:49,874 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 10:47:49,874 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 10:47:49,875 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 10:47:49,876 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 10:47:49,876 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 10:47:49,877 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 10:47:49,877 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 10:47:49,878 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 10:47:49,879 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 10:47:49,879 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 10:47:49,880 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 10:47:49,880 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 10:47:49,880 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 10:47:49,881 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 10:47:49,882 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 10:47:49,882 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 10:47:49,882 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 10:47:49,883 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 10:47:49,883 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 10:47:49,884 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 10:47:49,884 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 10:47:49,884 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 10:47:49,885 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 10:47:49,885 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 10:47:49,886 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 10:47:49,886 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 10:47:49,886 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 10:47:49,886 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 10:47:49,887 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 10:47:49,887 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 10:47:49,888 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077 [2023-11-26 10:47:50,139 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 10:47:50,172 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 10:47:50,175 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 10:47:50,177 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 10:47:50,178 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 10:47:50,179 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/token_ring.13.cil-1.c [2023-11-26 10:47:53,348 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 10:47:53,701 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 10:47:53,706 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/sv-benchmarks/c/systemc/token_ring.13.cil-1.c [2023-11-26 10:47:53,724 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme/data/962a3c616/0f5f582d950144cdbca73a78d37d17bc/FLAGdcdf3620d [2023-11-26 10:47:53,737 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme/data/962a3c616/0f5f582d950144cdbca73a78d37d17bc [2023-11-26 10:47:53,740 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 10:47:53,748 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 10:47:53,749 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 10:47:53,749 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 10:47:53,755 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 10:47:53,756 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:47:53" (1/1) ... [2023-11-26 10:47:53,757 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5d82575e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:53, skipping insertion in model container [2023-11-26 10:47:53,757 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:47:53" (1/1) ... [2023-11-26 10:47:53,815 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 10:47:54,136 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:47:54,164 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 10:47:54,251 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:47:54,279 INFO L206 MainTranslator]: Completed translation [2023-11-26 10:47:54,279 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:54 WrapperNode [2023-11-26 10:47:54,279 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 10:47:54,281 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 10:47:54,281 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 10:47:54,281 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 10:47:54,289 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:54" (1/1) ... [2023-11-26 10:47:54,304 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:54" (1/1) ... [2023-11-26 10:47:54,543 INFO L138 Inliner]: procedures = 54, calls = 72, calls flagged for inlining = 67, calls inlined = 305, statements flattened = 4696 [2023-11-26 10:47:54,545 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 10:47:54,546 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 10:47:54,546 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 10:47:54,546 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 10:47:54,559 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:54" (1/1) ... [2023-11-26 10:47:54,560 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:54" (1/1) ... [2023-11-26 10:47:54,582 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:54" (1/1) ... [2023-11-26 10:47:54,648 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 10:47:54,649 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:54" (1/1) ... [2023-11-26 10:47:54,649 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:54" (1/1) ... [2023-11-26 10:47:54,720 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:54" (1/1) ... [2023-11-26 10:47:54,771 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:54" (1/1) ... [2023-11-26 10:47:54,780 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:54" (1/1) ... [2023-11-26 10:47:54,798 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:54" (1/1) ... [2023-11-26 10:47:54,820 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 10:47:54,821 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 10:47:54,821 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 10:47:54,821 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 10:47:54,822 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:54" (1/1) ... [2023-11-26 10:47:54,829 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 10:47:54,843 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:47:54,857 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 10:47:54,882 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_278d1a69-9d01-48ad-bbec-7e64a081ba1c/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 10:47:54,904 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 10:47:54,904 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 10:47:54,905 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 10:47:54,905 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 10:47:55,093 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 10:47:55,096 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 10:47:57,980 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 10:47:58,032 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 10:47:58,032 INFO L309 CfgBuilder]: Removed 16 assume(true) statements. [2023-11-26 10:47:58,035 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:47:58 BoogieIcfgContainer [2023-11-26 10:47:58,035 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 10:47:58,036 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 10:47:58,037 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 10:47:58,041 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 10:47:58,041 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:47:58,042 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 10:47:53" (1/3) ... [2023-11-26 10:47:58,043 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@58fb8721 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:47:58, skipping insertion in model container [2023-11-26 10:47:58,043 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:47:58,043 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:47:54" (2/3) ... [2023-11-26 10:47:58,044 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@58fb8721 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:47:58, skipping insertion in model container [2023-11-26 10:47:58,044 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:47:58,044 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:47:58" (3/3) ... [2023-11-26 10:47:58,045 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.13.cil-1.c [2023-11-26 10:47:58,149 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 10:47:58,149 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 10:47:58,149 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 10:47:58,149 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 10:47:58,149 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 10:47:58,149 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 10:47:58,150 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 10:47:58,150 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 10:47:58,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2047 states, 2046 states have (on average 1.4926686217008798) internal successors, (3054), 2046 states have internal predecessors, (3054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:58,263 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1868 [2023-11-26 10:47:58,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:58,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:58,284 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:58,284 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:58,285 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 10:47:58,290 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2047 states, 2046 states have (on average 1.4926686217008798) internal successors, (3054), 2046 states have internal predecessors, (3054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:58,319 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1868 [2023-11-26 10:47:58,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:58,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:58,328 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:58,328 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:58,341 INFO L748 eck$LassoCheckResult]: Stem: 138#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1967#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 740#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1959#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1864#L914true assume !(1 == ~m_i~0);~m_st~0 := 2; 846#L914-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 455#L919-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1235#L924-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1119#L929-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1871#L934-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1276#L939-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1657#L944-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 312#L949-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1326#L954-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1976#L959-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 651#L964-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1185#L969-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1779#L974-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 593#L979-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1903#L1291true assume 0 == ~M_E~0;~M_E~0 := 1; 1867#L1291-2true assume !(0 == ~T1_E~0); 1859#L1296-1true assume !(0 == ~T2_E~0); 700#L1301-1true assume !(0 == ~T3_E~0); 1230#L1306-1true assume !(0 == ~T4_E~0); 1204#L1311-1true assume !(0 == ~T5_E~0); 228#L1316-1true assume !(0 == ~T6_E~0); 1661#L1321-1true assume !(0 == ~T7_E~0); 711#L1326-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 136#L1331-1true assume !(0 == ~T9_E~0); 3#L1336-1true assume !(0 == ~T10_E~0); 1082#L1341-1true assume !(0 == ~T11_E~0); 33#L1346-1true assume !(0 == ~T12_E~0); 1459#L1351-1true assume !(0 == ~T13_E~0); 195#L1356-1true assume !(0 == ~E_M~0); 1985#L1361-1true assume !(0 == ~E_1~0); 1633#L1366-1true assume 0 == ~E_2~0;~E_2~0 := 1; 219#L1371-1true assume !(0 == ~E_3~0); 1437#L1376-1true assume !(0 == ~E_4~0); 764#L1381-1true assume !(0 == ~E_5~0); 1737#L1386-1true assume !(0 == ~E_6~0); 1896#L1391-1true assume !(0 == ~E_7~0); 1811#L1396-1true assume !(0 == ~E_8~0); 671#L1401-1true assume !(0 == ~E_9~0); 1292#L1406-1true assume 0 == ~E_10~0;~E_10~0 := 1; 917#L1411-1true assume !(0 == ~E_11~0); 1695#L1416-1true assume !(0 == ~E_12~0); 619#L1421-1true assume !(0 == ~E_13~0); 322#L1426-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 769#L640true assume !(1 == ~m_pc~0); 1815#L640-2true is_master_triggered_~__retres1~0#1 := 0; 727#L651true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 623#is_master_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 643#L1603true assume !(0 != activate_threads_~tmp~1#1); 1277#L1603-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 410#L659true assume 1 == ~t1_pc~0; 473#L660true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1419#L670true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1044#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 486#L1611true assume !(0 != activate_threads_~tmp___0~0#1); 495#L1611-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1601#L678true assume 1 == ~t2_pc~0; 1460#L679true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1715#L689true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 241#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 556#L1619true assume !(0 != activate_threads_~tmp___1~0#1); 696#L1619-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 640#L697true assume !(1 == ~t3_pc~0); 747#L697-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1505#L708true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1026#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 580#L1627true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1927#L1627-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1542#L716true assume 1 == ~t4_pc~0; 1514#L717true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 397#L727true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 118#L1635true assume !(0 != activate_threads_~tmp___3~0#1); 991#L1635-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1484#L735true assume !(1 == ~t5_pc~0); 104#L735-2true is_transmit5_triggered_~__retres1~5#1 := 0; 338#L746true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1648#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1015#L1643true assume !(0 != activate_threads_~tmp___4~0#1); 693#L1643-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 884#L754true assume 1 == ~t6_pc~0; 529#L755true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 464#L765true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 230#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 447#L1651true assume !(0 != activate_threads_~tmp___5~0#1); 1108#L1651-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1974#L773true assume !(1 == ~t7_pc~0); 904#L773-2true is_transmit7_triggered_~__retres1~7#1 := 0; 729#L784true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1987#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 702#L1659true assume !(0 != activate_threads_~tmp___6~0#1); 757#L1659-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 892#L792true assume 1 == ~t8_pc~0; 1969#L793true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1278#L803true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1571#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 694#L1667true assume !(0 != activate_threads_~tmp___7~0#1); 641#L1667-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 813#L811true assume 1 == ~t9_pc~0; 1341#L812true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1710#L822true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 269#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 809#L1675true assume !(0 != activate_threads_~tmp___8~0#1); 648#L1675-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1740#L830true assume !(1 == ~t10_pc~0); 2034#L830-2true is_transmit10_triggered_~__retres1~10#1 := 0; 185#L841true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1355#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 173#L1683true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1806#L1683-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1130#L849true assume 1 == ~t11_pc~0; 1629#L850true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 92#L860true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1461#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1149#L1691true assume !(0 != activate_threads_~tmp___10~0#1); 1021#L1691-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1813#L868true assume !(1 == ~t12_pc~0); 1391#L868-2true is_transmit12_triggered_~__retres1~12#1 := 0; 576#L879true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1730#L1699true assume !(0 != activate_threads_~tmp___11~0#1); 203#L1699-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1631#L887true assume 1 == ~t13_pc~0; 1031#L888true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 577#L898true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1396#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1097#L1707true assume !(0 != activate_threads_~tmp___12~0#1); 57#L1707-2true havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1687#L1439true assume !(1 == ~M_E~0); 689#L1439-2true assume !(1 == ~T1_E~0); 143#L1444-1true assume !(1 == ~T2_E~0); 922#L1449-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 412#L1454-1true assume !(1 == ~T4_E~0); 1458#L1459-1true assume !(1 == ~T5_E~0); 806#L1464-1true assume !(1 == ~T6_E~0); 868#L1469-1true assume !(1 == ~T7_E~0); 1718#L1474-1true assume !(1 == ~T8_E~0); 620#L1479-1true assume !(1 == ~T9_E~0); 810#L1484-1true assume !(1 == ~T10_E~0); 1249#L1489-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 542#L1494-1true assume !(1 == ~T12_E~0); 1849#L1499-1true assume !(1 == ~T13_E~0); 661#L1504-1true assume !(1 == ~E_M~0); 1513#L1509-1true assume !(1 == ~E_1~0); 1247#L1514-1true assume !(1 == ~E_2~0); 893#L1519-1true assume !(1 == ~E_3~0); 1968#L1524-1true assume !(1 == ~E_4~0); 1676#L1529-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1780#L1534-1true assume !(1 == ~E_6~0); 54#L1539-1true assume !(1 == ~E_7~0); 267#L1544-1true assume !(1 == ~E_8~0); 1593#L1549-1true assume !(1 == ~E_9~0); 1617#L1554-1true assume !(1 == ~E_10~0); 1589#L1559-1true assume !(1 == ~E_11~0); 1316#L1564-1true assume !(1 == ~E_12~0); 1658#L1569-1true assume 1 == ~E_13~0;~E_13~0 := 2; 1756#L1574-1true assume { :end_inline_reset_delta_events } true; 142#L1940-2true [2023-11-26 10:47:58,346 INFO L750 eck$LassoCheckResult]: Loop: 142#L1940-2true assume !false; 1560#L1941true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1831#L1266-1true assume false; 571#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 359#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 974#L1291-3true assume 0 == ~M_E~0;~M_E~0 := 1; 869#L1291-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1876#L1296-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1783#L1301-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1615#L1306-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 596#L1311-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 161#L1316-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 214#L1321-3true assume !(0 == ~T7_E~0); 684#L1326-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1578#L1331-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 897#L1336-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1499#L1341-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 408#L1346-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 393#L1351-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 358#L1356-3true assume 0 == ~E_M~0;~E_M~0 := 1; 748#L1361-3true assume !(0 == ~E_1~0); 777#L1366-3true assume 0 == ~E_2~0;~E_2~0 := 1; 24#L1371-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1286#L1376-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1551#L1381-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1084#L1386-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1685#L1391-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1332#L1396-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1990#L1401-3true assume !(0 == ~E_9~0); 192#L1406-3true assume 0 == ~E_10~0;~E_10~0 := 1; 122#L1411-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1782#L1416-3true assume 0 == ~E_12~0;~E_12~0 := 1; 502#L1421-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1118#L1426-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 574#L640-45true assume 1 == ~m_pc~0; 1144#L641-15true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 247#L651-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 939#is_master_triggered_returnLabel#16true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22#L1603-45true assume !(0 != activate_threads_~tmp~1#1); 1870#L1603-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60#L659-45true assume 1 == ~t1_pc~0; 1932#L660-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1796#L670-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1873#is_transmit1_triggered_returnLabel#16true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1556#L1611-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 999#L1611-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1525#L678-45true assume !(1 == ~t2_pc~0); 978#L678-47true is_transmit2_triggered_~__retres1~2#1 := 0; 578#L689-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 936#is_transmit2_triggered_returnLabel#16true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1363#L1619-45true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1672#L1619-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1609#L697-45true assume !(1 == ~t3_pc~0); 1242#L697-47true is_transmit3_triggered_~__retres1~3#1 := 0; 1863#L708-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2007#is_transmit3_triggered_returnLabel#16true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 905#L1627-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 941#L1627-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2030#L716-45true assume !(1 == ~t4_pc~0); 1074#L716-47true is_transmit4_triggered_~__retres1~4#1 := 0; 2025#L727-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1295#is_transmit4_triggered_returnLabel#16true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 631#L1635-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1508#L1635-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 418#L735-45true assume 1 == ~t5_pc~0; 803#L736-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1664#L746-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2002#is_transmit5_triggered_returnLabel#16true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1844#L1643-45true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1670#L1643-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1654#L754-45true assume !(1 == ~t6_pc~0); 1494#L754-47true is_transmit6_triggered_~__retres1~6#1 := 0; 2008#L765-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 668#is_transmit6_triggered_returnLabel#16true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1980#L1651-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 770#L1651-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 560#L773-45true assume 1 == ~t7_pc~0; 1175#L774-15true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 948#L784-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 738#is_transmit7_triggered_returnLabel#16true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1395#L1659-45true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 568#L1659-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 355#L792-45true assume 1 == ~t8_pc~0; 1507#L793-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1196#L803-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1725#is_transmit8_triggered_returnLabel#16true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 70#L1667-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 728#L1667-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 327#L811-45true assume 1 == ~t9_pc~0; 211#L812-15true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1098#L822-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1079#is_transmit9_triggered_returnLabel#16true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 932#L1675-45true assume !(0 != activate_threads_~tmp___8~0#1); 614#L1675-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 477#L830-45true assume !(1 == ~t10_pc~0); 38#L830-47true is_transmit10_triggered_~__retres1~10#1 := 0; 688#L841-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1195#is_transmit10_triggered_returnLabel#16true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 148#L1683-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1371#L1683-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31#L849-45true assume 1 == ~t11_pc~0; 739#L850-15true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 255#L860-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 177#is_transmit11_triggered_returnLabel#16true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25#L1691-45true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 175#L1691-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 146#L868-45true assume 1 == ~t12_pc~0; 404#L869-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 115#L879-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1123#is_transmit12_triggered_returnLabel#16true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1929#L1699-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1385#L1699-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1949#L887-45true assume 1 == ~t13_pc~0; 1124#L888-15true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1033#L898-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1056#is_transmit13_triggered_returnLabel#16true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1957#L1707-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 132#L1707-47true havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1050#L1439-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1025#L1439-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 141#L1444-3true assume !(1 == ~T2_E~0); 221#L1449-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1614#L1454-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 857#L1459-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 2028#L1464-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1393#L1469-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1291#L1474-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1623#L1479-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1397#L1484-3true assume !(1 == ~T10_E~0); 600#L1489-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1177#L1494-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1807#L1499-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 819#L1504-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1311#L1509-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1364#L1514-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1907#L1519-3true assume 1 == ~E_3~0;~E_3~0 := 2; 547#L1524-3true assume !(1 == ~E_4~0); 1443#L1529-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1675#L1534-3true assume 1 == ~E_6~0;~E_6~0 := 2; 754#L1539-3true assume 1 == ~E_7~0;~E_7~0 := 2; 384#L1544-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1407#L1549-3true assume 1 == ~E_9~0;~E_9~0 := 2; 714#L1554-3true assume 1 == ~E_10~0;~E_10~0 := 2; 164#L1559-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1206#L1564-3true assume !(1 == ~E_12~0); 942#L1569-3true assume 1 == ~E_13~0;~E_13~0 := 2; 1169#L1574-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 110#L992-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 160#L1064-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 205#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 113#L1959true assume !(0 == start_simulation_~tmp~3#1); 128#L1959-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 900#L992-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 980#L1064-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1429#L1914true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1600#L1921true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1374#stop_simulation_returnLabel#1true start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1616#L1972true assume !(0 != start_simulation_~tmp___0~1#1); 142#L1940-2true [2023-11-26 10:47:58,353 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:58,353 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2023-11-26 10:47:58,363 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:58,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294994786] [2023-11-26 10:47:58,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:58,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:58,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:58,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:58,865 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:58,866 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1294994786] [2023-11-26 10:47:58,866 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1294994786] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:58,867 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:58,867 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:47:58,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1640218665] [2023-11-26 10:47:58,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:58,874 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:47:58,875 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:58,876 INFO L85 PathProgramCache]: Analyzing trace with hash -462906928, now seen corresponding path program 1 times [2023-11-26 10:47:58,876 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:58,876 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1956229641] [2023-11-26 10:47:58,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:58,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:58,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:58,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:58,965 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:58,965 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1956229641] [2023-11-26 10:47:58,965 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1956229641] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:58,965 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:58,966 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:47:58,966 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1358440655] [2023-11-26 10:47:58,966 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:58,967 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:47:58,968 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:47:59,006 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-26 10:47:59,007 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-26 10:47:59,013 INFO L87 Difference]: Start difference. First operand has 2047 states, 2046 states have (on average 1.4926686217008798) internal successors, (3054), 2046 states have internal predecessors, (3054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:59,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:47:59,111 INFO L93 Difference]: Finished difference Result 2043 states and 3016 transitions. [2023-11-26 10:47:59,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2043 states and 3016 transitions. [2023-11-26 10:47:59,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:47:59,165 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2043 states to 2037 states and 3010 transitions. [2023-11-26 10:47:59,166 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2023-11-26 10:47:59,169 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2023-11-26 10:47:59,170 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3010 transitions. [2023-11-26 10:47:59,184 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:47:59,184 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3010 transitions. [2023-11-26 10:47:59,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3010 transitions. [2023-11-26 10:47:59,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2023-11-26 10:47:59,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.47766323024055) internal successors, (3010), 2036 states have internal predecessors, (3010), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:59,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3010 transitions. [2023-11-26 10:47:59,303 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3010 transitions. [2023-11-26 10:47:59,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-26 10:47:59,309 INFO L428 stractBuchiCegarLoop]: Abstraction has 2037 states and 3010 transitions. [2023-11-26 10:47:59,310 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 10:47:59,310 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3010 transitions. [2023-11-26 10:47:59,325 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:47:59,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:59,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:59,330 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:59,331 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:59,332 INFO L748 eck$LassoCheckResult]: Stem: 4391#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5385#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5386#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6121#L914 assume !(1 == ~m_i~0);~m_st~0 := 2; 5513#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4982#L919-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4983#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5787#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5788#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5892#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5893#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4731#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4732#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5927#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5283#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5284#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5833#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5197#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5198#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 6122#L1291-2 assume !(0 == ~T1_E~0); 6119#L1296-1 assume !(0 == ~T2_E~0); 5347#L1301-1 assume !(0 == ~T3_E~0); 5348#L1306-1 assume !(0 == ~T4_E~0); 5843#L1311-1 assume !(0 == ~T5_E~0); 4568#L1316-1 assume !(0 == ~T6_E~0); 4569#L1321-1 assume !(0 == ~T7_E~0); 5361#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4388#L1331-1 assume !(0 == ~T9_E~0); 4101#L1336-1 assume !(0 == ~T10_E~0); 4102#L1341-1 assume !(0 == ~T11_E~0); 4175#L1346-1 assume !(0 == ~T12_E~0); 4176#L1351-1 assume !(0 == ~T13_E~0); 4505#L1356-1 assume !(0 == ~E_M~0); 4506#L1361-1 assume !(0 == ~E_1~0); 6059#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4552#L1371-1 assume !(0 == ~E_3~0); 4553#L1376-1 assume !(0 == ~E_4~0); 5413#L1381-1 assume !(0 == ~E_5~0); 5414#L1386-1 assume !(0 == ~E_6~0); 6090#L1391-1 assume !(0 == ~E_7~0); 6110#L1396-1 assume !(0 == ~E_8~0); 5315#L1401-1 assume !(0 == ~E_9~0); 5316#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5603#L1411-1 assume !(0 == ~E_11~0); 5604#L1416-1 assume !(0 == ~E_12~0); 5233#L1421-1 assume !(0 == ~E_13~0); 4752#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4753#L640 assume !(1 == ~m_pc~0); 5282#L640-2 is_master_triggered_~__retres1~0#1 := 0; 5281#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5241#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5242#L1603 assume !(0 != activate_threads_~tmp~1#1); 5270#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4902#L659 assume 1 == ~t1_pc~0; 4903#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5011#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5724#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5033#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 5034#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5050#L678 assume 1 == ~t2_pc~0; 5996#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5997#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4595#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4596#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 5144#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5263#L697 assume !(1 == ~t3_pc~0); 5264#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5394#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5714#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5177#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5178#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6029#L716 assume 1 == ~t4_pc~0; 6017#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4882#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4248#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4249#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 4356#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5678#L735 assume !(1 == ~t5_pc~0); 4323#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4324#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4779#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5704#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 5341#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5342#L754 assume 1 == ~t6_pc~0; 5095#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4995#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4572#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4573#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 4969#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5778#L773 assume !(1 == ~t7_pc~0); 4509#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4508#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5376#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5351#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 5352#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5405#L792 assume 1 == ~t8_pc~0; 5573#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5894#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5895#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5343#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 5266#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5267#L811 assume 1 == ~t9_pc~0; 5476#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5941#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4651#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4652#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 5278#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5279#L830 assume !(1 == ~t10_pc~0); 5004#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4485#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4486#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4463#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4464#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5796#L849 assume 1 == ~t11_pc~0; 5797#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4302#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4303#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5807#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 5708#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5709#L868 assume !(1 == ~t12_pc~0); 5128#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 5127#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4190#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4191#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 4520#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4521#L887 assume 1 == ~t13_pc~0; 5716#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5171#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5172#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5772#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 4230#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4231#L1439 assume !(1 == ~M_E~0); 5335#L1439-2 assume !(1 == ~T1_E~0); 4401#L1444-1 assume !(1 == ~T2_E~0); 4402#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4907#L1454-1 assume !(1 == ~T4_E~0); 4908#L1459-1 assume !(1 == ~T5_E~0); 5468#L1464-1 assume !(1 == ~T6_E~0); 5469#L1469-1 assume !(1 == ~T7_E~0); 5542#L1474-1 assume !(1 == ~T8_E~0); 5234#L1479-1 assume !(1 == ~T9_E~0); 5235#L1484-1 assume !(1 == ~T10_E~0); 5472#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5117#L1494-1 assume !(1 == ~T12_E~0); 5118#L1499-1 assume !(1 == ~T13_E~0); 5300#L1504-1 assume !(1 == ~E_M~0); 5301#L1509-1 assume !(1 == ~E_1~0); 5879#L1514-1 assume !(1 == ~E_2~0); 5575#L1519-1 assume !(1 == ~E_3~0); 5576#L1524-1 assume !(1 == ~E_4~0); 6074#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 6075#L1534-1 assume !(1 == ~E_6~0); 4224#L1539-1 assume !(1 == ~E_7~0); 4225#L1544-1 assume !(1 == ~E_8~0); 4648#L1549-1 assume !(1 == ~E_9~0); 6047#L1554-1 assume !(1 == ~E_10~0); 6044#L1559-1 assume !(1 == ~E_11~0); 5919#L1564-1 assume !(1 == ~E_12~0); 5920#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 6069#L1574-1 assume { :end_inline_reset_delta_events } true; 4399#L1940-2 [2023-11-26 10:47:59,333 INFO L750 eck$LassoCheckResult]: Loop: 4399#L1940-2 assume !false; 4400#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4943#L1266-1 assume !false; 6113#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4964#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4678#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5878#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5887#L1079 assume !(0 != eval_~tmp~0#1); 5161#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4816#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4817#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5543#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5544#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6100#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6055#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5201#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4437#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4438#L1321-3 assume !(0 == ~T7_E~0); 4542#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5330#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5581#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5582#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4899#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4876#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4814#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4815#L1361-3 assume !(0 == ~E_1~0); 5395#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4153#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4154#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5899#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5758#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5759#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5933#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5934#L1401-3 assume !(0 == ~E_9~0); 4500#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4364#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4365#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 5058#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5059#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5166#L640-45 assume 1 == ~m_pc~0; 5168#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4608#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4609#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4149#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 4150#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4238#L659-45 assume !(1 == ~t1_pc~0); 4240#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 4692#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6104#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6034#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5687#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5688#L678-45 assume 1 == ~t2_pc~0; 5639#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5173#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5174#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5621#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5950#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6053#L697-45 assume 1 == ~t3_pc~0; 5434#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5435#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6120#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5587#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5588#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5622#L716-45 assume 1 == ~t4_pc~0; 5246#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5248#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5905#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5253#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5254#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4917#L735-45 assume 1 == ~t5_pc~0; 4918#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5466#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6071#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6117#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6073#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6067#L754-45 assume 1 == ~t6_pc~0; 5417#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5418#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5311#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5312#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5422#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5149#L773-45 assume !(1 == ~t7_pc~0); 4688#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 4689#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5383#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5384#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5157#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4808#L792-45 assume 1 == ~t8_pc~0; 4809#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5837#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5838#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4259#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4260#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4758#L811-45 assume 1 == ~t9_pc~0; 4535#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4536#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5755#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5618#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 5225#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5016#L830-45 assume 1 == ~t10_pc~0; 5017#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4186#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5334#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4410#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4411#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4169#L849-45 assume !(1 == ~t11_pc~0); 4170#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4626#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4467#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4155#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4156#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4405#L868-45 assume 1 == ~t12_pc~0; 4406#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4349#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4350#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5790#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5963#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5964#L887-45 assume !(1 == ~t13_pc~0); 4412#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 4413#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5718#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5737#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4379#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4380#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5713#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4397#L1444-3 assume !(1 == ~T2_E~0); 4398#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4556#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5524#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5525#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5965#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5902#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5903#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5967#L1484-3 assume !(1 == ~T10_E~0); 5207#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5208#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5830#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5483#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5484#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5915#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5951#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5124#L1524-3 assume !(1 == ~E_4~0); 5125#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5989#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5402#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4859#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4860#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5365#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4444#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4445#L1564-3 assume !(1 == ~E_12~0); 5623#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5624#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4336#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4110#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4436#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4343#L1959 assume !(0 == start_simulation_~tmp~3#1); 4345#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4375#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4329#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4164#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 4165#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5983#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5958#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 5959#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 4399#L1940-2 [2023-11-26 10:47:59,334 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:59,334 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2023-11-26 10:47:59,335 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:59,335 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445983110] [2023-11-26 10:47:59,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:59,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:59,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:59,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:59,524 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:59,524 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1445983110] [2023-11-26 10:47:59,525 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1445983110] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:59,525 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:59,525 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:47:59,526 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266892496] [2023-11-26 10:47:59,526 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:59,527 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:47:59,529 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:59,530 INFO L85 PathProgramCache]: Analyzing trace with hash -1337622148, now seen corresponding path program 1 times [2023-11-26 10:47:59,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:59,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711788853] [2023-11-26 10:47:59,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:59,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:59,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:47:59,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:47:59,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:47:59,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1711788853] [2023-11-26 10:47:59,704 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1711788853] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:47:59,705 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:47:59,705 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:47:59,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [950826862] [2023-11-26 10:47:59,706 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:47:59,706 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:47:59,707 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:47:59,707 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:47:59,707 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:47:59,708 INFO L87 Difference]: Start difference. First operand 2037 states and 3010 transitions. cyclomatic complexity: 974 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:59,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:47:59,772 INFO L93 Difference]: Finished difference Result 2037 states and 3009 transitions. [2023-11-26 10:47:59,772 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3009 transitions. [2023-11-26 10:47:59,790 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:47:59,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3009 transitions. [2023-11-26 10:47:59,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2023-11-26 10:47:59,811 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2023-11-26 10:47:59,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3009 transitions. [2023-11-26 10:47:59,815 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:47:59,816 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3009 transitions. [2023-11-26 10:47:59,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3009 transitions. [2023-11-26 10:47:59,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2023-11-26 10:47:59,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4771723122238587) internal successors, (3009), 2036 states have internal predecessors, (3009), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:47:59,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3009 transitions. [2023-11-26 10:47:59,872 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3009 transitions. [2023-11-26 10:47:59,873 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:47:59,874 INFO L428 stractBuchiCegarLoop]: Abstraction has 2037 states and 3009 transitions. [2023-11-26 10:47:59,875 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 10:47:59,875 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3009 transitions. [2023-11-26 10:47:59,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:47:59,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:47:59,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:47:59,901 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:59,901 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:47:59,903 INFO L748 eck$LassoCheckResult]: Stem: 8472#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8473#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 9466#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9467#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10202#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 9594#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9063#L919-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 9064#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9868#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9869#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9973#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9974#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8812#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8813#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10008#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9364#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9365#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9914#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9278#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9279#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 10203#L1291-2 assume !(0 == ~T1_E~0); 10200#L1296-1 assume !(0 == ~T2_E~0); 9428#L1301-1 assume !(0 == ~T3_E~0); 9429#L1306-1 assume !(0 == ~T4_E~0); 9924#L1311-1 assume !(0 == ~T5_E~0); 8649#L1316-1 assume !(0 == ~T6_E~0); 8650#L1321-1 assume !(0 == ~T7_E~0); 9442#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8469#L1331-1 assume !(0 == ~T9_E~0); 8182#L1336-1 assume !(0 == ~T10_E~0); 8183#L1341-1 assume !(0 == ~T11_E~0); 8256#L1346-1 assume !(0 == ~T12_E~0); 8257#L1351-1 assume !(0 == ~T13_E~0); 8586#L1356-1 assume !(0 == ~E_M~0); 8587#L1361-1 assume !(0 == ~E_1~0); 10140#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 8633#L1371-1 assume !(0 == ~E_3~0); 8634#L1376-1 assume !(0 == ~E_4~0); 9494#L1381-1 assume !(0 == ~E_5~0); 9495#L1386-1 assume !(0 == ~E_6~0); 10171#L1391-1 assume !(0 == ~E_7~0); 10191#L1396-1 assume !(0 == ~E_8~0); 9396#L1401-1 assume !(0 == ~E_9~0); 9397#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 9684#L1411-1 assume !(0 == ~E_11~0); 9685#L1416-1 assume !(0 == ~E_12~0); 9314#L1421-1 assume !(0 == ~E_13~0); 8833#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8834#L640 assume !(1 == ~m_pc~0); 9363#L640-2 is_master_triggered_~__retres1~0#1 := 0; 9362#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9322#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9323#L1603 assume !(0 != activate_threads_~tmp~1#1); 9351#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8983#L659 assume 1 == ~t1_pc~0; 8984#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9092#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9805#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9114#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 9115#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9131#L678 assume 1 == ~t2_pc~0; 10077#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10078#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8676#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8677#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 9225#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9344#L697 assume !(1 == ~t3_pc~0); 9345#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9475#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9795#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9258#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9259#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10110#L716 assume 1 == ~t4_pc~0; 10098#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8963#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8329#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8330#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 8437#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9759#L735 assume !(1 == ~t5_pc~0); 8404#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8405#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8860#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9785#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 9422#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9423#L754 assume 1 == ~t6_pc~0; 9176#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9076#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8653#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8654#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 9050#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9859#L773 assume !(1 == ~t7_pc~0); 8590#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8589#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9457#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9432#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 9433#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9486#L792 assume 1 == ~t8_pc~0; 9654#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9975#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9976#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9424#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 9347#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9348#L811 assume 1 == ~t9_pc~0; 9557#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10022#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8732#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8733#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 9359#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9360#L830 assume !(1 == ~t10_pc~0); 9085#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8566#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8567#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8544#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8545#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9877#L849 assume 1 == ~t11_pc~0; 9878#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8383#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8384#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9888#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 9789#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9790#L868 assume !(1 == ~t12_pc~0); 9209#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 9208#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8271#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8272#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 8601#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8602#L887 assume 1 == ~t13_pc~0; 9797#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9252#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9253#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9853#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 8311#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8312#L1439 assume !(1 == ~M_E~0); 9416#L1439-2 assume !(1 == ~T1_E~0); 8482#L1444-1 assume !(1 == ~T2_E~0); 8483#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8988#L1454-1 assume !(1 == ~T4_E~0); 8989#L1459-1 assume !(1 == ~T5_E~0); 9549#L1464-1 assume !(1 == ~T6_E~0); 9550#L1469-1 assume !(1 == ~T7_E~0); 9623#L1474-1 assume !(1 == ~T8_E~0); 9315#L1479-1 assume !(1 == ~T9_E~0); 9316#L1484-1 assume !(1 == ~T10_E~0); 9553#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9198#L1494-1 assume !(1 == ~T12_E~0); 9199#L1499-1 assume !(1 == ~T13_E~0); 9381#L1504-1 assume !(1 == ~E_M~0); 9382#L1509-1 assume !(1 == ~E_1~0); 9960#L1514-1 assume !(1 == ~E_2~0); 9656#L1519-1 assume !(1 == ~E_3~0); 9657#L1524-1 assume !(1 == ~E_4~0); 10155#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 10156#L1534-1 assume !(1 == ~E_6~0); 8305#L1539-1 assume !(1 == ~E_7~0); 8306#L1544-1 assume !(1 == ~E_8~0); 8729#L1549-1 assume !(1 == ~E_9~0); 10128#L1554-1 assume !(1 == ~E_10~0); 10125#L1559-1 assume !(1 == ~E_11~0); 10000#L1564-1 assume !(1 == ~E_12~0); 10001#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 10150#L1574-1 assume { :end_inline_reset_delta_events } true; 8480#L1940-2 [2023-11-26 10:47:59,904 INFO L750 eck$LassoCheckResult]: Loop: 8480#L1940-2 assume !false; 8481#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9024#L1266-1 assume !false; 10194#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9045#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8759#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9959#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9968#L1079 assume !(0 != eval_~tmp~0#1); 9242#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8897#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8898#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9624#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9625#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10181#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10136#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9282#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8518#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8519#L1321-3 assume !(0 == ~T7_E~0); 8623#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9411#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9662#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9663#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8980#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8957#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8895#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8896#L1361-3 assume !(0 == ~E_1~0); 9476#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8234#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8235#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9980#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9839#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9840#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10014#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10015#L1401-3 assume !(0 == ~E_9~0); 8581#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8445#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 8446#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 9139#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9140#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9247#L640-45 assume !(1 == ~m_pc~0); 9248#L640-47 is_master_triggered_~__retres1~0#1 := 0; 8689#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8690#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8230#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 8231#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8319#L659-45 assume 1 == ~t1_pc~0; 8320#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8773#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10185#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10115#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9768#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9769#L678-45 assume 1 == ~t2_pc~0; 9720#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9254#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9255#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9702#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10031#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10134#L697-45 assume 1 == ~t3_pc~0; 9515#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9516#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10201#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9668#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9669#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9703#L716-45 assume !(1 == ~t4_pc~0); 9328#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 9329#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9986#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9334#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9335#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8998#L735-45 assume 1 == ~t5_pc~0; 8999#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9547#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10152#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10198#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10154#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10148#L754-45 assume 1 == ~t6_pc~0; 9498#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9499#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9392#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9393#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9503#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9230#L773-45 assume !(1 == ~t7_pc~0); 8769#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 8770#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9464#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9465#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9238#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8889#L792-45 assume 1 == ~t8_pc~0; 8890#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9918#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9919#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8340#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8341#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8839#L811-45 assume 1 == ~t9_pc~0; 8616#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8617#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9836#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9699#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 9306#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9097#L830-45 assume 1 == ~t10_pc~0; 9098#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8267#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9415#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8491#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8492#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8250#L849-45 assume !(1 == ~t11_pc~0); 8251#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 8707#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8548#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8236#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8237#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8486#L868-45 assume 1 == ~t12_pc~0; 8487#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8430#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8431#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9871#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10044#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 10045#L887-45 assume 1 == ~t13_pc~0; 9872#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8494#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9799#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9818#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8460#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8461#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9794#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8478#L1444-3 assume !(1 == ~T2_E~0); 8479#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8637#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9605#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9606#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10046#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9983#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9984#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10048#L1484-3 assume !(1 == ~T10_E~0); 9288#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9289#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9911#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 9564#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9565#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9996#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10032#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9205#L1524-3 assume !(1 == ~E_4~0); 9206#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10070#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9483#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8940#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8941#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9446#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8525#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8526#L1564-3 assume !(1 == ~E_12~0); 9704#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9705#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8417#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8191#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8517#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 8424#L1959 assume !(0 == start_simulation_~tmp~3#1); 8426#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8456#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8410#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8245#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 8246#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10064#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10039#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 10040#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 8480#L1940-2 [2023-11-26 10:47:59,907 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:47:59,908 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2023-11-26 10:47:59,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:47:59,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [734547037] [2023-11-26 10:47:59,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:47:59,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:47:59,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:00,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:00,009 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:00,009 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [734547037] [2023-11-26 10:48:00,009 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [734547037] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:00,010 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:00,010 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:00,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795237007] [2023-11-26 10:48:00,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:00,011 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:00,012 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:00,012 INFO L85 PathProgramCache]: Analyzing trace with hash -828534276, now seen corresponding path program 1 times [2023-11-26 10:48:00,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:00,012 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [156847733] [2023-11-26 10:48:00,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:00,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:00,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:00,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:00,137 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:00,138 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [156847733] [2023-11-26 10:48:00,138 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [156847733] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:00,139 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:00,139 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:00,139 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1574030398] [2023-11-26 10:48:00,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:00,140 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:00,140 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:00,140 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:00,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:00,141 INFO L87 Difference]: Start difference. First operand 2037 states and 3009 transitions. cyclomatic complexity: 973 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:00,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:00,202 INFO L93 Difference]: Finished difference Result 2037 states and 3008 transitions. [2023-11-26 10:48:00,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3008 transitions. [2023-11-26 10:48:00,221 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:00,238 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3008 transitions. [2023-11-26 10:48:00,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2023-11-26 10:48:00,291 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2023-11-26 10:48:00,291 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3008 transitions. [2023-11-26 10:48:00,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:00,294 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3008 transitions. [2023-11-26 10:48:00,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3008 transitions. [2023-11-26 10:48:00,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2023-11-26 10:48:00,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4766813942071675) internal successors, (3008), 2036 states have internal predecessors, (3008), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:00,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3008 transitions. [2023-11-26 10:48:00,354 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3008 transitions. [2023-11-26 10:48:00,355 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:00,356 INFO L428 stractBuchiCegarLoop]: Abstraction has 2037 states and 3008 transitions. [2023-11-26 10:48:00,357 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 10:48:00,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3008 transitions. [2023-11-26 10:48:00,369 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:00,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:00,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:00,374 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:00,374 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:00,375 INFO L748 eck$LassoCheckResult]: Stem: 12553#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 12554#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 13547#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13548#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14283#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 13675#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13144#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13145#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13949#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13950#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14054#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14055#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12893#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12894#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14089#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13445#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13446#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13995#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13359#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13360#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 14284#L1291-2 assume !(0 == ~T1_E~0); 14281#L1296-1 assume !(0 == ~T2_E~0); 13509#L1301-1 assume !(0 == ~T3_E~0); 13510#L1306-1 assume !(0 == ~T4_E~0); 14005#L1311-1 assume !(0 == ~T5_E~0); 12730#L1316-1 assume !(0 == ~T6_E~0); 12731#L1321-1 assume !(0 == ~T7_E~0); 13523#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12550#L1331-1 assume !(0 == ~T9_E~0); 12263#L1336-1 assume !(0 == ~T10_E~0); 12264#L1341-1 assume !(0 == ~T11_E~0); 12337#L1346-1 assume !(0 == ~T12_E~0); 12338#L1351-1 assume !(0 == ~T13_E~0); 12667#L1356-1 assume !(0 == ~E_M~0); 12668#L1361-1 assume !(0 == ~E_1~0); 14221#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12714#L1371-1 assume !(0 == ~E_3~0); 12715#L1376-1 assume !(0 == ~E_4~0); 13575#L1381-1 assume !(0 == ~E_5~0); 13576#L1386-1 assume !(0 == ~E_6~0); 14252#L1391-1 assume !(0 == ~E_7~0); 14272#L1396-1 assume !(0 == ~E_8~0); 13477#L1401-1 assume !(0 == ~E_9~0); 13478#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 13765#L1411-1 assume !(0 == ~E_11~0); 13766#L1416-1 assume !(0 == ~E_12~0); 13395#L1421-1 assume !(0 == ~E_13~0); 12914#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12915#L640 assume !(1 == ~m_pc~0); 13444#L640-2 is_master_triggered_~__retres1~0#1 := 0; 13443#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13403#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13404#L1603 assume !(0 != activate_threads_~tmp~1#1); 13432#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13064#L659 assume 1 == ~t1_pc~0; 13065#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13173#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13886#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13195#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 13196#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13212#L678 assume 1 == ~t2_pc~0; 14158#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14159#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12757#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12758#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 13306#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13425#L697 assume !(1 == ~t3_pc~0); 13426#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13556#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13876#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13339#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13340#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14191#L716 assume 1 == ~t4_pc~0; 14179#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13044#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12410#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12411#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 12518#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13840#L735 assume !(1 == ~t5_pc~0); 12485#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12486#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12941#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13866#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 13503#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13504#L754 assume 1 == ~t6_pc~0; 13257#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13157#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12734#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12735#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 13131#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13940#L773 assume !(1 == ~t7_pc~0); 12671#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12670#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13538#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13513#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 13514#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13567#L792 assume 1 == ~t8_pc~0; 13735#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14056#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14057#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13505#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 13428#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13429#L811 assume 1 == ~t9_pc~0; 13638#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14103#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12813#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12814#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 13440#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13441#L830 assume !(1 == ~t10_pc~0); 13166#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12647#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12648#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12625#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12626#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13958#L849 assume 1 == ~t11_pc~0; 13959#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12464#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12465#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13969#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 13870#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13871#L868 assume !(1 == ~t12_pc~0); 13290#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 13289#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12352#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12353#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 12682#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12683#L887 assume 1 == ~t13_pc~0; 13878#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13333#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13334#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13934#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 12392#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12393#L1439 assume !(1 == ~M_E~0); 13497#L1439-2 assume !(1 == ~T1_E~0); 12563#L1444-1 assume !(1 == ~T2_E~0); 12564#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13069#L1454-1 assume !(1 == ~T4_E~0); 13070#L1459-1 assume !(1 == ~T5_E~0); 13630#L1464-1 assume !(1 == ~T6_E~0); 13631#L1469-1 assume !(1 == ~T7_E~0); 13704#L1474-1 assume !(1 == ~T8_E~0); 13396#L1479-1 assume !(1 == ~T9_E~0); 13397#L1484-1 assume !(1 == ~T10_E~0); 13634#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13279#L1494-1 assume !(1 == ~T12_E~0); 13280#L1499-1 assume !(1 == ~T13_E~0); 13462#L1504-1 assume !(1 == ~E_M~0); 13463#L1509-1 assume !(1 == ~E_1~0); 14041#L1514-1 assume !(1 == ~E_2~0); 13737#L1519-1 assume !(1 == ~E_3~0); 13738#L1524-1 assume !(1 == ~E_4~0); 14236#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14237#L1534-1 assume !(1 == ~E_6~0); 12386#L1539-1 assume !(1 == ~E_7~0); 12387#L1544-1 assume !(1 == ~E_8~0); 12810#L1549-1 assume !(1 == ~E_9~0); 14209#L1554-1 assume !(1 == ~E_10~0); 14206#L1559-1 assume !(1 == ~E_11~0); 14081#L1564-1 assume !(1 == ~E_12~0); 14082#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 14231#L1574-1 assume { :end_inline_reset_delta_events } true; 12561#L1940-2 [2023-11-26 10:48:00,376 INFO L750 eck$LassoCheckResult]: Loop: 12561#L1940-2 assume !false; 12562#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13105#L1266-1 assume !false; 14275#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13126#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12840#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 14040#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14049#L1079 assume !(0 != eval_~tmp~0#1); 13323#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12978#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12979#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13705#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13706#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14262#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14217#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13363#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12599#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12600#L1321-3 assume !(0 == ~T7_E~0); 12704#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13492#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13743#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13744#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13061#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 13038#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 12976#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12977#L1361-3 assume !(0 == ~E_1~0); 13557#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12315#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12316#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14061#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13920#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13921#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14095#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14096#L1401-3 assume !(0 == ~E_9~0); 12662#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12526#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12527#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 13220#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13221#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13328#L640-45 assume !(1 == ~m_pc~0); 13329#L640-47 is_master_triggered_~__retres1~0#1 := 0; 12770#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12771#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12311#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 12312#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12400#L659-45 assume 1 == ~t1_pc~0; 12401#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12854#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14266#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14196#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13849#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13850#L678-45 assume 1 == ~t2_pc~0; 13801#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13335#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13336#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13783#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14112#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14215#L697-45 assume 1 == ~t3_pc~0; 13596#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13597#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14282#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13749#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13750#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13784#L716-45 assume 1 == ~t4_pc~0; 13408#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13410#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14067#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13415#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13416#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13079#L735-45 assume 1 == ~t5_pc~0; 13080#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13628#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14233#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14279#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14235#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14229#L754-45 assume 1 == ~t6_pc~0; 13579#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13580#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13473#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13474#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13584#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13311#L773-45 assume 1 == ~t7_pc~0; 13312#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12851#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13545#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13546#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13319#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12970#L792-45 assume 1 == ~t8_pc~0; 12971#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13999#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14000#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12421#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12422#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12920#L811-45 assume 1 == ~t9_pc~0; 12697#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12698#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13917#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13780#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 13387#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13178#L830-45 assume 1 == ~t10_pc~0; 13179#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12348#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13496#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12572#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12573#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12331#L849-45 assume !(1 == ~t11_pc~0); 12332#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 12788#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12629#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12317#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12318#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12567#L868-45 assume 1 == ~t12_pc~0; 12568#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12511#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12512#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13952#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14125#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 14126#L887-45 assume 1 == ~t13_pc~0; 13953#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12575#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13880#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13899#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12541#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12542#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13875#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12559#L1444-3 assume !(1 == ~T2_E~0); 12560#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12718#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13686#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13687#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14127#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14064#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14065#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14129#L1484-3 assume !(1 == ~T10_E~0); 13369#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13370#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 13992#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13645#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13646#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14077#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14113#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13286#L1524-3 assume !(1 == ~E_4~0); 13287#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14151#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13564#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13021#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13022#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13527#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12606#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12607#L1564-3 assume !(1 == ~E_12~0); 13785#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13786#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12498#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12272#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12598#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 12505#L1959 assume !(0 == start_simulation_~tmp~3#1); 12507#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12537#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12491#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12326#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 12327#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14145#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14120#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14121#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 12561#L1940-2 [2023-11-26 10:48:00,377 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:00,378 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2023-11-26 10:48:00,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:00,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780484665] [2023-11-26 10:48:00,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:00,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:00,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:00,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:00,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:00,456 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [780484665] [2023-11-26 10:48:00,457 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [780484665] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:00,457 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:00,457 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:00,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1085213570] [2023-11-26 10:48:00,462 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:00,462 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:00,463 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:00,463 INFO L85 PathProgramCache]: Analyzing trace with hash 1601605178, now seen corresponding path program 1 times [2023-11-26 10:48:00,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:00,464 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815026010] [2023-11-26 10:48:00,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:00,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:00,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:00,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:00,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:00,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815026010] [2023-11-26 10:48:00,562 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815026010] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:00,562 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:00,563 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:00,563 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [298119298] [2023-11-26 10:48:00,563 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:00,564 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:00,564 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:00,564 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:00,564 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:00,565 INFO L87 Difference]: Start difference. First operand 2037 states and 3008 transitions. cyclomatic complexity: 972 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:00,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:00,619 INFO L93 Difference]: Finished difference Result 2037 states and 3007 transitions. [2023-11-26 10:48:00,619 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3007 transitions. [2023-11-26 10:48:00,640 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:00,657 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3007 transitions. [2023-11-26 10:48:00,657 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2023-11-26 10:48:00,659 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2023-11-26 10:48:00,660 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3007 transitions. [2023-11-26 10:48:00,664 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:00,664 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3007 transitions. [2023-11-26 10:48:00,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3007 transitions. [2023-11-26 10:48:00,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2023-11-26 10:48:00,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4761904761904763) internal successors, (3007), 2036 states have internal predecessors, (3007), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:00,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3007 transitions. [2023-11-26 10:48:00,720 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3007 transitions. [2023-11-26 10:48:00,721 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:00,723 INFO L428 stractBuchiCegarLoop]: Abstraction has 2037 states and 3007 transitions. [2023-11-26 10:48:00,723 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 10:48:00,723 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3007 transitions. [2023-11-26 10:48:00,733 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:00,733 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:00,733 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:00,737 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:00,738 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:00,738 INFO L748 eck$LassoCheckResult]: Stem: 16634#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 16635#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 17628#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17629#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18364#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 17756#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17225#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17226#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18030#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18031#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 18135#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18136#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16974#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16975#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18170#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17526#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17527#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18076#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17440#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17441#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 18365#L1291-2 assume !(0 == ~T1_E~0); 18362#L1296-1 assume !(0 == ~T2_E~0); 17590#L1301-1 assume !(0 == ~T3_E~0); 17591#L1306-1 assume !(0 == ~T4_E~0); 18086#L1311-1 assume !(0 == ~T5_E~0); 16811#L1316-1 assume !(0 == ~T6_E~0); 16812#L1321-1 assume !(0 == ~T7_E~0); 17604#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16631#L1331-1 assume !(0 == ~T9_E~0); 16344#L1336-1 assume !(0 == ~T10_E~0); 16345#L1341-1 assume !(0 == ~T11_E~0); 16418#L1346-1 assume !(0 == ~T12_E~0); 16419#L1351-1 assume !(0 == ~T13_E~0); 16748#L1356-1 assume !(0 == ~E_M~0); 16749#L1361-1 assume !(0 == ~E_1~0); 18302#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 16795#L1371-1 assume !(0 == ~E_3~0); 16796#L1376-1 assume !(0 == ~E_4~0); 17656#L1381-1 assume !(0 == ~E_5~0); 17657#L1386-1 assume !(0 == ~E_6~0); 18333#L1391-1 assume !(0 == ~E_7~0); 18353#L1396-1 assume !(0 == ~E_8~0); 17558#L1401-1 assume !(0 == ~E_9~0); 17559#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 17846#L1411-1 assume !(0 == ~E_11~0); 17847#L1416-1 assume !(0 == ~E_12~0); 17476#L1421-1 assume !(0 == ~E_13~0); 16995#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16996#L640 assume !(1 == ~m_pc~0); 17525#L640-2 is_master_triggered_~__retres1~0#1 := 0; 17524#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17484#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17485#L1603 assume !(0 != activate_threads_~tmp~1#1); 17513#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17145#L659 assume 1 == ~t1_pc~0; 17146#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17254#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17967#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17276#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 17277#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17293#L678 assume 1 == ~t2_pc~0; 18239#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18240#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16838#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16839#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 17387#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17506#L697 assume !(1 == ~t3_pc~0); 17507#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17637#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17957#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17420#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17421#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18272#L716 assume 1 == ~t4_pc~0; 18260#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17125#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16491#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16492#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 16599#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17921#L735 assume !(1 == ~t5_pc~0); 16566#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16567#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17022#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17947#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 17584#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17585#L754 assume 1 == ~t6_pc~0; 17338#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17238#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16815#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16816#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 17212#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18021#L773 assume !(1 == ~t7_pc~0); 16752#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16751#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17619#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17594#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 17595#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17648#L792 assume 1 == ~t8_pc~0; 17816#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18137#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18138#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17586#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 17509#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17510#L811 assume 1 == ~t9_pc~0; 17719#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18184#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16894#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16895#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 17521#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17522#L830 assume !(1 == ~t10_pc~0); 17247#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16728#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16729#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16706#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16707#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18039#L849 assume 1 == ~t11_pc~0; 18040#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16545#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16546#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18050#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 17951#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17952#L868 assume !(1 == ~t12_pc~0); 17371#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 17370#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16433#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16434#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 16763#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16764#L887 assume 1 == ~t13_pc~0; 17959#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17414#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17415#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 18015#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 16473#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16474#L1439 assume !(1 == ~M_E~0); 17578#L1439-2 assume !(1 == ~T1_E~0); 16644#L1444-1 assume !(1 == ~T2_E~0); 16645#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17150#L1454-1 assume !(1 == ~T4_E~0); 17151#L1459-1 assume !(1 == ~T5_E~0); 17711#L1464-1 assume !(1 == ~T6_E~0); 17712#L1469-1 assume !(1 == ~T7_E~0); 17785#L1474-1 assume !(1 == ~T8_E~0); 17477#L1479-1 assume !(1 == ~T9_E~0); 17478#L1484-1 assume !(1 == ~T10_E~0); 17715#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17360#L1494-1 assume !(1 == ~T12_E~0); 17361#L1499-1 assume !(1 == ~T13_E~0); 17543#L1504-1 assume !(1 == ~E_M~0); 17544#L1509-1 assume !(1 == ~E_1~0); 18122#L1514-1 assume !(1 == ~E_2~0); 17818#L1519-1 assume !(1 == ~E_3~0); 17819#L1524-1 assume !(1 == ~E_4~0); 18317#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18318#L1534-1 assume !(1 == ~E_6~0); 16467#L1539-1 assume !(1 == ~E_7~0); 16468#L1544-1 assume !(1 == ~E_8~0); 16891#L1549-1 assume !(1 == ~E_9~0); 18290#L1554-1 assume !(1 == ~E_10~0); 18287#L1559-1 assume !(1 == ~E_11~0); 18162#L1564-1 assume !(1 == ~E_12~0); 18163#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 18312#L1574-1 assume { :end_inline_reset_delta_events } true; 16642#L1940-2 [2023-11-26 10:48:00,739 INFO L750 eck$LassoCheckResult]: Loop: 16642#L1940-2 assume !false; 16643#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17186#L1266-1 assume !false; 18356#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17207#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16921#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 18121#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18130#L1079 assume !(0 != eval_~tmp~0#1); 17404#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17059#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17060#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17786#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17787#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18343#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18298#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17444#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16680#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16681#L1321-3 assume !(0 == ~T7_E~0); 16785#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17573#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17824#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17825#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17142#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17119#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17057#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17058#L1361-3 assume !(0 == ~E_1~0); 17638#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16396#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16397#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18142#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18001#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18002#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18176#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18177#L1401-3 assume !(0 == ~E_9~0); 16743#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16607#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16608#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 17301#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 17302#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17409#L640-45 assume !(1 == ~m_pc~0); 17410#L640-47 is_master_triggered_~__retres1~0#1 := 0; 16851#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16852#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16392#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 16393#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16481#L659-45 assume 1 == ~t1_pc~0; 16482#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16935#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18347#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18277#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17930#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17931#L678-45 assume 1 == ~t2_pc~0; 17882#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17416#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17417#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17864#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18193#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18296#L697-45 assume 1 == ~t3_pc~0; 17677#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17678#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18363#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17830#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17831#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17865#L716-45 assume 1 == ~t4_pc~0; 17489#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17491#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18148#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17496#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17497#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17160#L735-45 assume 1 == ~t5_pc~0; 17161#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17709#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18314#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18360#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18316#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18310#L754-45 assume 1 == ~t6_pc~0; 17660#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17661#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17554#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17555#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17665#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17392#L773-45 assume 1 == ~t7_pc~0; 17393#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16932#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17626#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17627#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17400#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17051#L792-45 assume 1 == ~t8_pc~0; 17052#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18080#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18081#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16502#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16503#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17001#L811-45 assume 1 == ~t9_pc~0; 16778#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16779#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17998#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17861#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 17468#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17259#L830-45 assume 1 == ~t10_pc~0; 17260#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16429#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17577#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16653#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16654#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16412#L849-45 assume !(1 == ~t11_pc~0); 16413#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 16869#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16710#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16398#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16399#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16648#L868-45 assume 1 == ~t12_pc~0; 16649#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16592#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16593#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18033#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18206#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 18207#L887-45 assume 1 == ~t13_pc~0; 18034#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16656#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17961#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 17980#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16622#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16623#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17956#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16640#L1444-3 assume !(1 == ~T2_E~0); 16641#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16799#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17767#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17768#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18208#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18145#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18146#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18210#L1484-3 assume !(1 == ~T10_E~0); 17450#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17451#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18073#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 17726#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17727#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18158#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18194#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17367#L1524-3 assume !(1 == ~E_4~0); 17368#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18232#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17645#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17102#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17103#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17608#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16687#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16688#L1564-3 assume !(1 == ~E_12~0); 17866#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17867#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16579#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16353#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16679#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 16586#L1959 assume !(0 == start_simulation_~tmp~3#1); 16588#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16618#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16572#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16407#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 16408#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18226#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18201#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18202#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 16642#L1940-2 [2023-11-26 10:48:00,740 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:00,740 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2023-11-26 10:48:00,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:00,741 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218722078] [2023-11-26 10:48:00,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:00,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:00,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:00,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:00,809 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:00,809 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1218722078] [2023-11-26 10:48:00,809 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1218722078] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:00,809 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:00,809 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:00,810 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560762711] [2023-11-26 10:48:00,810 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:00,810 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:00,811 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:00,811 INFO L85 PathProgramCache]: Analyzing trace with hash 1601605178, now seen corresponding path program 2 times [2023-11-26 10:48:00,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:00,812 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145372629] [2023-11-26 10:48:00,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:00,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:00,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:00,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:00,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:00,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2145372629] [2023-11-26 10:48:00,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2145372629] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:00,950 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:00,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:00,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2112456043] [2023-11-26 10:48:00,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:00,952 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:00,952 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:00,952 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:00,952 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:00,953 INFO L87 Difference]: Start difference. First operand 2037 states and 3007 transitions. cyclomatic complexity: 971 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:01,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:01,002 INFO L93 Difference]: Finished difference Result 2037 states and 3006 transitions. [2023-11-26 10:48:01,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3006 transitions. [2023-11-26 10:48:01,017 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:01,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3006 transitions. [2023-11-26 10:48:01,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2023-11-26 10:48:01,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2023-11-26 10:48:01,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3006 transitions. [2023-11-26 10:48:01,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:01,040 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3006 transitions. [2023-11-26 10:48:01,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3006 transitions. [2023-11-26 10:48:01,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2023-11-26 10:48:01,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.475699558173785) internal successors, (3006), 2036 states have internal predecessors, (3006), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:01,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3006 transitions. [2023-11-26 10:48:01,092 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3006 transitions. [2023-11-26 10:48:01,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:01,096 INFO L428 stractBuchiCegarLoop]: Abstraction has 2037 states and 3006 transitions. [2023-11-26 10:48:01,096 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 10:48:01,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3006 transitions. [2023-11-26 10:48:01,106 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:01,106 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:01,106 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:01,109 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:01,109 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:01,110 INFO L748 eck$LassoCheckResult]: Stem: 20715#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 20716#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 21709#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21710#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22445#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 21837#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21306#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21307#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22111#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22112#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 22216#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22217#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21055#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21056#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22251#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21607#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21608#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22157#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21521#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21522#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 22446#L1291-2 assume !(0 == ~T1_E~0); 22443#L1296-1 assume !(0 == ~T2_E~0); 21671#L1301-1 assume !(0 == ~T3_E~0); 21672#L1306-1 assume !(0 == ~T4_E~0); 22167#L1311-1 assume !(0 == ~T5_E~0); 20892#L1316-1 assume !(0 == ~T6_E~0); 20893#L1321-1 assume !(0 == ~T7_E~0); 21685#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20712#L1331-1 assume !(0 == ~T9_E~0); 20425#L1336-1 assume !(0 == ~T10_E~0); 20426#L1341-1 assume !(0 == ~T11_E~0); 20499#L1346-1 assume !(0 == ~T12_E~0); 20500#L1351-1 assume !(0 == ~T13_E~0); 20829#L1356-1 assume !(0 == ~E_M~0); 20830#L1361-1 assume !(0 == ~E_1~0); 22383#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 20876#L1371-1 assume !(0 == ~E_3~0); 20877#L1376-1 assume !(0 == ~E_4~0); 21737#L1381-1 assume !(0 == ~E_5~0); 21738#L1386-1 assume !(0 == ~E_6~0); 22414#L1391-1 assume !(0 == ~E_7~0); 22434#L1396-1 assume !(0 == ~E_8~0); 21639#L1401-1 assume !(0 == ~E_9~0); 21640#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 21927#L1411-1 assume !(0 == ~E_11~0); 21928#L1416-1 assume !(0 == ~E_12~0); 21557#L1421-1 assume !(0 == ~E_13~0); 21076#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21077#L640 assume !(1 == ~m_pc~0); 21606#L640-2 is_master_triggered_~__retres1~0#1 := 0; 21605#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21565#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21566#L1603 assume !(0 != activate_threads_~tmp~1#1); 21594#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21226#L659 assume 1 == ~t1_pc~0; 21227#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21335#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22048#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21357#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 21358#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21374#L678 assume 1 == ~t2_pc~0; 22320#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22321#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20919#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20920#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 21468#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21587#L697 assume !(1 == ~t3_pc~0); 21588#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21718#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22038#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21501#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21502#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22353#L716 assume 1 == ~t4_pc~0; 22341#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21206#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20572#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20573#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 20680#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22002#L735 assume !(1 == ~t5_pc~0); 20647#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20648#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21103#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22028#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 21665#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21666#L754 assume 1 == ~t6_pc~0; 21419#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21319#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20896#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20897#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 21293#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22102#L773 assume !(1 == ~t7_pc~0); 20833#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20832#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21700#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21675#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 21676#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21729#L792 assume 1 == ~t8_pc~0; 21897#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22218#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22219#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21667#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 21590#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21591#L811 assume 1 == ~t9_pc~0; 21800#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22265#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20975#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20976#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 21602#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21603#L830 assume !(1 == ~t10_pc~0); 21328#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20809#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20810#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20787#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20788#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22120#L849 assume 1 == ~t11_pc~0; 22121#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20626#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20627#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22131#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 22032#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22033#L868 assume !(1 == ~t12_pc~0); 21452#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 21451#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20514#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 20515#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 20844#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20845#L887 assume 1 == ~t13_pc~0; 22040#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21495#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21496#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 22096#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 20554#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20555#L1439 assume !(1 == ~M_E~0); 21659#L1439-2 assume !(1 == ~T1_E~0); 20725#L1444-1 assume !(1 == ~T2_E~0); 20726#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21231#L1454-1 assume !(1 == ~T4_E~0); 21232#L1459-1 assume !(1 == ~T5_E~0); 21792#L1464-1 assume !(1 == ~T6_E~0); 21793#L1469-1 assume !(1 == ~T7_E~0); 21866#L1474-1 assume !(1 == ~T8_E~0); 21558#L1479-1 assume !(1 == ~T9_E~0); 21559#L1484-1 assume !(1 == ~T10_E~0); 21796#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21441#L1494-1 assume !(1 == ~T12_E~0); 21442#L1499-1 assume !(1 == ~T13_E~0); 21624#L1504-1 assume !(1 == ~E_M~0); 21625#L1509-1 assume !(1 == ~E_1~0); 22203#L1514-1 assume !(1 == ~E_2~0); 21899#L1519-1 assume !(1 == ~E_3~0); 21900#L1524-1 assume !(1 == ~E_4~0); 22398#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22399#L1534-1 assume !(1 == ~E_6~0); 20548#L1539-1 assume !(1 == ~E_7~0); 20549#L1544-1 assume !(1 == ~E_8~0); 20972#L1549-1 assume !(1 == ~E_9~0); 22371#L1554-1 assume !(1 == ~E_10~0); 22368#L1559-1 assume !(1 == ~E_11~0); 22243#L1564-1 assume !(1 == ~E_12~0); 22244#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 22393#L1574-1 assume { :end_inline_reset_delta_events } true; 20723#L1940-2 [2023-11-26 10:48:01,111 INFO L750 eck$LassoCheckResult]: Loop: 20723#L1940-2 assume !false; 20724#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21267#L1266-1 assume !false; 22437#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21288#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 21002#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 22202#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22211#L1079 assume !(0 != eval_~tmp~0#1); 21485#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21140#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21141#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21867#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21868#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22424#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22379#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21525#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20761#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20762#L1321-3 assume !(0 == ~T7_E~0); 20866#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21654#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21905#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21906#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21223#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21200#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21138#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21139#L1361-3 assume !(0 == ~E_1~0); 21719#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20477#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20478#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22223#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22082#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22083#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22257#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22258#L1401-3 assume !(0 == ~E_9~0); 20824#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20688#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20689#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 21382#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 21383#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21490#L640-45 assume !(1 == ~m_pc~0); 21491#L640-47 is_master_triggered_~__retres1~0#1 := 0; 20932#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20933#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20473#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 20474#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20562#L659-45 assume 1 == ~t1_pc~0; 20563#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21016#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22428#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22358#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22011#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22012#L678-45 assume 1 == ~t2_pc~0; 21963#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21497#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21498#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21945#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22274#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22377#L697-45 assume !(1 == ~t3_pc~0); 21760#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 21759#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22444#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21911#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21912#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21946#L716-45 assume 1 == ~t4_pc~0; 21570#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21572#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22229#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21577#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21578#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21241#L735-45 assume 1 == ~t5_pc~0; 21242#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21790#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22395#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22441#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22397#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22391#L754-45 assume 1 == ~t6_pc~0; 21741#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21742#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21635#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21636#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21746#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21473#L773-45 assume 1 == ~t7_pc~0; 21474#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21013#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21707#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21708#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21481#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21132#L792-45 assume 1 == ~t8_pc~0; 21133#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22161#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22162#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20583#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20584#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21082#L811-45 assume 1 == ~t9_pc~0; 20859#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20860#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22079#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21942#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 21549#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21340#L830-45 assume 1 == ~t10_pc~0; 21341#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20510#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21658#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20734#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20735#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20493#L849-45 assume !(1 == ~t11_pc~0); 20494#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 20950#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20791#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20479#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20480#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20729#L868-45 assume 1 == ~t12_pc~0; 20730#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20673#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20674#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22114#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22287#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22288#L887-45 assume !(1 == ~t13_pc~0); 20736#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 20737#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 22042#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 22061#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20703#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20704#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22037#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20721#L1444-3 assume !(1 == ~T2_E~0); 20722#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20880#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21848#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21849#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22289#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22226#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22227#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22291#L1484-3 assume !(1 == ~T10_E~0); 21531#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21532#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22154#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21807#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21808#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22239#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22275#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21448#L1524-3 assume !(1 == ~E_4~0); 21449#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22313#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21726#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21183#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21184#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21689#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20768#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20769#L1564-3 assume !(1 == ~E_12~0); 21947#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21948#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20660#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20434#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20760#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 20667#L1959 assume !(0 == start_simulation_~tmp~3#1); 20669#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20699#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20653#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20488#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 20489#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22307#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22282#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22283#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 20723#L1940-2 [2023-11-26 10:48:01,112 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:01,112 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2023-11-26 10:48:01,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:01,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277964885] [2023-11-26 10:48:01,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:01,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:01,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:01,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:01,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:01,183 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1277964885] [2023-11-26 10:48:01,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1277964885] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:01,188 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:01,188 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:01,189 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854456380] [2023-11-26 10:48:01,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:01,189 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:01,190 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:01,190 INFO L85 PathProgramCache]: Analyzing trace with hash 1079224764, now seen corresponding path program 1 times [2023-11-26 10:48:01,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:01,190 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977375324] [2023-11-26 10:48:01,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:01,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:01,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:01,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:01,301 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:01,302 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1977375324] [2023-11-26 10:48:01,302 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1977375324] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:01,302 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:01,302 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:01,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [626277491] [2023-11-26 10:48:01,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:01,303 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:01,303 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:01,304 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:01,304 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:01,305 INFO L87 Difference]: Start difference. First operand 2037 states and 3006 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:01,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:01,355 INFO L93 Difference]: Finished difference Result 2037 states and 3005 transitions. [2023-11-26 10:48:01,355 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3005 transitions. [2023-11-26 10:48:01,370 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:01,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3005 transitions. [2023-11-26 10:48:01,389 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2023-11-26 10:48:01,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2023-11-26 10:48:01,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3005 transitions. [2023-11-26 10:48:01,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:01,397 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3005 transitions. [2023-11-26 10:48:01,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3005 transitions. [2023-11-26 10:48:01,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2023-11-26 10:48:01,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4752086401570939) internal successors, (3005), 2036 states have internal predecessors, (3005), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:01,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3005 transitions. [2023-11-26 10:48:01,451 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3005 transitions. [2023-11-26 10:48:01,452 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:01,454 INFO L428 stractBuchiCegarLoop]: Abstraction has 2037 states and 3005 transitions. [2023-11-26 10:48:01,454 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 10:48:01,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3005 transitions. [2023-11-26 10:48:01,464 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:01,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:01,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:01,468 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:01,468 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:01,468 INFO L748 eck$LassoCheckResult]: Stem: 24796#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 24797#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 25790#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25791#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26526#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 25918#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25387#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25388#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26192#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26193#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26297#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 26298#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25136#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25137#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26332#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25688#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25689#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26238#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25602#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25603#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 26527#L1291-2 assume !(0 == ~T1_E~0); 26524#L1296-1 assume !(0 == ~T2_E~0); 25752#L1301-1 assume !(0 == ~T3_E~0); 25753#L1306-1 assume !(0 == ~T4_E~0); 26248#L1311-1 assume !(0 == ~T5_E~0); 24973#L1316-1 assume !(0 == ~T6_E~0); 24974#L1321-1 assume !(0 == ~T7_E~0); 25766#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24793#L1331-1 assume !(0 == ~T9_E~0); 24506#L1336-1 assume !(0 == ~T10_E~0); 24507#L1341-1 assume !(0 == ~T11_E~0); 24580#L1346-1 assume !(0 == ~T12_E~0); 24581#L1351-1 assume !(0 == ~T13_E~0); 24910#L1356-1 assume !(0 == ~E_M~0); 24911#L1361-1 assume !(0 == ~E_1~0); 26464#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 24957#L1371-1 assume !(0 == ~E_3~0); 24958#L1376-1 assume !(0 == ~E_4~0); 25818#L1381-1 assume !(0 == ~E_5~0); 25819#L1386-1 assume !(0 == ~E_6~0); 26495#L1391-1 assume !(0 == ~E_7~0); 26515#L1396-1 assume !(0 == ~E_8~0); 25720#L1401-1 assume !(0 == ~E_9~0); 25721#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 26008#L1411-1 assume !(0 == ~E_11~0); 26009#L1416-1 assume !(0 == ~E_12~0); 25638#L1421-1 assume !(0 == ~E_13~0); 25157#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25158#L640 assume !(1 == ~m_pc~0); 25687#L640-2 is_master_triggered_~__retres1~0#1 := 0; 25686#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25646#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25647#L1603 assume !(0 != activate_threads_~tmp~1#1); 25675#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25307#L659 assume 1 == ~t1_pc~0; 25308#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25416#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26129#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25438#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 25439#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25455#L678 assume 1 == ~t2_pc~0; 26401#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26402#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25000#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25001#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 25549#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25668#L697 assume !(1 == ~t3_pc~0); 25669#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25799#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26119#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25582#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25583#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26434#L716 assume 1 == ~t4_pc~0; 26422#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25287#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24653#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24654#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 24761#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26083#L735 assume !(1 == ~t5_pc~0); 24728#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24729#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25184#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26109#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 25746#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25747#L754 assume 1 == ~t6_pc~0; 25500#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25400#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24977#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24978#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 25374#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26183#L773 assume !(1 == ~t7_pc~0); 24914#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 24913#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25781#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25756#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 25757#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25810#L792 assume 1 == ~t8_pc~0; 25978#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26299#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26300#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25748#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 25671#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25672#L811 assume 1 == ~t9_pc~0; 25881#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26346#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25056#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25057#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 25683#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25684#L830 assume !(1 == ~t10_pc~0); 25409#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 24890#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24891#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24868#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24869#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26201#L849 assume 1 == ~t11_pc~0; 26202#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24707#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24708#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26212#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 26113#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26114#L868 assume !(1 == ~t12_pc~0); 25533#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25532#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24595#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 24596#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 24925#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24926#L887 assume 1 == ~t13_pc~0; 26121#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25576#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25577#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26177#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 24635#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24636#L1439 assume !(1 == ~M_E~0); 25740#L1439-2 assume !(1 == ~T1_E~0); 24806#L1444-1 assume !(1 == ~T2_E~0); 24807#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25312#L1454-1 assume !(1 == ~T4_E~0); 25313#L1459-1 assume !(1 == ~T5_E~0); 25873#L1464-1 assume !(1 == ~T6_E~0); 25874#L1469-1 assume !(1 == ~T7_E~0); 25947#L1474-1 assume !(1 == ~T8_E~0); 25639#L1479-1 assume !(1 == ~T9_E~0); 25640#L1484-1 assume !(1 == ~T10_E~0); 25877#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25522#L1494-1 assume !(1 == ~T12_E~0); 25523#L1499-1 assume !(1 == ~T13_E~0); 25705#L1504-1 assume !(1 == ~E_M~0); 25706#L1509-1 assume !(1 == ~E_1~0); 26284#L1514-1 assume !(1 == ~E_2~0); 25980#L1519-1 assume !(1 == ~E_3~0); 25981#L1524-1 assume !(1 == ~E_4~0); 26479#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26480#L1534-1 assume !(1 == ~E_6~0); 24629#L1539-1 assume !(1 == ~E_7~0); 24630#L1544-1 assume !(1 == ~E_8~0); 25053#L1549-1 assume !(1 == ~E_9~0); 26452#L1554-1 assume !(1 == ~E_10~0); 26449#L1559-1 assume !(1 == ~E_11~0); 26324#L1564-1 assume !(1 == ~E_12~0); 26325#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 26474#L1574-1 assume { :end_inline_reset_delta_events } true; 24804#L1940-2 [2023-11-26 10:48:01,469 INFO L750 eck$LassoCheckResult]: Loop: 24804#L1940-2 assume !false; 24805#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25348#L1266-1 assume !false; 26518#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25369#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 25083#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 26283#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26292#L1079 assume !(0 != eval_~tmp~0#1); 25566#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25221#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25222#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25948#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25949#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26505#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26460#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25606#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24842#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24843#L1321-3 assume !(0 == ~T7_E~0); 24947#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25735#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25986#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25987#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25304#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25281#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25219#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25220#L1361-3 assume !(0 == ~E_1~0); 25800#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24558#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24559#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26304#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26163#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26164#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26338#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26339#L1401-3 assume !(0 == ~E_9~0); 24905#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24769#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24770#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25463#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 25464#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25571#L640-45 assume !(1 == ~m_pc~0); 25572#L640-47 is_master_triggered_~__retres1~0#1 := 0; 25013#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25014#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24554#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 24555#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24643#L659-45 assume 1 == ~t1_pc~0; 24644#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25097#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26509#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26439#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26092#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26093#L678-45 assume 1 == ~t2_pc~0; 26044#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25578#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25579#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26026#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26355#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26458#L697-45 assume !(1 == ~t3_pc~0); 25841#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 25840#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26525#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25992#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25993#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26027#L716-45 assume 1 == ~t4_pc~0; 25651#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25653#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26310#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25658#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25659#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25322#L735-45 assume 1 == ~t5_pc~0; 25323#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25871#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26476#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26522#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26478#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26472#L754-45 assume !(1 == ~t6_pc~0); 25824#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 25823#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25716#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25717#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25827#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25554#L773-45 assume 1 == ~t7_pc~0; 25555#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25094#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25788#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25789#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25562#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25213#L792-45 assume 1 == ~t8_pc~0; 25214#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26242#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26243#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24664#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24665#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25163#L811-45 assume 1 == ~t9_pc~0; 24940#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24941#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26160#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26023#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 25630#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25421#L830-45 assume 1 == ~t10_pc~0; 25422#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24591#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25739#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24815#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24816#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24574#L849-45 assume 1 == ~t11_pc~0; 24576#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25031#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24872#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24560#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24561#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24810#L868-45 assume 1 == ~t12_pc~0; 24811#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24754#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24755#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26195#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 26368#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 26369#L887-45 assume !(1 == ~t13_pc~0); 24817#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 24818#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 26123#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26142#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 24784#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24785#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26118#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24802#L1444-3 assume !(1 == ~T2_E~0); 24803#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24961#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25929#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25930#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26370#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26307#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26308#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26372#L1484-3 assume !(1 == ~T10_E~0); 25612#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25613#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26235#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 25888#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25889#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26320#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26356#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25529#L1524-3 assume !(1 == ~E_4~0); 25530#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26394#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25807#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25264#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25265#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25770#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24849#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24850#L1564-3 assume !(1 == ~E_12~0); 26028#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 26029#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24741#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24515#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24841#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 24748#L1959 assume !(0 == start_simulation_~tmp~3#1); 24750#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24780#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24734#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24569#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 24570#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26388#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26363#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26364#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 24804#L1940-2 [2023-11-26 10:48:01,470 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:01,470 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2023-11-26 10:48:01,471 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:01,471 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [266074128] [2023-11-26 10:48:01,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:01,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:01,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:01,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:01,567 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:01,568 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [266074128] [2023-11-26 10:48:01,568 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [266074128] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:01,568 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:01,568 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:01,569 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [132970117] [2023-11-26 10:48:01,569 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:01,569 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:01,570 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:01,570 INFO L85 PathProgramCache]: Analyzing trace with hash 723874300, now seen corresponding path program 1 times [2023-11-26 10:48:01,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:01,571 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308364204] [2023-11-26 10:48:01,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:01,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:01,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:01,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:01,669 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:01,670 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308364204] [2023-11-26 10:48:01,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308364204] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:01,670 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:01,670 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:01,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1116505128] [2023-11-26 10:48:01,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:01,671 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:01,672 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:01,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:01,672 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:01,673 INFO L87 Difference]: Start difference. First operand 2037 states and 3005 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:01,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:01,737 INFO L93 Difference]: Finished difference Result 2037 states and 3004 transitions. [2023-11-26 10:48:01,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3004 transitions. [2023-11-26 10:48:01,754 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:01,775 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3004 transitions. [2023-11-26 10:48:01,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2023-11-26 10:48:01,778 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2023-11-26 10:48:01,778 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3004 transitions. [2023-11-26 10:48:01,782 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:01,782 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3004 transitions. [2023-11-26 10:48:01,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3004 transitions. [2023-11-26 10:48:01,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2023-11-26 10:48:01,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4747177221404026) internal successors, (3004), 2036 states have internal predecessors, (3004), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:01,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3004 transitions. [2023-11-26 10:48:01,850 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3004 transitions. [2023-11-26 10:48:01,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:01,853 INFO L428 stractBuchiCegarLoop]: Abstraction has 2037 states and 3004 transitions. [2023-11-26 10:48:01,853 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 10:48:01,853 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3004 transitions. [2023-11-26 10:48:01,863 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:01,864 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:01,864 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:01,867 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:01,867 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:01,867 INFO L748 eck$LassoCheckResult]: Stem: 28877#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 28878#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 29871#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29872#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30607#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 29999#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29468#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29469#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30273#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30274#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30378#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30379#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29217#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29218#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30413#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29769#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29770#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 30319#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29683#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29684#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 30608#L1291-2 assume !(0 == ~T1_E~0); 30605#L1296-1 assume !(0 == ~T2_E~0); 29833#L1301-1 assume !(0 == ~T3_E~0); 29834#L1306-1 assume !(0 == ~T4_E~0); 30329#L1311-1 assume !(0 == ~T5_E~0); 29054#L1316-1 assume !(0 == ~T6_E~0); 29055#L1321-1 assume !(0 == ~T7_E~0); 29847#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28874#L1331-1 assume !(0 == ~T9_E~0); 28587#L1336-1 assume !(0 == ~T10_E~0); 28588#L1341-1 assume !(0 == ~T11_E~0); 28661#L1346-1 assume !(0 == ~T12_E~0); 28662#L1351-1 assume !(0 == ~T13_E~0); 28991#L1356-1 assume !(0 == ~E_M~0); 28992#L1361-1 assume !(0 == ~E_1~0); 30545#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 29038#L1371-1 assume !(0 == ~E_3~0); 29039#L1376-1 assume !(0 == ~E_4~0); 29899#L1381-1 assume !(0 == ~E_5~0); 29900#L1386-1 assume !(0 == ~E_6~0); 30576#L1391-1 assume !(0 == ~E_7~0); 30596#L1396-1 assume !(0 == ~E_8~0); 29801#L1401-1 assume !(0 == ~E_9~0); 29802#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 30089#L1411-1 assume !(0 == ~E_11~0); 30090#L1416-1 assume !(0 == ~E_12~0); 29719#L1421-1 assume !(0 == ~E_13~0); 29238#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29239#L640 assume !(1 == ~m_pc~0); 29768#L640-2 is_master_triggered_~__retres1~0#1 := 0; 29767#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29727#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29728#L1603 assume !(0 != activate_threads_~tmp~1#1); 29756#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29388#L659 assume 1 == ~t1_pc~0; 29389#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29497#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30210#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29519#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 29520#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29536#L678 assume 1 == ~t2_pc~0; 30482#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30483#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29081#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29082#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 29630#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29749#L697 assume !(1 == ~t3_pc~0); 29750#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29880#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30200#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29663#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29664#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30515#L716 assume 1 == ~t4_pc~0; 30503#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29368#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28734#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28735#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 28842#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30164#L735 assume !(1 == ~t5_pc~0); 28809#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28810#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29265#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30190#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 29827#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29828#L754 assume 1 == ~t6_pc~0; 29581#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29481#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29058#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29059#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 29455#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30264#L773 assume !(1 == ~t7_pc~0); 28995#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28994#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29862#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29837#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 29838#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29891#L792 assume 1 == ~t8_pc~0; 30059#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30380#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30381#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29829#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 29752#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29753#L811 assume 1 == ~t9_pc~0; 29962#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30427#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29137#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29138#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 29764#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29765#L830 assume !(1 == ~t10_pc~0); 29490#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28971#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28972#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28949#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28950#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30282#L849 assume 1 == ~t11_pc~0; 30283#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28788#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28789#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30293#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 30194#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30195#L868 assume !(1 == ~t12_pc~0); 29614#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29613#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28676#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28677#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 29006#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29007#L887 assume 1 == ~t13_pc~0; 30202#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29657#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29658#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30258#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 28716#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28717#L1439 assume !(1 == ~M_E~0); 29821#L1439-2 assume !(1 == ~T1_E~0); 28887#L1444-1 assume !(1 == ~T2_E~0); 28888#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29393#L1454-1 assume !(1 == ~T4_E~0); 29394#L1459-1 assume !(1 == ~T5_E~0); 29954#L1464-1 assume !(1 == ~T6_E~0); 29955#L1469-1 assume !(1 == ~T7_E~0); 30028#L1474-1 assume !(1 == ~T8_E~0); 29720#L1479-1 assume !(1 == ~T9_E~0); 29721#L1484-1 assume !(1 == ~T10_E~0); 29958#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29603#L1494-1 assume !(1 == ~T12_E~0); 29604#L1499-1 assume !(1 == ~T13_E~0); 29786#L1504-1 assume !(1 == ~E_M~0); 29787#L1509-1 assume !(1 == ~E_1~0); 30365#L1514-1 assume !(1 == ~E_2~0); 30061#L1519-1 assume !(1 == ~E_3~0); 30062#L1524-1 assume !(1 == ~E_4~0); 30560#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30561#L1534-1 assume !(1 == ~E_6~0); 28710#L1539-1 assume !(1 == ~E_7~0); 28711#L1544-1 assume !(1 == ~E_8~0); 29134#L1549-1 assume !(1 == ~E_9~0); 30533#L1554-1 assume !(1 == ~E_10~0); 30530#L1559-1 assume !(1 == ~E_11~0); 30405#L1564-1 assume !(1 == ~E_12~0); 30406#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 30555#L1574-1 assume { :end_inline_reset_delta_events } true; 28885#L1940-2 [2023-11-26 10:48:01,868 INFO L750 eck$LassoCheckResult]: Loop: 28885#L1940-2 assume !false; 28886#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29429#L1266-1 assume !false; 30599#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29450#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 29164#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30364#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30373#L1079 assume !(0 != eval_~tmp~0#1); 29647#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29302#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29303#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30029#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30030#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30586#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30541#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29687#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28923#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28924#L1321-3 assume !(0 == ~T7_E~0); 29028#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29816#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30067#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30068#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29385#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29362#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29300#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29301#L1361-3 assume !(0 == ~E_1~0); 29881#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28639#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28640#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30385#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30244#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30245#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30419#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30420#L1401-3 assume !(0 == ~E_9~0); 28986#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28850#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28851#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29544#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 29545#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29652#L640-45 assume !(1 == ~m_pc~0); 29653#L640-47 is_master_triggered_~__retres1~0#1 := 0; 29094#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29095#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28635#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 28636#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28724#L659-45 assume 1 == ~t1_pc~0; 28725#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29178#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30590#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30520#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30173#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30174#L678-45 assume 1 == ~t2_pc~0; 30125#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29659#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29660#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30107#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30436#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30539#L697-45 assume 1 == ~t3_pc~0; 29920#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29921#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30606#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30073#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30074#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30108#L716-45 assume 1 == ~t4_pc~0; 29732#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29734#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30391#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29739#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29740#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29403#L735-45 assume 1 == ~t5_pc~0; 29404#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29952#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30557#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30603#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30559#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30553#L754-45 assume !(1 == ~t6_pc~0); 29905#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 29904#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29797#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29798#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29908#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29635#L773-45 assume 1 == ~t7_pc~0; 29636#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29175#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29869#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29870#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29643#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29294#L792-45 assume !(1 == ~t8_pc~0); 29296#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 30323#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30324#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28745#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28746#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29244#L811-45 assume 1 == ~t9_pc~0; 29021#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29022#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30241#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30104#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 29711#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29502#L830-45 assume 1 == ~t10_pc~0; 29503#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28672#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29820#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28896#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28897#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28655#L849-45 assume !(1 == ~t11_pc~0); 28656#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 29112#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28953#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28641#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28642#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28891#L868-45 assume 1 == ~t12_pc~0; 28892#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28835#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28836#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30276#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30449#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30450#L887-45 assume !(1 == ~t13_pc~0); 28898#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 28899#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30204#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30223#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 28865#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28866#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30199#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28883#L1444-3 assume !(1 == ~T2_E~0); 28884#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29042#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30010#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30011#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30451#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30388#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30389#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30453#L1484-3 assume !(1 == ~T10_E~0); 29693#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29694#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30316#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 29969#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29970#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30401#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30437#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29610#L1524-3 assume !(1 == ~E_4~0); 29611#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30475#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29888#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29345#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29346#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29851#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28930#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28931#L1564-3 assume !(1 == ~E_12~0); 30109#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 30110#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28822#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28596#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28922#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 28829#L1959 assume !(0 == start_simulation_~tmp~3#1); 28831#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28861#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28815#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28650#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 28651#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30469#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30444#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30445#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 28885#L1940-2 [2023-11-26 10:48:01,869 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:01,870 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2023-11-26 10:48:01,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:01,871 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326050496] [2023-11-26 10:48:01,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:01,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:01,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:01,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:01,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:01,934 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [326050496] [2023-11-26 10:48:01,934 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [326050496] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:01,934 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:01,934 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:01,935 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885922210] [2023-11-26 10:48:01,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:01,935 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:01,936 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:01,936 INFO L85 PathProgramCache]: Analyzing trace with hash 774135229, now seen corresponding path program 1 times [2023-11-26 10:48:01,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:01,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1696242543] [2023-11-26 10:48:01,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:01,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:01,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:02,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:02,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:02,020 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1696242543] [2023-11-26 10:48:02,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1696242543] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:02,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:02,023 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:02,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2076741520] [2023-11-26 10:48:02,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:02,024 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:02,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:02,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:02,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:02,025 INFO L87 Difference]: Start difference. First operand 2037 states and 3004 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:02,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:02,071 INFO L93 Difference]: Finished difference Result 2037 states and 3003 transitions. [2023-11-26 10:48:02,071 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3003 transitions. [2023-11-26 10:48:02,084 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:02,099 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3003 transitions. [2023-11-26 10:48:02,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2023-11-26 10:48:02,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2023-11-26 10:48:02,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3003 transitions. [2023-11-26 10:48:02,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:02,105 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3003 transitions. [2023-11-26 10:48:02,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3003 transitions. [2023-11-26 10:48:02,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2023-11-26 10:48:02,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4742268041237114) internal successors, (3003), 2036 states have internal predecessors, (3003), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:02,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3003 transitions. [2023-11-26 10:48:02,154 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3003 transitions. [2023-11-26 10:48:02,154 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:02,157 INFO L428 stractBuchiCegarLoop]: Abstraction has 2037 states and 3003 transitions. [2023-11-26 10:48:02,157 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 10:48:02,157 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3003 transitions. [2023-11-26 10:48:02,167 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:02,167 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:02,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:02,170 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:02,171 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:02,171 INFO L748 eck$LassoCheckResult]: Stem: 32958#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 32959#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 33952#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33953#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34688#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 34080#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33549#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33550#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34354#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34355#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34459#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34460#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33298#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33299#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34494#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33850#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33851#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 34400#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33764#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33765#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 34689#L1291-2 assume !(0 == ~T1_E~0); 34686#L1296-1 assume !(0 == ~T2_E~0); 33914#L1301-1 assume !(0 == ~T3_E~0); 33915#L1306-1 assume !(0 == ~T4_E~0); 34410#L1311-1 assume !(0 == ~T5_E~0); 33135#L1316-1 assume !(0 == ~T6_E~0); 33136#L1321-1 assume !(0 == ~T7_E~0); 33928#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32955#L1331-1 assume !(0 == ~T9_E~0); 32668#L1336-1 assume !(0 == ~T10_E~0); 32669#L1341-1 assume !(0 == ~T11_E~0); 32742#L1346-1 assume !(0 == ~T12_E~0); 32743#L1351-1 assume !(0 == ~T13_E~0); 33072#L1356-1 assume !(0 == ~E_M~0); 33073#L1361-1 assume !(0 == ~E_1~0); 34626#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 33119#L1371-1 assume !(0 == ~E_3~0); 33120#L1376-1 assume !(0 == ~E_4~0); 33980#L1381-1 assume !(0 == ~E_5~0); 33981#L1386-1 assume !(0 == ~E_6~0); 34657#L1391-1 assume !(0 == ~E_7~0); 34677#L1396-1 assume !(0 == ~E_8~0); 33882#L1401-1 assume !(0 == ~E_9~0); 33883#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 34170#L1411-1 assume !(0 == ~E_11~0); 34171#L1416-1 assume !(0 == ~E_12~0); 33800#L1421-1 assume !(0 == ~E_13~0); 33319#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33320#L640 assume !(1 == ~m_pc~0); 33849#L640-2 is_master_triggered_~__retres1~0#1 := 0; 33848#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33808#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33809#L1603 assume !(0 != activate_threads_~tmp~1#1); 33837#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33469#L659 assume 1 == ~t1_pc~0; 33470#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33578#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34291#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33600#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 33601#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33617#L678 assume 1 == ~t2_pc~0; 34563#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34564#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33162#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33163#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 33711#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33830#L697 assume !(1 == ~t3_pc~0); 33831#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33961#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34281#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33744#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33745#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34596#L716 assume 1 == ~t4_pc~0; 34584#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33449#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32815#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32816#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 32923#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34245#L735 assume !(1 == ~t5_pc~0); 32890#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32891#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33346#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34271#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 33908#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33909#L754 assume 1 == ~t6_pc~0; 33662#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33562#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33139#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33140#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 33536#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34345#L773 assume !(1 == ~t7_pc~0); 33076#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 33075#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33943#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33918#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 33919#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33972#L792 assume 1 == ~t8_pc~0; 34140#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34461#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34462#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33910#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 33833#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33834#L811 assume 1 == ~t9_pc~0; 34043#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34508#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33218#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33219#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 33845#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33846#L830 assume !(1 == ~t10_pc~0); 33571#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33052#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33053#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33030#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33031#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34363#L849 assume 1 == ~t11_pc~0; 34364#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32869#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32870#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34374#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 34275#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34276#L868 assume !(1 == ~t12_pc~0); 33695#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33694#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32757#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 32758#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 33087#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33088#L887 assume 1 == ~t13_pc~0; 34283#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33738#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33739#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34339#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 32797#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32798#L1439 assume !(1 == ~M_E~0); 33902#L1439-2 assume !(1 == ~T1_E~0); 32968#L1444-1 assume !(1 == ~T2_E~0); 32969#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33474#L1454-1 assume !(1 == ~T4_E~0); 33475#L1459-1 assume !(1 == ~T5_E~0); 34035#L1464-1 assume !(1 == ~T6_E~0); 34036#L1469-1 assume !(1 == ~T7_E~0); 34109#L1474-1 assume !(1 == ~T8_E~0); 33801#L1479-1 assume !(1 == ~T9_E~0); 33802#L1484-1 assume !(1 == ~T10_E~0); 34039#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33684#L1494-1 assume !(1 == ~T12_E~0); 33685#L1499-1 assume !(1 == ~T13_E~0); 33867#L1504-1 assume !(1 == ~E_M~0); 33868#L1509-1 assume !(1 == ~E_1~0); 34446#L1514-1 assume !(1 == ~E_2~0); 34142#L1519-1 assume !(1 == ~E_3~0); 34143#L1524-1 assume !(1 == ~E_4~0); 34641#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34642#L1534-1 assume !(1 == ~E_6~0); 32791#L1539-1 assume !(1 == ~E_7~0); 32792#L1544-1 assume !(1 == ~E_8~0); 33215#L1549-1 assume !(1 == ~E_9~0); 34614#L1554-1 assume !(1 == ~E_10~0); 34611#L1559-1 assume !(1 == ~E_11~0); 34486#L1564-1 assume !(1 == ~E_12~0); 34487#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 34636#L1574-1 assume { :end_inline_reset_delta_events } true; 32966#L1940-2 [2023-11-26 10:48:02,172 INFO L750 eck$LassoCheckResult]: Loop: 32966#L1940-2 assume !false; 32967#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33510#L1266-1 assume !false; 34680#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33531#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33245#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 34445#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 34454#L1079 assume !(0 != eval_~tmp~0#1); 33728#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33383#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33384#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34110#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34111#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34667#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34622#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33768#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33004#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33005#L1321-3 assume !(0 == ~T7_E~0); 33109#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33897#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34148#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34149#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33466#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33443#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33381#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33382#L1361-3 assume !(0 == ~E_1~0); 33962#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32720#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32721#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34466#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34325#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34326#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34500#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34501#L1401-3 assume !(0 == ~E_9~0); 33067#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32931#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32932#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 33625#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 33626#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33733#L640-45 assume !(1 == ~m_pc~0); 33734#L640-47 is_master_triggered_~__retres1~0#1 := 0; 33175#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33176#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32716#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 32717#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32805#L659-45 assume 1 == ~t1_pc~0; 32806#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33259#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34671#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34601#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34254#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34255#L678-45 assume 1 == ~t2_pc~0; 34206#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33740#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33741#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34188#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34517#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34620#L697-45 assume 1 == ~t3_pc~0; 34001#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34002#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34687#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34154#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34155#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34189#L716-45 assume 1 == ~t4_pc~0; 33813#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33815#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34472#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33820#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33821#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33484#L735-45 assume 1 == ~t5_pc~0; 33485#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34033#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34638#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34684#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34640#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34634#L754-45 assume 1 == ~t6_pc~0; 33984#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33985#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33878#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33879#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33989#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33716#L773-45 assume 1 == ~t7_pc~0; 33717#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33256#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33950#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33951#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33724#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33375#L792-45 assume 1 == ~t8_pc~0; 33376#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34404#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34405#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32826#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32827#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33325#L811-45 assume !(1 == ~t9_pc~0); 33104#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 33103#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34322#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34185#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 33792#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33583#L830-45 assume 1 == ~t10_pc~0; 33584#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32753#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33901#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32977#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32978#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32736#L849-45 assume !(1 == ~t11_pc~0); 32737#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 33193#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33034#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32722#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32723#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32972#L868-45 assume 1 == ~t12_pc~0; 32973#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32916#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32917#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34357#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 34530#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 34531#L887-45 assume !(1 == ~t13_pc~0); 32979#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 32980#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34285#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34304#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 32946#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32947#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34280#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32964#L1444-3 assume !(1 == ~T2_E~0); 32965#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33123#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34091#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34092#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34532#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34469#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34470#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34534#L1484-3 assume !(1 == ~T10_E~0); 33774#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33775#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 34397#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 34050#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34051#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34482#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34518#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33691#L1524-3 assume !(1 == ~E_4~0); 33692#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34556#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33969#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33426#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33427#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33932#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33011#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33012#L1564-3 assume !(1 == ~E_12~0); 34190#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 34191#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32903#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32677#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33003#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 32910#L1959 assume !(0 == start_simulation_~tmp~3#1); 32912#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32942#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32896#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32731#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 32732#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34550#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34525#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34526#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 32966#L1940-2 [2023-11-26 10:48:02,173 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:02,173 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2023-11-26 10:48:02,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:02,174 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285589241] [2023-11-26 10:48:02,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:02,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:02,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:02,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:02,236 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:02,236 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285589241] [2023-11-26 10:48:02,237 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [285589241] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:02,237 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:02,237 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:02,237 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [388857161] [2023-11-26 10:48:02,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:02,238 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:02,238 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:02,239 INFO L85 PathProgramCache]: Analyzing trace with hash 2047809084, now seen corresponding path program 1 times [2023-11-26 10:48:02,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:02,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406769399] [2023-11-26 10:48:02,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:02,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:02,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:02,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:02,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:02,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1406769399] [2023-11-26 10:48:02,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1406769399] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:02,345 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:02,345 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:02,346 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [26393743] [2023-11-26 10:48:02,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:02,346 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:02,347 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:02,347 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:02,347 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:02,347 INFO L87 Difference]: Start difference. First operand 2037 states and 3003 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:02,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:02,394 INFO L93 Difference]: Finished difference Result 2037 states and 3002 transitions. [2023-11-26 10:48:02,394 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3002 transitions. [2023-11-26 10:48:02,407 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:02,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3002 transitions. [2023-11-26 10:48:02,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2023-11-26 10:48:02,435 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2023-11-26 10:48:02,435 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3002 transitions. [2023-11-26 10:48:02,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:02,439 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3002 transitions. [2023-11-26 10:48:02,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3002 transitions. [2023-11-26 10:48:02,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2023-11-26 10:48:02,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4737358861070202) internal successors, (3002), 2036 states have internal predecessors, (3002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:02,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3002 transitions. [2023-11-26 10:48:02,506 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3002 transitions. [2023-11-26 10:48:02,507 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:02,508 INFO L428 stractBuchiCegarLoop]: Abstraction has 2037 states and 3002 transitions. [2023-11-26 10:48:02,508 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 10:48:02,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3002 transitions. [2023-11-26 10:48:02,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:02,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:02,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:02,522 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:02,522 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:02,523 INFO L748 eck$LassoCheckResult]: Stem: 37039#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 37040#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 38033#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38034#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38769#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 38161#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37630#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37631#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38435#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38436#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38540#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38541#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37379#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37380#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38575#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37931#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37932#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38481#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37845#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37846#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 38770#L1291-2 assume !(0 == ~T1_E~0); 38767#L1296-1 assume !(0 == ~T2_E~0); 37995#L1301-1 assume !(0 == ~T3_E~0); 37996#L1306-1 assume !(0 == ~T4_E~0); 38491#L1311-1 assume !(0 == ~T5_E~0); 37216#L1316-1 assume !(0 == ~T6_E~0); 37217#L1321-1 assume !(0 == ~T7_E~0); 38009#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37036#L1331-1 assume !(0 == ~T9_E~0); 36749#L1336-1 assume !(0 == ~T10_E~0); 36750#L1341-1 assume !(0 == ~T11_E~0); 36823#L1346-1 assume !(0 == ~T12_E~0); 36824#L1351-1 assume !(0 == ~T13_E~0); 37153#L1356-1 assume !(0 == ~E_M~0); 37154#L1361-1 assume !(0 == ~E_1~0); 38707#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 37200#L1371-1 assume !(0 == ~E_3~0); 37201#L1376-1 assume !(0 == ~E_4~0); 38061#L1381-1 assume !(0 == ~E_5~0); 38062#L1386-1 assume !(0 == ~E_6~0); 38738#L1391-1 assume !(0 == ~E_7~0); 38758#L1396-1 assume !(0 == ~E_8~0); 37963#L1401-1 assume !(0 == ~E_9~0); 37964#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 38251#L1411-1 assume !(0 == ~E_11~0); 38252#L1416-1 assume !(0 == ~E_12~0); 37881#L1421-1 assume !(0 == ~E_13~0); 37400#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37401#L640 assume !(1 == ~m_pc~0); 37930#L640-2 is_master_triggered_~__retres1~0#1 := 0; 37929#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37889#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37890#L1603 assume !(0 != activate_threads_~tmp~1#1); 37918#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37550#L659 assume 1 == ~t1_pc~0; 37551#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37659#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38372#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37681#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 37682#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37698#L678 assume 1 == ~t2_pc~0; 38644#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38645#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37243#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37244#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 37792#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37911#L697 assume !(1 == ~t3_pc~0); 37912#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 38042#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38362#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37825#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37826#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38677#L716 assume 1 == ~t4_pc~0; 38665#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37530#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36896#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36897#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 37004#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38326#L735 assume !(1 == ~t5_pc~0); 36971#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36972#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37427#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38352#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 37989#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37990#L754 assume 1 == ~t6_pc~0; 37743#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37643#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37220#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37221#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 37617#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38426#L773 assume !(1 == ~t7_pc~0); 37157#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 37156#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38024#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37999#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 38000#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38053#L792 assume 1 == ~t8_pc~0; 38221#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38542#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38543#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37991#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 37914#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37915#L811 assume 1 == ~t9_pc~0; 38124#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38589#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37299#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37300#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 37926#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37927#L830 assume !(1 == ~t10_pc~0); 37652#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 37133#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37134#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37111#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37112#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38444#L849 assume 1 == ~t11_pc~0; 38445#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36950#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36951#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38455#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 38356#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38357#L868 assume !(1 == ~t12_pc~0); 37776#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37775#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36838#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 36839#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 37168#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37169#L887 assume 1 == ~t13_pc~0; 38364#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37819#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37820#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38420#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 36878#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36879#L1439 assume !(1 == ~M_E~0); 37983#L1439-2 assume !(1 == ~T1_E~0); 37049#L1444-1 assume !(1 == ~T2_E~0); 37050#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37555#L1454-1 assume !(1 == ~T4_E~0); 37556#L1459-1 assume !(1 == ~T5_E~0); 38116#L1464-1 assume !(1 == ~T6_E~0); 38117#L1469-1 assume !(1 == ~T7_E~0); 38190#L1474-1 assume !(1 == ~T8_E~0); 37882#L1479-1 assume !(1 == ~T9_E~0); 37883#L1484-1 assume !(1 == ~T10_E~0); 38120#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37765#L1494-1 assume !(1 == ~T12_E~0); 37766#L1499-1 assume !(1 == ~T13_E~0); 37948#L1504-1 assume !(1 == ~E_M~0); 37949#L1509-1 assume !(1 == ~E_1~0); 38527#L1514-1 assume !(1 == ~E_2~0); 38223#L1519-1 assume !(1 == ~E_3~0); 38224#L1524-1 assume !(1 == ~E_4~0); 38722#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38723#L1534-1 assume !(1 == ~E_6~0); 36872#L1539-1 assume !(1 == ~E_7~0); 36873#L1544-1 assume !(1 == ~E_8~0); 37296#L1549-1 assume !(1 == ~E_9~0); 38695#L1554-1 assume !(1 == ~E_10~0); 38692#L1559-1 assume !(1 == ~E_11~0); 38567#L1564-1 assume !(1 == ~E_12~0); 38568#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 38717#L1574-1 assume { :end_inline_reset_delta_events } true; 37047#L1940-2 [2023-11-26 10:48:02,523 INFO L750 eck$LassoCheckResult]: Loop: 37047#L1940-2 assume !false; 37048#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37591#L1266-1 assume !false; 38761#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37612#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37326#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38526#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 38535#L1079 assume !(0 != eval_~tmp~0#1); 37809#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37464#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37465#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38191#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38192#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38748#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38703#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37849#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37085#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37086#L1321-3 assume !(0 == ~T7_E~0); 37190#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37978#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38229#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38230#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37547#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37524#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37462#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37463#L1361-3 assume !(0 == ~E_1~0); 38043#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36801#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36802#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38547#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38406#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38407#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38581#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38582#L1401-3 assume !(0 == ~E_9~0); 37148#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37012#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 37013#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 37706#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 37707#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37814#L640-45 assume !(1 == ~m_pc~0); 37815#L640-47 is_master_triggered_~__retres1~0#1 := 0; 37256#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37257#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36797#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 36798#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36886#L659-45 assume 1 == ~t1_pc~0; 36887#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37340#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38752#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38682#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38335#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38336#L678-45 assume !(1 == ~t2_pc~0); 38288#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 37821#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37822#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38269#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38598#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38701#L697-45 assume 1 == ~t3_pc~0; 38082#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38083#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38768#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38235#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38236#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38270#L716-45 assume 1 == ~t4_pc~0; 37894#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37896#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38553#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37901#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37902#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37565#L735-45 assume 1 == ~t5_pc~0; 37566#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38114#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38719#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38765#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38721#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38715#L754-45 assume 1 == ~t6_pc~0; 38065#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38066#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37959#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37960#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38070#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37797#L773-45 assume 1 == ~t7_pc~0; 37798#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37337#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38031#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38032#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37805#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37456#L792-45 assume 1 == ~t8_pc~0; 37457#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38485#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38486#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36907#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36908#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37406#L811-45 assume !(1 == ~t9_pc~0); 37185#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 37184#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38403#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38266#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 37873#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37664#L830-45 assume 1 == ~t10_pc~0; 37665#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36834#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37982#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37058#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37059#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36817#L849-45 assume !(1 == ~t11_pc~0); 36818#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37274#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37115#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36803#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36804#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37053#L868-45 assume 1 == ~t12_pc~0; 37054#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36997#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36998#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38438#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 38611#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38612#L887-45 assume !(1 == ~t13_pc~0); 37060#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 37061#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38366#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38385#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 37027#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37028#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38361#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37045#L1444-3 assume !(1 == ~T2_E~0); 37046#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37204#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38172#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38173#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38613#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38550#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38551#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38615#L1484-3 assume !(1 == ~T10_E~0); 37855#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37856#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38478#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38131#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38132#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38563#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38599#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37772#L1524-3 assume !(1 == ~E_4~0); 37773#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38637#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38050#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37507#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37508#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38013#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37092#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37093#L1564-3 assume !(1 == ~E_12~0); 38271#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 38272#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36984#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36758#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37084#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 36991#L1959 assume !(0 == start_simulation_~tmp~3#1); 36993#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37023#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36977#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36812#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 36813#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38631#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38606#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38607#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 37047#L1940-2 [2023-11-26 10:48:02,524 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:02,525 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2023-11-26 10:48:02,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:02,526 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027366886] [2023-11-26 10:48:02,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:02,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:02,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:02,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:02,594 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:02,595 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027366886] [2023-11-26 10:48:02,595 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2027366886] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:02,595 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:02,595 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:02,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [892954229] [2023-11-26 10:48:02,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:02,597 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:02,598 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:02,598 INFO L85 PathProgramCache]: Analyzing trace with hash -1230532739, now seen corresponding path program 1 times [2023-11-26 10:48:02,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:02,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998926540] [2023-11-26 10:48:02,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:02,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:02,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:02,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:02,680 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:02,680 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [998926540] [2023-11-26 10:48:02,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [998926540] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:02,681 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:02,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:02,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260571203] [2023-11-26 10:48:02,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:02,682 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:02,682 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:02,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:02,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:02,683 INFO L87 Difference]: Start difference. First operand 2037 states and 3002 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:02,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:02,731 INFO L93 Difference]: Finished difference Result 2037 states and 3001 transitions. [2023-11-26 10:48:02,731 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3001 transitions. [2023-11-26 10:48:02,743 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:02,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3001 transitions. [2023-11-26 10:48:02,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2023-11-26 10:48:02,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2023-11-26 10:48:02,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3001 transitions. [2023-11-26 10:48:02,761 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:02,761 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3001 transitions. [2023-11-26 10:48:02,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3001 transitions. [2023-11-26 10:48:02,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2023-11-26 10:48:02,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.473244968090329) internal successors, (3001), 2036 states have internal predecessors, (3001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:02,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3001 transitions. [2023-11-26 10:48:02,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3001 transitions. [2023-11-26 10:48:02,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:02,810 INFO L428 stractBuchiCegarLoop]: Abstraction has 2037 states and 3001 transitions. [2023-11-26 10:48:02,810 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 10:48:02,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3001 transitions. [2023-11-26 10:48:02,820 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:02,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:02,821 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:02,823 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:02,824 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:02,824 INFO L748 eck$LassoCheckResult]: Stem: 41120#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 41121#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42114#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42115#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42850#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 42242#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41711#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41712#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42516#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42517#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42621#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42622#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41460#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41461#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42656#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 42012#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 42013#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 42562#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 41926#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41927#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 42851#L1291-2 assume !(0 == ~T1_E~0); 42848#L1296-1 assume !(0 == ~T2_E~0); 42076#L1301-1 assume !(0 == ~T3_E~0); 42077#L1306-1 assume !(0 == ~T4_E~0); 42572#L1311-1 assume !(0 == ~T5_E~0); 41297#L1316-1 assume !(0 == ~T6_E~0); 41298#L1321-1 assume !(0 == ~T7_E~0); 42090#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41117#L1331-1 assume !(0 == ~T9_E~0); 40830#L1336-1 assume !(0 == ~T10_E~0); 40831#L1341-1 assume !(0 == ~T11_E~0); 40904#L1346-1 assume !(0 == ~T12_E~0); 40905#L1351-1 assume !(0 == ~T13_E~0); 41234#L1356-1 assume !(0 == ~E_M~0); 41235#L1361-1 assume !(0 == ~E_1~0); 42788#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 41281#L1371-1 assume !(0 == ~E_3~0); 41282#L1376-1 assume !(0 == ~E_4~0); 42142#L1381-1 assume !(0 == ~E_5~0); 42143#L1386-1 assume !(0 == ~E_6~0); 42819#L1391-1 assume !(0 == ~E_7~0); 42839#L1396-1 assume !(0 == ~E_8~0); 42044#L1401-1 assume !(0 == ~E_9~0); 42045#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 42332#L1411-1 assume !(0 == ~E_11~0); 42333#L1416-1 assume !(0 == ~E_12~0); 41962#L1421-1 assume !(0 == ~E_13~0); 41481#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41482#L640 assume !(1 == ~m_pc~0); 42011#L640-2 is_master_triggered_~__retres1~0#1 := 0; 42010#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41970#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41971#L1603 assume !(0 != activate_threads_~tmp~1#1); 41999#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41631#L659 assume 1 == ~t1_pc~0; 41632#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41740#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42453#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41762#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 41763#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41779#L678 assume 1 == ~t2_pc~0; 42725#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42726#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41324#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41325#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 41873#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41992#L697 assume !(1 == ~t3_pc~0); 41993#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 42123#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42443#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41906#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41907#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42758#L716 assume 1 == ~t4_pc~0; 42746#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41611#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40977#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40978#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 41085#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42407#L735 assume !(1 == ~t5_pc~0); 41052#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41053#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41508#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42433#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 42070#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42071#L754 assume 1 == ~t6_pc~0; 41824#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41724#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41301#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41302#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 41698#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42507#L773 assume !(1 == ~t7_pc~0); 41238#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 41237#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42105#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42080#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 42081#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42134#L792 assume 1 == ~t8_pc~0; 42302#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42623#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42624#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42072#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 41995#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41996#L811 assume 1 == ~t9_pc~0; 42205#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42670#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41380#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41381#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 42007#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42008#L830 assume !(1 == ~t10_pc~0); 41733#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41214#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41215#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41192#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41193#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42525#L849 assume 1 == ~t11_pc~0; 42526#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41031#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41032#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42536#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 42437#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42438#L868 assume !(1 == ~t12_pc~0); 41857#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 41856#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40919#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 40920#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 41249#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41250#L887 assume 1 == ~t13_pc~0; 42445#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41900#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41901#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42501#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 40959#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40960#L1439 assume !(1 == ~M_E~0); 42064#L1439-2 assume !(1 == ~T1_E~0); 41130#L1444-1 assume !(1 == ~T2_E~0); 41131#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41636#L1454-1 assume !(1 == ~T4_E~0); 41637#L1459-1 assume !(1 == ~T5_E~0); 42197#L1464-1 assume !(1 == ~T6_E~0); 42198#L1469-1 assume !(1 == ~T7_E~0); 42271#L1474-1 assume !(1 == ~T8_E~0); 41963#L1479-1 assume !(1 == ~T9_E~0); 41964#L1484-1 assume !(1 == ~T10_E~0); 42201#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41846#L1494-1 assume !(1 == ~T12_E~0); 41847#L1499-1 assume !(1 == ~T13_E~0); 42029#L1504-1 assume !(1 == ~E_M~0); 42030#L1509-1 assume !(1 == ~E_1~0); 42608#L1514-1 assume !(1 == ~E_2~0); 42304#L1519-1 assume !(1 == ~E_3~0); 42305#L1524-1 assume !(1 == ~E_4~0); 42803#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42804#L1534-1 assume !(1 == ~E_6~0); 40953#L1539-1 assume !(1 == ~E_7~0); 40954#L1544-1 assume !(1 == ~E_8~0); 41377#L1549-1 assume !(1 == ~E_9~0); 42776#L1554-1 assume !(1 == ~E_10~0); 42773#L1559-1 assume !(1 == ~E_11~0); 42648#L1564-1 assume !(1 == ~E_12~0); 42649#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 42798#L1574-1 assume { :end_inline_reset_delta_events } true; 41128#L1940-2 [2023-11-26 10:48:02,825 INFO L750 eck$LassoCheckResult]: Loop: 41128#L1940-2 assume !false; 41129#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41672#L1266-1 assume !false; 42842#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41693#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41407#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42607#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 42616#L1079 assume !(0 != eval_~tmp~0#1); 41890#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41545#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41546#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42272#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42273#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42829#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42784#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41930#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41166#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41167#L1321-3 assume !(0 == ~T7_E~0); 41271#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 42059#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42310#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 42311#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41628#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41605#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41543#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41544#L1361-3 assume !(0 == ~E_1~0); 42124#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40882#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40883#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42628#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42487#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42488#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42662#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42663#L1401-3 assume !(0 == ~E_9~0); 41229#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41093#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41094#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 41787#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 41788#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41895#L640-45 assume !(1 == ~m_pc~0); 41896#L640-47 is_master_triggered_~__retres1~0#1 := 0; 41337#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41338#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40878#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 40879#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40967#L659-45 assume 1 == ~t1_pc~0; 40968#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41421#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42833#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42763#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42416#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42417#L678-45 assume 1 == ~t2_pc~0; 42368#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41902#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41903#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42350#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42679#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42782#L697-45 assume 1 == ~t3_pc~0; 42163#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42164#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42849#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42316#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42317#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42351#L716-45 assume 1 == ~t4_pc~0; 41975#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41977#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42634#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41982#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41983#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41646#L735-45 assume !(1 == ~t5_pc~0); 41648#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 42195#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42800#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42846#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42802#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42796#L754-45 assume 1 == ~t6_pc~0; 42146#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42147#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42040#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42041#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42151#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41878#L773-45 assume 1 == ~t7_pc~0; 41879#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41418#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42112#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42113#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41886#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41537#L792-45 assume 1 == ~t8_pc~0; 41538#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42566#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42567#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40988#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40989#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41487#L811-45 assume 1 == ~t9_pc~0; 41264#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41265#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42484#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42347#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 41954#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41745#L830-45 assume 1 == ~t10_pc~0; 41746#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40915#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42063#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41139#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41140#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40898#L849-45 assume !(1 == ~t11_pc~0); 40899#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 41355#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41196#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40884#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40885#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41134#L868-45 assume !(1 == ~t12_pc~0); 41136#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 41078#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41079#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42519#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 42692#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42693#L887-45 assume !(1 == ~t13_pc~0); 41141#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 41142#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42447#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42466#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 41108#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41109#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42442#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41126#L1444-3 assume !(1 == ~T2_E~0); 41127#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41285#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42253#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42254#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42694#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42631#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42632#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42696#L1484-3 assume !(1 == ~T10_E~0); 41936#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41937#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42559#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42212#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 42213#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42644#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42680#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41853#L1524-3 assume !(1 == ~E_4~0); 41854#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42718#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42131#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41588#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41589#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 42094#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41173#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41174#L1564-3 assume !(1 == ~E_12~0); 42352#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42353#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41065#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40839#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41165#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 41072#L1959 assume !(0 == start_simulation_~tmp~3#1); 41074#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41104#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41058#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40893#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 40894#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42712#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42687#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 42688#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 41128#L1940-2 [2023-11-26 10:48:02,826 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:02,826 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2023-11-26 10:48:02,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:02,826 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458500882] [2023-11-26 10:48:02,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:02,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:02,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:02,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:02,883 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:02,883 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1458500882] [2023-11-26 10:48:02,883 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1458500882] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:02,883 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:02,883 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:02,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982439574] [2023-11-26 10:48:02,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:02,884 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:02,885 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:02,885 INFO L85 PathProgramCache]: Analyzing trace with hash -692691971, now seen corresponding path program 1 times [2023-11-26 10:48:02,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:02,885 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433272044] [2023-11-26 10:48:02,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:02,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:02,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:02,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:02,967 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:02,967 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1433272044] [2023-11-26 10:48:02,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1433272044] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:02,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:02,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:02,968 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1109084565] [2023-11-26 10:48:02,968 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:02,969 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:02,969 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:02,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:02,972 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:02,972 INFO L87 Difference]: Start difference. First operand 2037 states and 3001 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:03,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:03,018 INFO L93 Difference]: Finished difference Result 2037 states and 3000 transitions. [2023-11-26 10:48:03,019 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3000 transitions. [2023-11-26 10:48:03,054 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:03,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3000 transitions. [2023-11-26 10:48:03,065 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2023-11-26 10:48:03,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2023-11-26 10:48:03,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3000 transitions. [2023-11-26 10:48:03,071 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:03,071 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3000 transitions. [2023-11-26 10:48:03,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3000 transitions. [2023-11-26 10:48:03,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2023-11-26 10:48:03,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4727540500736378) internal successors, (3000), 2036 states have internal predecessors, (3000), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:03,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3000 transitions. [2023-11-26 10:48:03,117 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3000 transitions. [2023-11-26 10:48:03,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:03,118 INFO L428 stractBuchiCegarLoop]: Abstraction has 2037 states and 3000 transitions. [2023-11-26 10:48:03,118 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 10:48:03,118 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3000 transitions. [2023-11-26 10:48:03,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:03,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:03,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:03,131 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:03,131 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:03,132 INFO L748 eck$LassoCheckResult]: Stem: 45201#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45202#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46195#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46196#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46931#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 46323#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45792#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45793#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46597#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46598#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46702#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46703#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45541#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45542#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46737#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 46093#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 46094#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 46643#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46007#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46008#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 46932#L1291-2 assume !(0 == ~T1_E~0); 46929#L1296-1 assume !(0 == ~T2_E~0); 46157#L1301-1 assume !(0 == ~T3_E~0); 46158#L1306-1 assume !(0 == ~T4_E~0); 46653#L1311-1 assume !(0 == ~T5_E~0); 45378#L1316-1 assume !(0 == ~T6_E~0); 45379#L1321-1 assume !(0 == ~T7_E~0); 46171#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45198#L1331-1 assume !(0 == ~T9_E~0); 44911#L1336-1 assume !(0 == ~T10_E~0); 44912#L1341-1 assume !(0 == ~T11_E~0); 44985#L1346-1 assume !(0 == ~T12_E~0); 44986#L1351-1 assume !(0 == ~T13_E~0); 45315#L1356-1 assume !(0 == ~E_M~0); 45316#L1361-1 assume !(0 == ~E_1~0); 46869#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 45362#L1371-1 assume !(0 == ~E_3~0); 45363#L1376-1 assume !(0 == ~E_4~0); 46223#L1381-1 assume !(0 == ~E_5~0); 46224#L1386-1 assume !(0 == ~E_6~0); 46900#L1391-1 assume !(0 == ~E_7~0); 46920#L1396-1 assume !(0 == ~E_8~0); 46125#L1401-1 assume !(0 == ~E_9~0); 46126#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 46413#L1411-1 assume !(0 == ~E_11~0); 46414#L1416-1 assume !(0 == ~E_12~0); 46043#L1421-1 assume !(0 == ~E_13~0); 45562#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45563#L640 assume !(1 == ~m_pc~0); 46092#L640-2 is_master_triggered_~__retres1~0#1 := 0; 46091#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46051#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46052#L1603 assume !(0 != activate_threads_~tmp~1#1); 46080#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45712#L659 assume 1 == ~t1_pc~0; 45713#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45821#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46534#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45843#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 45844#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45860#L678 assume 1 == ~t2_pc~0; 46806#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46807#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45405#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45406#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 45954#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46073#L697 assume !(1 == ~t3_pc~0); 46074#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46204#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46524#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45987#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45988#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46839#L716 assume 1 == ~t4_pc~0; 46827#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45692#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45058#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45059#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 45166#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46488#L735 assume !(1 == ~t5_pc~0); 45133#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 45134#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45589#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46514#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 46151#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46152#L754 assume 1 == ~t6_pc~0; 45905#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45805#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45382#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45383#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 45779#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46588#L773 assume !(1 == ~t7_pc~0); 45319#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45318#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46186#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46161#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 46162#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46215#L792 assume 1 == ~t8_pc~0; 46383#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46704#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46705#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46153#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 46076#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46077#L811 assume 1 == ~t9_pc~0; 46286#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46751#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45461#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45462#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 46088#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46089#L830 assume !(1 == ~t10_pc~0); 45814#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45295#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45296#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45273#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45274#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46606#L849 assume 1 == ~t11_pc~0; 46607#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45112#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45113#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46617#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 46518#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46519#L868 assume !(1 == ~t12_pc~0); 45938#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 45937#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45000#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45001#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 45330#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45331#L887 assume 1 == ~t13_pc~0; 46526#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45981#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45982#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46582#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 45040#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45041#L1439 assume !(1 == ~M_E~0); 46145#L1439-2 assume !(1 == ~T1_E~0); 45211#L1444-1 assume !(1 == ~T2_E~0); 45212#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45717#L1454-1 assume !(1 == ~T4_E~0); 45718#L1459-1 assume !(1 == ~T5_E~0); 46278#L1464-1 assume !(1 == ~T6_E~0); 46279#L1469-1 assume !(1 == ~T7_E~0); 46352#L1474-1 assume !(1 == ~T8_E~0); 46044#L1479-1 assume !(1 == ~T9_E~0); 46045#L1484-1 assume !(1 == ~T10_E~0); 46282#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45927#L1494-1 assume !(1 == ~T12_E~0); 45928#L1499-1 assume !(1 == ~T13_E~0); 46110#L1504-1 assume !(1 == ~E_M~0); 46111#L1509-1 assume !(1 == ~E_1~0); 46689#L1514-1 assume !(1 == ~E_2~0); 46385#L1519-1 assume !(1 == ~E_3~0); 46386#L1524-1 assume !(1 == ~E_4~0); 46884#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46885#L1534-1 assume !(1 == ~E_6~0); 45034#L1539-1 assume !(1 == ~E_7~0); 45035#L1544-1 assume !(1 == ~E_8~0); 45458#L1549-1 assume !(1 == ~E_9~0); 46857#L1554-1 assume !(1 == ~E_10~0); 46854#L1559-1 assume !(1 == ~E_11~0); 46729#L1564-1 assume !(1 == ~E_12~0); 46730#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 46879#L1574-1 assume { :end_inline_reset_delta_events } true; 45209#L1940-2 [2023-11-26 10:48:03,132 INFO L750 eck$LassoCheckResult]: Loop: 45209#L1940-2 assume !false; 45210#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45753#L1266-1 assume !false; 46923#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45774#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45488#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46688#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 46697#L1079 assume !(0 != eval_~tmp~0#1); 45971#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45626#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45627#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46353#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46354#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46910#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46865#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46011#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45247#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45248#L1321-3 assume !(0 == ~T7_E~0); 45352#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 46140#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46391#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 46392#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45709#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45686#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45624#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45625#L1361-3 assume !(0 == ~E_1~0); 46205#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44963#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44964#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46709#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46568#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46569#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46743#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46744#L1401-3 assume !(0 == ~E_9~0); 45310#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45174#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 45175#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 45868#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 45869#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45976#L640-45 assume !(1 == ~m_pc~0); 45977#L640-47 is_master_triggered_~__retres1~0#1 := 0; 45418#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45419#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44959#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 44960#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45048#L659-45 assume 1 == ~t1_pc~0; 45049#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45502#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46914#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46844#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46497#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46498#L678-45 assume 1 == ~t2_pc~0; 46449#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45983#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45984#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46431#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46760#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46863#L697-45 assume 1 == ~t3_pc~0; 46244#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46245#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46930#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46397#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46398#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46432#L716-45 assume 1 == ~t4_pc~0; 46056#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46058#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46715#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46063#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46064#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45727#L735-45 assume 1 == ~t5_pc~0; 45728#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46276#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46881#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46927#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46883#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46877#L754-45 assume 1 == ~t6_pc~0; 46227#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46228#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46121#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46122#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46232#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45959#L773-45 assume 1 == ~t7_pc~0; 45960#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45499#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46193#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46194#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45967#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45618#L792-45 assume 1 == ~t8_pc~0; 45619#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46647#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46648#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45069#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45070#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45568#L811-45 assume 1 == ~t9_pc~0; 45345#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45346#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46565#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46428#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 46035#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45826#L830-45 assume 1 == ~t10_pc~0; 45827#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44996#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46144#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45220#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45221#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44979#L849-45 assume !(1 == ~t11_pc~0); 44980#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 45436#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45277#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44965#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44966#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45215#L868-45 assume 1 == ~t12_pc~0; 45216#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 45159#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45160#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46600#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 46773#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46774#L887-45 assume !(1 == ~t13_pc~0); 45222#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 45223#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46528#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46547#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 45189#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45190#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46523#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45207#L1444-3 assume !(1 == ~T2_E~0); 45208#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45366#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46334#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46335#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46775#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46712#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46713#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46777#L1484-3 assume !(1 == ~T10_E~0); 46017#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46018#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46640#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46293#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 46294#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46725#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46761#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45934#L1524-3 assume !(1 == ~E_4~0); 45935#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46799#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46212#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45669#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45670#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46175#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 45254#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45255#L1564-3 assume !(1 == ~E_12~0); 46433#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46434#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45146#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44920#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45246#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 45153#L1959 assume !(0 == start_simulation_~tmp~3#1); 45155#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45185#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45139#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44974#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 44975#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46793#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46768#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 46769#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 45209#L1940-2 [2023-11-26 10:48:03,133 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:03,134 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2023-11-26 10:48:03,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:03,134 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1322946362] [2023-11-26 10:48:03,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:03,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:03,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:03,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:03,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:03,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1322946362] [2023-11-26 10:48:03,242 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1322946362] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:03,242 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:03,242 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:03,243 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [87697814] [2023-11-26 10:48:03,243 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:03,243 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:03,244 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:03,244 INFO L85 PathProgramCache]: Analyzing trace with hash -291836997, now seen corresponding path program 1 times [2023-11-26 10:48:03,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:03,244 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694341671] [2023-11-26 10:48:03,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:03,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:03,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:03,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:03,316 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:03,316 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [694341671] [2023-11-26 10:48:03,316 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [694341671] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:03,316 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:03,317 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:03,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767902954] [2023-11-26 10:48:03,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:03,317 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:03,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:03,318 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:03,318 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:03,319 INFO L87 Difference]: Start difference. First operand 2037 states and 3000 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:03,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:03,363 INFO L93 Difference]: Finished difference Result 2037 states and 2999 transitions. [2023-11-26 10:48:03,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 2999 transitions. [2023-11-26 10:48:03,377 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:03,389 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 2999 transitions. [2023-11-26 10:48:03,389 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2023-11-26 10:48:03,391 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2023-11-26 10:48:03,391 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 2999 transitions. [2023-11-26 10:48:03,395 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:03,395 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 2999 transitions. [2023-11-26 10:48:03,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 2999 transitions. [2023-11-26 10:48:03,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2023-11-26 10:48:03,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4722631320569466) internal successors, (2999), 2036 states have internal predecessors, (2999), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:03,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 2999 transitions. [2023-11-26 10:48:03,444 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 2999 transitions. [2023-11-26 10:48:03,444 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:03,445 INFO L428 stractBuchiCegarLoop]: Abstraction has 2037 states and 2999 transitions. [2023-11-26 10:48:03,445 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 10:48:03,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 2999 transitions. [2023-11-26 10:48:03,455 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:03,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:03,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:03,458 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:03,459 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:03,459 INFO L748 eck$LassoCheckResult]: Stem: 49282#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 49283#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50276#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50277#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51012#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 50404#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49873#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49874#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50678#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50679#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50783#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50784#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49622#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49623#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50818#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50174#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 50175#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50724#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 50088#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50089#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 51013#L1291-2 assume !(0 == ~T1_E~0); 51010#L1296-1 assume !(0 == ~T2_E~0); 50238#L1301-1 assume !(0 == ~T3_E~0); 50239#L1306-1 assume !(0 == ~T4_E~0); 50734#L1311-1 assume !(0 == ~T5_E~0); 49459#L1316-1 assume !(0 == ~T6_E~0); 49460#L1321-1 assume !(0 == ~T7_E~0); 50252#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49279#L1331-1 assume !(0 == ~T9_E~0); 48992#L1336-1 assume !(0 == ~T10_E~0); 48993#L1341-1 assume !(0 == ~T11_E~0); 49066#L1346-1 assume !(0 == ~T12_E~0); 49067#L1351-1 assume !(0 == ~T13_E~0); 49396#L1356-1 assume !(0 == ~E_M~0); 49397#L1361-1 assume !(0 == ~E_1~0); 50950#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 49443#L1371-1 assume !(0 == ~E_3~0); 49444#L1376-1 assume !(0 == ~E_4~0); 50304#L1381-1 assume !(0 == ~E_5~0); 50305#L1386-1 assume !(0 == ~E_6~0); 50981#L1391-1 assume !(0 == ~E_7~0); 51001#L1396-1 assume !(0 == ~E_8~0); 50206#L1401-1 assume !(0 == ~E_9~0); 50207#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 50494#L1411-1 assume !(0 == ~E_11~0); 50495#L1416-1 assume !(0 == ~E_12~0); 50124#L1421-1 assume !(0 == ~E_13~0); 49643#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49644#L640 assume !(1 == ~m_pc~0); 50173#L640-2 is_master_triggered_~__retres1~0#1 := 0; 50172#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50132#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50133#L1603 assume !(0 != activate_threads_~tmp~1#1); 50161#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49793#L659 assume 1 == ~t1_pc~0; 49794#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49902#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50615#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49924#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 49925#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49941#L678 assume 1 == ~t2_pc~0; 50887#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50888#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49486#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49487#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 50035#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50154#L697 assume !(1 == ~t3_pc~0); 50155#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50285#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50605#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50068#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50069#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50920#L716 assume 1 == ~t4_pc~0; 50908#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49773#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49139#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49140#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 49247#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50569#L735 assume !(1 == ~t5_pc~0); 49214#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 49215#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49670#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50595#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 50232#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50233#L754 assume 1 == ~t6_pc~0; 49986#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49886#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49463#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49464#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 49860#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50669#L773 assume !(1 == ~t7_pc~0); 49400#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49399#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50267#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50242#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 50243#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50296#L792 assume 1 == ~t8_pc~0; 50464#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50785#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50786#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50234#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 50157#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50158#L811 assume 1 == ~t9_pc~0; 50367#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50832#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49542#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49543#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 50169#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50170#L830 assume !(1 == ~t10_pc~0); 49895#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49376#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49377#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49354#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49355#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50687#L849 assume 1 == ~t11_pc~0; 50688#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49193#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49194#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50698#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 50599#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50600#L868 assume !(1 == ~t12_pc~0); 50019#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 50018#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49081#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49082#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 49411#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49412#L887 assume 1 == ~t13_pc~0; 50607#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50062#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50063#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50663#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 49121#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49122#L1439 assume !(1 == ~M_E~0); 50226#L1439-2 assume !(1 == ~T1_E~0); 49292#L1444-1 assume !(1 == ~T2_E~0); 49293#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49798#L1454-1 assume !(1 == ~T4_E~0); 49799#L1459-1 assume !(1 == ~T5_E~0); 50359#L1464-1 assume !(1 == ~T6_E~0); 50360#L1469-1 assume !(1 == ~T7_E~0); 50433#L1474-1 assume !(1 == ~T8_E~0); 50125#L1479-1 assume !(1 == ~T9_E~0); 50126#L1484-1 assume !(1 == ~T10_E~0); 50363#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50008#L1494-1 assume !(1 == ~T12_E~0); 50009#L1499-1 assume !(1 == ~T13_E~0); 50191#L1504-1 assume !(1 == ~E_M~0); 50192#L1509-1 assume !(1 == ~E_1~0); 50770#L1514-1 assume !(1 == ~E_2~0); 50466#L1519-1 assume !(1 == ~E_3~0); 50467#L1524-1 assume !(1 == ~E_4~0); 50965#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50966#L1534-1 assume !(1 == ~E_6~0); 49115#L1539-1 assume !(1 == ~E_7~0); 49116#L1544-1 assume !(1 == ~E_8~0); 49539#L1549-1 assume !(1 == ~E_9~0); 50938#L1554-1 assume !(1 == ~E_10~0); 50935#L1559-1 assume !(1 == ~E_11~0); 50810#L1564-1 assume !(1 == ~E_12~0); 50811#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 50960#L1574-1 assume { :end_inline_reset_delta_events } true; 49290#L1940-2 [2023-11-26 10:48:03,460 INFO L750 eck$LassoCheckResult]: Loop: 49290#L1940-2 assume !false; 49291#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49834#L1266-1 assume !false; 51004#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49855#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49569#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50769#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 50778#L1079 assume !(0 != eval_~tmp~0#1); 50052#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49707#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49708#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50434#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50435#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50991#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50946#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50092#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49328#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49329#L1321-3 assume !(0 == ~T7_E~0); 49433#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50221#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50472#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 50473#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49790#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 49767#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 49705#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49706#L1361-3 assume !(0 == ~E_1~0); 50286#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49044#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49045#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50790#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50649#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50650#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50824#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50825#L1401-3 assume !(0 == ~E_9~0); 49391#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49255#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 49256#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 49949#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 49950#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50057#L640-45 assume !(1 == ~m_pc~0); 50058#L640-47 is_master_triggered_~__retres1~0#1 := 0; 49499#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49500#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49040#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 49041#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49129#L659-45 assume 1 == ~t1_pc~0; 49130#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49583#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50995#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50925#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50578#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50579#L678-45 assume 1 == ~t2_pc~0; 50530#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50064#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50065#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50512#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50841#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50944#L697-45 assume 1 == ~t3_pc~0; 50325#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50326#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51011#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50478#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50479#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50513#L716-45 assume 1 == ~t4_pc~0; 50137#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50139#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50796#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50144#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50145#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49808#L735-45 assume 1 == ~t5_pc~0; 49809#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50357#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50962#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51008#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50964#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50958#L754-45 assume 1 == ~t6_pc~0; 50308#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50309#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50202#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50203#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50313#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50040#L773-45 assume 1 == ~t7_pc~0; 50041#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49580#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50274#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50275#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50048#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49699#L792-45 assume 1 == ~t8_pc~0; 49700#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50728#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50729#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49150#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49151#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49649#L811-45 assume 1 == ~t9_pc~0; 49426#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49427#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50646#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50509#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 50116#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49907#L830-45 assume 1 == ~t10_pc~0; 49908#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49077#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50225#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49301#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49302#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49060#L849-45 assume !(1 == ~t11_pc~0); 49061#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 49517#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49358#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49046#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 49047#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49296#L868-45 assume 1 == ~t12_pc~0; 49297#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 49240#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49241#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50681#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 50854#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50855#L887-45 assume !(1 == ~t13_pc~0); 49303#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 49304#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50609#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50628#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 49270#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49271#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50604#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49288#L1444-3 assume !(1 == ~T2_E~0); 49289#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49447#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50415#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50416#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50856#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50793#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50794#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50858#L1484-3 assume !(1 == ~T10_E~0); 50098#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50099#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50721#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50374#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50375#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50806#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50842#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50015#L1524-3 assume !(1 == ~E_4~0); 50016#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50880#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50293#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49750#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49751#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50256#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49335#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49336#L1564-3 assume !(1 == ~E_12~0); 50514#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50515#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49227#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49001#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49327#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 49234#L1959 assume !(0 == start_simulation_~tmp~3#1); 49236#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49266#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49220#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49055#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 49056#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50874#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50849#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 50850#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 49290#L1940-2 [2023-11-26 10:48:03,461 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:03,461 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2023-11-26 10:48:03,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:03,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651744589] [2023-11-26 10:48:03,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:03,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:03,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:03,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:03,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:03,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [651744589] [2023-11-26 10:48:03,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [651744589] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:03,520 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:03,520 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:03,521 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1105401058] [2023-11-26 10:48:03,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:03,522 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:03,522 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:03,522 INFO L85 PathProgramCache]: Analyzing trace with hash -291836997, now seen corresponding path program 2 times [2023-11-26 10:48:03,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:03,523 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082375877] [2023-11-26 10:48:03,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:03,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:03,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:03,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:03,601 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:03,602 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2082375877] [2023-11-26 10:48:03,602 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2082375877] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:03,602 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:03,602 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:03,602 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [74964337] [2023-11-26 10:48:03,602 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:03,603 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:03,604 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:03,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:03,605 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:03,605 INFO L87 Difference]: Start difference. First operand 2037 states and 2999 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:03,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:03,648 INFO L93 Difference]: Finished difference Result 2037 states and 2998 transitions. [2023-11-26 10:48:03,649 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 2998 transitions. [2023-11-26 10:48:03,661 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:03,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 2998 transitions. [2023-11-26 10:48:03,681 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2023-11-26 10:48:03,684 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2023-11-26 10:48:03,684 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 2998 transitions. [2023-11-26 10:48:03,687 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:03,688 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 2998 transitions. [2023-11-26 10:48:03,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 2998 transitions. [2023-11-26 10:48:03,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2023-11-26 10:48:03,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4717722140402554) internal successors, (2998), 2036 states have internal predecessors, (2998), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:03,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 2998 transitions. [2023-11-26 10:48:03,735 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 2998 transitions. [2023-11-26 10:48:03,735 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:03,736 INFO L428 stractBuchiCegarLoop]: Abstraction has 2037 states and 2998 transitions. [2023-11-26 10:48:03,737 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 10:48:03,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 2998 transitions. [2023-11-26 10:48:03,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2023-11-26 10:48:03,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:03,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:03,750 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:03,750 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:03,751 INFO L748 eck$LassoCheckResult]: Stem: 53363#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53364#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 54357#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54358#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55093#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 54485#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53954#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53955#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54759#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54760#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54864#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54865#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53703#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53704#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54899#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54255#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54256#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54805#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 54169#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54170#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 55094#L1291-2 assume !(0 == ~T1_E~0); 55091#L1296-1 assume !(0 == ~T2_E~0); 54319#L1301-1 assume !(0 == ~T3_E~0); 54320#L1306-1 assume !(0 == ~T4_E~0); 54815#L1311-1 assume !(0 == ~T5_E~0); 53540#L1316-1 assume !(0 == ~T6_E~0); 53541#L1321-1 assume !(0 == ~T7_E~0); 54333#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53360#L1331-1 assume !(0 == ~T9_E~0); 53073#L1336-1 assume !(0 == ~T10_E~0); 53074#L1341-1 assume !(0 == ~T11_E~0); 53147#L1346-1 assume !(0 == ~T12_E~0); 53148#L1351-1 assume !(0 == ~T13_E~0); 53477#L1356-1 assume !(0 == ~E_M~0); 53478#L1361-1 assume !(0 == ~E_1~0); 55031#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 53524#L1371-1 assume !(0 == ~E_3~0); 53525#L1376-1 assume !(0 == ~E_4~0); 54385#L1381-1 assume !(0 == ~E_5~0); 54386#L1386-1 assume !(0 == ~E_6~0); 55062#L1391-1 assume !(0 == ~E_7~0); 55082#L1396-1 assume !(0 == ~E_8~0); 54287#L1401-1 assume !(0 == ~E_9~0); 54288#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 54575#L1411-1 assume !(0 == ~E_11~0); 54576#L1416-1 assume !(0 == ~E_12~0); 54205#L1421-1 assume !(0 == ~E_13~0); 53724#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53725#L640 assume !(1 == ~m_pc~0); 54254#L640-2 is_master_triggered_~__retres1~0#1 := 0; 54253#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54213#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54214#L1603 assume !(0 != activate_threads_~tmp~1#1); 54242#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53874#L659 assume 1 == ~t1_pc~0; 53875#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53983#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54696#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54005#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 54006#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54022#L678 assume 1 == ~t2_pc~0; 54968#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54969#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53567#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53568#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 54116#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54235#L697 assume !(1 == ~t3_pc~0); 54236#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54366#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54686#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54149#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54150#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55001#L716 assume 1 == ~t4_pc~0; 54989#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53854#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53220#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53221#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 53328#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54650#L735 assume !(1 == ~t5_pc~0); 53295#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 53296#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53751#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54676#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 54313#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54314#L754 assume 1 == ~t6_pc~0; 54067#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53967#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53544#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53545#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 53941#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54750#L773 assume !(1 == ~t7_pc~0); 53481#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53480#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54348#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54323#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 54324#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54377#L792 assume 1 == ~t8_pc~0; 54545#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54866#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54867#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54315#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 54238#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54239#L811 assume 1 == ~t9_pc~0; 54448#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54913#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53623#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53624#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 54250#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54251#L830 assume !(1 == ~t10_pc~0); 53976#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53457#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53458#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53435#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53436#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54768#L849 assume 1 == ~t11_pc~0; 54769#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53274#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53275#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54779#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 54680#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54681#L868 assume !(1 == ~t12_pc~0); 54100#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 54099#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53162#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53163#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 53492#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53493#L887 assume 1 == ~t13_pc~0; 54688#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54143#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54144#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54744#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 53202#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53203#L1439 assume !(1 == ~M_E~0); 54307#L1439-2 assume !(1 == ~T1_E~0); 53373#L1444-1 assume !(1 == ~T2_E~0); 53374#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53879#L1454-1 assume !(1 == ~T4_E~0); 53880#L1459-1 assume !(1 == ~T5_E~0); 54440#L1464-1 assume !(1 == ~T6_E~0); 54441#L1469-1 assume !(1 == ~T7_E~0); 54514#L1474-1 assume !(1 == ~T8_E~0); 54206#L1479-1 assume !(1 == ~T9_E~0); 54207#L1484-1 assume !(1 == ~T10_E~0); 54444#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54089#L1494-1 assume !(1 == ~T12_E~0); 54090#L1499-1 assume !(1 == ~T13_E~0); 54272#L1504-1 assume !(1 == ~E_M~0); 54273#L1509-1 assume !(1 == ~E_1~0); 54851#L1514-1 assume !(1 == ~E_2~0); 54547#L1519-1 assume !(1 == ~E_3~0); 54548#L1524-1 assume !(1 == ~E_4~0); 55046#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 55047#L1534-1 assume !(1 == ~E_6~0); 53196#L1539-1 assume !(1 == ~E_7~0); 53197#L1544-1 assume !(1 == ~E_8~0); 53620#L1549-1 assume !(1 == ~E_9~0); 55019#L1554-1 assume !(1 == ~E_10~0); 55016#L1559-1 assume !(1 == ~E_11~0); 54891#L1564-1 assume !(1 == ~E_12~0); 54892#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 55041#L1574-1 assume { :end_inline_reset_delta_events } true; 53371#L1940-2 [2023-11-26 10:48:03,752 INFO L750 eck$LassoCheckResult]: Loop: 53371#L1940-2 assume !false; 53372#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53915#L1266-1 assume !false; 55085#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53936#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53650#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54850#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 54859#L1079 assume !(0 != eval_~tmp~0#1); 54133#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53788#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53789#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54515#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54516#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55072#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55027#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54173#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53409#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53410#L1321-3 assume !(0 == ~T7_E~0); 53514#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 54302#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54553#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54554#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53871#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 53848#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53786#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53787#L1361-3 assume !(0 == ~E_1~0); 54367#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53125#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53126#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54871#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54730#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54731#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54905#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54906#L1401-3 assume !(0 == ~E_9~0); 53472#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53336#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 53337#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 54030#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54031#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54138#L640-45 assume !(1 == ~m_pc~0); 54139#L640-47 is_master_triggered_~__retres1~0#1 := 0; 53580#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53581#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53121#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 53122#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53210#L659-45 assume 1 == ~t1_pc~0; 53211#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53664#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55076#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55006#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54659#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54660#L678-45 assume 1 == ~t2_pc~0; 54611#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54145#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54146#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54593#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54922#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55025#L697-45 assume 1 == ~t3_pc~0; 54406#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54407#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55092#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54559#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54560#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54594#L716-45 assume 1 == ~t4_pc~0; 54218#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54220#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54877#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54225#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54226#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53889#L735-45 assume 1 == ~t5_pc~0; 53890#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54438#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55043#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55089#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 55045#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55039#L754-45 assume 1 == ~t6_pc~0; 54389#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54390#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54283#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54284#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54394#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54121#L773-45 assume 1 == ~t7_pc~0; 54122#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53661#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54355#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54356#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54129#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53780#L792-45 assume 1 == ~t8_pc~0; 53781#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54809#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54810#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53231#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53232#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53730#L811-45 assume 1 == ~t9_pc~0; 53507#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53508#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54727#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54590#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 54197#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53988#L830-45 assume 1 == ~t10_pc~0; 53989#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53158#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54306#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53382#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53383#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53141#L849-45 assume !(1 == ~t11_pc~0); 53142#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53598#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53439#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53127#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 53128#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53377#L868-45 assume 1 == ~t12_pc~0; 53378#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 53321#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53322#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54762#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54935#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54936#L887-45 assume !(1 == ~t13_pc~0); 53384#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 53385#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54690#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54709#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 53351#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53352#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54685#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53369#L1444-3 assume !(1 == ~T2_E~0); 53370#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53528#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54496#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54497#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54937#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54874#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54875#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54939#L1484-3 assume !(1 == ~T10_E~0); 54179#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54180#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 54802#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54455#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54456#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54887#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54923#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54096#L1524-3 assume !(1 == ~E_4~0); 54097#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54961#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54374#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53831#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53832#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54337#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53416#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53417#L1564-3 assume !(1 == ~E_12~0); 54595#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54596#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53308#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53082#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53408#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 53315#L1959 assume !(0 == start_simulation_~tmp~3#1); 53317#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53347#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53301#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53136#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 53137#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54955#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54930#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 54931#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 53371#L1940-2 [2023-11-26 10:48:03,752 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:03,753 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2023-11-26 10:48:03,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:03,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286100179] [2023-11-26 10:48:03,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:03,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:03,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:03,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:03,895 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:03,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1286100179] [2023-11-26 10:48:03,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1286100179] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:03,896 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:03,896 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:48:03,896 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1850128781] [2023-11-26 10:48:03,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:03,899 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:03,900 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:03,900 INFO L85 PathProgramCache]: Analyzing trace with hash -291836997, now seen corresponding path program 3 times [2023-11-26 10:48:03,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:03,900 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [626870400] [2023-11-26 10:48:03,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:03,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:03,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:03,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:03,973 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:03,973 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [626870400] [2023-11-26 10:48:03,973 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [626870400] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:03,973 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:03,973 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:03,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [286771070] [2023-11-26 10:48:03,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:03,975 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:03,975 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:03,975 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:03,976 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:03,976 INFO L87 Difference]: Start difference. First operand 2037 states and 2998 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:04,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:04,129 INFO L93 Difference]: Finished difference Result 3799 states and 5574 transitions. [2023-11-26 10:48:04,129 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3799 states and 5574 transitions. [2023-11-26 10:48:04,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3624 [2023-11-26 10:48:04,167 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3799 states to 3799 states and 5574 transitions. [2023-11-26 10:48:04,168 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3799 [2023-11-26 10:48:04,172 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3799 [2023-11-26 10:48:04,172 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3799 states and 5574 transitions. [2023-11-26 10:48:04,178 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:04,178 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3799 states and 5574 transitions. [2023-11-26 10:48:04,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3799 states and 5574 transitions. [2023-11-26 10:48:04,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3799 to 3799. [2023-11-26 10:48:04,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3799 states, 3799 states have (on average 1.4672282179520926) internal successors, (5574), 3798 states have internal predecessors, (5574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:04,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3799 states to 3799 states and 5574 transitions. [2023-11-26 10:48:04,267 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3799 states and 5574 transitions. [2023-11-26 10:48:04,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:04,268 INFO L428 stractBuchiCegarLoop]: Abstraction has 3799 states and 5574 transitions. [2023-11-26 10:48:04,269 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 10:48:04,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3799 states and 5574 transitions. [2023-11-26 10:48:04,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3624 [2023-11-26 10:48:04,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:04,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:04,289 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:04,289 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:04,289 INFO L748 eck$LassoCheckResult]: Stem: 59206#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 59207#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 60206#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60207#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60959#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 60333#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59798#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59799#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60612#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60613#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60719#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60720#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59549#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59550#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60754#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 60102#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 60103#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 60659#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 60017#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60018#L1291 assume !(0 == ~M_E~0); 60960#L1291-2 assume !(0 == ~T1_E~0); 60957#L1296-1 assume !(0 == ~T2_E~0); 60166#L1301-1 assume !(0 == ~T3_E~0); 60167#L1306-1 assume !(0 == ~T4_E~0); 60669#L1311-1 assume !(0 == ~T5_E~0); 59383#L1316-1 assume !(0 == ~T6_E~0); 59384#L1321-1 assume !(0 == ~T7_E~0); 60180#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59203#L1331-1 assume !(0 == ~T9_E~0); 58916#L1336-1 assume !(0 == ~T10_E~0); 58917#L1341-1 assume !(0 == ~T11_E~0); 58990#L1346-1 assume !(0 == ~T12_E~0); 58991#L1351-1 assume !(0 == ~T13_E~0); 59320#L1356-1 assume !(0 == ~E_M~0); 59321#L1361-1 assume !(0 == ~E_1~0); 60890#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 59367#L1371-1 assume !(0 == ~E_3~0); 59368#L1376-1 assume !(0 == ~E_4~0); 60233#L1381-1 assume !(0 == ~E_5~0); 60234#L1386-1 assume !(0 == ~E_6~0); 60925#L1391-1 assume !(0 == ~E_7~0); 60948#L1396-1 assume !(0 == ~E_8~0); 60134#L1401-1 assume !(0 == ~E_9~0); 60135#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 60423#L1411-1 assume !(0 == ~E_11~0); 60424#L1416-1 assume !(0 == ~E_12~0); 60052#L1421-1 assume !(0 == ~E_13~0); 59569#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59570#L640 assume !(1 == ~m_pc~0); 60101#L640-2 is_master_triggered_~__retres1~0#1 := 0; 60100#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60060#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60061#L1603 assume !(0 != activate_threads_~tmp~1#1); 60089#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59717#L659 assume 1 == ~t1_pc~0; 59718#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59828#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60545#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59850#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 59851#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59867#L678 assume 1 == ~t2_pc~0; 60826#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60827#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59410#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59411#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 59963#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60084#L697 assume !(1 == ~t3_pc~0); 60085#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 60214#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60535#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59996#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59997#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60859#L716 assume 1 == ~t4_pc~0; 60847#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59699#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59065#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59066#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 59171#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60500#L735 assume !(1 == ~t5_pc~0); 59138#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 59139#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59594#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60525#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 60160#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60161#L754 assume 1 == ~t6_pc~0; 59914#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59812#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59387#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59388#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 59785#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60603#L773 assume !(1 == ~t7_pc~0); 59324#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 59323#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60195#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60170#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 60171#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60225#L792 assume 1 == ~t8_pc~0; 60394#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60721#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60722#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60164#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 60087#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60088#L811 assume 1 == ~t9_pc~0; 60297#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60768#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59466#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59467#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 60097#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60098#L830 assume !(1 == ~t10_pc~0); 59823#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 59300#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59301#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59278#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59279#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60620#L849 assume 1 == ~t11_pc~0; 60621#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59117#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59118#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60631#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 60531#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60532#L868 assume !(1 == ~t12_pc~0); 59947#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 59946#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 59005#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59006#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 59335#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 59336#L887 assume 1 == ~t13_pc~0; 60537#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59990#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59991#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60594#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 59045#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59046#L1439 assume !(1 == ~M_E~0); 60156#L1439-2 assume !(1 == ~T1_E~0); 59216#L1444-1 assume !(1 == ~T2_E~0); 59217#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59723#L1454-1 assume !(1 == ~T4_E~0); 59724#L1459-1 assume !(1 == ~T5_E~0); 60289#L1464-1 assume !(1 == ~T6_E~0); 60290#L1469-1 assume !(1 == ~T7_E~0); 60362#L1474-1 assume !(1 == ~T8_E~0); 60053#L1479-1 assume !(1 == ~T9_E~0); 60054#L1484-1 assume !(1 == ~T10_E~0); 60292#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59938#L1494-1 assume !(1 == ~T12_E~0); 59939#L1499-1 assume !(1 == ~T13_E~0); 60119#L1504-1 assume !(1 == ~E_M~0); 60120#L1509-1 assume !(1 == ~E_1~0); 60706#L1514-1 assume !(1 == ~E_2~0); 60396#L1519-1 assume !(1 == ~E_3~0); 60397#L1524-1 assume !(1 == ~E_4~0); 60909#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60910#L1534-1 assume !(1 == ~E_6~0); 59039#L1539-1 assume !(1 == ~E_7~0); 59040#L1544-1 assume !(1 == ~E_8~0); 59465#L1549-1 assume !(1 == ~E_9~0); 60881#L1554-1 assume !(1 == ~E_10~0); 60875#L1559-1 assume !(1 == ~E_11~0); 60746#L1564-1 assume !(1 == ~E_12~0); 60747#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 60901#L1574-1 assume { :end_inline_reset_delta_events } true; 60934#L1940-2 [2023-11-26 10:48:04,290 INFO L750 eck$LassoCheckResult]: Loop: 60934#L1940-2 assume !false; 61001#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60997#L1266-1 assume !false; 60964#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59780#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 59494#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60705#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 60714#L1079 assume !(0 != eval_~tmp~0#1); 59980#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59631#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59632#L1291-3 assume !(0 == ~M_E~0); 60478#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62389#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62388#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62387#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62386#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62385#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62384#L1321-3 assume !(0 == ~T7_E~0); 62383#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62382#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62381#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 62380#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 62379#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 62378#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 62377#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62376#L1361-3 assume !(0 == ~E_1~0); 62375#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62374#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62373#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62372#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62371#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62370#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62369#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62368#L1401-3 assume !(0 == ~E_9~0); 62367#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 62366#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62365#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 62364#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 62363#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62362#L640-45 assume 1 == ~m_pc~0; 62360#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62359#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62358#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62357#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 60961#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59053#L659-45 assume 1 == ~t1_pc~0; 59054#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59506#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60942#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60864#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60508#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60509#L678-45 assume 1 == ~t2_pc~0; 60459#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59992#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59993#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60441#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60777#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60883#L697-45 assume !(1 == ~t3_pc~0); 60256#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 60255#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60958#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60407#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60408#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60442#L716-45 assume 1 == ~t4_pc~0; 60065#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 60067#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60732#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60072#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60073#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59732#L735-45 assume 1 == ~t5_pc~0; 59733#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 60286#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60903#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60955#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 60907#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60899#L754-45 assume 1 == ~t6_pc~0; 60237#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 60238#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60130#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 60131#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 60242#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59968#L773-45 assume 1 == ~t7_pc~0; 59969#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59504#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60203#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60204#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 59976#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59623#L792-45 assume 1 == ~t8_pc~0; 59624#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60663#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60664#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59074#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 59075#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59573#L811-45 assume 1 == ~t9_pc~0; 59347#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59348#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60577#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 60438#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 60044#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59833#L830-45 assume !(1 == ~t10_pc~0); 59000#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 59001#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60153#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59225#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59226#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58984#L849-45 assume !(1 == ~t11_pc~0); 58985#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 59441#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59282#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58970#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58971#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59220#L868-45 assume 1 == ~t12_pc~0; 59221#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 59164#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 59165#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 60614#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 60790#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60791#L887-45 assume 1 == ~t13_pc~0; 60615#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59228#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60539#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60559#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 59194#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59195#L1439-3 assume !(1 == ~M_E~0); 60550#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62521#L1444-3 assume !(1 == ~T2_E~0); 62520#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62519#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62518#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62517#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62516#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62515#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 62514#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62513#L1484-3 assume !(1 == ~T10_E~0); 62512#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 62511#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 62510#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 62509#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 62508#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62507#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62506#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62505#L1524-3 assume !(1 == ~E_4~0); 62504#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62503#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62502#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 62501#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 62500#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 60183#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 59259#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 59260#L1564-3 assume !(1 == ~E_12~0); 60670#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 60647#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 60648#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61481#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61478#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 61476#L1959 assume !(0 == start_simulation_~tmp~3#1); 61473#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 61058#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61049#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61047#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 61045#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 61030#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 61019#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 61012#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 60934#L1940-2 [2023-11-26 10:48:04,291 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:04,291 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2023-11-26 10:48:04,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:04,292 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405533879] [2023-11-26 10:48:04,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:04,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:04,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:04,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:04,388 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:04,388 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405533879] [2023-11-26 10:48:04,388 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [405533879] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:04,388 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:04,389 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:04,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336559584] [2023-11-26 10:48:04,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:04,389 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:04,390 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:04,390 INFO L85 PathProgramCache]: Analyzing trace with hash 647178235, now seen corresponding path program 1 times [2023-11-26 10:48:04,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:04,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1551009532] [2023-11-26 10:48:04,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:04,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:04,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:04,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:04,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:04,473 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1551009532] [2023-11-26 10:48:04,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1551009532] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:04,474 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:04,474 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:04,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [247289664] [2023-11-26 10:48:04,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:04,475 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:04,475 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:04,475 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:48:04,475 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:48:04,476 INFO L87 Difference]: Start difference. First operand 3799 states and 5574 transitions. cyclomatic complexity: 1776 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:04,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:04,679 INFO L93 Difference]: Finished difference Result 5553 states and 8132 transitions. [2023-11-26 10:48:04,679 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5553 states and 8132 transitions. [2023-11-26 10:48:04,715 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5358 [2023-11-26 10:48:04,739 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5553 states to 5553 states and 8132 transitions. [2023-11-26 10:48:04,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5553 [2023-11-26 10:48:04,746 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5553 [2023-11-26 10:48:04,746 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5553 states and 8132 transitions. [2023-11-26 10:48:04,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:04,755 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5553 states and 8132 transitions. [2023-11-26 10:48:04,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5553 states and 8132 transitions. [2023-11-26 10:48:04,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5553 to 3799. [2023-11-26 10:48:04,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3799 states, 3799 states have (on average 1.4664385364569623) internal successors, (5571), 3798 states have internal predecessors, (5571), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:04,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3799 states to 3799 states and 5571 transitions. [2023-11-26 10:48:04,870 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3799 states and 5571 transitions. [2023-11-26 10:48:04,870 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:48:04,871 INFO L428 stractBuchiCegarLoop]: Abstraction has 3799 states and 5571 transitions. [2023-11-26 10:48:04,871 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 10:48:04,871 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3799 states and 5571 transitions. [2023-11-26 10:48:04,891 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3624 [2023-11-26 10:48:04,891 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:04,892 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:04,896 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:04,896 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:04,897 INFO L748 eck$LassoCheckResult]: Stem: 68568#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 68569#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 69564#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69565#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 70302#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 69691#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69159#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69160#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69966#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69967#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 70071#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 70072#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68911#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68912#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 70106#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 69461#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 69462#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 70011#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 69376#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69377#L1291 assume !(0 == ~M_E~0); 70303#L1291-2 assume !(0 == ~T1_E~0); 70300#L1296-1 assume !(0 == ~T2_E~0); 69525#L1301-1 assume !(0 == ~T3_E~0); 69526#L1306-1 assume !(0 == ~T4_E~0); 70021#L1311-1 assume !(0 == ~T5_E~0); 68745#L1316-1 assume !(0 == ~T6_E~0); 68746#L1321-1 assume !(0 == ~T7_E~0); 69539#L1326-1 assume !(0 == ~T8_E~0); 68565#L1331-1 assume !(0 == ~T9_E~0); 68278#L1336-1 assume !(0 == ~T10_E~0); 68279#L1341-1 assume !(0 == ~T11_E~0); 68352#L1346-1 assume !(0 == ~T12_E~0); 68353#L1351-1 assume !(0 == ~T13_E~0); 68682#L1356-1 assume !(0 == ~E_M~0); 68683#L1361-1 assume !(0 == ~E_1~0); 70240#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 68729#L1371-1 assume !(0 == ~E_3~0); 68730#L1376-1 assume !(0 == ~E_4~0); 69591#L1381-1 assume !(0 == ~E_5~0); 69592#L1386-1 assume !(0 == ~E_6~0); 70271#L1391-1 assume !(0 == ~E_7~0); 70291#L1396-1 assume !(0 == ~E_8~0); 69493#L1401-1 assume !(0 == ~E_9~0); 69494#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 69781#L1411-1 assume !(0 == ~E_11~0); 69782#L1416-1 assume !(0 == ~E_12~0); 69411#L1421-1 assume !(0 == ~E_13~0); 68933#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68934#L640 assume !(1 == ~m_pc~0); 69460#L640-2 is_master_triggered_~__retres1~0#1 := 0; 69459#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69419#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69420#L1603 assume !(0 != activate_threads_~tmp~1#1); 69448#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69079#L659 assume 1 == ~t1_pc~0; 69080#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 69189#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69902#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69211#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 69212#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69228#L678 assume 1 == ~t2_pc~0; 70175#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 70176#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68772#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68773#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 69322#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69443#L697 assume !(1 == ~t3_pc~0); 69444#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69572#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69892#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69355#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69356#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70209#L716 assume 1 == ~t4_pc~0; 70197#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 69061#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68427#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68428#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 68533#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69857#L735 assume !(1 == ~t5_pc~0); 68500#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 68501#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68956#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69882#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 69519#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69520#L754 assume 1 == ~t6_pc~0; 69275#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69173#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68749#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68750#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 69146#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69957#L773 assume !(1 == ~t7_pc~0); 68686#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68685#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69554#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69529#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 69530#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69583#L792 assume 1 == ~t8_pc~0; 69752#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 70073#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70074#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69523#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 69446#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69447#L811 assume 1 == ~t9_pc~0; 69655#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 70120#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68828#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 68829#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 69456#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69457#L830 assume !(1 == ~t10_pc~0); 69184#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 68662#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 68663#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68640#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68641#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69974#L849 assume 1 == ~t11_pc~0; 69975#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68479#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68480#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69985#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 69888#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69889#L868 assume !(1 == ~t12_pc~0); 69306#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 69305#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68367#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 68368#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 68697#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 68698#L887 assume 1 == ~t13_pc~0; 69894#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 69349#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69350#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 69950#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 68407#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68408#L1439 assume !(1 == ~M_E~0); 69515#L1439-2 assume !(1 == ~T1_E~0); 68578#L1444-1 assume !(1 == ~T2_E~0); 68579#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69085#L1454-1 assume !(1 == ~T4_E~0); 69086#L1459-1 assume !(1 == ~T5_E~0); 69647#L1464-1 assume !(1 == ~T6_E~0); 69648#L1469-1 assume !(1 == ~T7_E~0); 69723#L1474-1 assume !(1 == ~T8_E~0); 69412#L1479-1 assume !(1 == ~T9_E~0); 69413#L1484-1 assume !(1 == ~T10_E~0); 69650#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69297#L1494-1 assume !(1 == ~T12_E~0); 69298#L1499-1 assume !(1 == ~T13_E~0); 69478#L1504-1 assume !(1 == ~E_M~0); 69479#L1509-1 assume !(1 == ~E_1~0); 70057#L1514-1 assume !(1 == ~E_2~0); 69754#L1519-1 assume !(1 == ~E_3~0); 69755#L1524-1 assume !(1 == ~E_4~0); 70255#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 70256#L1534-1 assume !(1 == ~E_6~0); 68401#L1539-1 assume !(1 == ~E_7~0); 68402#L1544-1 assume !(1 == ~E_8~0); 68827#L1549-1 assume !(1 == ~E_9~0); 70232#L1554-1 assume !(1 == ~E_10~0); 70226#L1559-1 assume !(1 == ~E_11~0); 70098#L1564-1 assume !(1 == ~E_12~0); 70099#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 70250#L1574-1 assume { :end_inline_reset_delta_events } true; 68576#L1940-2 [2023-11-26 10:48:04,898 INFO L750 eck$LassoCheckResult]: Loop: 68576#L1940-2 assume !false; 68577#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69120#L1266-1 assume !false; 70294#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69141#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68856#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 70056#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 70065#L1079 assume !(0 != eval_~tmp~0#1); 69339#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68993#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68994#L1291-3 assume !(0 == ~M_E~0); 69720#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69721#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70281#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70236#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69379#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68614#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68615#L1321-3 assume !(0 == ~T7_E~0); 68719#L1326-3 assume !(0 == ~T8_E~0); 69508#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69759#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 69760#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 69076#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 69053#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 68991#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 68992#L1361-3 assume !(0 == ~E_1~0); 69573#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68330#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 68331#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 70078#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69936#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 69937#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 70112#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 70113#L1401-3 assume !(0 == ~E_9~0); 68679#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 68541#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 68542#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 69236#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 69237#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69344#L640-45 assume !(1 == ~m_pc~0); 69345#L640-47 is_master_triggered_~__retres1~0#1 := 0; 68785#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68786#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68326#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 68327#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68415#L659-45 assume !(1 == ~t1_pc~0); 68417#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 68872#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70285#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70214#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 69865#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69866#L678-45 assume 1 == ~t2_pc~0; 69817#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69351#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69352#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69799#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70129#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70234#L697-45 assume 1 == ~t3_pc~0; 69612#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69613#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70301#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69765#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69766#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69800#L716-45 assume !(1 == ~t4_pc~0); 69425#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 69426#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70084#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69431#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69432#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69094#L735-45 assume 1 == ~t5_pc~0; 69095#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69644#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70252#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70298#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 70254#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70248#L754-45 assume 1 == ~t6_pc~0; 69595#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69596#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69489#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69490#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69600#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69328#L773-45 assume 1 == ~t7_pc~0; 69329#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68867#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69561#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69562#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 69335#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68984#L792-45 assume 1 == ~t8_pc~0; 68985#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 70015#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70016#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 68436#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68437#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68935#L811-45 assume 1 == ~t9_pc~0; 68709#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 68710#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69933#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69796#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 69403#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69194#L830-45 assume 1 == ~t10_pc~0; 69195#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 68363#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69512#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68587#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68588#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 68346#L849-45 assume !(1 == ~t11_pc~0); 68347#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 68803#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68642#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68332#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 68333#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68582#L868-45 assume 1 == ~t12_pc~0; 68583#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 68526#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68527#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69968#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 70142#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70143#L887-45 assume 1 == ~t13_pc~0; 69969#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68590#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69896#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 69915#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 68556#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68557#L1439-3 assume !(1 == ~M_E~0); 69891#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68574#L1444-3 assume !(1 == ~T2_E~0); 68575#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68733#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69702#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69703#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70144#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70081#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 70082#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70146#L1484-3 assume !(1 == ~T10_E~0); 69384#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69385#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 70008#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 69661#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69662#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70094#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70130#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69302#L1524-3 assume !(1 == ~E_4~0); 69303#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70168#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69580#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 69036#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 69037#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69542#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 68621#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 68622#L1564-3 assume !(1 == ~E_12~0); 69801#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 69802#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68513#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68287#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68610#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 68520#L1959 assume !(0 == start_simulation_~tmp~3#1); 68522#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68550#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68506#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68341#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 68342#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70161#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70136#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 70137#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 68576#L1940-2 [2023-11-26 10:48:04,899 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:04,899 INFO L85 PathProgramCache]: Analyzing trace with hash 1809696709, now seen corresponding path program 1 times [2023-11-26 10:48:04,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:04,899 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290123977] [2023-11-26 10:48:04,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:04,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:04,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:04,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:04,999 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:05,000 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290123977] [2023-11-26 10:48:05,000 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290123977] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:05,000 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:05,000 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:48:05,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1525432297] [2023-11-26 10:48:05,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:05,001 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:05,002 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:05,002 INFO L85 PathProgramCache]: Analyzing trace with hash 1930683898, now seen corresponding path program 1 times [2023-11-26 10:48:05,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:05,002 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530108962] [2023-11-26 10:48:05,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:05,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:05,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:05,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:05,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:05,075 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [530108962] [2023-11-26 10:48:05,075 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [530108962] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:05,075 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:05,075 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:05,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1794963016] [2023-11-26 10:48:05,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:05,076 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:05,076 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:05,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:05,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:05,077 INFO L87 Difference]: Start difference. First operand 3799 states and 5571 transitions. cyclomatic complexity: 1773 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:05,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:05,179 INFO L93 Difference]: Finished difference Result 3799 states and 5533 transitions. [2023-11-26 10:48:05,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3799 states and 5533 transitions. [2023-11-26 10:48:05,201 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3624 [2023-11-26 10:48:05,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3799 states to 3799 states and 5533 transitions. [2023-11-26 10:48:05,217 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3799 [2023-11-26 10:48:05,221 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3799 [2023-11-26 10:48:05,221 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3799 states and 5533 transitions. [2023-11-26 10:48:05,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:05,226 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3799 states and 5533 transitions. [2023-11-26 10:48:05,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3799 states and 5533 transitions. [2023-11-26 10:48:05,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3799 to 3799. [2023-11-26 10:48:05,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3799 states, 3799 states have (on average 1.4564359041853119) internal successors, (5533), 3798 states have internal predecessors, (5533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:05,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3799 states to 3799 states and 5533 transitions. [2023-11-26 10:48:05,302 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3799 states and 5533 transitions. [2023-11-26 10:48:05,302 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:05,304 INFO L428 stractBuchiCegarLoop]: Abstraction has 3799 states and 5533 transitions. [2023-11-26 10:48:05,304 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 10:48:05,304 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3799 states and 5533 transitions. [2023-11-26 10:48:05,320 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3624 [2023-11-26 10:48:05,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:05,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:05,323 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:05,324 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:05,324 INFO L748 eck$LassoCheckResult]: Stem: 76171#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 76172#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 77170#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77171#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77923#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 77297#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76762#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76763#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77574#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77575#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77679#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 77680#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76513#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76514#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77715#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77066#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 77067#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 77620#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 76982#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76983#L1291 assume !(0 == ~M_E~0); 77924#L1291-2 assume !(0 == ~T1_E~0); 77921#L1296-1 assume !(0 == ~T2_E~0); 77131#L1301-1 assume !(0 == ~T3_E~0); 77132#L1306-1 assume !(0 == ~T4_E~0); 77630#L1311-1 assume !(0 == ~T5_E~0); 76347#L1316-1 assume !(0 == ~T6_E~0); 76348#L1321-1 assume !(0 == ~T7_E~0); 77145#L1326-1 assume !(0 == ~T8_E~0); 76168#L1331-1 assume !(0 == ~T9_E~0); 75883#L1336-1 assume !(0 == ~T10_E~0); 75884#L1341-1 assume !(0 == ~T11_E~0); 75956#L1346-1 assume !(0 == ~T12_E~0); 75957#L1351-1 assume !(0 == ~T13_E~0); 76284#L1356-1 assume !(0 == ~E_M~0); 76285#L1361-1 assume !(0 == ~E_1~0); 77852#L1366-1 assume !(0 == ~E_2~0); 76331#L1371-1 assume !(0 == ~E_3~0); 76332#L1376-1 assume !(0 == ~E_4~0); 77197#L1381-1 assume !(0 == ~E_5~0); 77198#L1386-1 assume !(0 == ~E_6~0); 77886#L1391-1 assume !(0 == ~E_7~0); 77912#L1396-1 assume !(0 == ~E_8~0); 77098#L1401-1 assume !(0 == ~E_9~0); 77099#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 77388#L1411-1 assume !(0 == ~E_11~0); 77389#L1416-1 assume !(0 == ~E_12~0); 77017#L1421-1 assume !(0 == ~E_13~0); 76535#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76536#L640 assume !(1 == ~m_pc~0); 77065#L640-2 is_master_triggered_~__retres1~0#1 := 0; 77064#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77025#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77026#L1603 assume !(0 != activate_threads_~tmp~1#1); 77053#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76682#L659 assume 1 == ~t1_pc~0; 76683#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76792#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77509#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76814#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 76815#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76831#L678 assume !(1 == ~t2_pc~0); 77789#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 77883#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76374#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76375#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 76928#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77048#L697 assume !(1 == ~t3_pc~0); 77049#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77178#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77499#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76961#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76962#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77821#L716 assume 1 == ~t4_pc~0; 77808#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76664#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76031#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76032#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 76136#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77464#L735 assume !(1 == ~t5_pc~0); 76104#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 76105#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76558#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77489#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 77124#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77125#L754 assume 1 == ~t6_pc~0; 76878#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76776#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76351#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76352#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 76749#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77565#L773 assume !(1 == ~t7_pc~0); 76288#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 76287#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77160#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77135#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 77136#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77189#L792 assume 1 == ~t8_pc~0; 77359#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 77681#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77682#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 77128#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 77051#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77052#L811 assume 1 == ~t9_pc~0; 77261#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77729#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76430#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76431#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 77061#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77062#L830 assume !(1 == ~t10_pc~0); 76787#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76264#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76265#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76242#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 76243#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77582#L849 assume 1 == ~t11_pc~0; 77583#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 76083#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76084#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77594#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 77495#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77496#L868 assume !(1 == ~t12_pc~0); 76912#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 76911#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75971#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 75972#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 76299#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 76300#L887 assume 1 == ~t13_pc~0; 77501#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 76955#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76956#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 77558#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 76011#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76012#L1439 assume !(1 == ~M_E~0); 77120#L1439-2 assume !(1 == ~T1_E~0); 76181#L1444-1 assume !(1 == ~T2_E~0); 76182#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76688#L1454-1 assume !(1 == ~T4_E~0); 76689#L1459-1 assume !(1 == ~T5_E~0); 77253#L1464-1 assume !(1 == ~T6_E~0); 77254#L1469-1 assume !(1 == ~T7_E~0); 77329#L1474-1 assume !(1 == ~T8_E~0); 77018#L1479-1 assume !(1 == ~T9_E~0); 77019#L1484-1 assume !(1 == ~T10_E~0); 77256#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76903#L1494-1 assume !(1 == ~T12_E~0); 76904#L1499-1 assume !(1 == ~T13_E~0); 77083#L1504-1 assume !(1 == ~E_M~0); 77084#L1509-1 assume !(1 == ~E_1~0); 77666#L1514-1 assume !(1 == ~E_2~0); 77361#L1519-1 assume !(1 == ~E_3~0); 77362#L1524-1 assume !(1 == ~E_4~0); 77868#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 77869#L1534-1 assume !(1 == ~E_6~0); 76005#L1539-1 assume !(1 == ~E_7~0); 76006#L1544-1 assume !(1 == ~E_8~0); 76429#L1549-1 assume !(1 == ~E_9~0); 77844#L1554-1 assume !(1 == ~E_10~0); 77838#L1559-1 assume !(1 == ~E_11~0); 77707#L1564-1 assume !(1 == ~E_12~0); 77708#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 77862#L1574-1 assume { :end_inline_reset_delta_events } true; 76179#L1940-2 [2023-11-26 10:48:05,325 INFO L750 eck$LassoCheckResult]: Loop: 76179#L1940-2 assume !false; 76180#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76723#L1266-1 assume !false; 77915#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 76744#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76458#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77665#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 77674#L1079 assume !(0 != eval_~tmp~0#1); 76945#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76595#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76596#L1291-3 assume !(0 == ~M_E~0); 77326#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77327#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 77902#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77848#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76985#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 76216#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 76217#L1321-3 assume !(0 == ~T7_E~0); 76321#L1326-3 assume !(0 == ~T8_E~0); 77113#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 77366#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 77367#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 76679#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 76656#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 76593#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 76594#L1361-3 assume !(0 == ~E_1~0); 77179#L1366-3 assume !(0 == ~E_2~0); 75934#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 75935#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 77686#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 77544#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 77545#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 77721#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 77722#L1401-3 assume !(0 == ~E_9~0); 76279#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 76144#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 76145#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 76839#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 76840#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76950#L640-45 assume !(1 == ~m_pc~0); 76951#L640-47 is_master_triggered_~__retres1~0#1 := 0; 76387#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76388#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75930#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 75931#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76019#L659-45 assume !(1 == ~t1_pc~0); 76021#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 76474#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77906#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77827#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77472#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77473#L678-45 assume !(1 == ~t2_pc~0); 77426#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 76957#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76958#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77406#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77739#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77846#L697-45 assume 1 == ~t3_pc~0; 77218#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 77219#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77922#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77372#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77373#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77407#L716-45 assume !(1 == ~t4_pc~0); 77031#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 77032#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77693#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77036#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77037#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76697#L735-45 assume !(1 == ~t5_pc~0); 76699#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 77250#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77864#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77919#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 77866#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77860#L754-45 assume 1 == ~t6_pc~0; 77201#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77202#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77094#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77095#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 77206#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76934#L773-45 assume !(1 == ~t7_pc~0); 76468#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 76469#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77167#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77168#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 76941#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76587#L792-45 assume !(1 == ~t8_pc~0); 76589#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 77624#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77625#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76040#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 76041#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76537#L811-45 assume 1 == ~t9_pc~0; 76311#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76312#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77541#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77403#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 77009#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76796#L830-45 assume 1 == ~t10_pc~0; 76797#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 75967#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77117#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76190#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 76191#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 75947#L849-45 assume 1 == ~t11_pc~0; 75949#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 76405#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76244#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75936#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 75937#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76185#L868-45 assume !(1 == ~t12_pc~0); 76187#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 76129#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 76130#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 77576#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 77752#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 77753#L887-45 assume !(1 == ~t13_pc~0); 76192#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 76193#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 77503#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 77522#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 76159#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76160#L1439-3 assume !(1 == ~M_E~0); 77498#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 76177#L1444-3 assume !(1 == ~T2_E~0); 76178#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76335#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77308#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77309#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 77754#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77690#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 77691#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 77756#L1484-3 assume !(1 == ~T10_E~0); 76990#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76991#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 77617#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 77267#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 77268#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77703#L1514-3 assume !(1 == ~E_2~0); 77740#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 76908#L1524-3 assume !(1 == ~E_4~0); 76909#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77780#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77186#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 76639#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 76640#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 77148#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 76223#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 76224#L1564-3 assume !(1 == ~E_12~0); 77408#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 77409#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 76117#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 75892#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 76212#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 76123#L1959 assume !(0 == start_simulation_~tmp~3#1); 76125#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 76153#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76110#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 75945#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 75946#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77773#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77746#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 77747#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 76179#L1940-2 [2023-11-26 10:48:05,327 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:05,327 INFO L85 PathProgramCache]: Analyzing trace with hash 350046660, now seen corresponding path program 1 times [2023-11-26 10:48:05,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:05,327 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432292871] [2023-11-26 10:48:05,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:05,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:05,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:05,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:05,425 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:05,425 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432292871] [2023-11-26 10:48:05,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [432292871] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:05,426 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:05,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:05,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [151262058] [2023-11-26 10:48:05,426 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:05,427 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:05,427 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:05,427 INFO L85 PathProgramCache]: Analyzing trace with hash 741514239, now seen corresponding path program 1 times [2023-11-26 10:48:05,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:05,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013942982] [2023-11-26 10:48:05,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:05,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:05,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:05,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:05,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:05,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2013942982] [2023-11-26 10:48:05,531 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2013942982] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:05,531 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:05,531 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:05,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1622341448] [2023-11-26 10:48:05,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:05,532 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:05,532 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:05,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:48:05,533 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:48:05,533 INFO L87 Difference]: Start difference. First operand 3799 states and 5533 transitions. cyclomatic complexity: 1735 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:05,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:05,771 INFO L93 Difference]: Finished difference Result 5438 states and 7902 transitions. [2023-11-26 10:48:05,771 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5438 states and 7902 transitions. [2023-11-26 10:48:05,797 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5258 [2023-11-26 10:48:05,818 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5438 states to 5438 states and 7902 transitions. [2023-11-26 10:48:05,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5438 [2023-11-26 10:48:05,824 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5438 [2023-11-26 10:48:05,824 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5438 states and 7902 transitions. [2023-11-26 10:48:05,830 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:05,830 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5438 states and 7902 transitions. [2023-11-26 10:48:05,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5438 states and 7902 transitions. [2023-11-26 10:48:05,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5438 to 3799. [2023-11-26 10:48:05,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3799 states, 3799 states have (on average 1.4556462226901816) internal successors, (5530), 3798 states have internal predecessors, (5530), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:05,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3799 states to 3799 states and 5530 transitions. [2023-11-26 10:48:05,916 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3799 states and 5530 transitions. [2023-11-26 10:48:05,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:48:05,917 INFO L428 stractBuchiCegarLoop]: Abstraction has 3799 states and 5530 transitions. [2023-11-26 10:48:05,917 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 10:48:05,917 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3799 states and 5530 transitions. [2023-11-26 10:48:05,931 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3624 [2023-11-26 10:48:05,931 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:05,931 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:05,935 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:05,935 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:05,935 INFO L748 eck$LassoCheckResult]: Stem: 85418#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 85419#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 86416#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86417#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87178#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 86544#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86010#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86011#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86825#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86826#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86935#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86936#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85761#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85762#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 86970#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 86312#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 86313#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 86872#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 86228#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86229#L1291 assume !(0 == ~M_E~0); 87179#L1291-2 assume !(0 == ~T1_E~0); 87176#L1296-1 assume !(0 == ~T2_E~0); 86377#L1301-1 assume !(0 == ~T3_E~0); 86378#L1306-1 assume !(0 == ~T4_E~0); 86882#L1311-1 assume !(0 == ~T5_E~0); 85594#L1316-1 assume !(0 == ~T6_E~0); 85595#L1321-1 assume !(0 == ~T7_E~0); 86391#L1326-1 assume !(0 == ~T8_E~0); 85415#L1331-1 assume !(0 == ~T9_E~0); 85130#L1336-1 assume !(0 == ~T10_E~0); 85131#L1341-1 assume !(0 == ~T11_E~0); 85203#L1346-1 assume !(0 == ~T12_E~0); 85204#L1351-1 assume !(0 == ~T13_E~0); 85531#L1356-1 assume !(0 == ~E_M~0); 85532#L1361-1 assume !(0 == ~E_1~0); 87108#L1366-1 assume !(0 == ~E_2~0); 85578#L1371-1 assume !(0 == ~E_3~0); 85579#L1376-1 assume !(0 == ~E_4~0); 86444#L1381-1 assume !(0 == ~E_5~0); 86445#L1386-1 assume !(0 == ~E_6~0); 87142#L1391-1 assume !(0 == ~E_7~0); 87165#L1396-1 assume !(0 == ~E_8~0); 86344#L1401-1 assume !(0 == ~E_9~0); 86345#L1406-1 assume !(0 == ~E_10~0); 86638#L1411-1 assume !(0 == ~E_11~0); 86639#L1416-1 assume !(0 == ~E_12~0); 86263#L1421-1 assume !(0 == ~E_13~0); 85783#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85784#L640 assume !(1 == ~m_pc~0); 86311#L640-2 is_master_triggered_~__retres1~0#1 := 0; 86310#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86271#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86272#L1603 assume !(0 != activate_threads_~tmp~1#1); 86299#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85930#L659 assume 1 == ~t1_pc~0; 85931#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 86041#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86761#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86063#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 86064#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86080#L678 assume !(1 == ~t2_pc~0); 87043#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 87139#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85621#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 85622#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 86174#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86294#L697 assume !(1 == ~t3_pc~0); 86295#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86424#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86749#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86207#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86208#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87075#L716 assume 1 == ~t4_pc~0; 87063#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85912#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85278#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85279#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 85383#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86714#L735 assume !(1 == ~t5_pc~0); 85351#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 85352#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85806#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86739#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 86370#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86371#L754 assume 1 == ~t6_pc~0; 86127#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 86024#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85598#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85599#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 85997#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86816#L773 assume !(1 == ~t7_pc~0); 85535#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 85534#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86406#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86381#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 86382#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86436#L792 assume 1 == ~t8_pc~0; 86609#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 86937#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86938#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86374#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 86297#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86298#L811 assume 1 == ~t9_pc~0; 86508#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 86984#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85677#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85678#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 86307#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86308#L830 assume !(1 == ~t10_pc~0); 86035#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 85511#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85512#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85489#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85490#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86834#L849 assume 1 == ~t11_pc~0; 86835#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85330#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85331#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86846#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 86745#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86746#L868 assume !(1 == ~t12_pc~0); 86158#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 86157#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85218#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 85219#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 85546#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 85547#L887 assume 1 == ~t13_pc~0; 86751#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 86201#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86202#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86809#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 85258#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85259#L1439 assume !(1 == ~M_E~0); 86366#L1439-2 assume !(1 == ~T1_E~0); 85428#L1444-1 assume !(1 == ~T2_E~0); 85429#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85936#L1454-1 assume !(1 == ~T4_E~0); 85937#L1459-1 assume !(1 == ~T5_E~0); 86500#L1464-1 assume !(1 == ~T6_E~0); 86501#L1469-1 assume !(1 == ~T7_E~0); 86580#L1474-1 assume !(1 == ~T8_E~0); 86264#L1479-1 assume !(1 == ~T9_E~0); 86265#L1484-1 assume !(1 == ~T10_E~0); 86503#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86149#L1494-1 assume !(1 == ~T12_E~0); 86150#L1499-1 assume !(1 == ~T13_E~0); 86329#L1504-1 assume !(1 == ~E_M~0); 86330#L1509-1 assume !(1 == ~E_1~0); 86921#L1514-1 assume !(1 == ~E_2~0); 86611#L1519-1 assume !(1 == ~E_3~0); 86612#L1524-1 assume !(1 == ~E_4~0); 87125#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 87126#L1534-1 assume !(1 == ~E_6~0); 85252#L1539-1 assume !(1 == ~E_7~0); 85253#L1544-1 assume !(1 == ~E_8~0); 85676#L1549-1 assume !(1 == ~E_9~0); 87098#L1554-1 assume !(1 == ~E_10~0); 87092#L1559-1 assume !(1 == ~E_11~0); 86962#L1564-1 assume !(1 == ~E_12~0); 86963#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 87118#L1574-1 assume { :end_inline_reset_delta_events } true; 85426#L1940-2 [2023-11-26 10:48:05,936 INFO L750 eck$LassoCheckResult]: Loop: 85426#L1940-2 assume !false; 85427#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85971#L1266-1 assume !false; 87169#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85992#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85705#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86920#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 86929#L1079 assume !(0 != eval_~tmp~0#1); 86191#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85843#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 85844#L1291-3 assume !(0 == ~M_E~0); 86577#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 86578#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 87152#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87104#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 86231#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 85463#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 85464#L1321-3 assume !(0 == ~T7_E~0); 85568#L1326-3 assume !(0 == ~T8_E~0); 86359#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 86616#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 86617#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 85927#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 85904#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 85841#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 85842#L1361-3 assume !(0 == ~E_1~0); 86425#L1366-3 assume !(0 == ~E_2~0); 85181#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 85182#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 86942#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86795#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 86796#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 86976#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 86977#L1401-3 assume !(0 == ~E_9~0); 85528#L1406-3 assume !(0 == ~E_10~0); 85391#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 85392#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 86088#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 86089#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86196#L640-45 assume !(1 == ~m_pc~0); 86197#L640-47 is_master_triggered_~__retres1~0#1 := 0; 85634#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85635#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85177#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 85178#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85266#L659-45 assume 1 == ~t1_pc~0; 85267#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85721#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87156#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87080#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 86722#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86723#L678-45 assume !(1 == ~t2_pc~0); 86676#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 86203#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86204#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86656#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86993#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87100#L697-45 assume 1 == ~t3_pc~0; 86466#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 86467#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87177#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86622#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86623#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86657#L716-45 assume !(1 == ~t4_pc~0); 86277#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 86278#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86949#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86282#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 86283#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85945#L735-45 assume !(1 == ~t5_pc~0); 85947#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 86497#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87121#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 87174#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 87124#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87116#L754-45 assume 1 == ~t6_pc~0; 86448#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 86449#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86340#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86341#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86453#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86179#L773-45 assume !(1 == ~t7_pc~0); 85714#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 85715#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86413#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86414#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 86187#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85835#L792-45 assume !(1 == ~t8_pc~0); 85837#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 86876#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86877#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 85287#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 85288#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85785#L811-45 assume 1 == ~t9_pc~0; 85558#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85559#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86792#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 86653#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 86255#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86046#L830-45 assume !(1 == ~t10_pc~0); 85213#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 85214#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86363#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85437#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85438#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85197#L849-45 assume 1 == ~t11_pc~0; 85199#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85652#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85491#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 85183#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 85184#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 85432#L868-45 assume 1 == ~t12_pc~0; 85433#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 85376#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85377#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86828#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 87006#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 87007#L887-45 assume 1 == ~t13_pc~0; 86829#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85440#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86753#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86774#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 85406#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85407#L1439-3 assume !(1 == ~M_E~0); 86748#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 85424#L1444-3 assume !(1 == ~T2_E~0); 85425#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85582#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86556#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86557#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 87008#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86945#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86946#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 87010#L1484-3 assume !(1 == ~T10_E~0); 86236#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86237#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 86869#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 86514#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 86515#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 86958#L1514-3 assume !(1 == ~E_2~0); 86994#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86154#L1524-3 assume !(1 == ~E_4~0); 86155#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 87034#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86432#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 85887#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85888#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 86394#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 85470#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 85471#L1564-3 assume !(1 == ~E_12~0); 86658#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 86659#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85364#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85139#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85459#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 85370#L1959 assume !(0 == start_simulation_~tmp~3#1); 85372#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85400#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85357#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85192#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 85193#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 87028#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 87000#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 87001#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 85426#L1940-2 [2023-11-26 10:48:05,937 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:05,937 INFO L85 PathProgramCache]: Analyzing trace with hash -1492429054, now seen corresponding path program 1 times [2023-11-26 10:48:05,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:05,937 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130943681] [2023-11-26 10:48:05,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:05,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:05,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:06,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:06,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:06,028 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1130943681] [2023-11-26 10:48:06,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1130943681] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:06,029 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:06,029 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:48:06,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [270110117] [2023-11-26 10:48:06,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:06,030 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:06,030 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:06,030 INFO L85 PathProgramCache]: Analyzing trace with hash 1091666107, now seen corresponding path program 1 times [2023-11-26 10:48:06,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:06,031 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108640344] [2023-11-26 10:48:06,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:06,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:06,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:06,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:06,108 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:06,108 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [108640344] [2023-11-26 10:48:06,108 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [108640344] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:06,108 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:06,109 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:06,109 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [501364484] [2023-11-26 10:48:06,109 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:06,110 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:06,110 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:06,110 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:06,111 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:06,111 INFO L87 Difference]: Start difference. First operand 3799 states and 5530 transitions. cyclomatic complexity: 1732 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:06,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:06,285 INFO L93 Difference]: Finished difference Result 7191 states and 10414 transitions. [2023-11-26 10:48:06,285 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7191 states and 10414 transitions. [2023-11-26 10:48:06,321 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7013 [2023-11-26 10:48:06,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7191 states to 7191 states and 10414 transitions. [2023-11-26 10:48:06,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7191 [2023-11-26 10:48:06,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7191 [2023-11-26 10:48:06,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7191 states and 10414 transitions. [2023-11-26 10:48:06,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:06,366 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7191 states and 10414 transitions. [2023-11-26 10:48:06,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7191 states and 10414 transitions. [2023-11-26 10:48:06,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7191 to 7187. [2023-11-26 10:48:06,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7187 states, 7187 states have (on average 1.448448587727842) internal successors, (10410), 7186 states have internal predecessors, (10410), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:06,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7187 states to 7187 states and 10410 transitions. [2023-11-26 10:48:06,588 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7187 states and 10410 transitions. [2023-11-26 10:48:06,588 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:06,588 INFO L428 stractBuchiCegarLoop]: Abstraction has 7187 states and 10410 transitions. [2023-11-26 10:48:06,589 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 10:48:06,589 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7187 states and 10410 transitions. [2023-11-26 10:48:06,616 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7009 [2023-11-26 10:48:06,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:06,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:06,620 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:06,620 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:06,620 INFO L748 eck$LassoCheckResult]: Stem: 96415#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 96416#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 97448#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 97449#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 98498#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 97601#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97014#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97015#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97942#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 97943#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98106#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 98107#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96756#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 96757#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 98152#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97332#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 97333#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 98016#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 97237#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 97238#L1291 assume !(0 == ~M_E~0); 98500#L1291-2 assume !(0 == ~T1_E~0); 98493#L1296-1 assume !(0 == ~T2_E~0); 97402#L1301-1 assume !(0 == ~T3_E~0); 97403#L1306-1 assume !(0 == ~T4_E~0); 98035#L1311-1 assume !(0 == ~T5_E~0); 96592#L1316-1 assume !(0 == ~T6_E~0); 96593#L1321-1 assume !(0 == ~T7_E~0); 97418#L1326-1 assume !(0 == ~T8_E~0); 96412#L1331-1 assume !(0 == ~T9_E~0); 96127#L1336-1 assume !(0 == ~T10_E~0); 96128#L1341-1 assume !(0 == ~T11_E~0); 96200#L1346-1 assume !(0 == ~T12_E~0); 96201#L1351-1 assume !(0 == ~T13_E~0); 96528#L1356-1 assume !(0 == ~E_M~0); 96529#L1361-1 assume !(0 == ~E_1~0); 98374#L1366-1 assume !(0 == ~E_2~0); 96576#L1371-1 assume !(0 == ~E_3~0); 96577#L1376-1 assume !(0 == ~E_4~0); 97481#L1381-1 assume !(0 == ~E_5~0); 97482#L1386-1 assume !(0 == ~E_6~0); 98438#L1391-1 assume !(0 == ~E_7~0); 98468#L1396-1 assume !(0 == ~E_8~0); 97368#L1401-1 assume !(0 == ~E_9~0); 97369#L1406-1 assume !(0 == ~E_10~0); 97701#L1411-1 assume !(0 == ~E_11~0); 97702#L1416-1 assume !(0 == ~E_12~0); 97278#L1421-1 assume !(0 == ~E_13~0); 96777#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96778#L640 assume !(1 == ~m_pc~0); 97331#L640-2 is_master_triggered_~__retres1~0#1 := 0; 97330#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97286#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 97287#L1603 assume !(0 != activate_threads_~tmp~1#1); 97317#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96933#L659 assume !(1 == ~t1_pc~0); 96934#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 98221#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97858#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 97065#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 97066#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97082#L678 assume !(1 == ~t2_pc~0); 98260#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 98429#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96619#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96620#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 97183#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 97310#L697 assume !(1 == ~t3_pc~0); 97311#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 97459#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97844#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97217#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 97218#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98310#L716 assume 1 == ~t4_pc~0; 98289#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 96913#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96272#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96273#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 96380#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97795#L735 assume !(1 == ~t5_pc~0); 96348#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 96349#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96807#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 97829#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 97395#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 97396#L754 assume 1 == ~t6_pc~0; 97131#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 97028#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96596#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 96597#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 97001#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 97932#L773 assume !(1 == ~t7_pc~0); 96532#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 96531#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 97438#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 97406#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 97407#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 97471#L792 assume 1 == ~t8_pc~0; 97667#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 98108#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 98109#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 97397#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 97313#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 97314#L811 assume 1 == ~t9_pc~0; 97556#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 98166#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 96675#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 96676#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 97327#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97328#L830 assume !(1 == ~t10_pc~0); 97037#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 96508#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 96509#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 96487#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 96488#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 97956#L849 assume 1 == ~t11_pc~0; 97957#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 96327#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 96328#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 97975#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 97836#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 97837#L868 assume !(1 == ~t12_pc~0); 97167#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 97166#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 96215#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 96216#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 96543#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 96544#L887 assume 1 == ~t13_pc~0; 97847#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 97211#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 97212#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 97920#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 96255#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96256#L1439 assume !(1 == ~M_E~0); 97389#L1439-2 assume !(1 == ~T1_E~0); 96425#L1444-1 assume !(1 == ~T2_E~0); 96426#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 96937#L1454-1 assume !(1 == ~T4_E~0); 96938#L1459-1 assume !(1 == ~T5_E~0); 97548#L1464-1 assume !(1 == ~T6_E~0); 97549#L1469-1 assume !(1 == ~T7_E~0); 97633#L1474-1 assume !(1 == ~T8_E~0); 97279#L1479-1 assume !(1 == ~T9_E~0); 97280#L1484-1 assume !(1 == ~T10_E~0); 97552#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 97154#L1494-1 assume !(1 == ~T12_E~0); 97155#L1499-1 assume !(1 == ~T13_E~0); 97350#L1504-1 assume !(1 == ~E_M~0); 97351#L1509-1 assume !(1 == ~E_1~0); 98083#L1514-1 assume !(1 == ~E_2~0); 97669#L1519-1 assume !(1 == ~E_3~0); 97670#L1524-1 assume !(1 == ~E_4~0); 98405#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 98406#L1534-1 assume !(1 == ~E_6~0); 96249#L1539-1 assume !(1 == ~E_7~0); 96250#L1544-1 assume !(1 == ~E_8~0); 96672#L1549-1 assume !(1 == ~E_9~0); 98347#L1554-1 assume !(1 == ~E_10~0); 98345#L1559-1 assume !(1 == ~E_11~0); 98141#L1564-1 assume !(1 == ~E_12~0); 98142#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 98399#L1574-1 assume { :end_inline_reset_delta_events } true; 98445#L1940-2 [2023-11-26 10:48:06,621 INFO L750 eck$LassoCheckResult]: Loop: 98445#L1940-2 assume !false; 100333#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 100330#L1266-1 assume !false; 100329#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 100322#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 98081#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 98082#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 98093#L1079 assume !(0 != eval_~tmp~0#1); 97200#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 97201#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 97774#L1291-3 assume !(0 == ~M_E~0); 97634#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 97635#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 98457#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 98359#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 97242#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96460#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 96461#L1321-3 assume !(0 == ~T7_E~0); 96565#L1326-3 assume !(0 == ~T8_E~0); 97383#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 97676#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 97677#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 96930#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 96907#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 96843#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 96844#L1361-3 assume !(0 == ~E_1~0); 97460#L1366-3 assume !(0 == ~E_2~0); 96178#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 96179#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 98115#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 97906#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 97907#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 98158#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 98159#L1401-3 assume !(0 == ~E_9~0); 96523#L1406-3 assume !(0 == ~E_10~0); 96388#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 96389#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 97090#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 97091#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97206#L640-45 assume !(1 == ~m_pc~0); 97207#L640-47 is_master_triggered_~__retres1~0#1 := 0; 96632#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96633#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96174#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 96175#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96263#L659-45 assume !(1 == ~t1_pc~0); 96264#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 96718#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 98462#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 98320#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 97806#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97807#L678-45 assume !(1 == ~t2_pc~0); 97751#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 97213#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97214#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97728#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 98178#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98356#L697-45 assume 1 == ~t3_pc~0; 97505#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 97506#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98497#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97683#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 97684#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97731#L716-45 assume !(1 == ~t4_pc~0); 97293#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 97294#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98123#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 97298#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 97299#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96947#L735-45 assume !(1 == ~t5_pc~0); 96949#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 97545#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98401#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 98489#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 98403#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98393#L754-45 assume 1 == ~t6_pc~0; 97485#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 97486#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 97364#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 97365#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 97490#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 97188#L773-45 assume 1 == ~t7_pc~0; 97189#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 96713#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 97446#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 97447#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 97196#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96836#L792-45 assume 1 == ~t8_pc~0; 96837#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 98025#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 98026#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96284#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 96285#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96784#L811-45 assume !(1 == ~t9_pc~0); 96560#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 96559#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97898#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 97725#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 97269#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97270#L830-45 assume !(1 == ~t10_pc~0); 101037#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 101034#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 101032#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 101031#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 101030#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 101029#L849-45 assume !(1 == ~t11_pc~0); 101027#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 101024#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 101023#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 101022#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 101021#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 101019#L868-45 assume 1 == ~t12_pc~0; 101015#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 101013#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 101011#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 101009#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 101007#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 101005#L887-45 assume 1 == ~t13_pc~0; 101001#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 100998#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 97874#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 97875#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 98543#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97864#L1439-3 assume !(1 == ~M_E~0); 97865#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101604#L1444-3 assume !(1 == ~T2_E~0); 101603#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101602#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101601#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101600#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 101599#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 101598#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 101597#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 101596#L1484-3 assume !(1 == ~T10_E~0); 101595#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 101594#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 101593#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 101592#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 101591#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 101590#L1514-3 assume !(1 == ~E_2~0); 101589#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 101588#L1524-3 assume !(1 == ~E_4~0); 101587#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 101586#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 101585#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 101584#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 101583#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 101582#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 101581#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 101580#L1564-3 assume !(1 == ~E_12~0); 101579#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 101578#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 100371#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 100362#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 100361#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 100360#L1959 assume !(0 == start_simulation_~tmp~3#1); 100358#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 100347#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 100339#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 100338#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 100337#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 100336#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 100335#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 100334#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 98445#L1940-2 [2023-11-26 10:48:06,622 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:06,622 INFO L85 PathProgramCache]: Analyzing trace with hash -121367293, now seen corresponding path program 1 times [2023-11-26 10:48:06,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:06,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982553965] [2023-11-26 10:48:06,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:06,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:06,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:06,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:06,729 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:06,729 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982553965] [2023-11-26 10:48:06,729 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [982553965] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:06,729 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:06,730 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:48:06,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1455020191] [2023-11-26 10:48:06,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:06,731 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:06,731 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:06,732 INFO L85 PathProgramCache]: Analyzing trace with hash -77619972, now seen corresponding path program 1 times [2023-11-26 10:48:06,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:06,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150626754] [2023-11-26 10:48:06,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:06,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:06,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:06,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:06,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:06,805 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [150626754] [2023-11-26 10:48:06,805 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [150626754] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:06,805 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:06,805 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:06,806 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1921299654] [2023-11-26 10:48:06,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:06,807 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:06,808 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:06,808 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 10:48:06,808 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 10:48:06,808 INFO L87 Difference]: Start difference. First operand 7187 states and 10410 transitions. cyclomatic complexity: 3225 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:07,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:07,384 INFO L93 Difference]: Finished difference Result 18454 states and 26515 transitions. [2023-11-26 10:48:07,384 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18454 states and 26515 transitions. [2023-11-26 10:48:07,473 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18098 [2023-11-26 10:48:07,655 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18454 states to 18454 states and 26515 transitions. [2023-11-26 10:48:07,656 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18454 [2023-11-26 10:48:07,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18454 [2023-11-26 10:48:07,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18454 states and 26515 transitions. [2023-11-26 10:48:07,698 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:07,698 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18454 states and 26515 transitions. [2023-11-26 10:48:07,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18454 states and 26515 transitions. [2023-11-26 10:48:07,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18454 to 7370. [2023-11-26 10:48:07,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7370 states, 7370 states have (on average 1.4373134328358208) internal successors, (10593), 7369 states have internal predecessors, (10593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:07,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7370 states to 7370 states and 10593 transitions. [2023-11-26 10:48:07,891 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7370 states and 10593 transitions. [2023-11-26 10:48:07,891 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 10:48:07,892 INFO L428 stractBuchiCegarLoop]: Abstraction has 7370 states and 10593 transitions. [2023-11-26 10:48:07,892 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-26 10:48:07,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7370 states and 10593 transitions. [2023-11-26 10:48:07,917 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7189 [2023-11-26 10:48:07,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:07,918 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:07,921 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:07,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:07,922 INFO L748 eck$LassoCheckResult]: Stem: 122075#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 122076#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 123124#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 123125#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 124119#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 123275#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 122688#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122689#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 123587#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 123588#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 123730#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 123731#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 122427#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 122428#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 123774#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 123011#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 123012#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 123648#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 122920#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 122921#L1291 assume !(0 == ~M_E~0); 124120#L1291-2 assume !(0 == ~T1_E~0); 124117#L1296-1 assume !(0 == ~T2_E~0); 123081#L1301-1 assume !(0 == ~T3_E~0); 123082#L1306-1 assume !(0 == ~T4_E~0); 123663#L1311-1 assume !(0 == ~T5_E~0); 122260#L1316-1 assume !(0 == ~T6_E~0); 122261#L1321-1 assume !(0 == ~T7_E~0); 123097#L1326-1 assume !(0 == ~T8_E~0); 122072#L1331-1 assume !(0 == ~T9_E~0); 121781#L1336-1 assume !(0 == ~T10_E~0); 121782#L1341-1 assume !(0 == ~T11_E~0); 121854#L1346-1 assume !(0 == ~T12_E~0); 121855#L1351-1 assume !(0 == ~T13_E~0); 122192#L1356-1 assume !(0 == ~E_M~0); 122193#L1361-1 assume !(0 == ~E_1~0); 123982#L1366-1 assume !(0 == ~E_2~0); 122244#L1371-1 assume !(0 == ~E_3~0); 122245#L1376-1 assume !(0 == ~E_4~0); 123158#L1381-1 assume !(0 == ~E_5~0); 123159#L1386-1 assume !(0 == ~E_6~0); 124048#L1391-1 assume !(0 == ~E_7~0); 124086#L1396-1 assume !(0 == ~E_8~0); 123045#L1401-1 assume !(0 == ~E_9~0); 123046#L1406-1 assume !(0 == ~E_10~0); 123368#L1411-1 assume !(0 == ~E_11~0); 123369#L1416-1 assume !(0 == ~E_12~0); 122959#L1421-1 assume !(0 == ~E_13~0); 122448#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 122449#L640 assume !(1 == ~m_pc~0); 123010#L640-2 is_master_triggered_~__retres1~0#1 := 0; 123009#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122967#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 122968#L1603 assume !(0 != activate_threads_~tmp~1#1); 122998#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122604#L659 assume !(1 == ~t1_pc~0); 122605#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 123836#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123509#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 122740#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 122741#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122758#L678 assume !(1 == ~t2_pc~0); 123867#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 124040#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 122288#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 122289#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 122864#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122991#L697 assume !(1 == ~t3_pc~0); 122992#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 123137#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123891#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 122898#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 122899#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123917#L716 assume 1 == ~t4_pc~0; 123896#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 122582#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121929#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 121930#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 122039#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123456#L735 assume !(1 == ~t5_pc~0); 122005#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 122006#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 122477#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 123483#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 123074#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 123075#L754 assume 1 == ~t6_pc~0; 122811#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 122702#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 122264#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 122265#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 122672#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 123578#L773 assume !(1 == ~t7_pc~0); 122196#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 122195#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 123113#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 123085#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 123086#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 123149#L792 assume 1 == ~t8_pc~0; 123336#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 123732#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 123733#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 123076#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 122994#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 122995#L811 assume 1 == ~t9_pc~0; 123234#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 123789#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 122345#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 122346#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 123006#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 123007#L830 assume !(1 == ~t10_pc~0); 122711#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 122172#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 122173#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 122151#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 122152#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 123599#L849 assume 1 == ~t11_pc~0; 123600#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 121984#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 121985#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 123615#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 123489#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 123490#L868 assume !(1 == ~t12_pc~0); 122848#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 122847#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 121870#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 121871#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 122207#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 122208#L887 assume 1 == ~t13_pc~0; 123498#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 122892#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 122893#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 123570#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 121912#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 121913#L1439 assume !(1 == ~M_E~0); 123068#L1439-2 assume !(1 == ~T1_E~0); 122085#L1444-1 assume !(1 == ~T2_E~0); 122086#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 122608#L1454-1 assume !(1 == ~T4_E~0); 122609#L1459-1 assume !(1 == ~T5_E~0); 123225#L1464-1 assume !(1 == ~T6_E~0); 123226#L1469-1 assume !(1 == ~T7_E~0); 123305#L1474-1 assume !(1 == ~T8_E~0); 122960#L1479-1 assume !(1 == ~T9_E~0); 122961#L1484-1 assume !(1 == ~T10_E~0); 123229#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 122836#L1494-1 assume !(1 == ~T12_E~0); 122837#L1499-1 assume !(1 == ~T13_E~0); 123030#L1504-1 assume !(1 == ~E_M~0); 123031#L1509-1 assume !(1 == ~E_1~0); 123709#L1514-1 assume !(1 == ~E_2~0); 123338#L1519-1 assume !(1 == ~E_3~0); 123339#L1524-1 assume !(1 == ~E_4~0); 124021#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 124022#L1534-1 assume !(1 == ~E_6~0); 121905#L1539-1 assume !(1 == ~E_7~0); 121906#L1544-1 assume !(1 == ~E_8~0); 122342#L1549-1 assume !(1 == ~E_9~0); 123957#L1554-1 assume !(1 == ~E_10~0); 123952#L1559-1 assume !(1 == ~E_11~0); 123763#L1564-1 assume !(1 == ~E_12~0); 123764#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 124005#L1574-1 assume { :end_inline_reset_delta_events } true; 122083#L1940-2 [2023-11-26 10:48:07,923 INFO L750 eck$LassoCheckResult]: Loop: 122083#L1940-2 assume !false; 122084#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 122646#L1266-1 assume !false; 125188#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 122667#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 122372#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 125173#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 125170#L1079 assume !(0 != eval_~tmp~0#1); 125171#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 125750#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 125749#L1291-3 assume !(0 == ~M_E~0); 125748#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 125747#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 125746#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 125745#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 125744#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 125743#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 125742#L1321-3 assume !(0 == ~T7_E~0); 125741#L1326-3 assume !(0 == ~T8_E~0); 125740#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 125739#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 125738#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 125737#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 125736#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 125735#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 125734#L1361-3 assume !(0 == ~E_1~0); 125733#L1366-3 assume !(0 == ~E_2~0); 125732#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 125731#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 125730#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 125729#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 125728#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 125727#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 125726#L1401-3 assume !(0 == ~E_9~0); 125725#L1406-3 assume !(0 == ~E_10~0); 125724#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 125723#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 125722#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 125721#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 125720#L640-45 assume !(1 == ~m_pc~0); 125719#L640-47 is_master_triggered_~__retres1~0#1 := 0; 125717#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 125716#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 125715#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 125714#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125713#L659-45 assume !(1 == ~t1_pc~0); 125712#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 125711#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125710#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 125709#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 125708#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 125707#L678-45 assume !(1 == ~t2_pc~0); 125705#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 125703#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 125701#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 125698#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 125694#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 125693#L697-45 assume 1 == ~t3_pc~0; 125691#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 125689#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125687#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 125685#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 125682#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 125680#L716-45 assume !(1 == ~t4_pc~0); 125677#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 125675#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 125673#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 125671#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 125668#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 125666#L735-45 assume !(1 == ~t5_pc~0); 125664#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 125661#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 125659#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 125657#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 125654#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 125652#L754-45 assume !(1 == ~t6_pc~0); 125649#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 125647#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 125645#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 125643#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 125640#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 125638#L773-45 assume 1 == ~t7_pc~0; 125635#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 125633#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125631#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 125629#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 125626#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 125624#L792-45 assume !(1 == ~t8_pc~0); 125621#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 125619#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 125617#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 125615#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 125612#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 125610#L811-45 assume 1 == ~t9_pc~0; 125607#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 125605#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 125603#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 125601#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 125598#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 125596#L830-45 assume 1 == ~t10_pc~0; 125593#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 125591#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 125589#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 125587#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 125584#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 125582#L849-45 assume !(1 == ~t11_pc~0); 125579#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 125577#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 125575#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 125573#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 125570#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 125568#L868-45 assume 1 == ~t12_pc~0; 125565#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 125563#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 125561#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 125559#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 125556#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 125554#L887-45 assume 1 == ~t13_pc~0; 125552#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 125549#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 125548#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 125547#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 125546#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 125545#L1439-3 assume !(1 == ~M_E~0); 125537#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 125544#L1444-3 assume !(1 == ~T2_E~0); 125543#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 125542#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 125541#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 125540#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 125538#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 125535#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 125533#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 125531#L1484-3 assume !(1 == ~T10_E~0); 125529#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 125527#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 125525#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 125523#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 125521#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 125519#L1514-3 assume !(1 == ~E_2~0); 125517#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 125515#L1524-3 assume !(1 == ~E_4~0); 125513#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 125511#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 125509#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 124551#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 124550#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 124549#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 124537#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 124536#L1564-3 assume !(1 == ~E_12~0); 124535#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 124533#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 124534#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 122121#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 122122#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 122026#L1959 assume !(0 == start_simulation_~tmp~3#1); 122028#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 122058#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 122011#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 121843#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 121844#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 123843#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123812#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 123813#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 122083#L1940-2 [2023-11-26 10:48:07,923 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:07,924 INFO L85 PathProgramCache]: Analyzing trace with hash -2061949307, now seen corresponding path program 1 times [2023-11-26 10:48:07,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:07,924 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989821305] [2023-11-26 10:48:07,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:07,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:07,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:08,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:08,009 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:08,009 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [989821305] [2023-11-26 10:48:08,009 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [989821305] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:08,009 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:08,010 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:48:08,010 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1600815148] [2023-11-26 10:48:08,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:08,012 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:08,012 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:08,013 INFO L85 PathProgramCache]: Analyzing trace with hash -1728936644, now seen corresponding path program 1 times [2023-11-26 10:48:08,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:08,013 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1512604757] [2023-11-26 10:48:08,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:08,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:08,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:08,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:08,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:08,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1512604757] [2023-11-26 10:48:08,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1512604757] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:08,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:08,091 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:08,091 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [489425835] [2023-11-26 10:48:08,091 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:08,091 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:08,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:08,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:08,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:08,093 INFO L87 Difference]: Start difference. First operand 7370 states and 10593 transitions. cyclomatic complexity: 3225 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:08,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:08,388 INFO L93 Difference]: Finished difference Result 14092 states and 20169 transitions. [2023-11-26 10:48:08,388 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14092 states and 20169 transitions. [2023-11-26 10:48:08,471 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13900 [2023-11-26 10:48:08,534 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14092 states to 14092 states and 20169 transitions. [2023-11-26 10:48:08,535 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14092 [2023-11-26 10:48:08,549 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14092 [2023-11-26 10:48:08,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14092 states and 20169 transitions. [2023-11-26 10:48:08,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:08,565 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14092 states and 20169 transitions. [2023-11-26 10:48:08,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14092 states and 20169 transitions. [2023-11-26 10:48:08,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14092 to 14084. [2023-11-26 10:48:08,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14084 states, 14084 states have (on average 1.4314825333712013) internal successors, (20161), 14083 states have internal predecessors, (20161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:08,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14084 states to 14084 states and 20161 transitions. [2023-11-26 10:48:08,932 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14084 states and 20161 transitions. [2023-11-26 10:48:08,933 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:08,933 INFO L428 stractBuchiCegarLoop]: Abstraction has 14084 states and 20161 transitions. [2023-11-26 10:48:08,934 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-26 10:48:08,934 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14084 states and 20161 transitions. [2023-11-26 10:48:08,995 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13892 [2023-11-26 10:48:08,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:08,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:09,000 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:09,000 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:09,001 INFO L748 eck$LassoCheckResult]: Stem: 143539#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 143540#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 144568#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 144569#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 145503#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 144705#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 144139#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 144140#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 145020#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 145021#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 145158#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 145159#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 143881#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 143882#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 145203#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 144456#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 144457#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 145084#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 144368#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 144369#L1291 assume !(0 == ~M_E~0); 145504#L1291-2 assume !(0 == ~T1_E~0); 145497#L1296-1 assume !(0 == ~T2_E~0); 144525#L1301-1 assume !(0 == ~T3_E~0); 144526#L1306-1 assume !(0 == ~T4_E~0); 145097#L1311-1 assume !(0 == ~T5_E~0); 143716#L1316-1 assume !(0 == ~T6_E~0); 143717#L1321-1 assume !(0 == ~T7_E~0); 144540#L1326-1 assume !(0 == ~T8_E~0); 143536#L1331-1 assume !(0 == ~T9_E~0); 143250#L1336-1 assume !(0 == ~T10_E~0); 143251#L1341-1 assume !(0 == ~T11_E~0); 143323#L1346-1 assume !(0 == ~T12_E~0); 143324#L1351-1 assume !(0 == ~T13_E~0); 143652#L1356-1 assume !(0 == ~E_M~0); 143653#L1361-1 assume !(0 == ~E_1~0); 145396#L1366-1 assume !(0 == ~E_2~0); 143700#L1371-1 assume !(0 == ~E_3~0); 143701#L1376-1 assume !(0 == ~E_4~0); 144597#L1381-1 assume !(0 == ~E_5~0); 144598#L1386-1 assume !(0 == ~E_6~0); 145442#L1391-1 assume !(0 == ~E_7~0); 145478#L1396-1 assume !(0 == ~E_8~0); 144489#L1401-1 assume !(0 == ~E_9~0); 144490#L1406-1 assume !(0 == ~E_10~0); 144798#L1411-1 assume !(0 == ~E_11~0); 144799#L1416-1 assume !(0 == ~E_12~0); 144406#L1421-1 assume !(0 == ~E_13~0); 143905#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 143906#L640 assume !(1 == ~m_pc~0); 144455#L640-2 is_master_triggered_~__retres1~0#1 := 0; 144454#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144413#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 144414#L1603 assume !(0 != activate_threads_~tmp~1#1); 144443#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144058#L659 assume !(1 == ~t1_pc~0); 144059#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 145266#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 144936#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 144195#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 144196#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 144213#L678 assume !(1 == ~t2_pc~0); 145296#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 145436#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 143742#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 143743#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 144314#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144438#L697 assume !(1 == ~t3_pc~0); 144439#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 144578#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144922#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 144347#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 144348#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 145343#L716 assume !(1 == ~t4_pc~0); 144867#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 144039#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 143397#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 143398#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 143503#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144882#L735 assume !(1 == ~t5_pc~0); 143471#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 143472#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 143929#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 144912#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 144518#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 144519#L754 assume 1 == ~t6_pc~0; 144262#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 144154#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 143720#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 143721#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 144126#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 145008#L773 assume !(1 == ~t7_pc~0); 143656#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 143655#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 144557#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 144529#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 144530#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 144589#L792 assume 1 == ~t8_pc~0; 144769#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 145160#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 145161#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 144522#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 144441#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 144442#L811 assume 1 == ~t9_pc~0; 144665#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 145217#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 143798#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 143799#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 144451#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 144452#L830 assume !(1 == ~t10_pc~0); 144168#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 143632#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 143633#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 143611#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 143612#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 145029#L849 assume 1 == ~t11_pc~0; 145030#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 143450#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 143451#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 145048#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 144918#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 144919#L868 assume !(1 == ~t12_pc~0); 144298#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 144297#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 143338#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 143339#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 143668#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 143669#L887 assume 1 == ~t13_pc~0; 144925#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 144341#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 144342#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 144994#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 143378#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 143379#L1439 assume !(1 == ~M_E~0); 144514#L1439-2 assume !(1 == ~T1_E~0); 143549#L1444-1 assume !(1 == ~T2_E~0); 143550#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 144064#L1454-1 assume !(1 == ~T4_E~0); 144065#L1459-1 assume !(1 == ~T5_E~0); 144657#L1464-1 assume !(1 == ~T6_E~0); 144658#L1469-1 assume !(1 == ~T7_E~0); 144739#L1474-1 assume !(1 == ~T8_E~0); 144407#L1479-1 assume !(1 == ~T9_E~0); 144408#L1484-1 assume !(1 == ~T10_E~0); 144660#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 144288#L1494-1 assume !(1 == ~T12_E~0); 144289#L1499-1 assume !(1 == ~T13_E~0); 144474#L1504-1 assume !(1 == ~E_M~0); 144475#L1509-1 assume !(1 == ~E_1~0); 145137#L1514-1 assume !(1 == ~E_2~0); 144771#L1519-1 assume !(1 == ~E_3~0); 144772#L1524-1 assume !(1 == ~E_4~0); 145420#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 145421#L1534-1 assume !(1 == ~E_6~0); 143372#L1539-1 assume !(1 == ~E_7~0); 143373#L1544-1 assume !(1 == ~E_8~0); 143797#L1549-1 assume !(1 == ~E_9~0); 145379#L1554-1 assume !(1 == ~E_10~0); 145371#L1559-1 assume !(1 == ~E_11~0); 145192#L1564-1 assume !(1 == ~E_12~0); 145193#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 145409#L1574-1 assume { :end_inline_reset_delta_events } true; 145453#L1940-2 [2023-11-26 10:48:09,001 INFO L750 eck$LassoCheckResult]: Loop: 145453#L1940-2 assume !false; 148065#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 148058#L1266-1 assume !false; 148055#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 147796#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 147783#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 147776#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 147769#L1079 assume !(0 != eval_~tmp~0#1); 147770#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 153583#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 153582#L1291-3 assume !(0 == ~M_E~0); 153581#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 153580#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 153579#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 153578#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 153577#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 153576#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 153575#L1321-3 assume !(0 == ~T7_E~0); 153574#L1326-3 assume !(0 == ~T8_E~0); 153573#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 153572#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 153571#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 153570#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 153569#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 153568#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 153567#L1361-3 assume !(0 == ~E_1~0); 153566#L1366-3 assume !(0 == ~E_2~0); 153565#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 153564#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 153563#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 153562#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 153561#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 153560#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 153559#L1401-3 assume !(0 == ~E_9~0); 153558#L1406-3 assume !(0 == ~E_10~0); 153557#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 153556#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 153555#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 153554#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 153553#L640-45 assume !(1 == ~m_pc~0); 153552#L640-47 is_master_triggered_~__retres1~0#1 := 0; 153550#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153549#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 153548#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 145505#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 143383#L659-45 assume !(1 == ~t1_pc~0); 143384#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 143838#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 145471#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 153099#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 153098#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 153095#L678-45 assume !(1 == ~t2_pc~0); 153092#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 153090#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 153087#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 153086#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 153083#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 153080#L697-45 assume 1 == ~t3_pc~0; 153075#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 153069#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153063#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 153057#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 153053#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 153049#L716-45 assume !(1 == ~t4_pc~0); 153045#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 153042#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153040#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 153037#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 153034#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 150325#L735-45 assume 1 == ~t5_pc~0; 150212#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 150210#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 150208#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 150206#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 150204#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 150202#L754-45 assume !(1 == ~t6_pc~0); 150199#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 150189#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 150183#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 150182#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 150181#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 150180#L773-45 assume 1 == ~t7_pc~0; 150178#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 150177#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 150175#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 150174#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 150170#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 150168#L792-45 assume 1 == ~t8_pc~0; 150166#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 150164#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 150152#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 150138#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 150111#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 150100#L811-45 assume 1 == ~t9_pc~0; 150096#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 150094#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 149824#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 149817#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 149814#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 149812#L830-45 assume !(1 == ~t10_pc~0); 149810#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 149803#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 149793#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 149787#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 149782#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 149777#L849-45 assume !(1 == ~t11_pc~0); 149767#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 149764#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 149762#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 149760#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 149758#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 149756#L868-45 assume !(1 == ~t12_pc~0); 149754#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 149743#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 149736#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 149730#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 149725#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 149720#L887-45 assume !(1 == ~t13_pc~0); 149714#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 149707#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 149701#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 149696#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 149691#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 149686#L1439-3 assume !(1 == ~M_E~0); 149679#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 149674#L1444-3 assume !(1 == ~T2_E~0); 149669#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 149665#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 149661#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 149657#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 149652#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 149647#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 149642#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 149638#L1484-3 assume !(1 == ~T10_E~0); 149634#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 149630#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 149624#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 149620#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 149614#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 149608#L1514-3 assume !(1 == ~E_2~0); 149603#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 149598#L1524-3 assume !(1 == ~E_4~0); 149592#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 149587#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 149581#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 149577#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 149573#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 149569#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 149564#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 149559#L1564-3 assume !(1 == ~E_12~0); 149554#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 149552#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 149441#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 149430#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 149426#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 149420#L1959 assume !(0 == start_simulation_~tmp~3#1); 149413#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 148146#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 148137#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 148134#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 148132#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 148130#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 148091#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 148081#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 145453#L1940-2 [2023-11-26 10:48:09,002 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:09,003 INFO L85 PathProgramCache]: Analyzing trace with hash 846336710, now seen corresponding path program 1 times [2023-11-26 10:48:09,003 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:09,003 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775417892] [2023-11-26 10:48:09,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:09,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:09,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:09,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:09,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:09,101 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775417892] [2023-11-26 10:48:09,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775417892] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:09,101 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:09,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:48:09,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [179531045] [2023-11-26 10:48:09,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:09,103 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:09,103 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:09,104 INFO L85 PathProgramCache]: Analyzing trace with hash -1549124227, now seen corresponding path program 1 times [2023-11-26 10:48:09,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:09,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706187654] [2023-11-26 10:48:09,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:09,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:09,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:09,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:09,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:09,193 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706187654] [2023-11-26 10:48:09,193 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1706187654] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:09,194 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:09,194 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:09,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1065554097] [2023-11-26 10:48:09,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:09,195 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:09,195 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:09,196 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:09,196 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:09,196 INFO L87 Difference]: Start difference. First operand 14084 states and 20161 transitions. cyclomatic complexity: 6081 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:09,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:09,515 INFO L93 Difference]: Finished difference Result 27059 states and 38586 transitions. [2023-11-26 10:48:09,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27059 states and 38586 transitions. [2023-11-26 10:48:09,802 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26836 [2023-11-26 10:48:09,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27059 states to 27059 states and 38586 transitions. [2023-11-26 10:48:09,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27059 [2023-11-26 10:48:09,942 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27059 [2023-11-26 10:48:09,942 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27059 states and 38586 transitions. [2023-11-26 10:48:09,965 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:09,966 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27059 states and 38586 transitions. [2023-11-26 10:48:09,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27059 states and 38586 transitions. [2023-11-26 10:48:10,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27059 to 27043. [2023-11-26 10:48:10,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27043 states, 27043 states have (on average 1.4262470879710092) internal successors, (38570), 27042 states have internal predecessors, (38570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:10,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27043 states to 27043 states and 38570 transitions. [2023-11-26 10:48:10,490 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27043 states and 38570 transitions. [2023-11-26 10:48:10,491 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:10,491 INFO L428 stractBuchiCegarLoop]: Abstraction has 27043 states and 38570 transitions. [2023-11-26 10:48:10,492 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-26 10:48:10,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27043 states and 38570 transitions. [2023-11-26 10:48:10,683 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26820 [2023-11-26 10:48:10,692 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:10,692 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:10,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:10,696 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:10,696 INFO L748 eck$LassoCheckResult]: Stem: 184687#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 184688#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 185704#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 185705#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 186604#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 185841#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 185284#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 185285#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 186157#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 186158#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 186284#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 186285#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 185028#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 185029#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 186323#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 185596#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 185597#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 186219#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 185509#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 185510#L1291 assume !(0 == ~M_E~0); 186605#L1291-2 assume !(0 == ~T1_E~0); 186602#L1296-1 assume !(0 == ~T2_E~0); 185664#L1301-1 assume !(0 == ~T3_E~0); 185665#L1306-1 assume !(0 == ~T4_E~0); 186230#L1311-1 assume !(0 == ~T5_E~0); 184863#L1316-1 assume !(0 == ~T6_E~0); 184864#L1321-1 assume !(0 == ~T7_E~0); 185679#L1326-1 assume !(0 == ~T8_E~0); 184684#L1331-1 assume !(0 == ~T9_E~0); 184400#L1336-1 assume !(0 == ~T10_E~0); 184401#L1341-1 assume !(0 == ~T11_E~0); 184471#L1346-1 assume !(0 == ~T12_E~0); 184472#L1351-1 assume !(0 == ~T13_E~0); 184799#L1356-1 assume !(0 == ~E_M~0); 184800#L1361-1 assume !(0 == ~E_1~0); 186504#L1366-1 assume !(0 == ~E_2~0); 184847#L1371-1 assume !(0 == ~E_3~0); 184848#L1376-1 assume !(0 == ~E_4~0); 185735#L1381-1 assume !(0 == ~E_5~0); 185736#L1386-1 assume !(0 == ~E_6~0); 186554#L1391-1 assume !(0 == ~E_7~0); 186588#L1396-1 assume !(0 == ~E_8~0); 185628#L1401-1 assume !(0 == ~E_9~0); 185629#L1406-1 assume !(0 == ~E_10~0); 185938#L1411-1 assume !(0 == ~E_11~0); 185939#L1416-1 assume !(0 == ~E_12~0); 185546#L1421-1 assume !(0 == ~E_13~0); 185051#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 185052#L640 assume !(1 == ~m_pc~0); 185594#L640-2 is_master_triggered_~__retres1~0#1 := 0; 185593#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 185553#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 185554#L1603 assume !(0 != activate_threads_~tmp~1#1); 185582#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 185205#L659 assume !(1 == ~t1_pc~0); 185206#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 186382#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 186072#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 185337#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 185338#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 185354#L678 assume !(1 == ~t2_pc~0); 186415#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 186542#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 184889#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 184890#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 185451#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 185575#L697 assume !(1 == ~t3_pc~0); 185576#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 185715#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 186651#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 185486#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 185487#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 186460#L716 assume !(1 == ~t4_pc~0); 186006#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 185183#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 184543#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 184544#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 184650#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 186019#L735 assume !(1 == ~t5_pc~0); 184618#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 184619#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 185078#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 186047#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 185656#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 185657#L754 assume !(1 == ~t6_pc~0); 185895#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 185300#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 184867#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 184868#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 185268#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 186145#L773 assume !(1 == ~t7_pc~0); 184803#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 184802#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 185695#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 185668#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 185669#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 185727#L792 assume 1 == ~t8_pc~0; 185905#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 186286#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 186287#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 185658#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 185578#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 185579#L811 assume 1 == ~t9_pc~0; 185800#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 186337#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 184946#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 184947#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 185590#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 185591#L830 assume !(1 == ~t10_pc~0); 185309#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 184780#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 184781#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 184759#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 184760#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 186168#L849 assume 1 == ~t11_pc~0; 186169#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 184597#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 184598#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 186188#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 186051#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 186052#L868 assume !(1 == ~t12_pc~0); 185435#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 185434#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 184486#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 184487#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 184815#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 184816#L887 assume 1 == ~t13_pc~0; 186060#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 185480#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 185481#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 186135#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 184526#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 184527#L1439 assume !(1 == ~M_E~0); 185650#L1439-2 assume !(1 == ~T1_E~0); 184697#L1444-1 assume !(1 == ~T2_E~0); 184698#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 185209#L1454-1 assume !(1 == ~T4_E~0); 185210#L1459-1 assume !(1 == ~T5_E~0); 185792#L1464-1 assume !(1 == ~T6_E~0); 185793#L1469-1 assume !(1 == ~T7_E~0); 185873#L1474-1 assume !(1 == ~T8_E~0); 185547#L1479-1 assume !(1 == ~T9_E~0); 185548#L1484-1 assume !(1 == ~T10_E~0); 185796#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 185424#L1494-1 assume !(1 == ~T12_E~0); 185425#L1499-1 assume !(1 == ~T13_E~0); 185613#L1504-1 assume !(1 == ~E_M~0); 185614#L1509-1 assume !(1 == ~E_1~0); 186268#L1514-1 assume !(1 == ~E_2~0); 185907#L1519-1 assume !(1 == ~E_3~0); 185908#L1524-1 assume !(1 == ~E_4~0); 186523#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 186524#L1534-1 assume !(1 == ~E_6~0); 184520#L1539-1 assume !(1 == ~E_7~0); 184521#L1544-1 assume !(1 == ~E_8~0); 184943#L1549-1 assume !(1 == ~E_9~0); 186487#L1554-1 assume !(1 == ~E_10~0); 186483#L1559-1 assume !(1 == ~E_11~0); 186314#L1564-1 assume !(1 == ~E_12~0); 186315#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 186515#L1574-1 assume { :end_inline_reset_delta_events } true; 186562#L1940-2 [2023-11-26 10:48:10,697 INFO L750 eck$LassoCheckResult]: Loop: 186562#L1940-2 assume !false; 201143#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 201139#L1266-1 assume !false; 201138#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 201129#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 201120#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 201118#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 201116#L1079 assume !(0 != eval_~tmp~0#1); 201113#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 201111#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 201109#L1291-3 assume !(0 == ~M_E~0); 201107#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 201105#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 201103#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 201100#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 201098#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 201096#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 201094#L1321-3 assume !(0 == ~T7_E~0); 201092#L1326-3 assume !(0 == ~T8_E~0); 201090#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 201087#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 201085#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 201083#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 201081#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 201079#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 201077#L1361-3 assume !(0 == ~E_1~0); 201074#L1366-3 assume !(0 == ~E_2~0); 201072#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 201070#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 201068#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 201066#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 201064#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 201061#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 201059#L1401-3 assume !(0 == ~E_9~0); 201057#L1406-3 assume !(0 == ~E_10~0); 201055#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 201053#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 201051#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 201048#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 201046#L640-45 assume 1 == ~m_pc~0; 201043#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 201041#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 201039#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 201037#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 201034#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 201032#L659-45 assume !(1 == ~t1_pc~0); 201030#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 201028#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201026#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 201025#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 201024#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 201023#L678-45 assume !(1 == ~t2_pc~0); 201021#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 201020#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 201019#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 201018#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 201017#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 201016#L697-45 assume 1 == ~t3_pc~0; 201015#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 201013#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 201011#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 201008#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 201007#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 201006#L716-45 assume !(1 == ~t4_pc~0); 201005#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 201004#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 201003#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 201002#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 201001#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 201000#L735-45 assume !(1 == ~t5_pc~0); 200999#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 200997#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 200996#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 200995#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 200994#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 200992#L754-45 assume !(1 == ~t6_pc~0); 200990#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 200988#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 200986#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 200983#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 200981#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 200979#L773-45 assume !(1 == ~t7_pc~0); 200977#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 200974#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 200972#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 200970#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 200968#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 200966#L792-45 assume !(1 == ~t8_pc~0); 200963#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 200961#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 200959#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 200956#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 200954#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 200952#L811-45 assume !(1 == ~t9_pc~0); 200950#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 200947#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 200945#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 200942#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 200940#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 200938#L830-45 assume 1 == ~t10_pc~0; 200935#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 200933#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 200931#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 200928#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 200926#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 200924#L849-45 assume 1 == ~t11_pc~0; 200922#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 200919#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 200917#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 200914#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 200912#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 200910#L868-45 assume 1 == ~t12_pc~0; 200907#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 200905#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 200903#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 200900#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 200898#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 200896#L887-45 assume 1 == ~t13_pc~0; 200894#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 200891#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 200889#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 200886#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 200884#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 200882#L1439-3 assume !(1 == ~M_E~0); 195911#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 200879#L1444-3 assume !(1 == ~T2_E~0); 200877#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 200874#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 200872#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 200870#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 200868#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 200866#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 200863#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 200861#L1484-3 assume !(1 == ~T10_E~0); 200859#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 200857#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 200855#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 200853#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 200851#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 200849#L1514-3 assume !(1 == ~E_2~0); 200847#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 200845#L1524-3 assume !(1 == ~E_4~0); 200843#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 200841#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 200839#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 200837#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 200835#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 200833#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 200831#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 197399#L1564-3 assume !(1 == ~E_12~0); 197397#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 197396#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 197205#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 197194#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 197190#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 192427#L1959 assume !(0 == start_simulation_~tmp~3#1); 192428#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 201170#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 201161#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 201159#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 201158#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 201155#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 201151#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 201147#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 186562#L1940-2 [2023-11-26 10:48:10,697 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:10,698 INFO L85 PathProgramCache]: Analyzing trace with hash -995977081, now seen corresponding path program 1 times [2023-11-26 10:48:10,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:10,698 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549973185] [2023-11-26 10:48:10,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:10,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:10,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:10,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:10,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:10,782 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549973185] [2023-11-26 10:48:10,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [549973185] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:10,782 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:10,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:48:10,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1222991891] [2023-11-26 10:48:10,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:10,784 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:10,784 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:10,785 INFO L85 PathProgramCache]: Analyzing trace with hash 2021350652, now seen corresponding path program 1 times [2023-11-26 10:48:10,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:10,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694687760] [2023-11-26 10:48:10,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:10,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:10,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:10,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:10,867 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:10,867 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [694687760] [2023-11-26 10:48:10,867 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [694687760] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:10,868 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:10,868 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:10,868 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1918871902] [2023-11-26 10:48:10,868 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:10,869 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:10,869 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:10,869 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:10,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:10,870 INFO L87 Difference]: Start difference. First operand 27043 states and 38570 transitions. cyclomatic complexity: 11535 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:11,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:11,365 INFO L93 Difference]: Finished difference Result 52062 states and 73987 transitions. [2023-11-26 10:48:11,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52062 states and 73987 transitions. [2023-11-26 10:48:11,833 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51760 [2023-11-26 10:48:12,211 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52062 states to 52062 states and 73987 transitions. [2023-11-26 10:48:12,211 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52062 [2023-11-26 10:48:12,237 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52062 [2023-11-26 10:48:12,237 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52062 states and 73987 transitions. [2023-11-26 10:48:12,276 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:12,276 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52062 states and 73987 transitions. [2023-11-26 10:48:12,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52062 states and 73987 transitions. [2023-11-26 10:48:12,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52062 to 52030. [2023-11-26 10:48:13,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52030 states, 52030 states have (on average 1.4213915049010186) internal successors, (73955), 52029 states have internal predecessors, (73955), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:13,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52030 states to 52030 states and 73955 transitions. [2023-11-26 10:48:13,184 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52030 states and 73955 transitions. [2023-11-26 10:48:13,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:13,185 INFO L428 stractBuchiCegarLoop]: Abstraction has 52030 states and 73955 transitions. [2023-11-26 10:48:13,185 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-26 10:48:13,185 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52030 states and 73955 transitions. [2023-11-26 10:48:13,370 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51728 [2023-11-26 10:48:13,371 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:13,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:13,547 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:13,547 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:13,548 INFO L748 eck$LassoCheckResult]: Stem: 263801#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 263802#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 264819#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 264820#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 265734#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 264959#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 264401#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 264402#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 265274#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 265275#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 265402#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 265403#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 264143#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 264144#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 265439#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 264713#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 264714#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 265328#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 264622#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 264623#L1291 assume !(0 == ~M_E~0); 265735#L1291-2 assume !(0 == ~T1_E~0); 265732#L1296-1 assume !(0 == ~T2_E~0); 264778#L1301-1 assume !(0 == ~T3_E~0); 264779#L1306-1 assume !(0 == ~T4_E~0); 265341#L1311-1 assume !(0 == ~T5_E~0); 263975#L1316-1 assume !(0 == ~T6_E~0); 263976#L1321-1 assume !(0 == ~T7_E~0); 264792#L1326-1 assume !(0 == ~T8_E~0); 263798#L1331-1 assume !(0 == ~T9_E~0); 263512#L1336-1 assume !(0 == ~T10_E~0); 263513#L1341-1 assume !(0 == ~T11_E~0); 263584#L1346-1 assume !(0 == ~T12_E~0); 263585#L1351-1 assume !(0 == ~T13_E~0); 263911#L1356-1 assume !(0 == ~E_M~0); 263912#L1361-1 assume !(0 == ~E_1~0); 265635#L1366-1 assume !(0 == ~E_2~0); 263959#L1371-1 assume !(0 == ~E_3~0); 263960#L1376-1 assume !(0 == ~E_4~0); 264850#L1381-1 assume !(0 == ~E_5~0); 264851#L1386-1 assume !(0 == ~E_6~0); 265684#L1391-1 assume !(0 == ~E_7~0); 265713#L1396-1 assume !(0 == ~E_8~0); 264745#L1401-1 assume !(0 == ~E_9~0); 264746#L1406-1 assume !(0 == ~E_10~0); 265053#L1411-1 assume !(0 == ~E_11~0); 265054#L1416-1 assume !(0 == ~E_12~0); 264661#L1421-1 assume !(0 == ~E_13~0); 264167#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 264168#L640 assume !(1 == ~m_pc~0); 264711#L640-2 is_master_triggered_~__retres1~0#1 := 0; 264710#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 264669#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 264670#L1603 assume !(0 != activate_threads_~tmp~1#1); 264699#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 264323#L659 assume !(1 == ~t1_pc~0); 264324#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 265502#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 265195#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 264452#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 264453#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 264471#L678 assume !(1 == ~t2_pc~0); 265527#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 265678#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 264004#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 264005#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 264569#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 264692#L697 assume !(1 == ~t3_pc~0); 264693#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 264828#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 265788#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 264602#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 264603#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 265587#L716 assume !(1 == ~t4_pc~0); 265123#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 264301#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 263658#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 263659#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 263765#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 265137#L735 assume !(1 == ~t5_pc~0); 263733#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 263734#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 264192#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 265170#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 264771#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 264772#L754 assume !(1 == ~t6_pc~0); 265012#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 264414#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 263979#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 263980#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 264388#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 265264#L773 assume !(1 == ~t7_pc~0); 263915#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 263914#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 264807#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 264782#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 264783#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 264841#L792 assume !(1 == ~t8_pc~0); 265023#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 265404#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 265405#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 264773#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 264695#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 264696#L811 assume 1 == ~t9_pc~0; 264916#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 265453#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 264061#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 264062#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 264707#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 264708#L830 assume !(1 == ~t10_pc~0); 264423#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 263892#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 263893#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 263870#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 263871#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 265284#L849 assume 1 == ~t11_pc~0; 265285#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 263712#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 263713#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 265298#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 265174#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 265175#L868 assume !(1 == ~t12_pc~0); 264553#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 264552#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 263599#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 263600#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 263927#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 263928#L887 assume 1 == ~t13_pc~0; 265185#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 264596#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 264597#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 265252#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 263640#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 263641#L1439 assume !(1 == ~M_E~0); 264765#L1439-2 assume !(1 == ~T1_E~0); 263811#L1444-1 assume !(1 == ~T2_E~0); 263812#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 264327#L1454-1 assume !(1 == ~T4_E~0); 264328#L1459-1 assume !(1 == ~T5_E~0); 264908#L1464-1 assume !(1 == ~T6_E~0); 264909#L1469-1 assume !(1 == ~T7_E~0); 264988#L1474-1 assume !(1 == ~T8_E~0); 264662#L1479-1 assume !(1 == ~T9_E~0); 264663#L1484-1 assume !(1 == ~T10_E~0); 264912#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 264542#L1494-1 assume !(1 == ~T12_E~0); 264543#L1499-1 assume !(1 == ~T13_E~0); 264730#L1504-1 assume !(1 == ~E_M~0); 264731#L1509-1 assume !(1 == ~E_1~0); 265385#L1514-1 assume !(1 == ~E_2~0); 265024#L1519-1 assume !(1 == ~E_3~0); 265025#L1524-1 assume !(1 == ~E_4~0); 265657#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 265658#L1534-1 assume !(1 == ~E_6~0); 263634#L1539-1 assume !(1 == ~E_7~0); 263635#L1544-1 assume !(1 == ~E_8~0); 264058#L1549-1 assume !(1 == ~E_9~0); 265618#L1554-1 assume !(1 == ~E_10~0); 265614#L1559-1 assume !(1 == ~E_11~0); 265431#L1564-1 assume !(1 == ~E_12~0); 265432#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 265651#L1574-1 assume { :end_inline_reset_delta_events } true; 265692#L1940-2 [2023-11-26 10:48:13,548 INFO L750 eck$LassoCheckResult]: Loop: 265692#L1940-2 assume !false; 282476#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 282471#L1266-1 assume !false; 282469#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 282449#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 282440#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 282438#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 282433#L1079 assume !(0 != eval_~tmp~0#1); 282434#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 282864#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 282862#L1291-3 assume !(0 == ~M_E~0); 282860#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 282858#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 282856#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 282854#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 282852#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 282850#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 282848#L1321-3 assume !(0 == ~T7_E~0); 282846#L1326-3 assume !(0 == ~T8_E~0); 282844#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 282842#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 282840#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 282838#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 282836#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 282834#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 282832#L1361-3 assume !(0 == ~E_1~0); 282830#L1366-3 assume !(0 == ~E_2~0); 282827#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 282825#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 282823#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 282821#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 282819#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 282817#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 282815#L1401-3 assume !(0 == ~E_9~0); 282813#L1406-3 assume !(0 == ~E_10~0); 282811#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 282809#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 282807#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 282804#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 282802#L640-45 assume !(1 == ~m_pc~0); 282800#L640-47 is_master_triggered_~__retres1~0#1 := 0; 282797#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 282795#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 282793#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 282789#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 282787#L659-45 assume !(1 == ~t1_pc~0); 282785#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 282783#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 282780#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 282778#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 282776#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 282774#L678-45 assume !(1 == ~t2_pc~0); 282771#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 282769#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 282767#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 282765#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 282763#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 282760#L697-45 assume !(1 == ~t3_pc~0); 282756#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 282754#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 282752#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 282750#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 282747#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 282745#L716-45 assume !(1 == ~t4_pc~0); 282743#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 282741#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 282739#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 282737#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 282735#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 282732#L735-45 assume 1 == ~t5_pc~0; 282729#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 282727#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 282725#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 282723#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 282721#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 282719#L754-45 assume !(1 == ~t6_pc~0); 282717#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 282715#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 282713#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 282711#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 282709#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 282706#L773-45 assume !(1 == ~t7_pc~0); 282704#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 282701#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 282699#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 282697#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 282695#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 282692#L792-45 assume !(1 == ~t8_pc~0); 282690#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 282688#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 282686#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 282684#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 282682#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 282679#L811-45 assume 1 == ~t9_pc~0; 282676#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 282674#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 282672#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 282670#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 282668#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 282665#L830-45 assume 1 == ~t10_pc~0; 282662#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 282660#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 282658#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 282656#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 282654#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 282651#L849-45 assume !(1 == ~t11_pc~0); 282648#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 282646#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 282644#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 282642#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 282641#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 282640#L868-45 assume 1 == ~t12_pc~0; 282638#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 282637#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 282636#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 282634#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 282631#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 282629#L887-45 assume !(1 == ~t13_pc~0); 282626#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 282624#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 282622#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 282620#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 282618#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 282616#L1439-3 assume !(1 == ~M_E~0); 282612#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 282610#L1444-3 assume !(1 == ~T2_E~0); 282608#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 282605#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 282603#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 282601#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 282599#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 282597#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 282595#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 282591#L1484-3 assume !(1 == ~T10_E~0); 282589#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 282587#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 282585#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 282582#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 282580#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 282578#L1514-3 assume !(1 == ~E_2~0); 282576#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 282574#L1524-3 assume !(1 == ~E_4~0); 282572#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 282570#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 282568#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 282566#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 282563#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 282561#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 282559#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 282557#L1564-3 assume !(1 == ~E_12~0); 282555#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 282553#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 282535#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 282526#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 282524#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 282521#L1959 assume !(0 == start_simulation_~tmp~3#1); 282518#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 282500#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 282490#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 282488#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 282486#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 282484#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 282482#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 282480#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 265692#L1940-2 [2023-11-26 10:48:13,548 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:13,549 INFO L85 PathProgramCache]: Analyzing trace with hash -618334264, now seen corresponding path program 1 times [2023-11-26 10:48:13,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:13,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1003002460] [2023-11-26 10:48:13,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:13,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:13,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:13,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:13,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:13,648 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1003002460] [2023-11-26 10:48:13,648 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1003002460] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:13,648 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:13,649 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:48:13,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1110606146] [2023-11-26 10:48:13,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:13,649 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:13,650 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:13,650 INFO L85 PathProgramCache]: Analyzing trace with hash -1262815040, now seen corresponding path program 1 times [2023-11-26 10:48:13,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:13,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761740357] [2023-11-26 10:48:13,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:13,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:13,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:13,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:13,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:13,718 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [761740357] [2023-11-26 10:48:13,718 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [761740357] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:13,718 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:13,718 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:13,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1749999034] [2023-11-26 10:48:13,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:13,719 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:13,719 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:13,719 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:13,720 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:13,720 INFO L87 Difference]: Start difference. First operand 52030 states and 73955 transitions. cyclomatic complexity: 21941 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:14,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:14,376 INFO L93 Difference]: Finished difference Result 100221 states and 141968 transitions. [2023-11-26 10:48:14,376 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100221 states and 141968 transitions. [2023-11-26 10:48:14,920 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99728 [2023-11-26 10:48:15,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100221 states to 100221 states and 141968 transitions. [2023-11-26 10:48:15,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100221 [2023-11-26 10:48:15,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100221 [2023-11-26 10:48:15,496 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100221 states and 141968 transitions. [2023-11-26 10:48:15,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:15,593 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100221 states and 141968 transitions. [2023-11-26 10:48:15,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100221 states and 141968 transitions. [2023-11-26 10:48:16,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100221 to 100157. [2023-11-26 10:48:16,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100157 states, 100157 states have (on average 1.4168155995087712) internal successors, (141904), 100156 states have internal predecessors, (141904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:17,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100157 states to 100157 states and 141904 transitions. [2023-11-26 10:48:17,046 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100157 states and 141904 transitions. [2023-11-26 10:48:17,047 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:48:17,048 INFO L428 stractBuchiCegarLoop]: Abstraction has 100157 states and 141904 transitions. [2023-11-26 10:48:17,048 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-26 10:48:17,048 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100157 states and 141904 transitions. [2023-11-26 10:48:17,797 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99664 [2023-11-26 10:48:17,798 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:17,798 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:17,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:17,801 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:17,801 INFO L748 eck$LassoCheckResult]: Stem: 416059#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 416060#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 417082#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 417083#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 418021#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 417216#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 416661#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 416662#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 417542#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 417543#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 417674#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 417675#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 416401#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 416402#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 417711#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 416974#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 416975#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 417603#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 416886#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 416887#L1291 assume !(0 == ~M_E~0); 418022#L1291-2 assume !(0 == ~T1_E~0); 418019#L1296-1 assume !(0 == ~T2_E~0); 417040#L1301-1 assume !(0 == ~T3_E~0); 417041#L1306-1 assume !(0 == ~T4_E~0); 417617#L1311-1 assume !(0 == ~T5_E~0); 416234#L1316-1 assume !(0 == ~T6_E~0); 416235#L1321-1 assume !(0 == ~T7_E~0); 417054#L1326-1 assume !(0 == ~T8_E~0); 416056#L1331-1 assume !(0 == ~T9_E~0); 415770#L1336-1 assume !(0 == ~T10_E~0); 415771#L1341-1 assume !(0 == ~T11_E~0); 415842#L1346-1 assume !(0 == ~T12_E~0); 415843#L1351-1 assume !(0 == ~T13_E~0); 416172#L1356-1 assume !(0 == ~E_M~0); 416173#L1361-1 assume !(0 == ~E_1~0); 417912#L1366-1 assume !(0 == ~E_2~0); 416218#L1371-1 assume !(0 == ~E_3~0); 416219#L1376-1 assume !(0 == ~E_4~0); 417110#L1381-1 assume !(0 == ~E_5~0); 417111#L1386-1 assume !(0 == ~E_6~0); 417963#L1391-1 assume !(0 == ~E_7~0); 417999#L1396-1 assume !(0 == ~E_8~0); 417006#L1401-1 assume !(0 == ~E_9~0); 417007#L1406-1 assume !(0 == ~E_10~0); 417310#L1411-1 assume !(0 == ~E_11~0); 417311#L1416-1 assume !(0 == ~E_12~0); 416923#L1421-1 assume !(0 == ~E_13~0); 416422#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 416423#L640 assume !(1 == ~m_pc~0); 416973#L640-2 is_master_triggered_~__retres1~0#1 := 0; 416972#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 416931#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 416932#L1603 assume !(0 != activate_threads_~tmp~1#1); 416960#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 416584#L659 assume !(1 == ~t1_pc~0); 416585#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 417780#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 417454#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 416716#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 416717#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 416734#L678 assume !(1 == ~t2_pc~0); 417808#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 417952#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 416261#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 416262#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 416831#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 416953#L697 assume !(1 == ~t3_pc~0); 416954#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 417091#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 418077#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 416866#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 416867#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 417862#L716 assume !(1 == ~t4_pc~0); 417384#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 416561#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 415915#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 415916#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 416022#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 417398#L735 assume !(1 == ~t5_pc~0); 415990#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 415991#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 416453#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 417431#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 417033#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 417034#L754 assume !(1 == ~t6_pc~0); 417271#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 416675#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 416238#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 416239#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 416648#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 417526#L773 assume !(1 == ~t7_pc~0); 416176#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 416175#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 417072#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 417044#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 417045#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 417102#L792 assume !(1 == ~t8_pc~0); 417281#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 417676#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 417677#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 417035#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 416956#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 416957#L811 assume !(1 == ~t9_pc~0); 417175#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 417762#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 416317#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 416318#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 416969#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 416970#L830 assume !(1 == ~t10_pc~0); 416685#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 416152#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 416153#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 416129#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 416130#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 417553#L849 assume 1 == ~t11_pc~0; 417554#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 415969#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 415970#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 417570#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 417435#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 417436#L868 assume !(1 == ~t12_pc~0); 416815#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 416814#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 415857#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 415858#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 416187#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 416188#L887 assume 1 == ~t13_pc~0; 417444#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 416860#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 416861#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 417515#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 415897#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 415898#L1439 assume !(1 == ~M_E~0); 417027#L1439-2 assume !(1 == ~T1_E~0); 416069#L1444-1 assume !(1 == ~T2_E~0); 416070#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 416588#L1454-1 assume !(1 == ~T4_E~0); 416589#L1459-1 assume !(1 == ~T5_E~0); 417167#L1464-1 assume !(1 == ~T6_E~0); 417168#L1469-1 assume !(1 == ~T7_E~0); 417249#L1474-1 assume !(1 == ~T8_E~0); 416924#L1479-1 assume !(1 == ~T9_E~0); 416925#L1484-1 assume !(1 == ~T10_E~0); 417171#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 416803#L1494-1 assume !(1 == ~T12_E~0); 416804#L1499-1 assume !(1 == ~T13_E~0); 416991#L1504-1 assume !(1 == ~E_M~0); 416992#L1509-1 assume !(1 == ~E_1~0); 417656#L1514-1 assume !(1 == ~E_2~0); 417282#L1519-1 assume !(1 == ~E_3~0); 417283#L1524-1 assume !(1 == ~E_4~0); 417937#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 417938#L1534-1 assume !(1 == ~E_6~0); 415891#L1539-1 assume !(1 == ~E_7~0); 415892#L1544-1 assume !(1 == ~E_8~0); 416314#L1549-1 assume !(1 == ~E_9~0); 417889#L1554-1 assume !(1 == ~E_10~0); 417886#L1559-1 assume !(1 == ~E_11~0); 417702#L1564-1 assume !(1 == ~E_12~0); 417703#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 417926#L1574-1 assume { :end_inline_reset_delta_events } true; 417973#L1940-2 [2023-11-26 10:48:17,802 INFO L750 eck$LassoCheckResult]: Loop: 417973#L1940-2 assume !false; 425927#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 425919#L1266-1 assume !false; 425915#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 425735#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 425720#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 425711#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 425702#L1079 assume !(0 != eval_~tmp~0#1); 425703#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 429071#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 429069#L1291-3 assume !(0 == ~M_E~0); 429067#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 429065#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 429063#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 429060#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 429058#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 429056#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 429054#L1321-3 assume !(0 == ~T7_E~0); 429052#L1326-3 assume !(0 == ~T8_E~0); 429050#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 429048#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 429046#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 429044#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 429042#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 429040#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 429038#L1361-3 assume !(0 == ~E_1~0); 429036#L1366-3 assume !(0 == ~E_2~0); 429014#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 429004#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 428993#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 428983#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 428845#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 428787#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 428772#L1401-3 assume !(0 == ~E_9~0); 428761#L1406-3 assume !(0 == ~E_10~0); 428752#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 428748#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 428745#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 427549#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 427480#L640-45 assume 1 == ~m_pc~0; 427472#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 427464#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 427456#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 427448#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 427441#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 427434#L659-45 assume !(1 == ~t1_pc~0); 427427#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 427420#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 427413#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 427407#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 427402#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 427251#L678-45 assume !(1 == ~t2_pc~0); 427248#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 427246#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 427244#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 427242#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 427240#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 427237#L697-45 assume 1 == ~t3_pc~0; 427235#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 427236#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 427257#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 427226#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 427224#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 427221#L716-45 assume !(1 == ~t4_pc~0); 427219#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 427217#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 427215#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 427213#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 427211#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 427210#L735-45 assume 1 == ~t5_pc~0; 427207#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 427205#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 427203#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 427201#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 427199#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 427197#L754-45 assume !(1 == ~t6_pc~0); 427195#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 427193#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 427191#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 427189#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 427187#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 427185#L773-45 assume 1 == ~t7_pc~0; 427182#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 427180#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 427178#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 427176#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 427174#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 427172#L792-45 assume !(1 == ~t8_pc~0); 427170#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 427168#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 427166#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 427164#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 427162#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 427160#L811-45 assume !(1 == ~t9_pc~0); 427158#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 427156#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 427154#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 427152#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 427150#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 427148#L830-45 assume 1 == ~t10_pc~0; 427100#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 427092#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 427085#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 427075#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 427053#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 427050#L849-45 assume !(1 == ~t11_pc~0); 427047#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 427045#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 427043#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 427041#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 427039#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 427037#L868-45 assume 1 == ~t12_pc~0; 427034#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 427032#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 427031#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 427028#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 427026#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 427024#L887-45 assume 1 == ~t13_pc~0; 427022#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 427019#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 427017#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 427015#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 426984#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 426976#L1439-3 assume !(1 == ~M_E~0); 426966#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 426959#L1444-3 assume !(1 == ~T2_E~0); 426950#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 426941#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 426934#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 426926#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 426919#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 426911#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 426902#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 426895#L1484-3 assume !(1 == ~T10_E~0); 426888#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 426881#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 426873#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 426864#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 426855#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 426848#L1514-3 assume !(1 == ~E_2~0); 426843#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 426838#L1524-3 assume !(1 == ~E_4~0); 426831#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 426826#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 426821#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 426814#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 426807#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 426800#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 426793#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 426787#L1564-3 assume !(1 == ~E_12~0); 426783#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 426778#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 426600#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 426586#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 426579#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 426574#L1959 assume !(0 == start_simulation_~tmp~3#1); 426571#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 426022#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 426013#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 426010#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 426008#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 426007#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 425959#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 425947#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 417973#L1940-2 [2023-11-26 10:48:17,802 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:17,803 INFO L85 PathProgramCache]: Analyzing trace with hash -1649665079, now seen corresponding path program 1 times [2023-11-26 10:48:17,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:17,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [138779271] [2023-11-26 10:48:17,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:17,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:17,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:17,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:17,889 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:17,889 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [138779271] [2023-11-26 10:48:17,889 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [138779271] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:17,889 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:17,889 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:48:17,890 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695681996] [2023-11-26 10:48:17,890 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:17,890 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:17,890 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:17,891 INFO L85 PathProgramCache]: Analyzing trace with hash -1777723269, now seen corresponding path program 1 times [2023-11-26 10:48:17,891 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:17,891 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138954341] [2023-11-26 10:48:17,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:17,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:17,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:17,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:17,956 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:17,956 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2138954341] [2023-11-26 10:48:17,956 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2138954341] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:17,956 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:17,956 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:17,956 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011041739] [2023-11-26 10:48:17,957 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:17,957 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:17,957 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:17,958 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 10:48:17,958 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 10:48:17,958 INFO L87 Difference]: Start difference. First operand 100157 states and 141904 transitions. cyclomatic complexity: 41779 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:19,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:19,383 INFO L93 Difference]: Finished difference Result 216025 states and 304472 transitions. [2023-11-26 10:48:19,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 216025 states and 304472 transitions. [2023-11-26 10:48:20,843 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 215136 [2023-11-26 10:48:21,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 216025 states to 216025 states and 304472 transitions. [2023-11-26 10:48:21,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 216025 [2023-11-26 10:48:21,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 216025 [2023-11-26 10:48:21,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 216025 states and 304472 transitions. [2023-11-26 10:48:21,633 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:21,633 INFO L218 hiAutomatonCegarLoop]: Abstraction has 216025 states and 304472 transitions. [2023-11-26 10:48:21,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216025 states and 304472 transitions. [2023-11-26 10:48:23,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216025 to 102656. [2023-11-26 10:48:23,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102656 states, 102656 states have (on average 1.4066688746882794) internal successors, (144403), 102655 states have internal predecessors, (144403), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:24,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102656 states to 102656 states and 144403 transitions. [2023-11-26 10:48:24,021 INFO L240 hiAutomatonCegarLoop]: Abstraction has 102656 states and 144403 transitions. [2023-11-26 10:48:24,021 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 10:48:24,022 INFO L428 stractBuchiCegarLoop]: Abstraction has 102656 states and 144403 transitions. [2023-11-26 10:48:24,022 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-26 10:48:24,022 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102656 states and 144403 transitions. [2023-11-26 10:48:24,238 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 102160 [2023-11-26 10:48:24,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:24,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:24,240 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:24,241 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:24,241 INFO L748 eck$LassoCheckResult]: Stem: 732252#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 732253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 733269#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 733270#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 734157#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 733401#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 732845#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 732846#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 733722#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 733723#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 733845#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 733846#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 732592#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 732593#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 733883#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 733157#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 733158#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 733780#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 733071#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 733072#L1291 assume !(0 == ~M_E~0); 734158#L1291-2 assume !(0 == ~T1_E~0); 734155#L1296-1 assume !(0 == ~T2_E~0); 733226#L1301-1 assume !(0 == ~T3_E~0); 733227#L1306-1 assume !(0 == ~T4_E~0); 733792#L1311-1 assume !(0 == ~T5_E~0); 732428#L1316-1 assume !(0 == ~T6_E~0); 732429#L1321-1 assume !(0 == ~T7_E~0); 733241#L1326-1 assume !(0 == ~T8_E~0); 732249#L1331-1 assume !(0 == ~T9_E~0); 731965#L1336-1 assume !(0 == ~T10_E~0); 731966#L1341-1 assume !(0 == ~T11_E~0); 732036#L1346-1 assume !(0 == ~T12_E~0); 732037#L1351-1 assume !(0 == ~T13_E~0); 732364#L1356-1 assume !(0 == ~E_M~0); 732365#L1361-1 assume !(0 == ~E_1~0); 734064#L1366-1 assume !(0 == ~E_2~0); 732412#L1371-1 assume !(0 == ~E_3~0); 732413#L1376-1 assume !(0 == ~E_4~0); 733299#L1381-1 assume !(0 == ~E_5~0); 733300#L1386-1 assume !(0 == ~E_6~0); 734109#L1391-1 assume !(0 == ~E_7~0); 734137#L1396-1 assume !(0 == ~E_8~0); 733190#L1401-1 assume !(0 == ~E_9~0); 733191#L1406-1 assume !(0 == ~E_10~0); 733498#L1411-1 assume !(0 == ~E_11~0); 733499#L1416-1 assume !(0 == ~E_12~0); 733108#L1421-1 assume !(0 == ~E_13~0); 732616#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 732617#L640 assume !(1 == ~m_pc~0); 733156#L640-2 is_master_triggered_~__retres1~0#1 := 0; 733155#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 733115#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 733116#L1603 assume !(0 != activate_threads_~tmp~1#1); 733144#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 732768#L659 assume !(1 == ~t1_pc~0); 732769#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 733944#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 733642#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 732899#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 732900#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 732917#L678 assume !(1 == ~t2_pc~0); 733978#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 734102#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 732454#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 732455#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 733014#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 733139#L697 assume !(1 == ~t3_pc~0); 733140#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 733279#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 733628#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 733048#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 733049#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 734021#L716 assume !(1 == ~t4_pc~0); 733569#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 732748#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 732110#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 732111#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 732217#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 733584#L735 assume !(1 == ~t5_pc~0); 732185#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 732186#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 732640#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 733615#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 733219#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 733220#L754 assume !(1 == ~t6_pc~0); 733458#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 732860#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 732432#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 732433#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 732832#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 733713#L773 assume !(1 == ~t7_pc~0); 732368#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 732367#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 733258#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 733230#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 733231#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 733291#L792 assume !(1 == ~t8_pc~0); 733469#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 733847#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 733848#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 733223#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 733142#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 733143#L811 assume !(1 == ~t9_pc~0); 733365#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 733927#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 732510#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 732511#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 733152#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 733153#L830 assume !(1 == ~t10_pc~0); 732872#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 732345#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 732346#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 732324#L1683 assume !(0 != activate_threads_~tmp___9~0#1); 732325#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 733733#L849 assume 1 == ~t11_pc~0; 733734#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 732163#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 732164#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 733747#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 733624#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 733625#L868 assume !(1 == ~t12_pc~0); 732998#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 732997#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 732051#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 732052#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 732380#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 732381#L887 assume 1 == ~t13_pc~0; 733630#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 733042#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 733043#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 733703#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 732091#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 732092#L1439 assume !(1 == ~M_E~0); 733215#L1439-2 assume !(1 == ~T1_E~0); 732262#L1444-1 assume !(1 == ~T2_E~0); 732263#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 732774#L1454-1 assume !(1 == ~T4_E~0); 732775#L1459-1 assume !(1 == ~T5_E~0); 733357#L1464-1 assume !(1 == ~T6_E~0); 733358#L1469-1 assume !(1 == ~T7_E~0); 733437#L1474-1 assume !(1 == ~T8_E~0); 733109#L1479-1 assume !(1 == ~T9_E~0); 733110#L1484-1 assume !(1 == ~T10_E~0); 733360#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 732989#L1494-1 assume !(1 == ~T12_E~0); 732990#L1499-1 assume !(1 == ~T13_E~0); 733174#L1504-1 assume !(1 == ~E_M~0); 733175#L1509-1 assume !(1 == ~E_1~0); 733828#L1514-1 assume !(1 == ~E_2~0); 733470#L1519-1 assume !(1 == ~E_3~0); 733471#L1524-1 assume !(1 == ~E_4~0); 734079#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 734080#L1534-1 assume !(1 == ~E_6~0); 732085#L1539-1 assume !(1 == ~E_7~0); 732086#L1544-1 assume !(1 == ~E_8~0); 732509#L1549-1 assume !(1 == ~E_9~0); 734052#L1554-1 assume !(1 == ~E_10~0); 734046#L1559-1 assume !(1 == ~E_11~0); 733873#L1564-1 assume !(1 == ~E_12~0); 733874#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 734074#L1574-1 assume { :end_inline_reset_delta_events } true; 734115#L1940-2 [2023-11-26 10:48:24,242 INFO L750 eck$LassoCheckResult]: Loop: 734115#L1940-2 assume !false; 753717#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 753713#L1266-1 assume !false; 753712#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 753705#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 753697#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 753696#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 753694#L1079 assume !(0 != eval_~tmp~0#1); 753693#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 753692#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 753691#L1291-3 assume !(0 == ~M_E~0); 753690#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 753689#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 753688#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 753687#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 753686#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 753685#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 753684#L1321-3 assume !(0 == ~T7_E~0); 753683#L1326-3 assume !(0 == ~T8_E~0); 753682#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 753681#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 753680#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 753679#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 753678#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 753677#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 753676#L1361-3 assume !(0 == ~E_1~0); 753675#L1366-3 assume !(0 == ~E_2~0); 753674#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 753673#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 753672#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 753671#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 753670#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 753669#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 753668#L1401-3 assume !(0 == ~E_9~0); 753667#L1406-3 assume !(0 == ~E_10~0); 753666#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 753665#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 753664#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 753663#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 753662#L640-45 assume !(1 == ~m_pc~0); 753661#L640-47 is_master_triggered_~__retres1~0#1 := 0; 753659#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 753658#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 753657#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 753656#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 753655#L659-45 assume !(1 == ~t1_pc~0); 753654#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 753653#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 753652#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 753651#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 753650#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 753649#L678-45 assume !(1 == ~t2_pc~0); 753647#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 753646#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 753645#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 753644#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 753643#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 753642#L697-45 assume !(1 == ~t3_pc~0); 753641#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 753639#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 753637#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 753635#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 753633#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 753632#L716-45 assume !(1 == ~t4_pc~0); 753631#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 753630#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 753629#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 753628#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 753627#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 753626#L735-45 assume !(1 == ~t5_pc~0); 753625#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 753623#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 753622#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 753621#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 753620#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 753619#L754-45 assume !(1 == ~t6_pc~0); 753618#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 753617#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 753616#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 753615#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 753614#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 753613#L773-45 assume 1 == ~t7_pc~0; 753611#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 753610#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 753609#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 753608#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 753607#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 753606#L792-45 assume !(1 == ~t8_pc~0); 753605#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 753604#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 753603#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 753602#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 753601#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 753600#L811-45 assume !(1 == ~t9_pc~0); 753599#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 753598#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 753597#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 753596#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 753595#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 753594#L830-45 assume !(1 == ~t10_pc~0); 753593#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 753591#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 753589#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 753587#L1683-45 assume !(0 != activate_threads_~tmp___9~0#1); 753337#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 753335#L849-45 assume 1 == ~t11_pc~0; 753333#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 753329#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 753327#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 753325#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 753323#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 753321#L868-45 assume !(1 == ~t12_pc~0); 753319#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 753315#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 753313#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 753311#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 753309#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 753307#L887-45 assume 1 == ~t13_pc~0; 753305#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 753301#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 753299#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 753297#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 753295#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 753294#L1439-3 assume !(1 == ~M_E~0); 748753#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 753293#L1444-3 assume !(1 == ~T2_E~0); 753292#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 753291#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 753290#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 753289#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 753288#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 753287#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 753286#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 753285#L1484-3 assume !(1 == ~T10_E~0); 753284#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 753283#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 753282#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 753281#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 753280#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 753279#L1514-3 assume !(1 == ~E_2~0); 753278#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 753277#L1524-3 assume !(1 == ~E_4~0); 753276#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 753275#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 753274#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 753273#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 753272#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 753271#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 753270#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 753269#L1564-3 assume !(1 == ~E_12~0); 753268#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 753267#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 753260#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 753252#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 753251#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 753249#L1959 assume !(0 == start_simulation_~tmp~3#1); 753250#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 753793#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 753769#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 753764#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 753759#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 753745#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 753725#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 753721#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 734115#L1940-2 [2023-11-26 10:48:24,243 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:24,243 INFO L85 PathProgramCache]: Analyzing trace with hash -1665183797, now seen corresponding path program 1 times [2023-11-26 10:48:24,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:24,243 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573090336] [2023-11-26 10:48:24,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:24,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:24,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:24,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:24,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:24,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573090336] [2023-11-26 10:48:24,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1573090336] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:24,335 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:24,335 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:24,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [676565239] [2023-11-26 10:48:24,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:24,336 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:24,336 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:24,337 INFO L85 PathProgramCache]: Analyzing trace with hash -1249820349, now seen corresponding path program 1 times [2023-11-26 10:48:24,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:24,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380872666] [2023-11-26 10:48:24,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:24,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:24,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:24,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:24,394 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:24,394 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [380872666] [2023-11-26 10:48:24,394 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [380872666] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:24,394 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:24,394 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:24,395 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293979524] [2023-11-26 10:48:24,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:24,395 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:24,395 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:24,396 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:48:24,396 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:48:24,397 INFO L87 Difference]: Start difference. First operand 102656 states and 144403 transitions. cyclomatic complexity: 41779 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:26,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:26,141 INFO L93 Difference]: Finished difference Result 284539 states and 397897 transitions. [2023-11-26 10:48:26,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 284539 states and 397897 transitions. [2023-11-26 10:48:27,770 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 282896 [2023-11-26 10:48:28,406 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 284539 states to 284539 states and 397897 transitions. [2023-11-26 10:48:28,406 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 284539 [2023-11-26 10:48:28,513 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 284539 [2023-11-26 10:48:28,513 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284539 states and 397897 transitions. [2023-11-26 10:48:28,660 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:48:28,661 INFO L218 hiAutomatonCegarLoop]: Abstraction has 284539 states and 397897 transitions. [2023-11-26 10:48:28,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284539 states and 397897 transitions. [2023-11-26 10:48:31,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284539 to 282747. [2023-11-26 10:48:31,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 282747 states, 282747 states have (on average 1.3991059144747777) internal successors, (395593), 282746 states have internal predecessors, (395593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:33,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 282747 states to 282747 states and 395593 transitions. [2023-11-26 10:48:33,115 INFO L240 hiAutomatonCegarLoop]: Abstraction has 282747 states and 395593 transitions. [2023-11-26 10:48:33,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:48:33,116 INFO L428 stractBuchiCegarLoop]: Abstraction has 282747 states and 395593 transitions. [2023-11-26 10:48:33,116 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-26 10:48:33,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 282747 states and 395593 transitions. [2023-11-26 10:48:33,772 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 281488 [2023-11-26 10:48:33,772 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:48:33,772 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:48:33,775 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:33,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:48:33,775 INFO L748 eck$LassoCheckResult]: Stem: 1119458#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1119459#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1120488#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1120489#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1121332#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 1120619#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1120056#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1120057#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1120917#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1120918#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1121038#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1121039#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1119798#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1119799#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1121073#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1120377#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1120378#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1120975#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1120290#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1120291#L1291 assume !(0 == ~M_E~0); 1121333#L1291-2 assume !(0 == ~T1_E~0); 1121330#L1296-1 assume !(0 == ~T2_E~0); 1120442#L1301-1 assume !(0 == ~T3_E~0); 1120443#L1306-1 assume !(0 == ~T4_E~0); 1120986#L1311-1 assume !(0 == ~T5_E~0); 1119632#L1316-1 assume !(0 == ~T6_E~0); 1119633#L1321-1 assume !(0 == ~T7_E~0); 1120458#L1326-1 assume !(0 == ~T8_E~0); 1119455#L1331-1 assume !(0 == ~T9_E~0); 1119170#L1336-1 assume !(0 == ~T10_E~0); 1119171#L1341-1 assume !(0 == ~T11_E~0); 1119242#L1346-1 assume !(0 == ~T12_E~0); 1119243#L1351-1 assume !(0 == ~T13_E~0); 1119571#L1356-1 assume !(0 == ~E_M~0); 1119572#L1361-1 assume !(0 == ~E_1~0); 1121239#L1366-1 assume !(0 == ~E_2~0); 1119616#L1371-1 assume !(0 == ~E_3~0); 1119617#L1376-1 assume !(0 == ~E_4~0); 1120516#L1381-1 assume !(0 == ~E_5~0); 1120517#L1386-1 assume !(0 == ~E_6~0); 1121282#L1391-1 assume !(0 == ~E_7~0); 1121311#L1396-1 assume !(0 == ~E_8~0); 1120409#L1401-1 assume !(0 == ~E_9~0); 1120410#L1406-1 assume !(0 == ~E_10~0); 1120715#L1411-1 assume !(0 == ~E_11~0); 1120716#L1416-1 assume !(0 == ~E_12~0); 1120327#L1421-1 assume !(0 == ~E_13~0); 1119821#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1119822#L640 assume !(1 == ~m_pc~0); 1120376#L640-2 is_master_triggered_~__retres1~0#1 := 0; 1120375#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1120335#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1120336#L1603 assume !(0 != activate_threads_~tmp~1#1); 1120363#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1119977#L659 assume !(1 == ~t1_pc~0); 1119978#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1121136#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1120850#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1120111#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 1120112#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1120129#L678 assume !(1 == ~t2_pc~0); 1121160#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1121276#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1119659#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1119660#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 1120229#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1120357#L697 assume !(1 == ~t3_pc~0); 1120358#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1120497#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1120839#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1120268#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 1120269#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1121197#L716 assume !(1 == ~t4_pc~0); 1120783#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1119958#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1119317#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1119318#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 1119423#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1120799#L735 assume !(1 == ~t5_pc~0); 1119391#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1119392#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1119849#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1120828#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 1120435#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1120436#L754 assume !(1 == ~t6_pc~0); 1120673#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1120069#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1119636#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1119637#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 1120043#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1120909#L773 assume !(1 == ~t7_pc~0); 1119575#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1119574#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1120476#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1120446#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 1120447#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1120508#L792 assume !(1 == ~t8_pc~0); 1120685#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1121040#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1121041#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1120437#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 1120359#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1120360#L811 assume !(1 == ~t9_pc~0); 1120583#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1121117#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1119714#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1119715#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 1120372#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1120373#L830 assume !(1 == ~t10_pc~0); 1120080#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1119551#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1119552#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1119529#L1683 assume !(0 != activate_threads_~tmp___9~0#1); 1119530#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1120927#L849 assume !(1 == ~t11_pc~0); 1120928#L849-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1119370#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1119371#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1120941#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 1120835#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1120836#L868 assume !(1 == ~t12_pc~0); 1120213#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1120212#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1119257#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1119258#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 1119586#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1119587#L887 assume 1 == ~t13_pc~0; 1120841#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1120262#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1120263#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1120902#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 1119297#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1119298#L1439 assume !(1 == ~M_E~0); 1120431#L1439-2 assume !(1 == ~T1_E~0); 1119468#L1444-1 assume !(1 == ~T2_E~0); 1119469#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1119982#L1454-1 assume !(1 == ~T4_E~0); 1119983#L1459-1 assume !(1 == ~T5_E~0); 1120575#L1464-1 assume !(1 == ~T6_E~0); 1120576#L1469-1 assume !(1 == ~T7_E~0); 1120650#L1474-1 assume !(1 == ~T8_E~0); 1120328#L1479-1 assume !(1 == ~T9_E~0); 1120329#L1484-1 assume !(1 == ~T10_E~0); 1120578#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1120201#L1494-1 assume !(1 == ~T12_E~0); 1120202#L1499-1 assume !(1 == ~T13_E~0); 1120394#L1504-1 assume !(1 == ~E_M~0); 1120395#L1509-1 assume !(1 == ~E_1~0); 1121023#L1514-1 assume !(1 == ~E_2~0); 1120686#L1519-1 assume !(1 == ~E_3~0); 1120687#L1524-1 assume !(1 == ~E_4~0); 1121256#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1121257#L1534-1 assume !(1 == ~E_6~0); 1119292#L1539-1 assume !(1 == ~E_7~0); 1119293#L1544-1 assume !(1 == ~E_8~0); 1119711#L1549-1 assume !(1 == ~E_9~0); 1121229#L1554-1 assume !(1 == ~E_10~0); 1121222#L1559-1 assume !(1 == ~E_11~0); 1121065#L1564-1 assume !(1 == ~E_12~0); 1121066#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1121250#L1574-1 assume { :end_inline_reset_delta_events } true; 1121289#L1940-2 [2023-11-26 10:48:33,776 INFO L750 eck$LassoCheckResult]: Loop: 1121289#L1940-2 assume !false; 1226876#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1226866#L1266-1 assume !false; 1226865#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1226666#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1226653#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1226647#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1226641#L1079 assume !(0 != eval_~tmp~0#1); 1226635#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1226627#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1226618#L1291-3 assume !(0 == ~M_E~0); 1226611#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1226605#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1226599#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1226593#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1226587#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1226577#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1226559#L1321-3 assume !(0 == ~T7_E~0); 1226556#L1326-3 assume !(0 == ~T8_E~0); 1226554#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1226552#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1226550#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1226548#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1226546#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1226544#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1226542#L1361-3 assume !(0 == ~E_1~0); 1226540#L1366-3 assume !(0 == ~E_2~0); 1226537#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1226535#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1226533#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1226531#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1226529#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1226527#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1226525#L1401-3 assume !(0 == ~E_9~0); 1226523#L1406-3 assume !(0 == ~E_10~0); 1226520#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1226507#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1226498#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1226490#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1226101#L640-45 assume 1 == ~m_pc~0; 1226096#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1226094#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1226092#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1226090#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 1226088#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1226086#L659-45 assume !(1 == ~t1_pc~0); 1226084#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 1226081#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1226079#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1226049#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1226040#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1226000#L678-45 assume !(1 == ~t2_pc~0); 1225997#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 1225995#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1225993#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1225991#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1225988#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1225986#L697-45 assume !(1 == ~t3_pc~0); 1225984#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 1225981#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1225979#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1225977#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 1225975#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1225973#L716-45 assume !(1 == ~t4_pc~0); 1225971#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1225969#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1225967#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1225965#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1225962#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1225960#L735-45 assume 1 == ~t5_pc~0; 1225947#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1225935#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1225927#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1225879#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1225860#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1225854#L754-45 assume !(1 == ~t6_pc~0); 1225848#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 1225840#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1225834#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1225828#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1225821#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1225814#L773-45 assume 1 == ~t7_pc~0; 1225806#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1225798#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1225789#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1225781#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1225774#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1225767#L792-45 assume !(1 == ~t8_pc~0); 1225761#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 1225756#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1225750#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1225744#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1225737#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1225731#L811-45 assume !(1 == ~t9_pc~0); 1225725#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 1225718#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1225711#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1225705#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 1225698#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1225248#L830-45 assume 1 == ~t10_pc~0; 1225246#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1225247#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1225250#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1225236#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1225234#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1225232#L849-45 assume !(1 == ~t11_pc~0); 1225231#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 1225227#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1225225#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1225223#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1225222#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1225219#L868-45 assume 1 == ~t12_pc~0; 1225214#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1225210#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1225206#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1225202#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1225198#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1225194#L887-45 assume !(1 == ~t13_pc~0); 1225192#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 1225191#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1225190#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1225189#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1225188#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1225187#L1439-3 assume !(1 == ~M_E~0); 1224498#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1225185#L1444-3 assume !(1 == ~T2_E~0); 1225184#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1225183#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1224978#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1224975#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1224973#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1224971#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1224969#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1224967#L1484-3 assume !(1 == ~T10_E~0); 1224965#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1224963#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1224961#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1224959#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1224957#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1224955#L1514-3 assume !(1 == ~E_2~0); 1224952#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1224939#L1524-3 assume !(1 == ~E_4~0); 1224929#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1224921#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1224915#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1224897#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1224892#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1224887#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1224880#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1224874#L1564-3 assume !(1 == ~E_12~0); 1224869#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1224868#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1224856#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1224844#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1224839#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1224833#L1959 assume !(0 == start_simulation_~tmp~3#1); 1224834#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1226934#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1226923#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1226921#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1226919#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1226918#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1226904#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1226895#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 1121289#L1940-2 [2023-11-26 10:48:33,777 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:33,777 INFO L85 PathProgramCache]: Analyzing trace with hash 736341324, now seen corresponding path program 1 times [2023-11-26 10:48:33,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:33,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116130084] [2023-11-26 10:48:33,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:33,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:33,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:33,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:33,846 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:33,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116130084] [2023-11-26 10:48:33,846 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1116130084] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:33,846 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:33,846 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:48:33,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1411379191] [2023-11-26 10:48:33,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:33,847 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:48:33,847 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:48:33,848 INFO L85 PathProgramCache]: Analyzing trace with hash -38530433, now seen corresponding path program 1 times [2023-11-26 10:48:33,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:48:33,848 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416769440] [2023-11-26 10:48:33,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:48:33,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:48:33,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:48:33,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:48:33,908 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:48:33,908 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416769440] [2023-11-26 10:48:33,908 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416769440] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:48:33,908 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:48:33,908 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:48:33,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [773976336] [2023-11-26 10:48:33,909 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:48:33,909 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:48:33,909 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:48:33,910 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:48:33,910 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:48:33,910 INFO L87 Difference]: Start difference. First operand 282747 states and 395593 transitions. cyclomatic complexity: 112910 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:48:36,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:48:36,508 INFO L93 Difference]: Finished difference Result 543530 states and 758262 transitions. [2023-11-26 10:48:36,508 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 543530 states and 758262 transitions.