./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 10:44:23,146 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 10:44:23,267 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 10:44:23,278 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 10:44:23,279 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 10:44:23,330 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 10:44:23,331 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 10:44:23,332 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 10:44:23,333 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 10:44:23,339 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 10:44:23,341 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 10:44:23,342 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 10:44:23,343 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 10:44:23,345 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 10:44:23,346 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 10:44:23,346 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 10:44:23,347 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 10:44:23,347 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 10:44:23,348 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 10:44:23,349 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 10:44:23,349 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 10:44:23,350 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 10:44:23,350 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 10:44:23,351 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 10:44:23,351 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 10:44:23,352 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 10:44:23,352 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 10:44:23,353 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 10:44:23,353 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 10:44:23,354 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 10:44:23,355 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 10:44:23,356 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 10:44:23,356 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 10:44:23,356 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 10:44:23,357 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 10:44:23,357 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 10:44:23,357 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 10:44:23,358 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 10:44:23,359 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1de07d37d630bd073064bf436fb9512b72ab982b0eaf3fcb1582f689c57482fa [2023-11-26 10:44:23,701 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 10:44:23,739 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 10:44:23,743 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 10:44:23,744 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 10:44:23,745 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 10:44:23,747 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/transmitter.04.cil.c [2023-11-26 10:44:27,051 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 10:44:27,315 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 10:44:27,318 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/sv-benchmarks/c/systemc/transmitter.04.cil.c [2023-11-26 10:44:27,337 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/data/d3b556152/1708748d74304870a0c5c85390b1d376/FLAGf54fce6b2 [2023-11-26 10:44:27,356 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/data/d3b556152/1708748d74304870a0c5c85390b1d376 [2023-11-26 10:44:27,360 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 10:44:27,362 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 10:44:27,363 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 10:44:27,364 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 10:44:27,373 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 10:44:27,378 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:44:27" (1/1) ... [2023-11-26 10:44:27,379 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@abdca8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27, skipping insertion in model container [2023-11-26 10:44:27,380 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:44:27" (1/1) ... [2023-11-26 10:44:27,462 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 10:44:27,721 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:44:27,736 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 10:44:27,782 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:44:27,801 INFO L206 MainTranslator]: Completed translation [2023-11-26 10:44:27,801 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27 WrapperNode [2023-11-26 10:44:27,802 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 10:44:27,803 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 10:44:27,803 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 10:44:27,803 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 10:44:27,811 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27" (1/1) ... [2023-11-26 10:44:27,821 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27" (1/1) ... [2023-11-26 10:44:27,886 INFO L138 Inliner]: procedures = 36, calls = 43, calls flagged for inlining = 38, calls inlined = 71, statements flattened = 976 [2023-11-26 10:44:27,887 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 10:44:27,888 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 10:44:27,888 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 10:44:27,888 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 10:44:27,899 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27" (1/1) ... [2023-11-26 10:44:27,899 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27" (1/1) ... [2023-11-26 10:44:27,904 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27" (1/1) ... [2023-11-26 10:44:27,928 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 10:44:27,928 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27" (1/1) ... [2023-11-26 10:44:27,929 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27" (1/1) ... [2023-11-26 10:44:27,945 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27" (1/1) ... [2023-11-26 10:44:27,958 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27" (1/1) ... [2023-11-26 10:44:27,961 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27" (1/1) ... [2023-11-26 10:44:27,966 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27" (1/1) ... [2023-11-26 10:44:27,974 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 10:44:27,980 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 10:44:27,993 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 10:44:27,993 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 10:44:27,994 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27" (1/1) ... [2023-11-26 10:44:28,001 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 10:44:28,037 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:44:28,058 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 10:44:28,087 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 10:44:28,117 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 10:44:28,117 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 10:44:28,117 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 10:44:28,118 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 10:44:28,210 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 10:44:28,212 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 10:44:29,285 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 10:44:29,323 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 10:44:29,323 INFO L309 CfgBuilder]: Removed 8 assume(true) statements. [2023-11-26 10:44:29,325 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:44:29 BoogieIcfgContainer [2023-11-26 10:44:29,325 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 10:44:29,326 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 10:44:29,327 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 10:44:29,336 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 10:44:29,337 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:44:29,337 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 10:44:27" (1/3) ... [2023-11-26 10:44:29,338 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1ac3b98 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:44:29, skipping insertion in model container [2023-11-26 10:44:29,338 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:44:29,340 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:44:27" (2/3) ... [2023-11-26 10:44:29,343 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1ac3b98 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:44:29, skipping insertion in model container [2023-11-26 10:44:29,343 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:44:29,343 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:44:29" (3/3) ... [2023-11-26 10:44:29,345 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.04.cil.c [2023-11-26 10:44:29,454 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 10:44:29,455 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 10:44:29,455 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 10:44:29,455 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 10:44:29,455 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 10:44:29,455 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 10:44:29,455 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 10:44:29,456 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 10:44:29,463 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 397 states, 396 states have (on average 1.5303030303030303) internal successors, (606), 396 states have internal predecessors, (606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:29,521 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 328 [2023-11-26 10:44:29,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:29,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:29,537 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:29,537 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:29,538 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 10:44:29,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 397 states, 396 states have (on average 1.5303030303030303) internal successors, (606), 396 states have internal predecessors, (606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:29,559 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 328 [2023-11-26 10:44:29,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:29,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:29,564 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:29,564 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:29,576 INFO L748 eck$LassoCheckResult]: Stem: 119#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 330#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 183#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 326#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56#L341true assume !(1 == ~m_i~0);~m_st~0 := 2; 368#L341-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 213#L346-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 117#L351-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 22#L356-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 108#L361-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32#L502true assume !(0 == ~M_E~0); 85#L502-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 16#L507-1true assume !(0 == ~T2_E~0); 57#L512-1true assume !(0 == ~T3_E~0); 316#L517-1true assume !(0 == ~T4_E~0); 10#L522-1true assume !(0 == ~E_1~0); 281#L527-1true assume !(0 == ~E_2~0); 121#L532-1true assume !(0 == ~E_3~0); 360#L537-1true assume !(0 == ~E_4~0); 136#L542-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116#L238true assume 1 == ~m_pc~0; 321#L239true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 192#L249true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102#is_master_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 101#L615true assume !(0 != activate_threads_~tmp~1#1); 199#L615-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91#L257true assume 1 == ~t1_pc~0; 322#L258true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 113#L268true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 189#L623true assume !(0 != activate_threads_~tmp___0~0#1); 23#L623-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 188#L276true assume !(1 == ~t2_pc~0); 283#L276-2true is_transmit2_triggered_~__retres1~2#1 := 0; 341#L287true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 187#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 345#L631true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 358#L631-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100#L295true assume 1 == ~t3_pc~0; 37#L296true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 93#L306true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 324#L639true assume !(0 != activate_threads_~tmp___2~0#1); 319#L639-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 378#L314true assume !(1 == ~t4_pc~0); 349#L314-2true is_transmit4_triggered_~__retres1~4#1 := 0; 143#L325true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 90#L647true assume !(0 != activate_threads_~tmp___3~0#1); 277#L647-2true havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 392#L555true assume !(1 == ~M_E~0); 39#L555-2true assume !(1 == ~T1_E~0); 371#L560-1true assume !(1 == ~T2_E~0); 11#L565-1true assume !(1 == ~T3_E~0); 95#L570-1true assume !(1 == ~T4_E~0); 219#L575-1true assume !(1 == ~E_1~0); 295#L580-1true assume !(1 == ~E_2~0); 129#L585-1true assume 1 == ~E_3~0;~E_3~0 := 2; 29#L590-1true assume !(1 == ~E_4~0); 26#L595-1true assume { :end_inline_reset_delta_events } true; 175#L776-2true [2023-11-26 10:44:29,579 INFO L750 eck$LassoCheckResult]: Loop: 175#L776-2true assume !false; 18#L777true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 272#L477-1true assume false; 54#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 289#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78#L502-3true assume 0 == ~M_E~0;~M_E~0 := 1; 303#L502-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 314#L507-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 55#L512-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 397#L517-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 48#L522-3true assume 0 == ~E_1~0;~E_1~0 := 1; 92#L527-3true assume 0 == ~E_2~0;~E_2~0 := 1; 142#L532-3true assume !(0 == ~E_3~0); 268#L537-3true assume 0 == ~E_4~0;~E_4~0 := 1; 60#L542-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86#L238-15true assume 1 == ~m_pc~0; 9#L239-5true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 311#L249-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50#is_master_triggered_returnLabel#6true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 227#L615-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 155#L615-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 211#L257-15true assume !(1 == ~t1_pc~0); 74#L257-17true is_transmit1_triggered_~__retres1~1#1 := 0; 338#L268-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 246#is_transmit1_triggered_returnLabel#6true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 307#L623-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 315#L623-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 372#L276-15true assume !(1 == ~t2_pc~0); 382#L276-17true is_transmit2_triggered_~__retres1~2#1 := 0; 248#L287-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 367#is_transmit2_triggered_returnLabel#6true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 179#L631-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 290#L631-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24#L295-15true assume !(1 == ~t3_pc~0); 172#L295-17true is_transmit3_triggered_~__retres1~3#1 := 0; 335#L306-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 343#is_transmit3_triggered_returnLabel#6true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 162#L639-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 122#L639-17true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 161#L314-15true assume 1 == ~t4_pc~0; 285#L315-5true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 181#L325-5true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 308#is_transmit4_triggered_returnLabel#6true activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 318#L647-15true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 120#L647-17true havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84#L555-3true assume 1 == ~M_E~0;~M_E~0 := 2; 195#L555-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 42#L560-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 309#L565-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 350#L570-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 291#L575-3true assume !(1 == ~E_1~0); 191#L580-3true assume 1 == ~E_2~0;~E_2~0 := 2; 395#L585-3true assume 1 == ~E_3~0;~E_3~0 := 2; 234#L590-3true assume 1 == ~E_4~0;~E_4~0 := 2; 276#L595-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 163#L374-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 73#L401-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 160#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 99#L795true assume !(0 == start_simulation_~tmp~3#1); 320#L795-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 110#L374-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 273#L401-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 168#L750true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40#L757true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 299#stop_simulation_returnLabel#1true start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 280#L808true assume !(0 != start_simulation_~tmp___0~1#1); 175#L776-2true [2023-11-26 10:44:29,587 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:29,587 INFO L85 PathProgramCache]: Analyzing trace with hash 1110077256, now seen corresponding path program 1 times [2023-11-26 10:44:29,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:29,600 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675221613] [2023-11-26 10:44:29,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:29,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:29,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:29,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:29,895 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:29,895 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [675221613] [2023-11-26 10:44:29,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [675221613] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:29,896 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:29,897 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:29,899 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806880028] [2023-11-26 10:44:29,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:29,906 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:29,906 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:29,907 INFO L85 PathProgramCache]: Analyzing trace with hash -782872547, now seen corresponding path program 1 times [2023-11-26 10:44:29,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:29,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763591668] [2023-11-26 10:44:29,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:29,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:29,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:29,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:29,959 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:29,959 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763591668] [2023-11-26 10:44:29,959 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763591668] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:29,959 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:29,960 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:44:29,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1898642968] [2023-11-26 10:44:29,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:29,962 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:29,963 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:30,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:30,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:30,007 INFO L87 Difference]: Start difference. First operand has 397 states, 396 states have (on average 1.5303030303030303) internal successors, (606), 396 states have internal predecessors, (606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:30,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:30,064 INFO L93 Difference]: Finished difference Result 395 states and 586 transitions. [2023-11-26 10:44:30,065 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 395 states and 586 transitions. [2023-11-26 10:44:30,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-26 10:44:30,084 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 395 states to 389 states and 580 transitions. [2023-11-26 10:44:30,090 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2023-11-26 10:44:30,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2023-11-26 10:44:30,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 580 transitions. [2023-11-26 10:44:30,099 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:30,101 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 580 transitions. [2023-11-26 10:44:30,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 580 transitions. [2023-11-26 10:44:30,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2023-11-26 10:44:30,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4910025706940875) internal successors, (580), 388 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:30,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 580 transitions. [2023-11-26 10:44:30,160 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 580 transitions. [2023-11-26 10:44:30,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:30,166 INFO L428 stractBuchiCegarLoop]: Abstraction has 389 states and 580 transitions. [2023-11-26 10:44:30,166 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 10:44:30,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 580 transitions. [2023-11-26 10:44:30,171 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-26 10:44:30,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:30,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:30,173 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:30,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:30,174 INFO L748 eck$LassoCheckResult]: Stem: 1010#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1011#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1077#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1078#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 910#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 911#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1104#L346-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1008#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 845#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 846#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 865#L502 assume !(0 == ~M_E~0); 866#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 831#L507-1 assume !(0 == ~T2_E~0); 832#L512-1 assume !(0 == ~T3_E~0); 912#L517-1 assume !(0 == ~T4_E~0); 819#L522-1 assume !(0 == ~E_1~0); 820#L527-1 assume !(0 == ~E_2~0); 1013#L532-1 assume !(0 == ~E_3~0); 1014#L537-1 assume !(0 == ~E_4~0); 1029#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1005#L238 assume 1 == ~m_pc~0; 1006#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1052#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 988#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 986#L615 assume !(0 != activate_threads_~tmp~1#1); 987#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 968#L257 assume 1 == ~t1_pc~0; 969#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1003#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 863#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 864#L623 assume !(0 != activate_threads_~tmp___0~0#1); 847#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 848#L276 assume !(1 == ~t2_pc~0); 1082#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1158#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1080#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1081#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1182#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 985#L295 assume 1 == ~t3_pc~0; 877#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 853#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 814#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 815#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1176#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1177#L314 assume !(1 == ~t4_pc~0); 871#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 870#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 902#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 903#L647 assume !(0 != activate_threads_~tmp___3~0#1); 967#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1154#L555 assume !(1 == ~M_E~0); 880#L555-2 assume !(1 == ~T1_E~0); 881#L560-1 assume !(1 == ~T2_E~0); 821#L565-1 assume !(1 == ~T3_E~0); 822#L570-1 assume !(1 == ~T4_E~0); 974#L575-1 assume !(1 == ~E_1~0); 1109#L580-1 assume !(1 == ~E_2~0); 1021#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 860#L590-1 assume !(1 == ~E_4~0); 854#L595-1 assume { :end_inline_reset_delta_events } true; 855#L776-2 [2023-11-26 10:44:30,175 INFO L750 eck$LassoCheckResult]: Loop: 855#L776-2 assume !false; 836#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 837#L477-1 assume !false; 1127#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1128#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 956#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1089#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1093#L416 assume !(0 != eval_~tmp~0#1); 906#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 907#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 948#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 949#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1168#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 908#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 909#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 896#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 897#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 971#L532-3 assume !(0 == ~E_3~0); 1037#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 916#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 917#L238-15 assume 1 == ~m_pc~0; 816#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 817#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 900#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 901#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1047#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1048#L257-15 assume 1 == ~t1_pc~0; 1057#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 942#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1132#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1133#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1169#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1175#L276-15 assume 1 == ~t2_pc~0; 1143#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1138#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1139#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1070#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1071#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 849#L295-15 assume 1 == ~t3_pc~0; 850#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1065#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1179#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1055#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1015#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1016#L314-15 assume !(1 == ~t4_pc~0); 1053#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 1074#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1075#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1170#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1012#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 961#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 962#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 887#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 888#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1171#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1161#L575-3 assume !(1 == ~E_1~0); 1085#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1086#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1123#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1124#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1056#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 841#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 940#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 983#L795 assume !(0 == start_simulation_~tmp~3#1); 984#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 999#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1000#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 861#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 862#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 882#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 883#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1157#L808 assume !(0 != start_simulation_~tmp___0~1#1); 855#L776-2 [2023-11-26 10:44:30,176 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:30,177 INFO L85 PathProgramCache]: Analyzing trace with hash 1069402506, now seen corresponding path program 1 times [2023-11-26 10:44:30,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:30,177 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978448690] [2023-11-26 10:44:30,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:30,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:30,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:30,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:30,256 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:30,256 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [978448690] [2023-11-26 10:44:30,257 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [978448690] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:30,257 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:30,257 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:30,257 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396414686] [2023-11-26 10:44:30,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:30,258 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:30,258 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:30,259 INFO L85 PathProgramCache]: Analyzing trace with hash -1797968696, now seen corresponding path program 1 times [2023-11-26 10:44:30,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:30,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2118529300] [2023-11-26 10:44:30,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:30,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:30,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:30,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:30,411 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:30,412 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2118529300] [2023-11-26 10:44:30,412 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2118529300] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:30,413 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:30,413 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:30,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [923477515] [2023-11-26 10:44:30,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:30,417 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:30,417 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:30,418 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:30,418 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:30,419 INFO L87 Difference]: Start difference. First operand 389 states and 580 transitions. cyclomatic complexity: 192 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:30,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:30,457 INFO L93 Difference]: Finished difference Result 389 states and 579 transitions. [2023-11-26 10:44:30,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 579 transitions. [2023-11-26 10:44:30,463 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-26 10:44:30,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 579 transitions. [2023-11-26 10:44:30,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2023-11-26 10:44:30,472 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2023-11-26 10:44:30,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 579 transitions. [2023-11-26 10:44:30,481 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:30,482 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 579 transitions. [2023-11-26 10:44:30,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 579 transitions. [2023-11-26 10:44:30,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2023-11-26 10:44:30,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4884318766066837) internal successors, (579), 388 states have internal predecessors, (579), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:30,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 579 transitions. [2023-11-26 10:44:30,506 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 579 transitions. [2023-11-26 10:44:30,507 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:30,507 INFO L428 stractBuchiCegarLoop]: Abstraction has 389 states and 579 transitions. [2023-11-26 10:44:30,508 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 10:44:30,508 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 579 transitions. [2023-11-26 10:44:30,511 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-26 10:44:30,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:30,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:30,513 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:30,513 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:30,514 INFO L748 eck$LassoCheckResult]: Stem: 1795#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1796#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1862#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1863#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1695#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 1696#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1889#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1793#L351-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1630#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1631#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1650#L502 assume !(0 == ~M_E~0); 1651#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1616#L507-1 assume !(0 == ~T2_E~0); 1617#L512-1 assume !(0 == ~T3_E~0); 1697#L517-1 assume !(0 == ~T4_E~0); 1604#L522-1 assume !(0 == ~E_1~0); 1605#L527-1 assume !(0 == ~E_2~0); 1798#L532-1 assume !(0 == ~E_3~0); 1799#L537-1 assume !(0 == ~E_4~0); 1814#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1790#L238 assume 1 == ~m_pc~0; 1791#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1837#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1773#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1771#L615 assume !(0 != activate_threads_~tmp~1#1); 1772#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1753#L257 assume 1 == ~t1_pc~0; 1754#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1788#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1648#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1649#L623 assume !(0 != activate_threads_~tmp___0~0#1); 1632#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1633#L276 assume !(1 == ~t2_pc~0); 1867#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1943#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1865#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1866#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1967#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1770#L295 assume 1 == ~t3_pc~0; 1662#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1638#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1599#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1600#L639 assume !(0 != activate_threads_~tmp___2~0#1); 1961#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1962#L314 assume !(1 == ~t4_pc~0); 1656#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1655#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1687#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1688#L647 assume !(0 != activate_threads_~tmp___3~0#1); 1752#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1939#L555 assume !(1 == ~M_E~0); 1665#L555-2 assume !(1 == ~T1_E~0); 1666#L560-1 assume !(1 == ~T2_E~0); 1606#L565-1 assume !(1 == ~T3_E~0); 1607#L570-1 assume !(1 == ~T4_E~0); 1759#L575-1 assume !(1 == ~E_1~0); 1894#L580-1 assume !(1 == ~E_2~0); 1806#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1645#L590-1 assume !(1 == ~E_4~0); 1639#L595-1 assume { :end_inline_reset_delta_events } true; 1640#L776-2 [2023-11-26 10:44:30,514 INFO L750 eck$LassoCheckResult]: Loop: 1640#L776-2 assume !false; 1621#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1622#L477-1 assume !false; 1912#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1913#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1741#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1874#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1878#L416 assume !(0 != eval_~tmp~0#1); 1691#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1692#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1733#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1734#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1953#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1693#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1694#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1681#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1682#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1756#L532-3 assume !(0 == ~E_3~0); 1822#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1701#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1702#L238-15 assume 1 == ~m_pc~0; 1601#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1602#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1685#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1686#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1832#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1833#L257-15 assume 1 == ~t1_pc~0; 1842#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1727#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1917#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1918#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1954#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1960#L276-15 assume 1 == ~t2_pc~0; 1928#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1923#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1924#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1855#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1856#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1634#L295-15 assume 1 == ~t3_pc~0; 1635#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1850#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1964#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1840#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1800#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1801#L314-15 assume !(1 == ~t4_pc~0); 1838#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 1859#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1860#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1955#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1797#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1746#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1747#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1672#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1673#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1956#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1946#L575-3 assume !(1 == ~E_1~0); 1870#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1871#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1908#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1909#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1841#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1626#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1725#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1768#L795 assume !(0 == start_simulation_~tmp~3#1); 1769#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1784#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1785#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1646#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1647#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1667#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1668#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1942#L808 assume !(0 != start_simulation_~tmp___0~1#1); 1640#L776-2 [2023-11-26 10:44:30,515 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:30,515 INFO L85 PathProgramCache]: Analyzing trace with hash 193383500, now seen corresponding path program 1 times [2023-11-26 10:44:30,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:30,516 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449472116] [2023-11-26 10:44:30,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:30,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:30,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:30,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:30,585 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:30,585 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [449472116] [2023-11-26 10:44:30,585 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [449472116] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:30,586 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:30,586 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:30,587 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [450891697] [2023-11-26 10:44:30,587 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:30,587 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:30,588 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:30,588 INFO L85 PathProgramCache]: Analyzing trace with hash -1797968696, now seen corresponding path program 2 times [2023-11-26 10:44:30,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:30,588 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [375303811] [2023-11-26 10:44:30,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:30,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:30,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:30,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:30,702 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:30,702 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [375303811] [2023-11-26 10:44:30,703 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [375303811] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:30,703 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:30,703 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:30,703 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988848030] [2023-11-26 10:44:30,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:30,706 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:30,706 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:30,707 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:30,707 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:30,707 INFO L87 Difference]: Start difference. First operand 389 states and 579 transitions. cyclomatic complexity: 191 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:30,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:30,725 INFO L93 Difference]: Finished difference Result 389 states and 578 transitions. [2023-11-26 10:44:30,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 578 transitions. [2023-11-26 10:44:30,731 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-26 10:44:30,735 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 578 transitions. [2023-11-26 10:44:30,735 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2023-11-26 10:44:30,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2023-11-26 10:44:30,736 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 578 transitions. [2023-11-26 10:44:30,738 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:30,738 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 578 transitions. [2023-11-26 10:44:30,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 578 transitions. [2023-11-26 10:44:30,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2023-11-26 10:44:30,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4858611825192802) internal successors, (578), 388 states have internal predecessors, (578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:30,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 578 transitions. [2023-11-26 10:44:30,805 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 578 transitions. [2023-11-26 10:44:30,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:30,808 INFO L428 stractBuchiCegarLoop]: Abstraction has 389 states and 578 transitions. [2023-11-26 10:44:30,809 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 10:44:30,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 578 transitions. [2023-11-26 10:44:30,813 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-26 10:44:30,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:30,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:30,822 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:30,822 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:30,823 INFO L748 eck$LassoCheckResult]: Stem: 2580#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 2581#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2647#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2648#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2480#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 2481#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2674#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2578#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2415#L356-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2416#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2435#L502 assume !(0 == ~M_E~0); 2436#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2404#L507-1 assume !(0 == ~T2_E~0); 2405#L512-1 assume !(0 == ~T3_E~0); 2483#L517-1 assume !(0 == ~T4_E~0); 2391#L522-1 assume !(0 == ~E_1~0); 2392#L527-1 assume !(0 == ~E_2~0); 2583#L532-1 assume !(0 == ~E_3~0); 2584#L537-1 assume !(0 == ~E_4~0); 2599#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2575#L238 assume 1 == ~m_pc~0; 2576#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2622#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2558#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2556#L615 assume !(0 != activate_threads_~tmp~1#1); 2557#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2538#L257 assume 1 == ~t1_pc~0; 2539#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2574#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2433#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2434#L623 assume !(0 != activate_threads_~tmp___0~0#1); 2417#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2418#L276 assume !(1 == ~t2_pc~0); 2652#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2728#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2650#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2651#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2753#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2555#L295 assume 1 == ~t3_pc~0; 2447#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2423#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2384#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2385#L639 assume !(0 != activate_threads_~tmp___2~0#1); 2746#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2747#L314 assume !(1 == ~t4_pc~0); 2441#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2440#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2473#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2474#L647 assume !(0 != activate_threads_~tmp___3~0#1); 2537#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2724#L555 assume !(1 == ~M_E~0); 2450#L555-2 assume !(1 == ~T1_E~0); 2451#L560-1 assume !(1 == ~T2_E~0); 2393#L565-1 assume !(1 == ~T3_E~0); 2394#L570-1 assume !(1 == ~T4_E~0); 2544#L575-1 assume !(1 == ~E_1~0); 2679#L580-1 assume !(1 == ~E_2~0); 2592#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2432#L590-1 assume !(1 == ~E_4~0); 2424#L595-1 assume { :end_inline_reset_delta_events } true; 2425#L776-2 [2023-11-26 10:44:30,825 INFO L750 eck$LassoCheckResult]: Loop: 2425#L776-2 assume !false; 2406#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2407#L477-1 assume !false; 2697#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2698#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2526#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2659#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2663#L416 assume !(0 != eval_~tmp~0#1); 2476#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2477#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2518#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2519#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2738#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2478#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2479#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2466#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2467#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2541#L532-3 assume !(0 == ~E_3~0); 2607#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2486#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2487#L238-15 assume 1 == ~m_pc~0; 2386#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2387#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2470#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2471#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2617#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2618#L257-15 assume 1 == ~t1_pc~0; 2627#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2512#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2702#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2703#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2739#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2745#L276-15 assume 1 == ~t2_pc~0; 2713#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2708#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2709#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2640#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2641#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2419#L295-15 assume 1 == ~t3_pc~0; 2420#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2635#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2749#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2625#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2585#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2586#L314-15 assume 1 == ~t4_pc~0; 2624#L315-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2644#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2645#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2740#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2582#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2531#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2532#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2457#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2458#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2741#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2731#L575-3 assume !(1 == ~E_1~0); 2655#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2656#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2693#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2694#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2626#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2411#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2510#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2553#L795 assume !(0 == start_simulation_~tmp~3#1); 2554#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2569#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2570#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2430#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2431#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2452#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2453#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2727#L808 assume !(0 != start_simulation_~tmp___0~1#1); 2425#L776-2 [2023-11-26 10:44:30,826 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:30,826 INFO L85 PathProgramCache]: Analyzing trace with hash -250517174, now seen corresponding path program 1 times [2023-11-26 10:44:30,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:30,826 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1500668170] [2023-11-26 10:44:30,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:30,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:30,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:30,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:30,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:30,899 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1500668170] [2023-11-26 10:44:30,899 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1500668170] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:30,900 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:30,900 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:30,903 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2027160354] [2023-11-26 10:44:30,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:30,904 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:30,905 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:30,905 INFO L85 PathProgramCache]: Analyzing trace with hash -1489529687, now seen corresponding path program 1 times [2023-11-26 10:44:30,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:30,905 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578478953] [2023-11-26 10:44:30,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:30,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:30,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:30,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:30,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:30,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [578478953] [2023-11-26 10:44:30,975 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [578478953] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:30,975 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:30,975 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:30,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [322070592] [2023-11-26 10:44:30,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:30,976 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:30,976 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:30,977 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:30,977 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:30,977 INFO L87 Difference]: Start difference. First operand 389 states and 578 transitions. cyclomatic complexity: 190 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:30,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:30,999 INFO L93 Difference]: Finished difference Result 389 states and 577 transitions. [2023-11-26 10:44:30,999 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 577 transitions. [2023-11-26 10:44:31,002 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-26 10:44:31,006 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 577 transitions. [2023-11-26 10:44:31,006 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2023-11-26 10:44:31,007 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2023-11-26 10:44:31,007 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 577 transitions. [2023-11-26 10:44:31,008 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:31,008 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 577 transitions. [2023-11-26 10:44:31,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 577 transitions. [2023-11-26 10:44:31,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2023-11-26 10:44:31,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4832904884318765) internal successors, (577), 388 states have internal predecessors, (577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:31,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 577 transitions. [2023-11-26 10:44:31,029 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 577 transitions. [2023-11-26 10:44:31,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:31,031 INFO L428 stractBuchiCegarLoop]: Abstraction has 389 states and 577 transitions. [2023-11-26 10:44:31,031 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 10:44:31,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 577 transitions. [2023-11-26 10:44:31,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-26 10:44:31,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:31,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:31,036 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:31,042 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:31,042 INFO L748 eck$LassoCheckResult]: Stem: 3365#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3366#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3432#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3433#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3265#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 3266#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3459#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3363#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3200#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3201#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3220#L502 assume !(0 == ~M_E~0); 3221#L502-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3186#L507-1 assume !(0 == ~T2_E~0); 3187#L512-1 assume !(0 == ~T3_E~0); 3267#L517-1 assume !(0 == ~T4_E~0); 3174#L522-1 assume !(0 == ~E_1~0); 3175#L527-1 assume !(0 == ~E_2~0); 3368#L532-1 assume !(0 == ~E_3~0); 3369#L537-1 assume !(0 == ~E_4~0); 3384#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3360#L238 assume 1 == ~m_pc~0; 3361#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3407#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3343#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3341#L615 assume !(0 != activate_threads_~tmp~1#1); 3342#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3323#L257 assume 1 == ~t1_pc~0; 3324#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3359#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3218#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3219#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3202#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3203#L276 assume !(1 == ~t2_pc~0); 3437#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3513#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3435#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3436#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3537#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3340#L295 assume 1 == ~t3_pc~0; 3232#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3208#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3169#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3170#L639 assume !(0 != activate_threads_~tmp___2~0#1); 3531#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3532#L314 assume !(1 == ~t4_pc~0); 3226#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3225#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3258#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3259#L647 assume !(0 != activate_threads_~tmp___3~0#1); 3322#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3509#L555 assume !(1 == ~M_E~0); 3235#L555-2 assume !(1 == ~T1_E~0); 3236#L560-1 assume !(1 == ~T2_E~0); 3176#L565-1 assume !(1 == ~T3_E~0); 3177#L570-1 assume !(1 == ~T4_E~0); 3329#L575-1 assume !(1 == ~E_1~0); 3464#L580-1 assume !(1 == ~E_2~0); 3376#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3217#L590-1 assume !(1 == ~E_4~0); 3209#L595-1 assume { :end_inline_reset_delta_events } true; 3210#L776-2 [2023-11-26 10:44:31,043 INFO L750 eck$LassoCheckResult]: Loop: 3210#L776-2 assume !false; 3191#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3192#L477-1 assume !false; 3482#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3483#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3311#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3446#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3448#L416 assume !(0 != eval_~tmp~0#1); 3261#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3262#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3303#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3304#L502-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3523#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3263#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3264#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3251#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3252#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3326#L532-3 assume !(0 == ~E_3~0); 3392#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3271#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3272#L238-15 assume 1 == ~m_pc~0; 3171#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3172#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3255#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3256#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3402#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3403#L257-15 assume !(1 == ~t1_pc~0); 3296#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3297#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3489#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3490#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3524#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3530#L276-15 assume 1 == ~t2_pc~0; 3498#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3493#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3494#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3427#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3428#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3204#L295-15 assume 1 == ~t3_pc~0; 3205#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3420#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3534#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3410#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3370#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3371#L314-15 assume !(1 == ~t4_pc~0); 3408#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 3425#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3426#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3525#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3367#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3316#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3317#L555-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3242#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3243#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3526#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3516#L575-3 assume !(1 == ~E_1~0); 3440#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3441#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3478#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3479#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3411#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3196#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3295#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3338#L795 assume !(0 == start_simulation_~tmp~3#1); 3339#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3353#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3354#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3215#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 3216#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3237#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3238#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3512#L808 assume !(0 != start_simulation_~tmp___0~1#1); 3210#L776-2 [2023-11-26 10:44:31,043 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:31,044 INFO L85 PathProgramCache]: Analyzing trace with hash -1788857204, now seen corresponding path program 1 times [2023-11-26 10:44:31,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:31,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800757115] [2023-11-26 10:44:31,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:31,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:31,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:31,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:31,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:31,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [800757115] [2023-11-26 10:44:31,129 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [800757115] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:31,130 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:31,130 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:44:31,130 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [827033466] [2023-11-26 10:44:31,130 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:31,130 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:31,131 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:31,131 INFO L85 PathProgramCache]: Analyzing trace with hash 1188993831, now seen corresponding path program 1 times [2023-11-26 10:44:31,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:31,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [328484130] [2023-11-26 10:44:31,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:31,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:31,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:31,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:31,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:31,193 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [328484130] [2023-11-26 10:44:31,193 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [328484130] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:31,194 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:31,194 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:31,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [621237343] [2023-11-26 10:44:31,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:31,195 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:31,195 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:31,195 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:31,196 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:31,196 INFO L87 Difference]: Start difference. First operand 389 states and 577 transitions. cyclomatic complexity: 189 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:31,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:31,219 INFO L93 Difference]: Finished difference Result 389 states and 572 transitions. [2023-11-26 10:44:31,219 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 389 states and 572 transitions. [2023-11-26 10:44:31,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-26 10:44:31,227 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 389 states to 389 states and 572 transitions. [2023-11-26 10:44:31,227 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2023-11-26 10:44:31,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2023-11-26 10:44:31,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 389 states and 572 transitions. [2023-11-26 10:44:31,229 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:31,229 INFO L218 hiAutomatonCegarLoop]: Abstraction has 389 states and 572 transitions. [2023-11-26 10:44:31,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states and 572 transitions. [2023-11-26 10:44:31,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2023-11-26 10:44:31,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4704370179948587) internal successors, (572), 388 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:31,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 572 transitions. [2023-11-26 10:44:31,240 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389 states and 572 transitions. [2023-11-26 10:44:31,241 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:31,242 INFO L428 stractBuchiCegarLoop]: Abstraction has 389 states and 572 transitions. [2023-11-26 10:44:31,242 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 10:44:31,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 572 transitions. [2023-11-26 10:44:31,245 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 324 [2023-11-26 10:44:31,245 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:31,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:31,247 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:31,247 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:31,247 INFO L748 eck$LassoCheckResult]: Stem: 4150#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 4151#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4217#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4218#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4050#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 4051#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4244#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4148#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3985#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3986#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4005#L502 assume !(0 == ~M_E~0); 4006#L502-2 assume !(0 == ~T1_E~0); 3971#L507-1 assume !(0 == ~T2_E~0); 3972#L512-1 assume !(0 == ~T3_E~0); 4052#L517-1 assume !(0 == ~T4_E~0); 3959#L522-1 assume !(0 == ~E_1~0); 3960#L527-1 assume !(0 == ~E_2~0); 4153#L532-1 assume !(0 == ~E_3~0); 4154#L537-1 assume !(0 == ~E_4~0); 4169#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4145#L238 assume 1 == ~m_pc~0; 4146#L239 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4192#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4128#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4126#L615 assume !(0 != activate_threads_~tmp~1#1); 4127#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4108#L257 assume 1 == ~t1_pc~0; 4109#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4143#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4003#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4004#L623 assume !(0 != activate_threads_~tmp___0~0#1); 3987#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3988#L276 assume !(1 == ~t2_pc~0); 4222#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4298#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4220#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4221#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4322#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4125#L295 assume 1 == ~t3_pc~0; 4017#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3993#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3954#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3955#L639 assume !(0 != activate_threads_~tmp___2~0#1); 4316#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4317#L314 assume !(1 == ~t4_pc~0); 4011#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4010#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4042#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4043#L647 assume !(0 != activate_threads_~tmp___3~0#1); 4107#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4294#L555 assume !(1 == ~M_E~0); 4020#L555-2 assume !(1 == ~T1_E~0); 4021#L560-1 assume !(1 == ~T2_E~0); 3961#L565-1 assume !(1 == ~T3_E~0); 3962#L570-1 assume !(1 == ~T4_E~0); 4114#L575-1 assume !(1 == ~E_1~0); 4249#L580-1 assume !(1 == ~E_2~0); 4161#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4000#L590-1 assume !(1 == ~E_4~0); 3994#L595-1 assume { :end_inline_reset_delta_events } true; 3995#L776-2 [2023-11-26 10:44:31,248 INFO L750 eck$LassoCheckResult]: Loop: 3995#L776-2 assume !false; 3976#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3977#L477-1 assume !false; 4267#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4268#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4096#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4229#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4233#L416 assume !(0 != eval_~tmp~0#1); 4046#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4047#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4088#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4089#L502-5 assume !(0 == ~T1_E~0); 4308#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4048#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4049#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4036#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4037#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4111#L532-3 assume !(0 == ~E_3~0); 4177#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4056#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4057#L238-15 assume 1 == ~m_pc~0; 3956#L239-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3957#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4040#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4041#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4187#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4188#L257-15 assume !(1 == ~t1_pc~0); 4081#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 4082#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4272#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4273#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4309#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4315#L276-15 assume 1 == ~t2_pc~0; 4283#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4278#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4279#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4210#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4211#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3989#L295-15 assume 1 == ~t3_pc~0; 3990#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4205#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4319#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4195#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4155#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4156#L314-15 assume !(1 == ~t4_pc~0); 4193#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 4214#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4215#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4310#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4152#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4101#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4102#L555-5 assume !(1 == ~T1_E~0); 4027#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4028#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4311#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4301#L575-3 assume !(1 == ~E_1~0); 4225#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4226#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4263#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4264#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4196#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3981#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4080#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4123#L795 assume !(0 == start_simulation_~tmp~3#1); 4124#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4139#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4140#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4001#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 4002#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4022#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4023#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4297#L808 assume !(0 != start_simulation_~tmp___0~1#1); 3995#L776-2 [2023-11-26 10:44:31,249 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:31,249 INFO L85 PathProgramCache]: Analyzing trace with hash -1804375922, now seen corresponding path program 1 times [2023-11-26 10:44:31,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:31,249 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896905883] [2023-11-26 10:44:31,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:31,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:31,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:31,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:31,298 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:31,298 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [896905883] [2023-11-26 10:44:31,298 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [896905883] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:31,299 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:31,299 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:44:31,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193866594] [2023-11-26 10:44:31,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:31,300 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:31,300 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:31,300 INFO L85 PathProgramCache]: Analyzing trace with hash -721696981, now seen corresponding path program 1 times [2023-11-26 10:44:31,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:31,301 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894866623] [2023-11-26 10:44:31,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:31,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:31,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:31,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:31,364 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:31,365 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894866623] [2023-11-26 10:44:31,365 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [894866623] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:31,365 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:31,365 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:31,365 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463465928] [2023-11-26 10:44:31,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:31,366 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:31,366 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:31,367 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:31,367 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:31,367 INFO L87 Difference]: Start difference. First operand 389 states and 572 transitions. cyclomatic complexity: 184 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:31,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:31,430 INFO L93 Difference]: Finished difference Result 705 states and 1024 transitions. [2023-11-26 10:44:31,430 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 705 states and 1024 transitions. [2023-11-26 10:44:31,436 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 639 [2023-11-26 10:44:31,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 705 states to 705 states and 1024 transitions. [2023-11-26 10:44:31,443 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 705 [2023-11-26 10:44:31,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 705 [2023-11-26 10:44:31,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 705 states and 1024 transitions. [2023-11-26 10:44:31,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:31,445 INFO L218 hiAutomatonCegarLoop]: Abstraction has 705 states and 1024 transitions. [2023-11-26 10:44:31,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 705 states and 1024 transitions. [2023-11-26 10:44:31,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 705 to 669. [2023-11-26 10:44:31,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 669 states, 669 states have (on average 1.4573991031390134) internal successors, (975), 668 states have internal predecessors, (975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:31,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 669 states to 669 states and 975 transitions. [2023-11-26 10:44:31,463 INFO L240 hiAutomatonCegarLoop]: Abstraction has 669 states and 975 transitions. [2023-11-26 10:44:31,464 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:31,465 INFO L428 stractBuchiCegarLoop]: Abstraction has 669 states and 975 transitions. [2023-11-26 10:44:31,465 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 10:44:31,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 669 states and 975 transitions. [2023-11-26 10:44:31,470 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 603 [2023-11-26 10:44:31,470 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:31,470 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:31,471 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:31,471 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:31,472 INFO L748 eck$LassoCheckResult]: Stem: 5252#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 5253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5322#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5323#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5151#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 5152#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5350#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5250#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5086#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5087#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5106#L502 assume !(0 == ~M_E~0); 5107#L502-2 assume !(0 == ~T1_E~0); 5072#L507-1 assume !(0 == ~T2_E~0); 5073#L512-1 assume !(0 == ~T3_E~0); 5153#L517-1 assume !(0 == ~T4_E~0); 5060#L522-1 assume !(0 == ~E_1~0); 5061#L527-1 assume !(0 == ~E_2~0); 5255#L532-1 assume !(0 == ~E_3~0); 5256#L537-1 assume !(0 == ~E_4~0); 5274#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5248#L238 assume !(1 == ~m_pc~0); 5249#L238-2 is_master_triggered_~__retres1~0#1 := 0; 5297#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5230#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5228#L615 assume !(0 != activate_threads_~tmp~1#1); 5229#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5211#L257 assume 1 == ~t1_pc~0; 5212#L258 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5245#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5104#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5105#L623 assume !(0 != activate_threads_~tmp___0~0#1); 5088#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5089#L276 assume !(1 == ~t2_pc~0); 5327#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5409#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5325#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5326#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5434#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5227#L295 assume 1 == ~t3_pc~0; 5118#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5094#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5055#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5056#L639 assume !(0 != activate_threads_~tmp___2~0#1); 5427#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5428#L314 assume !(1 == ~t4_pc~0); 5112#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5111#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5143#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5144#L647 assume !(0 != activate_threads_~tmp___3~0#1); 5210#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5405#L555 assume !(1 == ~M_E~0); 5121#L555-2 assume !(1 == ~T1_E~0); 5122#L560-1 assume !(1 == ~T2_E~0); 5062#L565-1 assume !(1 == ~T3_E~0); 5063#L570-1 assume !(1 == ~T4_E~0); 5217#L575-1 assume !(1 == ~E_1~0); 5355#L580-1 assume !(1 == ~E_2~0); 5266#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5101#L590-1 assume !(1 == ~E_4~0); 5095#L595-1 assume { :end_inline_reset_delta_events } true; 5096#L776-2 [2023-11-26 10:44:31,472 INFO L750 eck$LassoCheckResult]: Loop: 5096#L776-2 assume !false; 5077#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5078#L477-1 assume !false; 5373#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5374#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5198#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5334#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5338#L416 assume !(0 != eval_~tmp~0#1); 5344#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5703#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5701#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5700#L502-5 assume !(0 == ~T1_E~0); 5699#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5697#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5696#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5695#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5694#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5693#L532-3 assume !(0 == ~E_3~0); 5692#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5157#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5158#L238-15 assume !(1 == ~m_pc~0); 5205#L238-17 is_master_triggered_~__retres1~0#1 := 0; 5246#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5141#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5142#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5292#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5293#L257-15 assume 1 == ~t1_pc~0; 5302#L258-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5184#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5378#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5379#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5420#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5425#L276-15 assume 1 == ~t2_pc~0; 5390#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5385#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5386#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5315#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5316#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5090#L295-15 assume 1 == ~t3_pc~0; 5091#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5310#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5431#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5300#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5257#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5258#L314-15 assume !(1 == ~t4_pc~0); 5298#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 5319#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5320#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5421#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5254#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5203#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5204#L555-5 assume !(1 == ~T1_E~0); 5128#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5129#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5422#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5412#L575-3 assume !(1 == ~E_1~0); 5330#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5331#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5369#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5370#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5301#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5082#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5182#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5225#L795 assume !(0 == start_simulation_~tmp~3#1); 5226#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5241#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5242#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5102#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 5103#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5123#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5124#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5408#L808 assume !(0 != start_simulation_~tmp___0~1#1); 5096#L776-2 [2023-11-26 10:44:31,473 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:31,473 INFO L85 PathProgramCache]: Analyzing trace with hash -1404384723, now seen corresponding path program 1 times [2023-11-26 10:44:31,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:31,474 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [106669685] [2023-11-26 10:44:31,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:31,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:31,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:31,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:31,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:31,512 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [106669685] [2023-11-26 10:44:31,512 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [106669685] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:31,512 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:31,512 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:44:31,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137447463] [2023-11-26 10:44:31,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:31,513 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:31,513 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:31,514 INFO L85 PathProgramCache]: Analyzing trace with hash -115260437, now seen corresponding path program 1 times [2023-11-26 10:44:31,514 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:31,514 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746193826] [2023-11-26 10:44:31,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:31,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:31,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:31,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:31,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:31,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1746193826] [2023-11-26 10:44:31,549 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1746193826] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:31,550 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:31,550 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:31,550 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790911683] [2023-11-26 10:44:31,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:31,550 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:31,551 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:31,551 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:31,551 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:31,552 INFO L87 Difference]: Start difference. First operand 669 states and 975 transitions. cyclomatic complexity: 308 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:31,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:31,606 INFO L93 Difference]: Finished difference Result 1189 states and 1721 transitions. [2023-11-26 10:44:31,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1189 states and 1721 transitions. [2023-11-26 10:44:31,617 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1118 [2023-11-26 10:44:31,627 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1189 states to 1189 states and 1721 transitions. [2023-11-26 10:44:31,627 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1189 [2023-11-26 10:44:31,628 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1189 [2023-11-26 10:44:31,629 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1189 states and 1721 transitions. [2023-11-26 10:44:31,631 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:31,631 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1189 states and 1721 transitions. [2023-11-26 10:44:31,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1189 states and 1721 transitions. [2023-11-26 10:44:31,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1189 to 1185. [2023-11-26 10:44:31,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.448945147679325) internal successors, (1717), 1184 states have internal predecessors, (1717), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:31,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1717 transitions. [2023-11-26 10:44:31,659 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1717 transitions. [2023-11-26 10:44:31,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:31,661 INFO L428 stractBuchiCegarLoop]: Abstraction has 1185 states and 1717 transitions. [2023-11-26 10:44:31,661 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 10:44:31,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1717 transitions. [2023-11-26 10:44:31,668 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1114 [2023-11-26 10:44:31,668 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:31,668 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:31,669 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:31,670 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:31,670 INFO L748 eck$LassoCheckResult]: Stem: 7117#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 7118#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7195#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7196#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7016#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 7017#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7229#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7115#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6951#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6952#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6971#L502 assume !(0 == ~M_E~0); 6972#L502-2 assume !(0 == ~T1_E~0); 6940#L507-1 assume !(0 == ~T2_E~0); 6941#L512-1 assume !(0 == ~T3_E~0); 7019#L517-1 assume !(0 == ~T4_E~0); 6927#L522-1 assume !(0 == ~E_1~0); 6928#L527-1 assume !(0 == ~E_2~0); 7120#L532-1 assume !(0 == ~E_3~0); 7121#L537-1 assume !(0 == ~E_4~0); 7140#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7113#L238 assume !(1 == ~m_pc~0); 7114#L238-2 is_master_triggered_~__retres1~0#1 := 0; 7168#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7094#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7092#L615 assume !(0 != activate_threads_~tmp~1#1); 7093#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7075#L257 assume !(1 == ~t1_pc~0); 7076#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7112#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6969#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6970#L623 assume !(0 != activate_threads_~tmp___0~0#1); 6953#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6954#L276 assume !(1 == ~t2_pc~0); 7200#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7290#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7198#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7199#L631 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7321#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7091#L295 assume 1 == ~t3_pc~0; 6983#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6959#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6920#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6921#L639 assume !(0 != activate_threads_~tmp___2~0#1); 7310#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7311#L314 assume !(1 == ~t4_pc~0); 6977#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6976#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7009#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7010#L647 assume !(0 != activate_threads_~tmp___3~0#1); 7074#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7286#L555 assume !(1 == ~M_E~0); 6986#L555-2 assume !(1 == ~T1_E~0); 6987#L560-1 assume !(1 == ~T2_E~0); 6929#L565-1 assume !(1 == ~T3_E~0); 6930#L570-1 assume !(1 == ~T4_E~0); 7080#L575-1 assume !(1 == ~E_1~0); 7234#L580-1 assume !(1 == ~E_2~0); 7132#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 6968#L590-1 assume !(1 == ~E_4~0); 6960#L595-1 assume { :end_inline_reset_delta_events } true; 6961#L776-2 [2023-11-26 10:44:31,671 INFO L750 eck$LassoCheckResult]: Loop: 6961#L776-2 assume !false; 6942#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6943#L477-1 assume !false; 7252#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7253#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7063#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7208#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7222#L416 assume !(0 != eval_~tmp~0#1); 7012#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7013#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7056#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7057#L502-5 assume !(0 == ~T1_E~0); 7302#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7014#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7015#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7002#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7003#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7077#L532-3 assume !(0 == ~E_3~0); 7148#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7022#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7023#L238-15 assume !(1 == ~m_pc~0); 7070#L238-17 is_master_triggered_~__retres1~0#1 := 0; 7110#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7006#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7007#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7163#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7164#L257-15 assume !(1 == ~t1_pc~0); 7047#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 7048#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7258#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7259#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7304#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7309#L276-15 assume 1 == ~t2_pc~0; 7269#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7264#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7265#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7192#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7193#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6955#L295-15 assume 1 == ~t3_pc~0; 6956#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7183#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7316#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7171#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7122#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7123#L314-15 assume !(1 == ~t4_pc~0); 7169#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 7190#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7191#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7305#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7119#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7068#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7069#L555-5 assume !(1 == ~T1_E~0); 6993#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6994#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7306#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7294#L575-3 assume !(1 == ~E_1~0); 7203#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7204#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7248#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7249#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7854#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7850#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7849#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 7848#L795 assume !(0 == start_simulation_~tmp~3#1); 7130#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7105#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7106#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6966#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 6967#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6988#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6989#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7289#L808 assume !(0 != start_simulation_~tmp___0~1#1); 6961#L776-2 [2023-11-26 10:44:31,671 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:31,672 INFO L85 PathProgramCache]: Analyzing trace with hash 1261932300, now seen corresponding path program 1 times [2023-11-26 10:44:31,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:31,672 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957174973] [2023-11-26 10:44:31,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:31,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:31,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:31,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:31,732 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:31,732 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1957174973] [2023-11-26 10:44:31,732 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1957174973] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:31,732 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:31,733 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:44:31,733 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1086958580] [2023-11-26 10:44:31,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:31,733 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:31,734 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:31,734 INFO L85 PathProgramCache]: Analyzing trace with hash -1423265206, now seen corresponding path program 1 times [2023-11-26 10:44:31,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:31,734 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1897385906] [2023-11-26 10:44:31,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:31,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:31,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:31,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:31,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:31,791 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1897385906] [2023-11-26 10:44:31,792 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1897385906] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:31,792 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:31,792 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:31,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048616349] [2023-11-26 10:44:31,793 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:31,793 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:31,793 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:31,794 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 10:44:31,794 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 10:44:31,794 INFO L87 Difference]: Start difference. First operand 1185 states and 1717 transitions. cyclomatic complexity: 536 Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:32,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:32,004 INFO L93 Difference]: Finished difference Result 2590 states and 3706 transitions. [2023-11-26 10:44:32,005 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2590 states and 3706 transitions. [2023-11-26 10:44:32,030 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2468 [2023-11-26 10:44:32,054 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2590 states to 2590 states and 3706 transitions. [2023-11-26 10:44:32,055 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2590 [2023-11-26 10:44:32,058 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2590 [2023-11-26 10:44:32,058 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2590 states and 3706 transitions. [2023-11-26 10:44:32,063 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:32,064 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2590 states and 3706 transitions. [2023-11-26 10:44:32,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2590 states and 3706 transitions. [2023-11-26 10:44:32,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2590 to 1248. [2023-11-26 10:44:32,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1248 states, 1248 states have (on average 1.4262820512820513) internal successors, (1780), 1247 states have internal predecessors, (1780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:32,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1248 states to 1248 states and 1780 transitions. [2023-11-26 10:44:32,108 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1248 states and 1780 transitions. [2023-11-26 10:44:32,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 10:44:32,109 INFO L428 stractBuchiCegarLoop]: Abstraction has 1248 states and 1780 transitions. [2023-11-26 10:44:32,109 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 10:44:32,109 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1248 states and 1780 transitions. [2023-11-26 10:44:32,118 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1174 [2023-11-26 10:44:32,119 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:32,119 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:32,120 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:32,120 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:32,121 INFO L748 eck$LassoCheckResult]: Stem: 10907#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 10908#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 10986#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10987#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10806#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 10807#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11015#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10905#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10739#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10740#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10759#L502 assume !(0 == ~M_E~0); 10760#L502-2 assume !(0 == ~T1_E~0); 10728#L507-1 assume !(0 == ~T2_E~0); 10729#L512-1 assume !(0 == ~T3_E~0); 10809#L517-1 assume !(0 == ~T4_E~0); 10717#L522-1 assume !(0 == ~E_1~0); 10718#L527-1 assume !(0 == ~E_2~0); 10910#L532-1 assume !(0 == ~E_3~0); 10911#L537-1 assume !(0 == ~E_4~0); 10931#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10903#L238 assume !(1 == ~m_pc~0); 10904#L238-2 is_master_triggered_~__retres1~0#1 := 0; 10957#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10885#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10883#L615 assume !(0 != activate_threads_~tmp~1#1); 10884#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10866#L257 assume !(1 == ~t1_pc~0); 10867#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10902#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10757#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10758#L623 assume !(0 != activate_threads_~tmp___0~0#1); 10741#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10742#L276 assume !(1 == ~t2_pc~0); 10991#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11087#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11120#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11125#L631 assume !(0 != activate_threads_~tmp___1~0#1); 11126#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10882#L295 assume 1 == ~t3_pc~0; 10771#L296 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10747#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10708#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10709#L639 assume !(0 != activate_threads_~tmp___2~0#1); 11109#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11110#L314 assume !(1 == ~t4_pc~0); 10765#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10764#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10799#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10800#L647 assume !(0 != activate_threads_~tmp___3~0#1); 10865#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11082#L555 assume !(1 == ~M_E~0); 10774#L555-2 assume !(1 == ~T1_E~0); 10775#L560-1 assume !(1 == ~T2_E~0); 10713#L565-1 assume !(1 == ~T3_E~0); 10714#L570-1 assume !(1 == ~T4_E~0); 10871#L575-1 assume !(1 == ~E_1~0); 11023#L580-1 assume !(1 == ~E_2~0); 10922#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 10754#L590-1 assume !(1 == ~E_4~0); 10748#L595-1 assume { :end_inline_reset_delta_events } true; 10749#L776-2 [2023-11-26 10:44:32,121 INFO L750 eck$LassoCheckResult]: Loop: 10749#L776-2 assume !false; 10730#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10731#L477-1 assume !false; 11043#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11044#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10853#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10998#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11002#L416 assume !(0 != eval_~tmp~0#1); 10802#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10803#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10845#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10846#L502-5 assume !(0 == ~T1_E~0); 11102#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10804#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10805#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10792#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10793#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10868#L532-3 assume !(0 == ~E_3~0); 10939#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10812#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10813#L238-15 assume !(1 == ~m_pc~0); 10860#L238-17 is_master_triggered_~__retres1~0#1 := 0; 10900#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10796#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10797#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10952#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10953#L257-15 assume !(1 == ~t1_pc~0); 10838#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 10839#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11049#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11050#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11103#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11108#L276-15 assume 1 == ~t2_pc~0; 11062#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11064#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11769#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11768#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10979#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10743#L295-15 assume 1 == ~t3_pc~0; 10744#L296-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10972#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11116#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10960#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10912#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10913#L314-15 assume !(1 == ~t4_pc~0); 10958#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 10982#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10983#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11104#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10909#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10858#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10859#L555-5 assume !(1 == ~T1_E~0); 10781#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10782#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11105#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11091#L575-3 assume !(1 == ~E_1~0); 10994#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10995#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11039#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11040#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10961#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10735#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10837#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 10879#L795 assume !(0 == start_simulation_~tmp~3#1); 10881#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10896#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10897#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10755#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 10756#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10776#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10777#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 11085#L808 assume !(0 != start_simulation_~tmp___0~1#1); 10749#L776-2 [2023-11-26 10:44:32,122 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:32,122 INFO L85 PathProgramCache]: Analyzing trace with hash 1127918794, now seen corresponding path program 1 times [2023-11-26 10:44:32,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:32,122 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [393526105] [2023-11-26 10:44:32,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:32,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:32,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:32,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:32,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:32,165 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [393526105] [2023-11-26 10:44:32,165 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [393526105] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:32,165 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:32,166 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:44:32,166 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1244804611] [2023-11-26 10:44:32,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:32,166 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:32,167 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:32,167 INFO L85 PathProgramCache]: Analyzing trace with hash -1423265206, now seen corresponding path program 2 times [2023-11-26 10:44:32,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:32,167 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20167840] [2023-11-26 10:44:32,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:32,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:32,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:32,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:32,202 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:32,202 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [20167840] [2023-11-26 10:44:32,202 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [20167840] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:32,202 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:32,202 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:32,203 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935594607] [2023-11-26 10:44:32,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:32,203 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:32,203 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:32,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:32,204 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:32,204 INFO L87 Difference]: Start difference. First operand 1248 states and 1780 transitions. cyclomatic complexity: 536 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:32,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:32,264 INFO L93 Difference]: Finished difference Result 2249 states and 3191 transitions. [2023-11-26 10:44:32,265 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2249 states and 3191 transitions. [2023-11-26 10:44:32,283 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2164 [2023-11-26 10:44:32,302 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2249 states to 2249 states and 3191 transitions. [2023-11-26 10:44:32,302 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2249 [2023-11-26 10:44:32,305 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2249 [2023-11-26 10:44:32,305 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2249 states and 3191 transitions. [2023-11-26 10:44:32,309 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:32,309 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2249 states and 3191 transitions. [2023-11-26 10:44:32,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2249 states and 3191 transitions. [2023-11-26 10:44:32,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2249 to 2241. [2023-11-26 10:44:32,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2241 states, 2241 states have (on average 1.4203480589022757) internal successors, (3183), 2240 states have internal predecessors, (3183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:32,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2241 states to 2241 states and 3183 transitions. [2023-11-26 10:44:32,359 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2241 states and 3183 transitions. [2023-11-26 10:44:32,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:32,361 INFO L428 stractBuchiCegarLoop]: Abstraction has 2241 states and 3183 transitions. [2023-11-26 10:44:32,361 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 10:44:32,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2241 states and 3183 transitions. [2023-11-26 10:44:32,374 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2156 [2023-11-26 10:44:32,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:32,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:32,390 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:32,390 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:32,390 INFO L748 eck$LassoCheckResult]: Stem: 14411#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 14412#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 14495#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14496#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14306#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 14307#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14529#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14409#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14243#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14244#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14262#L502 assume !(0 == ~M_E~0); 14263#L502-2 assume !(0 == ~T1_E~0); 14232#L507-1 assume !(0 == ~T2_E~0); 14233#L512-1 assume !(0 == ~T3_E~0); 14309#L517-1 assume !(0 == ~T4_E~0); 14219#L522-1 assume !(0 == ~E_1~0); 14220#L527-1 assume !(0 == ~E_2~0); 14415#L532-1 assume !(0 == ~E_3~0); 14416#L537-1 assume !(0 == ~E_4~0); 14434#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14407#L238 assume !(1 == ~m_pc~0); 14408#L238-2 is_master_triggered_~__retres1~0#1 := 0; 14464#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14389#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14387#L615 assume !(0 != activate_threads_~tmp~1#1); 14388#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14369#L257 assume !(1 == ~t1_pc~0); 14370#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14406#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14260#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14261#L623 assume !(0 != activate_threads_~tmp___0~0#1); 14245#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14246#L276 assume !(1 == ~t2_pc~0); 14503#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14602#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14501#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14502#L631 assume !(0 != activate_threads_~tmp___1~0#1); 14644#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14386#L295 assume !(1 == ~t3_pc~0); 14249#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 14250#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14212#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14213#L639 assume !(0 != activate_threads_~tmp___2~0#1); 14633#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14634#L314 assume !(1 == ~t4_pc~0); 14268#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14267#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14299#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14300#L647 assume !(0 != activate_threads_~tmp___3~0#1); 14368#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14597#L555 assume !(1 == ~M_E~0); 14276#L555-2 assume !(1 == ~T1_E~0); 14277#L560-1 assume !(1 == ~T2_E~0); 14221#L565-1 assume !(1 == ~T3_E~0); 14222#L570-1 assume !(1 == ~T4_E~0); 14375#L575-1 assume !(1 == ~E_1~0); 14535#L580-1 assume !(1 == ~E_2~0); 14427#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 14259#L590-1 assume !(1 == ~E_4~0); 14251#L595-1 assume { :end_inline_reset_delta_events } true; 14252#L776-2 [2023-11-26 10:44:32,391 INFO L750 eck$LassoCheckResult]: Loop: 14252#L776-2 assume !false; 16081#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16078#L477-1 assume !false; 16076#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 14618#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 14357#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 14510#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14516#L416 assume !(0 != eval_~tmp~0#1); 14302#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14303#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14348#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14349#L502-5 assume !(0 == ~T1_E~0); 14620#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14304#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14305#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14292#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14293#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14371#L532-3 assume !(0 == ~E_3~0); 14443#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14593#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16312#L238-15 assume !(1 == ~m_pc~0); 16311#L238-17 is_master_triggered_~__retres1~0#1 := 0; 16310#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16309#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16307#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16305#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16303#L257-15 assume !(1 == ~t1_pc~0); 16302#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 16299#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16298#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16297#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14630#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14631#L276-15 assume 1 == ~t2_pc~0; 14578#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14580#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16294#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16006#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16007#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16216#L295-15 assume !(1 == ~t3_pc~0); 16211#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 16207#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16203#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16199#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16196#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16193#L314-15 assume !(1 == ~t4_pc~0); 16189#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 16186#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16183#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16180#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16177#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16174#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16170#L555-5 assume !(1 == ~T1_E~0); 16167#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16164#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16156#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16153#L575-3 assume !(1 == ~E_1~0); 16150#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16146#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16143#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16139#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 16133#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16126#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16122#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 16118#L795 assume !(0 == start_simulation_~tmp~3#1); 16114#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 16110#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16104#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16102#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 16100#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16097#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16094#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 16090#L808 assume !(0 != start_simulation_~tmp___0~1#1); 14252#L776-2 [2023-11-26 10:44:32,391 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:32,391 INFO L85 PathProgramCache]: Analyzing trace with hash 1014532137, now seen corresponding path program 1 times [2023-11-26 10:44:32,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:32,391 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027326481] [2023-11-26 10:44:32,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:32,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:32,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:32,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:32,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:32,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027326481] [2023-11-26 10:44:32,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2027326481] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:32,475 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:32,475 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:32,476 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1141891930] [2023-11-26 10:44:32,476 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:32,477 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:32,477 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:32,478 INFO L85 PathProgramCache]: Analyzing trace with hash 1243051817, now seen corresponding path program 1 times [2023-11-26 10:44:32,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:32,478 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1788712735] [2023-11-26 10:44:32,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:32,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:32,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:32,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:32,516 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:32,516 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1788712735] [2023-11-26 10:44:32,516 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1788712735] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:32,516 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:32,516 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:32,516 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1025241902] [2023-11-26 10:44:32,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:32,517 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:32,517 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:32,518 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:44:32,518 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:44:32,518 INFO L87 Difference]: Start difference. First operand 2241 states and 3183 transitions. cyclomatic complexity: 950 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:32,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:32,660 INFO L93 Difference]: Finished difference Result 4638 states and 6533 transitions. [2023-11-26 10:44:32,660 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4638 states and 6533 transitions. [2023-11-26 10:44:32,695 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4428 [2023-11-26 10:44:32,732 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4638 states to 4638 states and 6533 transitions. [2023-11-26 10:44:32,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4638 [2023-11-26 10:44:32,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4638 [2023-11-26 10:44:32,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4638 states and 6533 transitions. [2023-11-26 10:44:32,745 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:32,745 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4638 states and 6533 transitions. [2023-11-26 10:44:32,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4638 states and 6533 transitions. [2023-11-26 10:44:32,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4638 to 4578. [2023-11-26 10:44:32,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4578 states, 4578 states have (on average 1.4104412407164701) internal successors, (6457), 4577 states have internal predecessors, (6457), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:32,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4578 states to 4578 states and 6457 transitions. [2023-11-26 10:44:32,847 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4578 states and 6457 transitions. [2023-11-26 10:44:32,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:44:32,848 INFO L428 stractBuchiCegarLoop]: Abstraction has 4578 states and 6457 transitions. [2023-11-26 10:44:32,848 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 10:44:32,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4578 states and 6457 transitions. [2023-11-26 10:44:32,868 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4376 [2023-11-26 10:44:32,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:32,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:32,870 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:32,870 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:32,870 INFO L748 eck$LassoCheckResult]: Stem: 21302#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 21303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 21388#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21389#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21198#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 21199#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21427#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21300#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21133#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21134#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21154#L502 assume !(0 == ~M_E~0); 21155#L502-2 assume !(0 == ~T1_E~0); 21118#L507-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21119#L512-1 assume !(0 == ~T3_E~0); 21200#L517-1 assume !(0 == ~T4_E~0); 21106#L522-1 assume !(0 == ~E_1~0); 21107#L527-1 assume !(0 == ~E_2~0); 21305#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 21306#L537-1 assume !(0 == ~E_4~0); 21616#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21615#L238 assume !(1 == ~m_pc~0); 21614#L238-2 is_master_triggered_~__retres1~0#1 := 0; 21613#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21612#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21611#L615 assume !(0 != activate_threads_~tmp~1#1); 21610#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21609#L257 assume !(1 == ~t1_pc~0); 21608#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21607#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21606#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21605#L623 assume !(0 != activate_threads_~tmp___0~0#1); 21604#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21603#L276 assume !(1 == ~t2_pc~0); 21602#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21618#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21617#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21597#L631 assume !(0 != activate_threads_~tmp___1~0#1); 21596#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21595#L295 assume !(1 == ~t3_pc~0); 21594#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21593#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21592#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21591#L639 assume !(0 != activate_threads_~tmp___2~0#1); 21590#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21589#L314 assume !(1 == ~t4_pc~0); 21588#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21586#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21585#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21584#L647 assume !(0 != activate_threads_~tmp___3~0#1); 21583#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21582#L555 assume !(1 == ~M_E~0); 21581#L555-2 assume !(1 == ~T1_E~0); 21580#L560-1 assume !(1 == ~T2_E~0); 21579#L565-1 assume !(1 == ~T3_E~0); 21578#L570-1 assume !(1 == ~T4_E~0); 21577#L575-1 assume !(1 == ~E_1~0); 21576#L580-1 assume !(1 == ~E_2~0); 21575#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 21148#L590-1 assume !(1 == ~E_4~0); 21149#L595-1 assume { :end_inline_reset_delta_events } true; 23763#L776-2 [2023-11-26 10:44:32,870 INFO L750 eck$LassoCheckResult]: Loop: 23763#L776-2 assume !false; 23756#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23752#L477-1 assume !false; 23747#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23732#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23727#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23725#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23722#L416 assume !(0 != eval_~tmp~0#1); 23723#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24890#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24888#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24886#L502-5 assume !(0 == ~T1_E~0); 24884#L507-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24068#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24587#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24249#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24247#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24245#L532-3 assume !(0 == ~E_3~0); 24243#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24241#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24239#L238-15 assume !(1 == ~m_pc~0); 24237#L238-17 is_master_triggered_~__retres1~0#1 := 0; 24235#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24232#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24229#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24226#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24223#L257-15 assume !(1 == ~t1_pc~0); 24220#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 24217#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24214#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24211#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24208#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24205#L276-15 assume 1 == ~t2_pc~0; 24201#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24196#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24191#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 24185#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24180#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24175#L295-15 assume !(1 == ~t3_pc~0); 24170#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 24166#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24162#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 24158#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24154#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24150#L314-15 assume !(1 == ~t4_pc~0); 24145#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 24140#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24136#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24131#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24127#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24123#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24118#L555-5 assume !(1 == ~T1_E~0); 24113#L560-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24108#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24103#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24099#L575-3 assume !(1 == ~E_1~0); 24095#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24091#L585-3 assume !(1 == ~E_3~0); 24087#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24084#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 24080#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23852#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23849#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 23846#L795 assume !(0 == start_simulation_~tmp~3#1); 23843#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23842#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23829#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23824#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 23817#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23810#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23803#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 23776#L808 assume !(0 != start_simulation_~tmp___0~1#1); 23763#L776-2 [2023-11-26 10:44:32,871 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:32,871 INFO L85 PathProgramCache]: Analyzing trace with hash -27236631, now seen corresponding path program 1 times [2023-11-26 10:44:32,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:32,871 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2035086698] [2023-11-26 10:44:32,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:32,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:32,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:32,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:32,938 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:32,938 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2035086698] [2023-11-26 10:44:32,938 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2035086698] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:32,939 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:32,939 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:44:32,939 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1825071292] [2023-11-26 10:44:32,939 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:32,940 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:32,940 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:32,940 INFO L85 PathProgramCache]: Analyzing trace with hash -36811861, now seen corresponding path program 1 times [2023-11-26 10:44:32,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:32,941 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251854369] [2023-11-26 10:44:32,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:32,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:32,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:32,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:32,991 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:32,991 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1251854369] [2023-11-26 10:44:32,991 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1251854369] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:32,991 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:32,992 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:32,992 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [873365629] [2023-11-26 10:44:32,992 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:32,992 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:32,992 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:32,993 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:32,993 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:32,994 INFO L87 Difference]: Start difference. First operand 4578 states and 6457 transitions. cyclomatic complexity: 1895 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 2 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:33,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:33,035 INFO L93 Difference]: Finished difference Result 4528 states and 6344 transitions. [2023-11-26 10:44:33,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4528 states and 6344 transitions. [2023-11-26 10:44:33,071 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4376 [2023-11-26 10:44:33,105 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4528 states to 4528 states and 6344 transitions. [2023-11-26 10:44:33,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4528 [2023-11-26 10:44:33,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4528 [2023-11-26 10:44:33,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4528 states and 6344 transitions. [2023-11-26 10:44:33,117 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:33,117 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4528 states and 6344 transitions. [2023-11-26 10:44:33,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4528 states and 6344 transitions. [2023-11-26 10:44:33,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4528 to 2658. [2023-11-26 10:44:33,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2658 states, 2658 states have (on average 1.3954100827689992) internal successors, (3709), 2657 states have internal predecessors, (3709), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:33,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2658 states to 2658 states and 3709 transitions. [2023-11-26 10:44:33,188 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2658 states and 3709 transitions. [2023-11-26 10:44:33,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:33,189 INFO L428 stractBuchiCegarLoop]: Abstraction has 2658 states and 3709 transitions. [2023-11-26 10:44:33,189 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 10:44:33,189 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2658 states and 3709 transitions. [2023-11-26 10:44:33,202 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2528 [2023-11-26 10:44:33,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:33,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:33,203 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:33,203 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:33,204 INFO L748 eck$LassoCheckResult]: Stem: 30415#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 30416#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 30503#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30504#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30308#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 30309#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30543#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30413#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30245#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30246#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30264#L502 assume !(0 == ~M_E~0); 30265#L502-2 assume !(0 == ~T1_E~0); 30231#L507-1 assume !(0 == ~T2_E~0); 30232#L512-1 assume !(0 == ~T3_E~0); 30310#L517-1 assume !(0 == ~T4_E~0); 30219#L522-1 assume !(0 == ~E_1~0); 30220#L527-1 assume !(0 == ~E_2~0); 30418#L532-1 assume 0 == ~E_3~0;~E_3~0 := 1; 30419#L537-1 assume !(0 == ~E_4~0); 30438#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30439#L238 assume !(1 == ~m_pc~0); 30471#L238-2 is_master_triggered_~__retres1~0#1 := 0; 30472#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30392#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 30393#L615 assume !(0 != activate_threads_~tmp~1#1); 30526#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30527#L257 assume !(1 == ~t1_pc~0); 30561#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30562#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30262#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30263#L623 assume !(0 != activate_threads_~tmp___0~0#1); 30247#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30248#L276 assume !(1 == ~t2_pc~0); 30613#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30614#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30507#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30508#L631 assume !(0 != activate_threads_~tmp___1~0#1); 30662#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30663#L295 assume !(1 == ~t3_pc~0); 30251#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30252#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30214#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30215#L639 assume !(0 != activate_threads_~tmp___2~0#1); 30640#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30641#L314 assume !(1 == ~t4_pc~0); 30270#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30269#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30300#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30301#L647 assume !(0 != activate_threads_~tmp___3~0#1); 30608#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30609#L555 assume !(1 == ~M_E~0); 30278#L555-2 assume !(1 == ~T1_E~0); 30279#L560-1 assume !(1 == ~T2_E~0); 30221#L565-1 assume !(1 == ~T3_E~0); 30222#L570-1 assume !(1 == ~T4_E~0); 30549#L575-1 assume !(1 == ~E_1~0); 30550#L580-1 assume !(1 == ~E_2~0); 30686#L585-1 assume 1 == ~E_3~0;~E_3~0 := 2; 30259#L590-1 assume !(1 == ~E_4~0); 30253#L595-1 assume { :end_inline_reset_delta_events } true; 30254#L776-2 [2023-11-26 10:44:33,204 INFO L750 eck$LassoCheckResult]: Loop: 30254#L776-2 assume !false; 32043#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32042#L477-1 assume !false; 32041#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 31921#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 31913#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31911#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31908#L416 assume !(0 != eval_~tmp~0#1); 31909#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32174#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32172#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32170#L502-5 assume !(0 == ~T1_E~0); 32168#L507-3 assume !(0 == ~T2_E~0); 32166#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32164#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32162#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32160#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32157#L532-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32156#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32155#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32154#L238-15 assume !(1 == ~m_pc~0); 32153#L238-17 is_master_triggered_~__retres1~0#1 := 0; 32152#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32151#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 32150#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32149#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32148#L257-15 assume !(1 == ~t1_pc~0); 32147#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 32146#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32145#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 32144#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32143#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32142#L276-15 assume 1 == ~t2_pc~0; 32140#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32138#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32136#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 32134#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32133#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32132#L295-15 assume !(1 == ~t3_pc~0); 32131#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 32130#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32129#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 32128#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32127#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32126#L314-15 assume !(1 == ~t4_pc~0); 32122#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 32120#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32118#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 32116#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32114#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32112#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32110#L555-5 assume !(1 == ~T1_E~0); 32108#L560-3 assume !(1 == ~T2_E~0); 32106#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32104#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32102#L575-3 assume !(1 == ~E_1~0); 32100#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32098#L585-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32097#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32096#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 32094#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 32090#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 32089#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 32087#L795 assume !(0 == start_simulation_~tmp~3#1); 32085#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 32084#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 32078#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 32075#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 32073#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32071#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32058#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 32057#L808 assume !(0 != start_simulation_~tmp___0~1#1); 30254#L776-2 [2023-11-26 10:44:33,205 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:33,205 INFO L85 PathProgramCache]: Analyzing trace with hash 1911925415, now seen corresponding path program 1 times [2023-11-26 10:44:33,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:33,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458880784] [2023-11-26 10:44:33,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:33,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:33,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:33,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:33,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:33,253 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1458880784] [2023-11-26 10:44:33,255 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1458880784] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:33,256 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:33,256 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:33,258 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1839443737] [2023-11-26 10:44:33,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:33,259 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:33,259 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:33,259 INFO L85 PathProgramCache]: Analyzing trace with hash -759558109, now seen corresponding path program 1 times [2023-11-26 10:44:33,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:33,260 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725321947] [2023-11-26 10:44:33,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:33,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:33,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:33,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:33,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:33,306 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [725321947] [2023-11-26 10:44:33,307 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [725321947] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:33,307 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:33,307 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:33,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310090736] [2023-11-26 10:44:33,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:33,308 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:33,308 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:33,308 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:44:33,308 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:44:33,309 INFO L87 Difference]: Start difference. First operand 2658 states and 3709 transitions. cyclomatic complexity: 1059 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:33,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:33,403 INFO L93 Difference]: Finished difference Result 4117 states and 5747 transitions. [2023-11-26 10:44:33,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4117 states and 5747 transitions. [2023-11-26 10:44:33,427 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4004 [2023-11-26 10:44:33,512 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4117 states to 4117 states and 5747 transitions. [2023-11-26 10:44:33,513 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4117 [2023-11-26 10:44:33,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4117 [2023-11-26 10:44:33,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4117 states and 5747 transitions. [2023-11-26 10:44:33,524 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:33,524 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4117 states and 5747 transitions. [2023-11-26 10:44:33,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4117 states and 5747 transitions. [2023-11-26 10:44:33,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4117 to 2241. [2023-11-26 10:44:33,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2241 states, 2241 states have (on average 1.390004462293619) internal successors, (3115), 2240 states have internal predecessors, (3115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:33,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2241 states to 2241 states and 3115 transitions. [2023-11-26 10:44:33,587 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2241 states and 3115 transitions. [2023-11-26 10:44:33,588 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:44:33,590 INFO L428 stractBuchiCegarLoop]: Abstraction has 2241 states and 3115 transitions. [2023-11-26 10:44:33,590 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 10:44:33,590 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2241 states and 3115 transitions. [2023-11-26 10:44:33,599 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2156 [2023-11-26 10:44:33,599 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:33,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:33,601 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:33,601 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:33,601 INFO L748 eck$LassoCheckResult]: Stem: 37200#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 37201#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 37282#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37283#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37096#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 37097#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37316#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37198#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37030#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37031#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37050#L502 assume !(0 == ~M_E~0); 37051#L502-2 assume !(0 == ~T1_E~0); 37016#L507-1 assume !(0 == ~T2_E~0); 37017#L512-1 assume !(0 == ~T3_E~0); 37098#L517-1 assume !(0 == ~T4_E~0); 37004#L522-1 assume !(0 == ~E_1~0); 37005#L527-1 assume !(0 == ~E_2~0); 37204#L532-1 assume !(0 == ~E_3~0); 37205#L537-1 assume !(0 == ~E_4~0); 37225#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37196#L238 assume !(1 == ~m_pc~0); 37197#L238-2 is_master_triggered_~__retres1~0#1 := 0; 37252#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37176#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 37174#L615 assume !(0 != activate_threads_~tmp~1#1); 37175#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37157#L257 assume !(1 == ~t1_pc~0); 37158#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37192#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37048#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 37049#L623 assume !(0 != activate_threads_~tmp___0~0#1); 37032#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37033#L276 assume !(1 == ~t2_pc~0); 37290#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 37383#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37288#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 37289#L631 assume !(0 != activate_threads_~tmp___1~0#1); 37421#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37173#L295 assume !(1 == ~t3_pc~0); 37037#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37038#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36999#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 37000#L639 assume !(0 != activate_threads_~tmp___2~0#1); 37407#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37408#L314 assume !(1 == ~t4_pc~0); 37056#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37055#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37088#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37089#L647 assume !(0 != activate_threads_~tmp___3~0#1); 37156#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37379#L555 assume !(1 == ~M_E~0); 37064#L555-2 assume !(1 == ~T1_E~0); 37065#L560-1 assume !(1 == ~T2_E~0); 37006#L565-1 assume !(1 == ~T3_E~0); 37007#L570-1 assume !(1 == ~T4_E~0); 37162#L575-1 assume !(1 == ~E_1~0); 37322#L580-1 assume !(1 == ~E_2~0); 37217#L585-1 assume !(1 == ~E_3~0); 37045#L590-1 assume !(1 == ~E_4~0); 37039#L595-1 assume { :end_inline_reset_delta_events } true; 37040#L776-2 [2023-11-26 10:44:33,602 INFO L750 eck$LassoCheckResult]: Loop: 37040#L776-2 assume !false; 38776#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38775#L477-1 assume !false; 38745#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 38511#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 38505#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 38504#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38501#L416 assume !(0 != eval_~tmp~0#1); 38502#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38928#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38926#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38924#L502-5 assume !(0 == ~T1_E~0); 38922#L507-3 assume !(0 == ~T2_E~0); 38920#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38918#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38916#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38914#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38912#L532-3 assume !(0 == ~E_3~0); 38910#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38908#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38906#L238-15 assume !(1 == ~m_pc~0); 38904#L238-17 is_master_triggered_~__retres1~0#1 := 0; 38902#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38901#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38900#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38898#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38897#L257-15 assume !(1 == ~t1_pc~0); 38896#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 38895#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38894#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38893#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38892#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38891#L276-15 assume !(1 == ~t2_pc~0); 38888#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 38886#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38885#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 38884#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 38881#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38879#L295-15 assume !(1 == ~t3_pc~0); 38877#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 38875#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38873#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38871#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38869#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38867#L314-15 assume !(1 == ~t4_pc~0); 38864#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 38862#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38860#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38858#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38856#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38854#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38852#L555-5 assume !(1 == ~T1_E~0); 38850#L560-3 assume !(1 == ~T2_E~0); 38848#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38846#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38843#L575-3 assume !(1 == ~E_1~0); 38841#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38839#L585-3 assume !(1 == ~E_3~0); 38837#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38835#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 38828#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 38823#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 38820#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 38817#L795 assume !(0 == start_simulation_~tmp~3#1); 38814#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 38812#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 38806#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 38804#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 38802#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38800#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38798#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 38795#L808 assume !(0 != start_simulation_~tmp___0~1#1); 37040#L776-2 [2023-11-26 10:44:33,602 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:33,602 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 1 times [2023-11-26 10:44:33,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:33,603 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246597578] [2023-11-26 10:44:33,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:33,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:33,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:33,616 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:33,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:33,662 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:33,664 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:33,664 INFO L85 PathProgramCache]: Analyzing trace with hash -647011964, now seen corresponding path program 1 times [2023-11-26 10:44:33,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:33,664 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967109748] [2023-11-26 10:44:33,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:33,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:33,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:33,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:33,696 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:33,696 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967109748] [2023-11-26 10:44:33,696 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967109748] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:33,696 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:33,696 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:33,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [66453975] [2023-11-26 10:44:33,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:33,697 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:33,697 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:33,698 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:33,698 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:33,698 INFO L87 Difference]: Start difference. First operand 2241 states and 3115 transitions. cyclomatic complexity: 882 Second operand has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:33,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:33,779 INFO L93 Difference]: Finished difference Result 3409 states and 4693 transitions. [2023-11-26 10:44:33,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3409 states and 4693 transitions. [2023-11-26 10:44:33,796 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3273 [2023-11-26 10:44:33,825 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3409 states to 3409 states and 4693 transitions. [2023-11-26 10:44:33,826 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3409 [2023-11-26 10:44:33,829 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3409 [2023-11-26 10:44:33,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3409 states and 4693 transitions. [2023-11-26 10:44:33,835 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:33,835 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3409 states and 4693 transitions. [2023-11-26 10:44:33,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3409 states and 4693 transitions. [2023-11-26 10:44:33,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3409 to 3397. [2023-11-26 10:44:33,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3397 states, 3397 states have (on average 1.3773918163085075) internal successors, (4679), 3396 states have internal predecessors, (4679), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:33,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3397 states to 3397 states and 4679 transitions. [2023-11-26 10:44:33,905 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3397 states and 4679 transitions. [2023-11-26 10:44:33,905 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:33,906 INFO L428 stractBuchiCegarLoop]: Abstraction has 3397 states and 4679 transitions. [2023-11-26 10:44:33,907 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 10:44:33,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3397 states and 4679 transitions. [2023-11-26 10:44:33,920 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3265 [2023-11-26 10:44:33,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:33,920 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:33,921 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:33,922 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:33,922 INFO L748 eck$LassoCheckResult]: Stem: 42857#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 42858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 42947#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42948#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42750#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 42751#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42985#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42855#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42686#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42687#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42705#L502 assume !(0 == ~M_E~0); 42706#L502-2 assume !(0 == ~T1_E~0); 42675#L507-1 assume !(0 == ~T2_E~0); 42676#L512-1 assume !(0 == ~T3_E~0); 42753#L517-1 assume !(0 == ~T4_E~0); 42661#L522-1 assume 0 == ~E_1~0;~E_1~0 := 1; 42662#L527-1 assume !(0 == ~E_2~0); 42860#L532-1 assume !(0 == ~E_3~0); 42861#L537-1 assume !(0 == ~E_4~0); 42882#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42853#L238 assume !(1 == ~m_pc~0); 42854#L238-2 is_master_triggered_~__retres1~0#1 := 0; 42965#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42832#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 42830#L615 assume !(0 != activate_threads_~tmp~1#1); 42831#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42973#L257 assume !(1 == ~t1_pc~0); 43171#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43170#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43169#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 43168#L623 assume !(0 != activate_threads_~tmp___0~0#1); 42688#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42689#L276 assume !(1 == ~t2_pc~0); 42956#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43158#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43156#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 43108#L631 assume !(0 != activate_threads_~tmp___1~0#1); 43109#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43155#L295 assume !(1 == ~t3_pc~0); 42692#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 42693#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42654#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 42655#L639 assume !(0 != activate_threads_~tmp___2~0#1); 43090#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43091#L314 assume !(1 == ~t4_pc~0); 43130#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 42892#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42743#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42744#L647 assume !(0 != activate_threads_~tmp___3~0#1); 43052#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43053#L555 assume !(1 == ~M_E~0); 43139#L555-2 assume !(1 == ~T1_E~0); 43127#L560-1 assume !(1 == ~T2_E~0); 43128#L565-1 assume !(1 == ~T3_E~0); 42817#L570-1 assume !(1 == ~T4_E~0); 42818#L575-1 assume 1 == ~E_1~0;~E_1~0 := 2; 42993#L580-1 assume !(1 == ~E_2~0); 42873#L585-1 assume !(1 == ~E_3~0); 42702#L590-1 assume !(1 == ~E_4~0); 42694#L595-1 assume { :end_inline_reset_delta_events } true; 42695#L776-2 [2023-11-26 10:44:33,922 INFO L750 eck$LassoCheckResult]: Loop: 42695#L776-2 assume !false; 43298#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43292#L477-1 assume !false; 43290#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 43286#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 43282#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 43273#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 43265#L416 assume !(0 != eval_~tmp~0#1); 43266#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43950#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43946#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 43944#L502-5 assume !(0 == ~T1_E~0); 43942#L507-3 assume !(0 == ~T2_E~0); 43940#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43937#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43934#L522-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43932#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43930#L532-3 assume !(0 == ~E_3~0); 43928#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43926#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43924#L238-15 assume !(1 == ~m_pc~0); 43922#L238-17 is_master_triggered_~__retres1~0#1 := 0; 43920#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43919#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 43918#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43916#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43915#L257-15 assume !(1 == ~t1_pc~0); 43914#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 43913#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43911#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 43909#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43907#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43905#L276-15 assume !(1 == ~t2_pc~0); 43901#L276-17 is_transmit2_triggered_~__retres1~2#1 := 0; 43899#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43897#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 43895#L631-15 assume !(0 != activate_threads_~tmp___1~0#1); 43892#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43890#L295-15 assume !(1 == ~t3_pc~0); 43888#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 43886#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43884#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 43882#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43880#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43878#L314-15 assume !(1 == ~t4_pc~0); 43875#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 43873#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43871#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43868#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43866#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43864#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43862#L555-5 assume !(1 == ~T1_E~0); 43831#L560-3 assume !(1 == ~T2_E~0); 43825#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43819#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43811#L575-3 assume 1 == ~E_1~0;~E_1~0 := 2; 43806#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 43802#L585-3 assume !(1 == ~E_3~0); 43797#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43795#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 43698#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 43689#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 43681#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 43675#L795 assume !(0 == start_simulation_~tmp~3#1); 43671#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 43431#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 43425#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 43423#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 43422#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43421#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43419#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 43417#L808 assume !(0 != start_simulation_~tmp___0~1#1); 42695#L776-2 [2023-11-26 10:44:33,923 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:33,923 INFO L85 PathProgramCache]: Analyzing trace with hash 119200679, now seen corresponding path program 1 times [2023-11-26 10:44:33,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:33,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520832278] [2023-11-26 10:44:33,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:33,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:33,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:33,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:33,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:33,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [520832278] [2023-11-26 10:44:33,986 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [520832278] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:33,986 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:33,987 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:33,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [642906985] [2023-11-26 10:44:33,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:33,989 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:33,990 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:33,990 INFO L85 PathProgramCache]: Analyzing trace with hash 941335938, now seen corresponding path program 1 times [2023-11-26 10:44:33,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:33,990 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497794423] [2023-11-26 10:44:33,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:33,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:34,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:34,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:34,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:34,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497794423] [2023-11-26 10:44:34,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [497794423] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:34,062 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:34,063 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:44:34,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [799585709] [2023-11-26 10:44:34,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:34,064 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:34,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:34,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:44:34,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:44:34,065 INFO L87 Difference]: Start difference. First operand 3397 states and 4679 transitions. cyclomatic complexity: 1290 Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:34,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:34,186 INFO L93 Difference]: Finished difference Result 4623 states and 6359 transitions. [2023-11-26 10:44:34,186 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4623 states and 6359 transitions. [2023-11-26 10:44:34,215 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 4333 [2023-11-26 10:44:34,238 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4623 states to 4623 states and 6359 transitions. [2023-11-26 10:44:34,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4623 [2023-11-26 10:44:34,243 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4623 [2023-11-26 10:44:34,244 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4623 states and 6359 transitions. [2023-11-26 10:44:34,252 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:34,252 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4623 states and 6359 transitions. [2023-11-26 10:44:34,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4623 states and 6359 transitions. [2023-11-26 10:44:34,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4623 to 3168. [2023-11-26 10:44:34,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3168 states, 3168 states have (on average 1.3778409090909092) internal successors, (4365), 3167 states have internal predecessors, (4365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:34,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3168 states to 3168 states and 4365 transitions. [2023-11-26 10:44:34,331 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3168 states and 4365 transitions. [2023-11-26 10:44:34,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:44:34,333 INFO L428 stractBuchiCegarLoop]: Abstraction has 3168 states and 4365 transitions. [2023-11-26 10:44:34,333 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 10:44:34,333 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3168 states and 4365 transitions. [2023-11-26 10:44:34,345 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3081 [2023-11-26 10:44:34,346 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:34,346 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:34,348 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:34,348 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:34,349 INFO L748 eck$LassoCheckResult]: Stem: 50883#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 50884#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 50963#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50964#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50781#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 50782#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50999#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50881#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50717#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50718#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50736#L502 assume !(0 == ~M_E~0); 50737#L502-2 assume !(0 == ~T1_E~0); 50703#L507-1 assume !(0 == ~T2_E~0); 50704#L512-1 assume !(0 == ~T3_E~0); 50784#L517-1 assume !(0 == ~T4_E~0); 50693#L522-1 assume !(0 == ~E_1~0); 50694#L527-1 assume !(0 == ~E_2~0); 50886#L532-1 assume !(0 == ~E_3~0); 50887#L537-1 assume !(0 == ~E_4~0); 50907#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50879#L238 assume !(1 == ~m_pc~0); 50880#L238-2 is_master_triggered_~__retres1~0#1 := 0; 50932#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50861#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 50859#L615 assume !(0 != activate_threads_~tmp~1#1); 50860#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50840#L257 assume !(1 == ~t1_pc~0); 50841#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50878#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50734#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 50735#L623 assume !(0 != activate_threads_~tmp___0~0#1); 50719#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50720#L276 assume !(1 == ~t2_pc~0); 50971#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 51077#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50969#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 50970#L631 assume !(0 != activate_threads_~tmp___1~0#1); 51121#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50858#L295 assume !(1 == ~t3_pc~0); 50723#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50724#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50686#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 50687#L639 assume !(0 != activate_threads_~tmp___2~0#1); 51105#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51106#L314 assume !(1 == ~t4_pc~0); 50742#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 50741#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50774#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50775#L647 assume !(0 != activate_threads_~tmp___3~0#1); 50839#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51072#L555 assume !(1 == ~M_E~0); 50750#L555-2 assume !(1 == ~T1_E~0); 50751#L560-1 assume !(1 == ~T2_E~0); 50695#L565-1 assume !(1 == ~T3_E~0); 50696#L570-1 assume !(1 == ~T4_E~0); 50847#L575-1 assume !(1 == ~E_1~0); 51005#L580-1 assume !(1 == ~E_2~0); 50899#L585-1 assume !(1 == ~E_3~0); 50733#L590-1 assume !(1 == ~E_4~0); 50725#L595-1 assume { :end_inline_reset_delta_events } true; 50726#L776-2 [2023-11-26 10:44:34,349 INFO L750 eck$LassoCheckResult]: Loop: 50726#L776-2 assume !false; 52782#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52775#L477-1 assume !false; 52770#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 52766#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 52762#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 52756#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 52753#L416 assume !(0 != eval_~tmp~0#1); 52754#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53187#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53186#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53185#L502-5 assume !(0 == ~T1_E~0); 53184#L507-3 assume !(0 == ~T2_E~0); 53183#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53182#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53181#L522-3 assume !(0 == ~E_1~0); 53180#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53179#L532-3 assume !(0 == ~E_3~0); 53178#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53177#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53176#L238-15 assume !(1 == ~m_pc~0); 53175#L238-17 is_master_triggered_~__retres1~0#1 := 0; 53174#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53173#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 53172#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53171#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53170#L257-15 assume !(1 == ~t1_pc~0); 53169#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 53168#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53167#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 53166#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53165#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53164#L276-15 assume 1 == ~t2_pc~0; 53161#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53158#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53155#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 53152#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53150#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53147#L295-15 assume !(1 == ~t3_pc~0); 53144#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 53141#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53138#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 53136#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53133#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53130#L314-15 assume !(1 == ~t4_pc~0); 53126#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 53123#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53120#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53117#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53114#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53110#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53107#L555-5 assume !(1 == ~T1_E~0); 53104#L560-3 assume !(1 == ~T2_E~0); 53101#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53098#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53095#L575-3 assume !(1 == ~E_1~0); 53091#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53087#L585-3 assume !(1 == ~E_3~0); 53083#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53079#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 53075#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 53069#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 53065#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 53062#L795 assume !(0 == start_simulation_~tmp~3#1); 53058#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 52840#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 52834#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 52832#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 52831#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 52828#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52827#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 52825#L808 assume !(0 != start_simulation_~tmp___0~1#1); 50726#L776-2 [2023-11-26 10:44:34,349 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:34,350 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 2 times [2023-11-26 10:44:34,350 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:34,350 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044522159] [2023-11-26 10:44:34,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:34,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:34,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:34,360 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:34,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:34,390 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:34,391 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:34,391 INFO L85 PathProgramCache]: Analyzing trace with hash 608280873, now seen corresponding path program 1 times [2023-11-26 10:44:34,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:34,391 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099609248] [2023-11-26 10:44:34,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:34,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:34,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:34,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:34,448 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:34,449 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099609248] [2023-11-26 10:44:34,449 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2099609248] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:34,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:34,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:44:34,449 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1335861238] [2023-11-26 10:44:34,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:34,450 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:34,450 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:34,450 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 10:44:34,450 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 10:44:34,451 INFO L87 Difference]: Start difference. First operand 3168 states and 4365 transitions. cyclomatic complexity: 1205 Second operand has 5 states, 5 states have (on average 14.4) internal successors, (72), 5 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:34,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:34,576 INFO L93 Difference]: Finished difference Result 5567 states and 7590 transitions. [2023-11-26 10:44:34,576 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5567 states and 7590 transitions. [2023-11-26 10:44:34,605 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5458 [2023-11-26 10:44:34,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5567 states to 5567 states and 7590 transitions. [2023-11-26 10:44:34,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5567 [2023-11-26 10:44:34,632 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5567 [2023-11-26 10:44:34,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5567 states and 7590 transitions. [2023-11-26 10:44:34,638 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:34,638 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5567 states and 7590 transitions. [2023-11-26 10:44:34,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5567 states and 7590 transitions. [2023-11-26 10:44:34,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5567 to 3204. [2023-11-26 10:44:34,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3204 states, 3204 states have (on average 1.3735955056179776) internal successors, (4401), 3203 states have internal predecessors, (4401), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:34,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3204 states to 3204 states and 4401 transitions. [2023-11-26 10:44:34,752 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3204 states and 4401 transitions. [2023-11-26 10:44:34,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-26 10:44:34,753 INFO L428 stractBuchiCegarLoop]: Abstraction has 3204 states and 4401 transitions. [2023-11-26 10:44:34,753 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 10:44:34,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3204 states and 4401 transitions. [2023-11-26 10:44:34,766 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3117 [2023-11-26 10:44:34,766 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:34,766 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:34,767 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:34,768 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:34,768 INFO L748 eck$LassoCheckResult]: Stem: 59635#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 59636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 59716#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59717#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59534#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 59535#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59749#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59633#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59469#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59470#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59488#L502 assume !(0 == ~M_E~0); 59489#L502-2 assume !(0 == ~T1_E~0); 59455#L507-1 assume !(0 == ~T2_E~0); 59456#L512-1 assume !(0 == ~T3_E~0); 59537#L517-1 assume !(0 == ~T4_E~0); 59445#L522-1 assume !(0 == ~E_1~0); 59446#L527-1 assume !(0 == ~E_2~0); 59639#L532-1 assume !(0 == ~E_3~0); 59640#L537-1 assume !(0 == ~E_4~0); 59658#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59631#L238 assume !(1 == ~m_pc~0); 59632#L238-2 is_master_triggered_~__retres1~0#1 := 0; 59686#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59614#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 59612#L615 assume !(0 != activate_threads_~tmp~1#1); 59613#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59594#L257 assume !(1 == ~t1_pc~0); 59595#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 59630#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59486#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 59487#L623 assume !(0 != activate_threads_~tmp___0~0#1); 59471#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59472#L276 assume !(1 == ~t2_pc~0); 59723#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 59820#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59721#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 59722#L631 assume !(0 != activate_threads_~tmp___1~0#1); 59872#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59611#L295 assume !(1 == ~t3_pc~0); 59475#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59476#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59438#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 59439#L639 assume !(0 != activate_threads_~tmp___2~0#1); 59860#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59861#L314 assume !(1 == ~t4_pc~0); 59494#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 59493#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59527#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 59528#L647 assume !(0 != activate_threads_~tmp___3~0#1); 59593#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59816#L555 assume !(1 == ~M_E~0); 59502#L555-2 assume !(1 == ~T1_E~0); 59503#L560-1 assume !(1 == ~T2_E~0); 59447#L565-1 assume !(1 == ~T3_E~0); 59448#L570-1 assume !(1 == ~T4_E~0); 59601#L575-1 assume !(1 == ~E_1~0); 59757#L580-1 assume !(1 == ~E_2~0); 59651#L585-1 assume !(1 == ~E_3~0); 59485#L590-1 assume !(1 == ~E_4~0); 59477#L595-1 assume { :end_inline_reset_delta_events } true; 59478#L776-2 [2023-11-26 10:44:34,768 INFO L750 eck$LassoCheckResult]: Loop: 59478#L776-2 assume !false; 60596#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60595#L477-1 assume !false; 60594#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 60590#L374 assume !(0 == ~m_st~0); 60591#L378 assume !(0 == ~t1_st~0); 60593#L382 assume !(0 == ~t2_st~0); 60588#L386 assume !(0 == ~t3_st~0); 60589#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 60592#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 60263#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 60264#L416 assume !(0 != eval_~tmp~0#1); 60707#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60706#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60705#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 60704#L502-5 assume !(0 == ~T1_E~0); 60703#L507-3 assume !(0 == ~T2_E~0); 60702#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60701#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60700#L522-3 assume !(0 == ~E_1~0); 60699#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60698#L532-3 assume !(0 == ~E_3~0); 60697#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 60696#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60695#L238-15 assume !(1 == ~m_pc~0); 60694#L238-17 is_master_triggered_~__retres1~0#1 := 0; 60693#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60692#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 60691#L615-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60690#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60689#L257-15 assume !(1 == ~t1_pc~0); 60688#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 60687#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60686#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 60685#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60684#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60683#L276-15 assume 1 == ~t2_pc~0; 60681#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60679#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60677#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 60675#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60674#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60673#L295-15 assume !(1 == ~t3_pc~0); 60672#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 60671#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60670#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 60669#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60668#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60667#L314-15 assume !(1 == ~t4_pc~0); 60665#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 60664#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60663#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 60662#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60661#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60660#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 60659#L555-5 assume !(1 == ~T1_E~0); 60658#L560-3 assume !(1 == ~T2_E~0); 60657#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60656#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60655#L575-3 assume !(1 == ~E_1~0); 60654#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60653#L585-3 assume !(1 == ~E_3~0); 60652#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 60651#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 60649#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 60642#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 60639#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 60635#L795 assume !(0 == start_simulation_~tmp~3#1); 60632#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 60631#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 60625#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 60621#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 60619#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60616#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60610#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 60605#L808 assume !(0 != start_simulation_~tmp___0~1#1); 59478#L776-2 [2023-11-26 10:44:34,769 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:34,769 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 3 times [2023-11-26 10:44:34,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:34,769 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827143256] [2023-11-26 10:44:34,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:34,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:34,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:34,779 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:34,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:34,796 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:34,797 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:34,797 INFO L85 PathProgramCache]: Analyzing trace with hash -1635244259, now seen corresponding path program 1 times [2023-11-26 10:44:34,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:34,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1401405730] [2023-11-26 10:44:34,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:34,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:34,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:34,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:34,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:34,870 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1401405730] [2023-11-26 10:44:34,870 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1401405730] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:34,870 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:34,870 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:44:34,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1517518341] [2023-11-26 10:44:34,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:34,871 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:34,871 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:34,871 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 10:44:34,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 10:44:34,872 INFO L87 Difference]: Start difference. First operand 3204 states and 4401 transitions. cyclomatic complexity: 1205 Second operand has 5 states, 5 states have (on average 15.2) internal successors, (76), 5 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:35,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:35,051 INFO L93 Difference]: Finished difference Result 5695 states and 7704 transitions. [2023-11-26 10:44:35,052 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5695 states and 7704 transitions. [2023-11-26 10:44:35,079 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5601 [2023-11-26 10:44:35,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5695 states to 5695 states and 7704 transitions. [2023-11-26 10:44:35,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5695 [2023-11-26 10:44:35,106 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5695 [2023-11-26 10:44:35,107 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5695 states and 7704 transitions. [2023-11-26 10:44:35,111 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:35,112 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5695 states and 7704 transitions. [2023-11-26 10:44:35,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5695 states and 7704 transitions. [2023-11-26 10:44:35,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5695 to 3285. [2023-11-26 10:44:35,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3285 states, 3285 states have (on average 1.3570776255707762) internal successors, (4458), 3284 states have internal predecessors, (4458), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:35,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3285 states to 3285 states and 4458 transitions. [2023-11-26 10:44:35,180 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3285 states and 4458 transitions. [2023-11-26 10:44:35,180 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 10:44:35,181 INFO L428 stractBuchiCegarLoop]: Abstraction has 3285 states and 4458 transitions. [2023-11-26 10:44:35,181 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 10:44:35,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3285 states and 4458 transitions. [2023-11-26 10:44:35,192 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3198 [2023-11-26 10:44:35,193 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:35,193 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:35,194 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:35,194 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:35,194 INFO L748 eck$LassoCheckResult]: Stem: 68549#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 68550#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 68639#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68640#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68445#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 68446#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68678#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68547#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68380#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68381#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68399#L502 assume !(0 == ~M_E~0); 68400#L502-2 assume !(0 == ~T1_E~0); 68366#L507-1 assume !(0 == ~T2_E~0); 68367#L512-1 assume !(0 == ~T3_E~0); 68449#L517-1 assume !(0 == ~T4_E~0); 68354#L522-1 assume !(0 == ~E_1~0); 68355#L527-1 assume !(0 == ~E_2~0); 68552#L532-1 assume !(0 == ~E_3~0); 68553#L537-1 assume !(0 == ~E_4~0); 68576#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68545#L238 assume !(1 == ~m_pc~0); 68546#L238-2 is_master_triggered_~__retres1~0#1 := 0; 68606#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68527#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 68525#L615 assume !(0 != activate_threads_~tmp~1#1); 68526#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68507#L257 assume !(1 == ~t1_pc~0); 68508#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68544#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68397#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 68398#L623 assume !(0 != activate_threads_~tmp___0~0#1); 68382#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68383#L276 assume !(1 == ~t2_pc~0); 68647#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 68753#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68645#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68646#L631 assume !(0 != activate_threads_~tmp___1~0#1); 68793#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68524#L295 assume !(1 == ~t3_pc~0); 68386#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68387#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68349#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68350#L639 assume !(0 != activate_threads_~tmp___2~0#1); 68778#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68779#L314 assume !(1 == ~t4_pc~0); 68405#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68404#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68437#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68438#L647 assume !(0 != activate_threads_~tmp___3~0#1); 68506#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68748#L555 assume !(1 == ~M_E~0); 68413#L555-2 assume !(1 == ~T1_E~0); 68414#L560-1 assume !(1 == ~T2_E~0); 68356#L565-1 assume !(1 == ~T3_E~0); 68357#L570-1 assume !(1 == ~T4_E~0); 68513#L575-1 assume !(1 == ~E_1~0); 68684#L580-1 assume !(1 == ~E_2~0); 68568#L585-1 assume !(1 == ~E_3~0); 68396#L590-1 assume !(1 == ~E_4~0); 68388#L595-1 assume { :end_inline_reset_delta_events } true; 68389#L776-2 [2023-11-26 10:44:35,195 INFO L750 eck$LassoCheckResult]: Loop: 68389#L776-2 assume !false; 69678#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69677#L477-1 assume !false; 69676#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69672#L374 assume !(0 == ~m_st~0); 69673#L378 assume !(0 == ~t1_st~0); 69675#L382 assume !(0 == ~t2_st~0); 69670#L386 assume !(0 == ~t3_st~0); 69671#L390 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 69674#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69384#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 69385#L416 assume !(0 != eval_~tmp~0#1); 69808#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 69807#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69806#L502-3 assume 0 == ~M_E~0;~M_E~0 := 1; 69805#L502-5 assume !(0 == ~T1_E~0); 69804#L507-3 assume !(0 == ~T2_E~0); 69803#L512-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69802#L517-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69801#L522-3 assume !(0 == ~E_1~0); 69800#L527-3 assume 0 == ~E_2~0;~E_2~0 := 1; 69799#L532-3 assume !(0 == ~E_3~0); 69798#L537-3 assume 0 == ~E_4~0;~E_4~0 := 1; 69797#L542-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69796#L238-15 assume !(1 == ~m_pc~0); 69795#L238-17 is_master_triggered_~__retres1~0#1 := 0; 69794#L249-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69793#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 69792#L615-15 assume !(0 != activate_threads_~tmp~1#1); 69790#L615-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69788#L257-15 assume !(1 == ~t1_pc~0); 69786#L257-17 is_transmit1_triggered_~__retres1~1#1 := 0; 69784#L268-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69782#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 69780#L623-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 69778#L623-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69776#L276-15 assume 1 == ~t2_pc~0; 69773#L277-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69770#L287-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69767#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 69764#L631-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69762#L631-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69759#L295-15 assume !(1 == ~t3_pc~0); 69756#L295-17 is_transmit3_triggered_~__retres1~3#1 := 0; 69753#L306-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69750#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 69748#L639-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69746#L639-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69744#L314-15 assume !(1 == ~t4_pc~0); 69741#L314-17 is_transmit4_triggered_~__retres1~4#1 := 0; 69739#L325-5 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69737#is_transmit4_triggered_returnLabel#6 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 69735#L647-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69733#L647-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69730#L555-3 assume 1 == ~M_E~0;~M_E~0 := 2; 69728#L555-5 assume !(1 == ~T1_E~0); 69726#L560-3 assume !(1 == ~T2_E~0); 69724#L565-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69722#L570-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69720#L575-3 assume !(1 == ~E_1~0); 69718#L580-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69716#L585-3 assume !(1 == ~E_3~0); 69714#L590-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69712#L595-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69709#L374-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69704#L401-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69702#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 69699#L795 assume !(0 == start_simulation_~tmp~3#1); 69697#L795-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69696#L374-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69691#L401-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69690#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 69689#L750 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69687#L757 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69685#stop_simulation_returnLabel#1 start_simulation_#t~ret17#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 69683#L808 assume !(0 != start_simulation_~tmp___0~1#1); 68389#L776-2 [2023-11-26 10:44:35,195 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:35,195 INFO L85 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 4 times [2023-11-26 10:44:35,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:35,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144242355] [2023-11-26 10:44:35,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:35,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:35,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:35,205 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:35,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:35,219 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:35,220 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:35,220 INFO L85 PathProgramCache]: Analyzing trace with hash 303917787, now seen corresponding path program 1 times [2023-11-26 10:44:35,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:35,220 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823336610] [2023-11-26 10:44:35,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:35,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:35,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:35,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:35,255 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:35,255 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1823336610] [2023-11-26 10:44:35,256 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1823336610] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:35,256 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:35,256 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:35,256 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1453367695] [2023-11-26 10:44:35,256 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:35,256 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:44:35,257 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:35,257 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:35,257 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:35,257 INFO L87 Difference]: Start difference. First operand 3285 states and 4458 transitions. cyclomatic complexity: 1181 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:35,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:35,382 INFO L93 Difference]: Finished difference Result 5477 states and 7333 transitions. [2023-11-26 10:44:35,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5477 states and 7333 transitions. [2023-11-26 10:44:35,407 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 5374 [2023-11-26 10:44:35,427 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5477 states to 5477 states and 7333 transitions. [2023-11-26 10:44:35,427 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5477 [2023-11-26 10:44:35,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5477 [2023-11-26 10:44:35,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5477 states and 7333 transitions. [2023-11-26 10:44:35,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:35,437 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5477 states and 7333 transitions. [2023-11-26 10:44:35,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5477 states and 7333 transitions. [2023-11-26 10:44:35,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5477 to 5341. [2023-11-26 10:44:35,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5341 states, 5341 states have (on average 1.3407601572739187) internal successors, (7161), 5340 states have internal predecessors, (7161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:35,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5341 states to 5341 states and 7161 transitions. [2023-11-26 10:44:35,518 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5341 states and 7161 transitions. [2023-11-26 10:44:35,518 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:35,519 INFO L428 stractBuchiCegarLoop]: Abstraction has 5341 states and 7161 transitions. [2023-11-26 10:44:35,519 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 10:44:35,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5341 states and 7161 transitions. [2023-11-26 10:44:35,538 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 5238 [2023-11-26 10:44:35,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:35,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:35,539 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:35,539 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:35,539 INFO L748 eck$LassoCheckResult]: Stem: 77314#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 77315#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 77394#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77395#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77212#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 77213#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77429#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77311#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77148#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77149#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77167#L502 assume !(0 == ~M_E~0); 77168#L502-2 assume !(0 == ~T1_E~0); 77137#L507-1 assume !(0 == ~T2_E~0); 77138#L512-1 assume !(0 == ~T3_E~0); 77215#L517-1 assume !(0 == ~T4_E~0); 77124#L522-1 assume !(0 == ~E_1~0); 77125#L527-1 assume !(0 == ~E_2~0); 77317#L532-1 assume !(0 == ~E_3~0); 77318#L537-1 assume !(0 == ~E_4~0); 77336#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77309#L238 assume !(1 == ~m_pc~0); 77310#L238-2 is_master_triggered_~__retres1~0#1 := 0; 77366#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77291#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 77289#L615 assume !(0 != activate_threads_~tmp~1#1); 77290#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77271#L257 assume !(1 == ~t1_pc~0); 77272#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 77308#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77165#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 77166#L623 assume !(0 != activate_threads_~tmp___0~0#1); 77150#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77151#L276 assume !(1 == ~t2_pc~0); 77401#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 77498#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77399#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 77400#L631 assume !(0 != activate_threads_~tmp___1~0#1); 77537#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77288#L295 assume !(1 == ~t3_pc~0); 77154#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77155#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77117#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77118#L639 assume !(0 != activate_threads_~tmp___2~0#1); 77527#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77528#L314 assume !(1 == ~t4_pc~0); 77173#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 77172#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77205#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 77206#L647 assume !(0 != activate_threads_~tmp___3~0#1); 77270#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77494#L555 assume !(1 == ~M_E~0); 77181#L555-2 assume !(1 == ~T1_E~0); 77182#L560-1 assume !(1 == ~T2_E~0); 77126#L565-1 assume !(1 == ~T3_E~0); 77127#L570-1 assume !(1 == ~T4_E~0); 77277#L575-1 assume !(1 == ~E_1~0); 77435#L580-1 assume !(1 == ~E_2~0); 77329#L585-1 assume !(1 == ~E_3~0); 77164#L590-1 assume !(1 == ~E_4~0); 77156#L595-1 assume { :end_inline_reset_delta_events } true; 77157#L776-2 assume !false; 78803#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 78793#L477-1 [2023-11-26 10:44:35,540 INFO L750 eck$LassoCheckResult]: Loop: 78793#L477-1 assume !false; 78786#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 78779#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 78773#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 78764#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 78704#L416 assume 0 != eval_~tmp~0#1; 78705#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 78730#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 78726#L424-2 havoc eval_~tmp_ndt_1~0#1; 78718#L421-1 assume !(0 == ~t1_st~0); 78719#L435-1 assume !(0 == ~t2_st~0); 78809#L449-1 assume !(0 == ~t3_st~0); 78805#L463-1 assume !(0 == ~t4_st~0); 78793#L477-1 [2023-11-26 10:44:35,540 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:35,540 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 1 times [2023-11-26 10:44:35,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:35,541 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898243397] [2023-11-26 10:44:35,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:35,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:35,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:35,550 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:35,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:35,565 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:35,566 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:35,566 INFO L85 PathProgramCache]: Analyzing trace with hash 105152312, now seen corresponding path program 1 times [2023-11-26 10:44:35,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:35,566 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94950824] [2023-11-26 10:44:35,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:35,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:35,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:35,570 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:35,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:35,574 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:35,574 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:35,574 INFO L85 PathProgramCache]: Analyzing trace with hash 2080098156, now seen corresponding path program 1 times [2023-11-26 10:44:35,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:35,575 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1360411525] [2023-11-26 10:44:35,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:35,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:35,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:35,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:35,611 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:35,611 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1360411525] [2023-11-26 10:44:35,612 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1360411525] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:35,612 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:35,612 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:35,612 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1965337917] [2023-11-26 10:44:35,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:35,710 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:35,711 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:35,711 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:35,712 INFO L87 Difference]: Start difference. First operand 5341 states and 7161 transitions. cyclomatic complexity: 1834 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:35,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:35,790 INFO L93 Difference]: Finished difference Result 9872 states and 13121 transitions. [2023-11-26 10:44:35,790 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9872 states and 13121 transitions. [2023-11-26 10:44:35,840 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 9094 [2023-11-26 10:44:35,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9872 states to 9872 states and 13121 transitions. [2023-11-26 10:44:35,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9872 [2023-11-26 10:44:35,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9872 [2023-11-26 10:44:35,953 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9872 states and 13121 transitions. [2023-11-26 10:44:35,961 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:35,961 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9872 states and 13121 transitions. [2023-11-26 10:44:35,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9872 states and 13121 transitions. [2023-11-26 10:44:36,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9872 to 9432. [2023-11-26 10:44:36,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9432 states, 9432 states have (on average 1.3317430025445292) internal successors, (12561), 9431 states have internal predecessors, (12561), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:36,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9432 states to 9432 states and 12561 transitions. [2023-11-26 10:44:36,101 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9432 states and 12561 transitions. [2023-11-26 10:44:36,101 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:36,102 INFO L428 stractBuchiCegarLoop]: Abstraction has 9432 states and 12561 transitions. [2023-11-26 10:44:36,102 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 10:44:36,102 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9432 states and 12561 transitions. [2023-11-26 10:44:36,137 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 8654 [2023-11-26 10:44:36,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:36,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:36,138 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:36,138 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:36,138 INFO L748 eck$LassoCheckResult]: Stem: 92547#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 92548#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 92635#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 92636#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 92434#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 92435#L341-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 92831#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 92544#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 92545#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 92532#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 92533#L502 assume !(0 == ~M_E~0); 92489#L502-2 assume !(0 == ~T1_E~0); 92490#L507-1 assume !(0 == ~T2_E~0); 92436#L512-1 assume !(0 == ~T3_E~0); 92437#L517-1 assume !(0 == ~T4_E~0); 92343#L522-1 assume !(0 == ~E_1~0); 92344#L527-1 assume !(0 == ~E_2~0); 92550#L532-1 assume !(0 == ~E_3~0); 92551#L537-1 assume !(0 == ~E_4~0); 92572#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92573#L238 assume !(1 == ~m_pc~0); 92602#L238-2 is_master_triggered_~__retres1~0#1 := 0; 92603#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92522#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 92523#L615 assume !(0 != activate_threads_~tmp~1#1); 92659#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92660#L257 assume !(1 == ~t1_pc~0); 92699#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 92700#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92387#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 92388#L623 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 92645#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92641#L276 assume !(1 == ~t2_pc~0); 92642#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 92808#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92809#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 92812#L631 assume !(0 != activate_threads_~tmp___1~0#1); 92813#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92518#L295 assume !(1 == ~t3_pc~0); 92519#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 92502#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92503#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 92795#L639 assume !(0 != activate_threads_~tmp___2~0#1); 92796#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 92840#L314 assume !(1 == ~t4_pc~0); 92841#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 92582#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92583#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 92497#L647 assume !(0 != activate_threads_~tmp___3~0#1); 92498#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92850#L555 assume !(1 == ~M_E~0); 92851#L555-2 assume !(1 == ~T1_E~0); 92834#L560-1 assume !(1 == ~T2_E~0); 92835#L565-1 assume !(1 == ~T3_E~0); 92507#L570-1 assume !(1 == ~T4_E~0); 92508#L575-1 assume !(1 == ~E_1~0); 92767#L580-1 assume !(1 == ~E_2~0); 92768#L585-1 assume !(1 == ~E_3~0); 92383#L590-1 assume !(1 == ~E_4~0); 92384#L595-1 assume { :end_inline_reset_delta_events } true; 93892#L776-2 assume !false; 93888#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 93887#L477-1 [2023-11-26 10:44:36,139 INFO L750 eck$LassoCheckResult]: Loop: 93887#L477-1 assume !false; 93886#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 93884#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 93883#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 93882#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 93881#L416 assume 0 != eval_~tmp~0#1; 93879#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 93877#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 93878#L424-2 havoc eval_~tmp_ndt_1~0#1; 93912#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 93909#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 93906#L438-2 havoc eval_~tmp_ndt_2~0#1; 93901#L435-1 assume !(0 == ~t2_st~0); 93896#L449-1 assume !(0 == ~t3_st~0); 93890#L463-1 assume !(0 == ~t4_st~0); 93887#L477-1 [2023-11-26 10:44:36,139 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:36,139 INFO L85 PathProgramCache]: Analyzing trace with hash 995820945, now seen corresponding path program 1 times [2023-11-26 10:44:36,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:36,140 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [21499800] [2023-11-26 10:44:36,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:36,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:36,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:36,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:36,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:36,166 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [21499800] [2023-11-26 10:44:36,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [21499800] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:36,166 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:36,166 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:36,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1785939017] [2023-11-26 10:44:36,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:36,167 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:44:36,167 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:36,168 INFO L85 PathProgramCache]: Analyzing trace with hash 1964339025, now seen corresponding path program 1 times [2023-11-26 10:44:36,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:36,168 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863377038] [2023-11-26 10:44:36,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:36,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:36,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:36,172 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:36,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:36,176 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:36,264 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:36,264 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:36,265 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:36,265 INFO L87 Difference]: Start difference. First operand 9432 states and 12561 transitions. cyclomatic complexity: 3149 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:36,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:36,368 INFO L93 Difference]: Finished difference Result 7188 states and 9566 transitions. [2023-11-26 10:44:36,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7188 states and 9566 transitions. [2023-11-26 10:44:36,412 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 7073 [2023-11-26 10:44:36,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7188 states to 7188 states and 9566 transitions. [2023-11-26 10:44:36,446 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7188 [2023-11-26 10:44:36,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7188 [2023-11-26 10:44:36,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7188 states and 9566 transitions. [2023-11-26 10:44:36,466 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:36,466 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7188 states and 9566 transitions. [2023-11-26 10:44:36,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7188 states and 9566 transitions. [2023-11-26 10:44:36,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7188 to 7188. [2023-11-26 10:44:36,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7188 states, 7188 states have (on average 1.3308291597106288) internal successors, (9566), 7187 states have internal predecessors, (9566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:36,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7188 states to 7188 states and 9566 transitions. [2023-11-26 10:44:36,596 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7188 states and 9566 transitions. [2023-11-26 10:44:36,597 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:36,597 INFO L428 stractBuchiCegarLoop]: Abstraction has 7188 states and 9566 transitions. [2023-11-26 10:44:36,597 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-26 10:44:36,598 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7188 states and 9566 transitions. [2023-11-26 10:44:36,629 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 7073 [2023-11-26 10:44:36,629 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:36,629 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:36,630 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:36,630 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:36,631 INFO L748 eck$LassoCheckResult]: Stem: 109163#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 109164#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 109245#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 109246#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 109060#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 109061#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 109279#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 109161#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 108995#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 108996#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 109015#L502 assume !(0 == ~M_E~0); 109016#L502-2 assume !(0 == ~T1_E~0); 108981#L507-1 assume !(0 == ~T2_E~0); 108982#L512-1 assume !(0 == ~T3_E~0); 109062#L517-1 assume !(0 == ~T4_E~0); 108969#L522-1 assume !(0 == ~E_1~0); 108970#L527-1 assume !(0 == ~E_2~0); 109166#L532-1 assume !(0 == ~E_3~0); 109167#L537-1 assume !(0 == ~E_4~0); 109187#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 109159#L238 assume !(1 == ~m_pc~0); 109160#L238-2 is_master_triggered_~__retres1~0#1 := 0; 109215#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 109141#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 109139#L615 assume !(0 != activate_threads_~tmp~1#1); 109140#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 109120#L257 assume !(1 == ~t1_pc~0); 109121#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 109156#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 109013#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 109014#L623 assume !(0 != activate_threads_~tmp___0~0#1); 108997#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108998#L276 assume !(1 == ~t2_pc~0); 109251#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 109350#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 109249#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 109250#L631 assume !(0 != activate_threads_~tmp___1~0#1); 109395#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 109138#L295 assume !(1 == ~t3_pc~0); 109002#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 109003#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108964#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 108965#L639 assume !(0 != activate_threads_~tmp___2~0#1); 109381#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 109382#L314 assume !(1 == ~t4_pc~0); 109021#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 109020#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 109052#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 109053#L647 assume !(0 != activate_threads_~tmp___3~0#1); 109119#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109344#L555 assume !(1 == ~M_E~0); 109029#L555-2 assume !(1 == ~T1_E~0); 109030#L560-1 assume !(1 == ~T2_E~0); 108971#L565-1 assume !(1 == ~T3_E~0); 108972#L570-1 assume !(1 == ~T4_E~0); 109127#L575-1 assume !(1 == ~E_1~0); 109285#L580-1 assume !(1 == ~E_2~0); 109179#L585-1 assume !(1 == ~E_3~0); 109010#L590-1 assume !(1 == ~E_4~0); 109004#L595-1 assume { :end_inline_reset_delta_events } true; 109005#L776-2 assume !false; 109485#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 109486#L477-1 [2023-11-26 10:44:36,631 INFO L750 eck$LassoCheckResult]: Loop: 109486#L477-1 assume !false; 109579#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 109577#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 109576#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 109575#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 109574#L416 assume 0 != eval_~tmp~0#1; 109572#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 109571#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 109567#L424-2 havoc eval_~tmp_ndt_1~0#1; 109565#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 109562#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 109561#L438-2 havoc eval_~tmp_ndt_2~0#1; 109550#L435-1 assume !(0 == ~t2_st~0); 109529#L449-1 assume !(0 == ~t3_st~0); 109496#L463-1 assume !(0 == ~t4_st~0); 109486#L477-1 [2023-11-26 10:44:36,632 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:36,632 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 2 times [2023-11-26 10:44:36,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:36,632 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838709440] [2023-11-26 10:44:36,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:36,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:36,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:36,646 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:36,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:36,668 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:36,669 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:36,669 INFO L85 PathProgramCache]: Analyzing trace with hash 1964339025, now seen corresponding path program 2 times [2023-11-26 10:44:36,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:36,670 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [615726110] [2023-11-26 10:44:36,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:36,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:36,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:36,675 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:36,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:36,682 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:36,683 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:36,683 INFO L85 PathProgramCache]: Analyzing trace with hash 1511750277, now seen corresponding path program 1 times [2023-11-26 10:44:36,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:36,684 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [64598005] [2023-11-26 10:44:36,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:36,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:36,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:36,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:36,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:36,737 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [64598005] [2023-11-26 10:44:36,737 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [64598005] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:36,739 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:36,740 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:36,740 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366162517] [2023-11-26 10:44:36,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:36,834 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:36,835 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:36,835 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:36,835 INFO L87 Difference]: Start difference. First operand 7188 states and 9566 transitions. cyclomatic complexity: 2392 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:36,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:36,938 INFO L93 Difference]: Finished difference Result 12625 states and 16724 transitions. [2023-11-26 10:44:36,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12625 states and 16724 transitions. [2023-11-26 10:44:37,016 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 12462 [2023-11-26 10:44:37,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12625 states to 12625 states and 16724 transitions. [2023-11-26 10:44:37,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12625 [2023-11-26 10:44:37,252 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12625 [2023-11-26 10:44:37,252 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12625 states and 16724 transitions. [2023-11-26 10:44:37,282 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:37,282 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12625 states and 16724 transitions. [2023-11-26 10:44:37,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12625 states and 16724 transitions. [2023-11-26 10:44:37,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12625 to 11925. [2023-11-26 10:44:37,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11925 states, 11925 states have (on average 1.3269601677148848) internal successors, (15824), 11924 states have internal predecessors, (15824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:37,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11925 states to 11925 states and 15824 transitions. [2023-11-26 10:44:37,439 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11925 states and 15824 transitions. [2023-11-26 10:44:37,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:37,440 INFO L428 stractBuchiCegarLoop]: Abstraction has 11925 states and 15824 transitions. [2023-11-26 10:44:37,440 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-26 10:44:37,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11925 states and 15824 transitions. [2023-11-26 10:44:37,480 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 11762 [2023-11-26 10:44:37,480 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:37,480 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:37,481 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:37,481 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:37,481 INFO L748 eck$LassoCheckResult]: Stem: 128986#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 128987#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 129084#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 129085#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 128879#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 128880#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 129125#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 128984#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 128815#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 128816#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 128834#L502 assume !(0 == ~M_E~0); 128835#L502-2 assume !(0 == ~T1_E~0); 128802#L507-1 assume !(0 == ~T2_E~0); 128803#L512-1 assume !(0 == ~T3_E~0); 128881#L517-1 assume !(0 == ~T4_E~0); 128790#L522-1 assume !(0 == ~E_1~0); 128791#L527-1 assume !(0 == ~E_2~0); 128989#L532-1 assume !(0 == ~E_3~0); 128990#L537-1 assume !(0 == ~E_4~0); 129013#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 128982#L238 assume !(1 == ~m_pc~0); 128983#L238-2 is_master_triggered_~__retres1~0#1 := 0; 129050#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128962#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 128960#L615 assume !(0 != activate_threads_~tmp~1#1); 128961#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 128942#L257 assume !(1 == ~t1_pc~0); 128943#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 128979#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 128832#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 128833#L623 assume !(0 != activate_threads_~tmp___0~0#1); 128817#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 128818#L276 assume !(1 == ~t2_pc~0); 129093#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 129205#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 129091#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 129092#L631 assume !(0 != activate_threads_~tmp___1~0#1); 129254#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 128959#L295 assume !(1 == ~t3_pc~0); 128821#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 128822#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 128785#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 128786#L639 assume !(0 != activate_threads_~tmp___2~0#1); 129239#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 129240#L314 assume !(1 == ~t4_pc~0); 128840#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 128839#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 128871#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 128872#L647 assume !(0 != activate_threads_~tmp___3~0#1); 128941#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 129200#L555 assume !(1 == ~M_E~0); 128848#L555-2 assume !(1 == ~T1_E~0); 128849#L560-1 assume !(1 == ~T2_E~0); 128792#L565-1 assume !(1 == ~T3_E~0); 128793#L570-1 assume !(1 == ~T4_E~0); 128949#L575-1 assume !(1 == ~E_1~0); 129134#L580-1 assume !(1 == ~E_2~0); 129003#L585-1 assume !(1 == ~E_3~0); 128829#L590-1 assume !(1 == ~E_4~0); 128823#L595-1 assume { :end_inline_reset_delta_events } true; 128824#L776-2 assume !false; 136197#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 136195#L477-1 [2023-11-26 10:44:37,482 INFO L750 eck$LassoCheckResult]: Loop: 136195#L477-1 assume !false; 136193#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 136190#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 136188#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 136186#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 136184#L416 assume 0 != eval_~tmp~0#1; 136180#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 136177#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 136178#L424-2 havoc eval_~tmp_ndt_1~0#1; 136220#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 136217#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 136213#L438-2 havoc eval_~tmp_ndt_2~0#1; 136211#L435-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 133982#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 136207#L452-2 havoc eval_~tmp_ndt_3~0#1; 136204#L449-1 assume !(0 == ~t3_st~0); 136199#L463-1 assume !(0 == ~t4_st~0); 136195#L477-1 [2023-11-26 10:44:37,482 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:37,482 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 3 times [2023-11-26 10:44:37,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:37,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2016252387] [2023-11-26 10:44:37,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:37,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:37,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:37,493 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:37,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:37,508 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:37,508 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:37,508 INFO L85 PathProgramCache]: Analyzing trace with hash 2090989624, now seen corresponding path program 1 times [2023-11-26 10:44:37,509 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:37,509 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143412413] [2023-11-26 10:44:37,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:37,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:37,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:37,513 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:37,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:37,517 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:37,517 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:37,517 INFO L85 PathProgramCache]: Analyzing trace with hash 944899692, now seen corresponding path program 1 times [2023-11-26 10:44:37,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:37,518 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433556791] [2023-11-26 10:44:37,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:37,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:37,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:37,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:37,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:37,675 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1433556791] [2023-11-26 10:44:37,675 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1433556791] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:37,675 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:37,675 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:44:37,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1022352087] [2023-11-26 10:44:37,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:37,767 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:37,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:37,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:37,768 INFO L87 Difference]: Start difference. First operand 11925 states and 15824 transitions. cyclomatic complexity: 3913 Second operand has 3 states, 3 states have (on average 26.333333333333332) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:37,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:37,866 INFO L93 Difference]: Finished difference Result 14963 states and 19745 transitions. [2023-11-26 10:44:37,866 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14963 states and 19745 transitions. [2023-11-26 10:44:37,937 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 14772 [2023-11-26 10:44:37,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14963 states to 14963 states and 19745 transitions. [2023-11-26 10:44:37,996 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14963 [2023-11-26 10:44:38,006 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14963 [2023-11-26 10:44:38,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14963 states and 19745 transitions. [2023-11-26 10:44:38,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:38,016 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14963 states and 19745 transitions. [2023-11-26 10:44:38,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14963 states and 19745 transitions. [2023-11-26 10:44:38,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14963 to 14523. [2023-11-26 10:44:38,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14523 states, 14523 states have (on average 1.3210080561867383) internal successors, (19185), 14522 states have internal predecessors, (19185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:38,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14523 states to 14523 states and 19185 transitions. [2023-11-26 10:44:38,298 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14523 states and 19185 transitions. [2023-11-26 10:44:38,299 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:38,299 INFO L428 stractBuchiCegarLoop]: Abstraction has 14523 states and 19185 transitions. [2023-11-26 10:44:38,299 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-26 10:44:38,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14523 states and 19185 transitions. [2023-11-26 10:44:38,347 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 14332 [2023-11-26 10:44:38,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:38,349 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:38,349 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:38,349 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:38,350 INFO L748 eck$LassoCheckResult]: Stem: 155882#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 155883#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 155974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 155975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 155776#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 155777#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 156016#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 155880#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 155711#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 155712#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 155731#L502 assume !(0 == ~M_E~0); 155732#L502-2 assume !(0 == ~T1_E~0); 155698#L507-1 assume !(0 == ~T2_E~0); 155699#L512-1 assume !(0 == ~T3_E~0); 155778#L517-1 assume !(0 == ~T4_E~0); 155686#L522-1 assume !(0 == ~E_1~0); 155687#L527-1 assume !(0 == ~E_2~0); 155885#L532-1 assume !(0 == ~E_3~0); 155886#L537-1 assume !(0 == ~E_4~0); 155908#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 155878#L238 assume !(1 == ~m_pc~0); 155879#L238-2 is_master_triggered_~__retres1~0#1 := 0; 155937#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 155860#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 155858#L615 assume !(0 != activate_threads_~tmp~1#1); 155859#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 155839#L257 assume !(1 == ~t1_pc~0); 155840#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 155875#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 155729#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 155730#L623 assume !(0 != activate_threads_~tmp___0~0#1); 155713#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 155714#L276 assume !(1 == ~t2_pc~0); 155982#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 156092#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 155980#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 155981#L631 assume !(0 != activate_threads_~tmp___1~0#1); 156137#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 155857#L295 assume !(1 == ~t3_pc~0); 155718#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 155719#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 155681#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 155682#L639 assume !(0 != activate_threads_~tmp___2~0#1); 156123#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 156124#L314 assume !(1 == ~t4_pc~0); 155737#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 155736#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155768#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 155769#L647 assume !(0 != activate_threads_~tmp___3~0#1); 155838#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 156088#L555 assume !(1 == ~M_E~0); 155745#L555-2 assume !(1 == ~T1_E~0); 155746#L560-1 assume !(1 == ~T2_E~0); 155688#L565-1 assume !(1 == ~T3_E~0); 155689#L570-1 assume !(1 == ~T4_E~0); 155846#L575-1 assume !(1 == ~E_1~0); 156023#L580-1 assume !(1 == ~E_2~0); 155898#L585-1 assume !(1 == ~E_3~0); 155726#L590-1 assume !(1 == ~E_4~0); 155720#L595-1 assume { :end_inline_reset_delta_events } true; 155721#L776-2 assume !false; 164467#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 164465#L477-1 [2023-11-26 10:44:38,350 INFO L750 eck$LassoCheckResult]: Loop: 164465#L477-1 assume !false; 164463#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 164459#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 164457#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 164455#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 164452#L416 assume 0 != eval_~tmp~0#1; 164449#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 164446#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 164447#L424-2 havoc eval_~tmp_ndt_1~0#1; 165162#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 165154#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 165156#L438-2 havoc eval_~tmp_ndt_2~0#1; 164486#L435-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 164483#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 164481#L452-2 havoc eval_~tmp_ndt_3~0#1; 164478#L449-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 164475#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 164473#L466-2 havoc eval_~tmp_ndt_4~0#1; 164469#L463-1 assume !(0 == ~t4_st~0); 164465#L477-1 [2023-11-26 10:44:38,350 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:38,351 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 4 times [2023-11-26 10:44:38,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:38,351 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [733889110] [2023-11-26 10:44:38,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:38,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:38,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:38,360 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:38,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:38,381 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:38,381 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:38,382 INFO L85 PathProgramCache]: Analyzing trace with hash -608301423, now seen corresponding path program 1 times [2023-11-26 10:44:38,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:38,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1432309653] [2023-11-26 10:44:38,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:38,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:38,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:38,387 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:38,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:38,393 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:38,393 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:38,393 INFO L85 PathProgramCache]: Analyzing trace with hash 1805868997, now seen corresponding path program 1 times [2023-11-26 10:44:38,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:38,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [109772547] [2023-11-26 10:44:38,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:38,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:38,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:44:38,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:44:38,439 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:44:38,439 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [109772547] [2023-11-26 10:44:38,439 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [109772547] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:44:38,439 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:44:38,439 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:44:38,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1603477692] [2023-11-26 10:44:38,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:44:38,533 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:44:38,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:44:38,533 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:44:38,534 INFO L87 Difference]: Start difference. First operand 14523 states and 19185 transitions. cyclomatic complexity: 4677 Second operand has 3 states, 2 states have (on average 40.5) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:38,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:44:38,787 INFO L93 Difference]: Finished difference Result 27493 states and 36157 transitions. [2023-11-26 10:44:38,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27493 states and 36157 transitions. [2023-11-26 10:44:38,946 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 27178 [2023-11-26 10:44:39,076 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27493 states to 27493 states and 36157 transitions. [2023-11-26 10:44:39,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27493 [2023-11-26 10:44:39,096 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27493 [2023-11-26 10:44:39,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27493 states and 36157 transitions. [2023-11-26 10:44:39,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:44:39,118 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27493 states and 36157 transitions. [2023-11-26 10:44:39,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27493 states and 36157 transitions. [2023-11-26 10:44:39,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27493 to 27493. [2023-11-26 10:44:39,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27493 states, 27493 states have (on average 1.3151347615756739) internal successors, (36157), 27492 states have internal predecessors, (36157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:44:39,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27493 states to 27493 states and 36157 transitions. [2023-11-26 10:44:39,831 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27493 states and 36157 transitions. [2023-11-26 10:44:39,831 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:44:39,832 INFO L428 stractBuchiCegarLoop]: Abstraction has 27493 states and 36157 transitions. [2023-11-26 10:44:39,832 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-26 10:44:39,832 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27493 states and 36157 transitions. [2023-11-26 10:44:39,928 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 27178 [2023-11-26 10:44:39,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:44:39,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:44:39,930 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:39,930 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:44:39,930 INFO L748 eck$LassoCheckResult]: Stem: 197905#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 197906#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 197997#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 197998#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 197801#L341 assume 1 == ~m_i~0;~m_st~0 := 0; 197802#L341-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 198034#L346-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 197902#L351-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 197735#L356-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 197736#L361-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 197755#L502 assume !(0 == ~M_E~0); 197756#L502-2 assume !(0 == ~T1_E~0); 197722#L507-1 assume !(0 == ~T2_E~0); 197723#L512-1 assume !(0 == ~T3_E~0); 197803#L517-1 assume !(0 == ~T4_E~0); 197710#L522-1 assume !(0 == ~E_1~0); 197711#L527-1 assume !(0 == ~E_2~0); 197908#L532-1 assume !(0 == ~E_3~0); 197909#L537-1 assume !(0 == ~E_4~0); 197929#L542-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 197900#L238 assume !(1 == ~m_pc~0); 197901#L238-2 is_master_triggered_~__retres1~0#1 := 0; 197960#L249 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 197884#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 197882#L615 assume !(0 != activate_threads_~tmp~1#1); 197883#L615-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 197863#L257 assume !(1 == ~t1_pc~0); 197864#L257-2 is_transmit1_triggered_~__retres1~1#1 := 0; 197897#L268 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 197753#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 197754#L623 assume !(0 != activate_threads_~tmp___0~0#1); 197737#L623-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 197738#L276 assume !(1 == ~t2_pc~0); 198004#L276-2 is_transmit2_triggered_~__retres1~2#1 := 0; 198115#L287 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198002#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 198003#L631 assume !(0 != activate_threads_~tmp___1~0#1); 198163#L631-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 197881#L295 assume !(1 == ~t3_pc~0); 197742#L295-2 is_transmit3_triggered_~__retres1~3#1 := 0; 197743#L306 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 197705#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 197706#L639 assume !(0 != activate_threads_~tmp___2~0#1); 198150#L639-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 198151#L314 assume !(1 == ~t4_pc~0); 197761#L314-2 is_transmit4_triggered_~__retres1~4#1 := 0; 197760#L325 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 197793#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 197794#L647 assume !(0 != activate_threads_~tmp___3~0#1); 197862#L647-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 198111#L555 assume !(1 == ~M_E~0); 197769#L555-2 assume !(1 == ~T1_E~0); 197770#L560-1 assume !(1 == ~T2_E~0); 197712#L565-1 assume !(1 == ~T3_E~0); 197713#L570-1 assume !(1 == ~T4_E~0); 197870#L575-1 assume !(1 == ~E_1~0); 198040#L580-1 assume !(1 == ~E_2~0); 197920#L585-1 assume !(1 == ~E_3~0); 197750#L590-1 assume !(1 == ~E_4~0); 197744#L595-1 assume { :end_inline_reset_delta_events } true; 197745#L776-2 assume !false; 202393#L777 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 202391#L477-1 [2023-11-26 10:44:39,930 INFO L750 eck$LassoCheckResult]: Loop: 202391#L477-1 assume !false; 202389#L412 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 202385#L374 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 202382#L401 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 202381#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 202379#L416 assume 0 != eval_~tmp~0#1; 202376#L416-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 202374#L424 assume !(0 != eval_~tmp_ndt_1~0#1); 202373#L424-2 havoc eval_~tmp_ndt_1~0#1; 202372#L421-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 202370#L438 assume !(0 != eval_~tmp_ndt_2~0#1); 202371#L438-2 havoc eval_~tmp_ndt_2~0#1; 202750#L435-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 202748#L452 assume !(0 != eval_~tmp_ndt_3~0#1); 202746#L452-2 havoc eval_~tmp_ndt_3~0#1; 202744#L449-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 202741#L466 assume !(0 != eval_~tmp_ndt_4~0#1); 202740#L466-2 havoc eval_~tmp_ndt_4~0#1; 202398#L463-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 202395#L480 assume !(0 != eval_~tmp_ndt_5~0#1); 202394#L480-2 havoc eval_~tmp_ndt_5~0#1; 202391#L477-1 [2023-11-26 10:44:39,931 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:39,932 INFO L85 PathProgramCache]: Analyzing trace with hash 9663309, now seen corresponding path program 5 times [2023-11-26 10:44:39,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:39,932 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2011327780] [2023-11-26 10:44:39,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:39,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:39,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:39,943 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:39,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:39,959 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:39,960 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:39,960 INFO L85 PathProgramCache]: Analyzing trace with hash -462124120, now seen corresponding path program 1 times [2023-11-26 10:44:39,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:39,960 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968233624] [2023-11-26 10:44:39,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:39,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:39,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:39,965 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:39,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:39,970 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:39,970 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:44:39,970 INFO L85 PathProgramCache]: Analyzing trace with hash 273309660, now seen corresponding path program 1 times [2023-11-26 10:44:39,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:44:39,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834044523] [2023-11-26 10:44:39,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:44:39,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:44:39,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:39,982 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:39,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:40,003 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-26 10:44:41,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:41,758 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-26 10:44:41,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-26 10:44:41,962 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.11 10:44:41 BoogieIcfgContainer [2023-11-26 10:44:41,962 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-26 10:44:41,963 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-26 10:44:41,963 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-26 10:44:41,963 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-26 10:44:41,964 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:44:29" (3/4) ... [2023-11-26 10:44:41,966 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-26 10:44:42,056 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/witness.graphml [2023-11-26 10:44:42,056 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-26 10:44:42,057 INFO L158 Benchmark]: Toolchain (without parser) took 14695.79ms. Allocated memory was 117.4MB in the beginning and 2.4GB in the end (delta: 2.3GB). Free memory was 72.0MB in the beginning and 2.0GB in the end (delta: -2.0GB). Peak memory consumption was 344.7MB. Max. memory is 16.1GB. [2023-11-26 10:44:42,057 INFO L158 Benchmark]: CDTParser took 0.34ms. Allocated memory is still 117.4MB. Free memory is still 91.6MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-26 10:44:42,058 INFO L158 Benchmark]: CACSL2BoogieTranslator took 438.68ms. Allocated memory is still 117.4MB. Free memory was 72.0MB in the beginning and 56.7MB in the end (delta: 15.2MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-26 10:44:42,058 INFO L158 Benchmark]: Boogie Procedure Inliner took 84.33ms. Allocated memory is still 117.4MB. Free memory was 56.7MB in the beginning and 52.7MB in the end (delta: 4.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-26 10:44:42,059 INFO L158 Benchmark]: Boogie Preprocessor took 91.97ms. Allocated memory is still 117.4MB. Free memory was 52.7MB in the beginning and 47.7MB in the end (delta: 5.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-26 10:44:42,059 INFO L158 Benchmark]: RCFGBuilder took 1345.01ms. Allocated memory was 117.4MB in the beginning and 155.2MB in the end (delta: 37.7MB). Free memory was 47.7MB in the beginning and 84.7MB in the end (delta: -37.0MB). Peak memory consumption was 10.7MB. Max. memory is 16.1GB. [2023-11-26 10:44:42,060 INFO L158 Benchmark]: BuchiAutomizer took 12635.82ms. Allocated memory was 155.2MB in the beginning and 2.4GB in the end (delta: 2.3GB). Free memory was 84.7MB in the beginning and 2.0GB in the end (delta: -2.0GB). Peak memory consumption was 308.8MB. Max. memory is 16.1GB. [2023-11-26 10:44:42,060 INFO L158 Benchmark]: Witness Printer took 93.82ms. Allocated memory is still 2.4GB. Free memory was 2.0GB in the beginning and 2.0GB in the end (delta: 9.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2023-11-26 10:44:42,062 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.34ms. Allocated memory is still 117.4MB. Free memory is still 91.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 438.68ms. Allocated memory is still 117.4MB. Free memory was 72.0MB in the beginning and 56.7MB in the end (delta: 15.2MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 84.33ms. Allocated memory is still 117.4MB. Free memory was 56.7MB in the beginning and 52.7MB in the end (delta: 4.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 91.97ms. Allocated memory is still 117.4MB. Free memory was 52.7MB in the beginning and 47.7MB in the end (delta: 5.0MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1345.01ms. Allocated memory was 117.4MB in the beginning and 155.2MB in the end (delta: 37.7MB). Free memory was 47.7MB in the beginning and 84.7MB in the end (delta: -37.0MB). Peak memory consumption was 10.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 12635.82ms. Allocated memory was 155.2MB in the beginning and 2.4GB in the end (delta: 2.3GB). Free memory was 84.7MB in the beginning and 2.0GB in the end (delta: -2.0GB). Peak memory consumption was 308.8MB. Max. memory is 16.1GB. * Witness Printer took 93.82ms. Allocated memory is still 2.4GB. Free memory was 2.0GB in the beginning and 2.0GB in the end (delta: 9.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (22 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.22 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 27493 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 12.4s and 23 iterations. TraceHistogramMax:1. Analysis of lassos took 5.2s. Construction of modules took 0.7s. Büchi inclusion checks took 5.7s. Highest rank in rank-based complementation 0. Minimization of det autom 22. Minimization of nondet autom 0. Automata minimization 2.4s AutomataMinimizationTime, 22 MinimizatonAttempts, 13152 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 1.6s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 13432 SdHoareTripleChecker+Valid, 0.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 13432 mSDsluCounter, 24279 SdHoareTripleChecker+Invalid, 0.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 10724 mSDsCounter, 236 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 619 IncrementalHoareTripleChecker+Invalid, 855 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 236 mSolverCounterUnsat, 13555 mSDtfsCounter, 619 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 411]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int m_i ; [L36] int t1_i ; [L37] int t2_i ; [L38] int t3_i ; [L39] int t4_i ; [L40] int M_E = 2; [L41] int T1_E = 2; [L42] int T2_E = 2; [L43] int T3_E = 2; [L44] int T4_E = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0] [L821] int __retres1 ; [L825] CALL init_model() [L733] m_i = 1 [L734] t1_i = 1 [L735] t2_i = 1 [L736] t3_i = 1 [L737] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L825] RET init_model() [L826] CALL start_simulation() [L762] int kernel_st ; [L763] int tmp ; [L764] int tmp___0 ; [L768] kernel_st = 0 [L769] FCALL update_channels() [L770] CALL init_threads() [L341] COND TRUE m_i == 1 [L342] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t1_i == 1 [L347] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t2_i == 1 [L352] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L356] COND TRUE t3_i == 1 [L357] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L361] COND TRUE t4_i == 1 [L362] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L770] RET init_threads() [L771] CALL fire_delta_events() [L502] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L537] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L542] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L771] RET fire_delta_events() [L772] CALL activate_threads() [L605] int tmp ; [L606] int tmp___0 ; [L607] int tmp___1 ; [L608] int tmp___2 ; [L609] int tmp___3 ; [L613] CALL, EXPR is_master_triggered() [L235] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L238] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L248] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L250] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L613] RET, EXPR is_master_triggered() [L613] tmp = is_master_triggered() [L615] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L621] CALL, EXPR is_transmit1_triggered() [L254] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L257] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L267] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L269] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L621] RET, EXPR is_transmit1_triggered() [L621] tmp___0 = is_transmit1_triggered() [L623] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L629] CALL, EXPR is_transmit2_triggered() [L273] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L276] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L286] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L288] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L629] RET, EXPR is_transmit2_triggered() [L629] tmp___1 = is_transmit2_triggered() [L631] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L637] CALL, EXPR is_transmit3_triggered() [L292] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L295] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L305] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L307] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L637] RET, EXPR is_transmit3_triggered() [L637] tmp___2 = is_transmit3_triggered() [L639] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L645] CALL, EXPR is_transmit4_triggered() [L311] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L314] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L324] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L326] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L645] RET, EXPR is_transmit4_triggered() [L645] tmp___3 = is_transmit4_triggered() [L647] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L772] RET activate_threads() [L773] CALL reset_delta_events() [L555] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L590] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L595] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L773] RET reset_delta_events() [L776] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L779] kernel_st = 1 [L780] CALL eval() [L407] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] Loop: [L411] COND TRUE 1 [L414] CALL, EXPR exists_runnable_thread() [L371] int __retres1 ; [L374] COND TRUE m_st == 0 [L375] __retres1 = 1 [L402] return (__retres1); [L414] RET, EXPR exists_runnable_thread() [L414] tmp = exists_runnable_thread() [L416] COND TRUE \read(tmp) [L421] COND TRUE m_st == 0 [L422] int tmp_ndt_1; [L423] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L424] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L421-L432] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L435] COND TRUE t1_st == 0 [L436] int tmp_ndt_2; [L437] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L438] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L435-L446] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L449] COND TRUE t2_st == 0 [L450] int tmp_ndt_3; [L451] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L452] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L449-L460] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L463] COND TRUE t3_st == 0 [L464] int tmp_ndt_4; [L465] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L466] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L463-L474] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L477] COND TRUE t4_st == 0 [L478] int tmp_ndt_5; [L479] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L480] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L477-L488] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 411]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int m_i ; [L36] int t1_i ; [L37] int t2_i ; [L38] int t3_i ; [L39] int t4_i ; [L40] int M_E = 2; [L41] int T1_E = 2; [L42] int T2_E = 2; [L43] int T3_E = 2; [L44] int T4_E = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0] [L821] int __retres1 ; [L825] CALL init_model() [L733] m_i = 1 [L734] t1_i = 1 [L735] t2_i = 1 [L736] t3_i = 1 [L737] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L825] RET init_model() [L826] CALL start_simulation() [L762] int kernel_st ; [L763] int tmp ; [L764] int tmp___0 ; [L768] kernel_st = 0 [L769] FCALL update_channels() [L770] CALL init_threads() [L341] COND TRUE m_i == 1 [L342] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L346] COND TRUE t1_i == 1 [L347] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L351] COND TRUE t2_i == 1 [L352] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L356] COND TRUE t3_i == 1 [L357] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L361] COND TRUE t4_i == 1 [L362] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L770] RET init_threads() [L771] CALL fire_delta_events() [L502] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L507] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L512] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L517] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L522] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L527] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L532] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L537] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L542] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L771] RET fire_delta_events() [L772] CALL activate_threads() [L605] int tmp ; [L606] int tmp___0 ; [L607] int tmp___1 ; [L608] int tmp___2 ; [L609] int tmp___3 ; [L613] CALL, EXPR is_master_triggered() [L235] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L238] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L248] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L250] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L613] RET, EXPR is_master_triggered() [L613] tmp = is_master_triggered() [L615] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0] [L621] CALL, EXPR is_transmit1_triggered() [L254] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L257] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L267] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L269] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L621] RET, EXPR is_transmit1_triggered() [L621] tmp___0 = is_transmit1_triggered() [L623] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0] [L629] CALL, EXPR is_transmit2_triggered() [L273] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L276] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L286] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L288] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L629] RET, EXPR is_transmit2_triggered() [L629] tmp___1 = is_transmit2_triggered() [L631] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0] [L637] CALL, EXPR is_transmit3_triggered() [L292] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L295] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L305] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L307] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L637] RET, EXPR is_transmit3_triggered() [L637] tmp___2 = is_transmit3_triggered() [L639] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L645] CALL, EXPR is_transmit4_triggered() [L311] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L314] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L324] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L326] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L645] RET, EXPR is_transmit4_triggered() [L645] tmp___3 = is_transmit4_triggered() [L647] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L772] RET activate_threads() [L773] CALL reset_delta_events() [L555] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L560] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L565] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L570] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L575] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L580] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L585] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L590] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L595] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L773] RET reset_delta_events() [L776] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] [L779] kernel_st = 1 [L780] CALL eval() [L407] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0] Loop: [L411] COND TRUE 1 [L414] CALL, EXPR exists_runnable_thread() [L371] int __retres1 ; [L374] COND TRUE m_st == 0 [L375] __retres1 = 1 [L402] return (__retres1); [L414] RET, EXPR exists_runnable_thread() [L414] tmp = exists_runnable_thread() [L416] COND TRUE \read(tmp) [L421] COND TRUE m_st == 0 [L422] int tmp_ndt_1; [L423] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L424] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L421-L432] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L435] COND TRUE t1_st == 0 [L436] int tmp_ndt_2; [L437] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L438] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L435-L446] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L449] COND TRUE t2_st == 0 [L450] int tmp_ndt_3; [L451] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L452] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L449-L460] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L463] COND TRUE t3_st == 0 [L464] int tmp_ndt_4; [L465] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L466] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L463-L474] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L477] COND TRUE t4_st == 0 [L478] int tmp_ndt_5; [L479] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L480] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L477-L488] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-26 10:44:42,180 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2533260b-82af-42cf-9cb5-a6b15429b16d/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)