./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.12.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.12.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-26 10:49:53,601 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-26 10:49:53,717 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-26 10:49:53,729 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-26 10:49:53,729 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-26 10:49:53,754 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-26 10:49:53,754 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-26 10:49:53,755 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-26 10:49:53,756 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-26 10:49:53,756 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-26 10:49:53,757 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-26 10:49:53,758 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-26 10:49:53,759 INFO L153 SettingsManager]: * Use SBE=true [2023-11-26 10:49:53,759 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-26 10:49:53,760 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-26 10:49:53,760 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-26 10:49:53,761 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-26 10:49:53,762 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-26 10:49:53,762 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-26 10:49:53,763 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-26 10:49:53,763 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-26 10:49:53,768 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-26 10:49:53,769 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-26 10:49:53,769 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-26 10:49:53,769 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-26 10:49:53,770 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-26 10:49:53,770 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-26 10:49:53,771 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-26 10:49:53,771 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-26 10:49:53,771 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-26 10:49:53,773 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-26 10:49:53,773 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-26 10:49:53,773 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-26 10:49:53,773 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-26 10:49:53,774 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-26 10:49:53,774 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-26 10:49:53,774 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-26 10:49:53,775 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-26 10:49:53,775 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 [2023-11-26 10:49:54,075 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-26 10:49:54,105 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-26 10:49:54,108 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-26 10:49:54,110 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-26 10:49:54,110 INFO L274 PluginConnector]: CDTParser initialized [2023-11-26 10:49:54,114 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme/../../sv-benchmarks/c/systemc/transmitter.12.cil.c [2023-11-26 10:49:57,282 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-26 10:49:57,519 INFO L384 CDTParser]: Found 1 translation units. [2023-11-26 10:49:57,523 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/sv-benchmarks/c/systemc/transmitter.12.cil.c [2023-11-26 10:49:57,556 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme/data/5125983ab/33e0434118ad4fc18a7dee65e5a0e4ef/FLAG2beeed436 [2023-11-26 10:49:57,575 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme/data/5125983ab/33e0434118ad4fc18a7dee65e5a0e4ef [2023-11-26 10:49:57,581 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-26 10:49:57,585 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-26 10:49:57,586 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-26 10:49:57,587 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-26 10:49:57,593 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-26 10:49:57,594 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:49:57" (1/1) ... [2023-11-26 10:49:57,595 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@167048db and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:57, skipping insertion in model container [2023-11-26 10:49:57,595 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 10:49:57" (1/1) ... [2023-11-26 10:49:57,663 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-26 10:49:58,033 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:49:58,051 INFO L202 MainTranslator]: Completed pre-run [2023-11-26 10:49:58,144 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-26 10:49:58,183 INFO L206 MainTranslator]: Completed translation [2023-11-26 10:49:58,183 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:58 WrapperNode [2023-11-26 10:49:58,183 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-26 10:49:58,185 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-26 10:49:58,185 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-26 10:49:58,185 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-26 10:49:58,194 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:58" (1/1) ... [2023-11-26 10:49:58,223 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:58" (1/1) ... [2023-11-26 10:49:58,389 INFO L138 Inliner]: procedures = 52, calls = 67, calls flagged for inlining = 62, calls inlined = 255, statements flattened = 3936 [2023-11-26 10:49:58,390 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-26 10:49:58,391 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-26 10:49:58,391 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-26 10:49:58,391 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-26 10:49:58,406 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:58" (1/1) ... [2023-11-26 10:49:58,407 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:58" (1/1) ... [2023-11-26 10:49:58,425 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:58" (1/1) ... [2023-11-26 10:49:58,476 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-26 10:49:58,476 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:58" (1/1) ... [2023-11-26 10:49:58,477 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:58" (1/1) ... [2023-11-26 10:49:58,543 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:58" (1/1) ... [2023-11-26 10:49:58,603 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:58" (1/1) ... [2023-11-26 10:49:58,609 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:58" (1/1) ... [2023-11-26 10:49:58,623 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:58" (1/1) ... [2023-11-26 10:49:58,640 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-26 10:49:58,641 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-26 10:49:58,641 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-26 10:49:58,641 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-26 10:49:58,642 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:58" (1/1) ... [2023-11-26 10:49:58,649 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-26 10:49:58,662 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme/z3 [2023-11-26 10:49:58,677 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-26 10:49:58,717 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_616a6f0d-b5ae-4153-9c23-1bd660bd5ba7/bin/uautomizer-verify-VRDe98Ueme/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-26 10:49:58,745 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-26 10:49:58,745 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-26 10:49:58,745 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-26 10:49:58,745 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-26 10:49:58,905 INFO L241 CfgBuilder]: Building ICFG [2023-11-26 10:49:58,907 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-26 10:50:01,258 INFO L282 CfgBuilder]: Performing block encoding [2023-11-26 10:50:01,309 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-26 10:50:01,309 INFO L309 CfgBuilder]: Removed 16 assume(true) statements. [2023-11-26 10:50:01,312 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:50:01 BoogieIcfgContainer [2023-11-26 10:50:01,313 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-26 10:50:01,315 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-26 10:50:01,315 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-26 10:50:01,319 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-26 10:50:01,320 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:50:01,321 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.11 10:49:57" (1/3) ... [2023-11-26 10:50:01,322 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4d74dacc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:50:01, skipping insertion in model container [2023-11-26 10:50:01,322 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:50:01,324 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 10:49:58" (2/3) ... [2023-11-26 10:50:01,326 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4d74dacc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.11 10:50:01, skipping insertion in model container [2023-11-26 10:50:01,326 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-26 10:50:01,327 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 10:50:01" (3/3) ... [2023-11-26 10:50:01,328 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.12.cil.c [2023-11-26 10:50:01,430 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-26 10:50:01,430 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-26 10:50:01,430 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-26 10:50:01,430 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-26 10:50:01,430 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-26 10:50:01,430 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-26 10:50:01,430 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-26 10:50:01,430 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-26 10:50:01,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1709 states, 1708 states have (on average 1.4976580796252927) internal successors, (2558), 1708 states have internal predecessors, (2558), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:01,535 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1544 [2023-11-26 10:50:01,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:01,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:01,562 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:01,565 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:01,565 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-26 10:50:01,570 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1709 states, 1708 states have (on average 1.4976580796252927) internal successors, (2558), 1708 states have internal predecessors, (2558), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:01,599 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1544 [2023-11-26 10:50:01,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:01,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:01,610 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:01,610 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:01,621 INFO L748 eck$LassoCheckResult]: Stem: 130#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1621#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 630#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1617#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 524#L821true assume !(1 == ~m_i~0);~m_st~0 := 2; 599#L821-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 871#L826-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1186#L831-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1028#L836-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1334#L841-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 119#L846-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1636#L851-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 941#L856-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 450#L861-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 477#L866-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 392#L871-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 706#L876-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 701#L881-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 240#L1174true assume !(0 == ~M_E~0); 1357#L1174-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 163#L1179-1true assume !(0 == ~T2_E~0); 117#L1184-1true assume !(0 == ~T3_E~0); 138#L1189-1true assume !(0 == ~T4_E~0); 184#L1194-1true assume !(0 == ~T5_E~0); 811#L1199-1true assume !(0 == ~T6_E~0); 977#L1204-1true assume !(0 == ~T7_E~0); 740#L1209-1true assume !(0 == ~T8_E~0); 1248#L1214-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1651#L1219-1true assume !(0 == ~T10_E~0); 1571#L1224-1true assume !(0 == ~T11_E~0); 306#L1229-1true assume !(0 == ~T12_E~0); 84#L1234-1true assume !(0 == ~E_1~0); 489#L1239-1true assume !(0 == ~E_2~0); 98#L1244-1true assume !(0 == ~E_3~0); 1340#L1249-1true assume !(0 == ~E_4~0); 465#L1254-1true assume 0 == ~E_5~0;~E_5~0 := 1; 50#L1259-1true assume !(0 == ~E_6~0); 30#L1264-1true assume !(0 == ~E_7~0); 1702#L1269-1true assume !(0 == ~E_8~0); 1624#L1274-1true assume !(0 == ~E_9~0); 1328#L1279-1true assume !(0 == ~E_10~0); 140#L1284-1true assume !(0 == ~E_11~0); 1473#L1289-1true assume !(0 == ~E_12~0); 503#L1294-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1344#L566true assume 1 == ~m_pc~0; 37#L567true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 970#L577true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 538#is_master_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1193#L1455true assume !(0 != activate_threads_~tmp~1#1); 252#L1455-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 783#L585true assume 1 == ~t1_pc~0; 83#L586true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1627#L596true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 861#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1546#L1463true assume !(0 != activate_threads_~tmp___0~0#1); 1414#L1463-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1405#L604true assume !(1 == ~t2_pc~0); 776#L604-2true is_transmit2_triggered_~__retres1~2#1 := 0; 1366#L615true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1202#L1471true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 984#L1471-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1471#L623true assume 1 == ~t3_pc~0; 356#L624true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1676#L634true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 836#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1021#L1479true assume !(0 != activate_threads_~tmp___2~0#1); 1246#L1479-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36#L642true assume !(1 == ~t4_pc~0); 670#L642-2true is_transmit4_triggered_~__retres1~4#1 := 0; 259#L653true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 72#L1487true assume !(0 != activate_threads_~tmp___3~0#1); 787#L1487-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1126#L661true assume 1 == ~t5_pc~0; 147#L662true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 714#L672true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1372#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1103#L1495true assume !(0 != activate_threads_~tmp___4~0#1); 818#L1495-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1703#L680true assume !(1 == ~t6_pc~0); 1705#L680-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1500#L691true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 218#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1118#L1503true assume !(0 != activate_threads_~tmp___5~0#1); 1410#L1503-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1401#L699true assume 1 == ~t7_pc~0; 682#L700true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 890#L710true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1637#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 588#L1511true assume !(0 != activate_threads_~tmp___6~0#1); 795#L1511-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 504#L718true assume !(1 == ~t8_pc~0); 1254#L718-2true is_transmit8_triggered_~__retres1~8#1 := 0; 137#L729true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1322#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 155#L1519true assume !(0 != activate_threads_~tmp___7~0#1); 221#L1519-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 849#L737true assume 1 == ~t9_pc~0; 1512#L738true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1291#L748true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 244#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1652#L1527true assume !(0 != activate_threads_~tmp___8~0#1); 405#L1527-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1097#L756true assume 1 == ~t10_pc~0; 882#L757true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 806#L767true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1119#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 531#L1535true assume !(0 != activate_threads_~tmp___9~0#1); 284#L1535-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 751#L775true assume !(1 == ~t11_pc~0); 446#L775-2true is_transmit11_triggered_~__retres1~11#1 := 0; 1269#L786true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1234#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 104#L1543true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 842#L1543-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 195#L794true assume 1 == ~t12_pc~0; 115#L795true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1104#L805true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 177#L1551true assume !(0 != activate_threads_~tmp___11~0#1); 698#L1551-2true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 454#L1307true assume !(1 == ~M_E~0); 535#L1307-2true assume !(1 == ~T1_E~0); 1452#L1312-1true assume !(1 == ~T2_E~0); 474#L1317-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 643#L1322-1true assume !(1 == ~T4_E~0); 291#L1327-1true assume !(1 == ~T5_E~0); 686#L1332-1true assume !(1 == ~T6_E~0); 1427#L1337-1true assume !(1 == ~T7_E~0); 638#L1342-1true assume !(1 == ~T8_E~0); 1326#L1347-1true assume !(1 == ~T9_E~0); 1065#L1352-1true assume !(1 == ~T10_E~0); 891#L1357-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 391#L1362-1true assume !(1 == ~T12_E~0); 1137#L1367-1true assume !(1 == ~E_1~0); 185#L1372-1true assume !(1 == ~E_2~0); 484#L1377-1true assume !(1 == ~E_3~0); 349#L1382-1true assume !(1 == ~E_4~0); 777#L1387-1true assume !(1 == ~E_5~0); 1264#L1392-1true assume !(1 == ~E_6~0); 360#L1397-1true assume 1 == ~E_7~0;~E_7~0 := 2; 1394#L1402-1true assume !(1 == ~E_8~0); 193#L1407-1true assume !(1 == ~E_9~0); 1529#L1412-1true assume !(1 == ~E_10~0); 973#L1417-1true assume !(1 == ~E_11~0); 1709#L1422-1true assume !(1 == ~E_12~0); 1390#L1427-1true assume { :end_inline_reset_delta_events } true; 96#L1768-2true [2023-11-26 10:50:01,625 INFO L750 eck$LassoCheckResult]: Loop: 96#L1768-2true assume !false; 520#L1769true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 799#L1149-1true assume false; 498#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 318#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 997#L1174-3true assume 0 == ~M_E~0;~M_E~0 := 1; 989#L1174-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 722#L1179-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1406#L1184-3true assume !(0 == ~T3_E~0); 892#L1189-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 576#L1194-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 173#L1199-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 815#L1204-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 302#L1209-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 11#L1214-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 628#L1219-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 414#L1224-3true assume !(0 == ~T11_E~0); 1707#L1229-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 425#L1234-3true assume 0 == ~E_1~0;~E_1~0 := 1; 101#L1239-3true assume 0 == ~E_2~0;~E_2~0 := 1; 336#L1244-3true assume 0 == ~E_3~0;~E_3~0 := 1; 668#L1249-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1453#L1254-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1241#L1259-3true assume 0 == ~E_6~0;~E_6~0 := 1; 763#L1264-3true assume !(0 == ~E_7~0); 103#L1269-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1513#L1274-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1325#L1279-3true assume 0 == ~E_10~0;~E_10~0 := 1; 412#L1284-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1382#L1289-3true assume 0 == ~E_12~0;~E_12~0 := 1; 403#L1294-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 213#L566-39true assume 1 == ~m_pc~0; 747#L567-13true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 607#L577-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 650#is_master_triggered_returnLabel#14true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1255#L1455-39true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 829#L1455-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1301#L585-39true assume !(1 == ~t1_pc~0); 217#L585-41true is_transmit1_triggered_~__retres1~1#1 := 0; 332#L596-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1487#is_transmit1_triggered_returnLabel#14true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1229#L1463-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 864#L1463-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 592#L604-39true assume !(1 == ~t2_pc~0); 1224#L604-41true is_transmit2_triggered_~__retres1~2#1 := 0; 338#L615-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 453#is_transmit2_triggered_returnLabel#14true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 632#L1471-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1005#L1471-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 324#L623-39true assume !(1 == ~t3_pc~0); 657#L623-41true is_transmit3_triggered_~__retres1~3#1 := 0; 845#L634-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1682#is_transmit3_triggered_returnLabel#14true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 241#L1479-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 794#L1479-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1307#L642-39true assume !(1 == ~t4_pc~0); 598#L642-41true is_transmit4_triggered_~__retres1~4#1 := 0; 750#L653-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 573#is_transmit4_triggered_returnLabel#14true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1040#L1487-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1183#L1487-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 199#L661-39true assume 1 == ~t5_pc~0; 1050#L662-13true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1641#L672-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 596#is_transmit5_triggered_returnLabel#14true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1153#L1495-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 847#L1495-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1176#L680-39true assume !(1 == ~t6_pc~0); 975#L680-41true is_transmit6_triggered_~__retres1~6#1 := 0; 1146#L691-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1576#is_transmit6_triggered_returnLabel#14true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 283#L1503-39true assume !(0 != activate_threads_~tmp___5~0#1); 1501#L1503-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1252#L699-39true assume 1 == ~t7_pc~0; 578#L700-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 380#L710-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 850#is_transmit7_triggered_returnLabel#14true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1275#L1511-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1143#L1511-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1141#L718-39true assume 1 == ~t8_pc~0; 507#L719-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1393#L729-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 952#is_transmit8_triggered_returnLabel#14true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1155#L1519-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 713#L1519-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 692#L737-39true assume 1 == ~t9_pc~0; 270#L738-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 451#L748-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66#is_transmit9_triggered_returnLabel#14true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1455#L1527-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1102#L1527-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1023#L756-39true assume 1 == ~t10_pc~0; 1379#L757-13true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1524#L767-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1228#is_transmit10_triggered_returnLabel#14true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 436#L1535-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 562#L1535-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77#L775-39true assume !(1 == ~t11_pc~0); 458#L775-41true is_transmit11_triggered_~__retres1~11#1 := 0; 432#L786-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 616#is_transmit11_triggered_returnLabel#14true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1556#L1543-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 757#L1543-41true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 464#L794-39true assume 1 == ~t12_pc~0; 271#L795-13true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 913#L805-13true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 322#is_transmit12_triggered_returnLabel#14true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 801#L1551-39true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 48#L1551-41true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1309#L1307-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1203#L1307-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1622#L1312-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1614#L1317-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 819#L1322-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1687#L1327-3true assume !(1 == ~T5_E~0); 110#L1332-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 99#L1337-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 528#L1342-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 954#L1347-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 634#L1352-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1114#L1357-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1697#L1362-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1551#L1367-3true assume !(1 == ~E_1~0); 1518#L1372-3true assume 1 == ~E_2~0;~E_2~0 := 2; 17#L1377-3true assume 1 == ~E_3~0;~E_3~0 := 2; 428#L1382-3true assume 1 == ~E_4~0;~E_4~0 := 2; 340#L1387-3true assume 1 == ~E_5~0;~E_5~0 := 2; 926#L1392-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1605#L1397-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1376#L1402-3true assume 1 == ~E_8~0;~E_8~0 := 2; 606#L1407-3true assume !(1 == ~E_9~0); 153#L1412-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1151#L1417-3true assume 1 == ~E_11~0;~E_11~0 := 2; 542#L1422-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1107#L1427-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 157#L894-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1665#L961-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 191#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 609#L1787true assume !(0 == start_simulation_~tmp~3#1); 1441#L1787-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1218#L894-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1008#L961-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1320#L1742true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 328#L1749true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1148#stop_simulation_returnLabel#1true start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1601#L1800true assume !(0 != start_simulation_~tmp___0~1#1); 96#L1768-2true [2023-11-26 10:50:01,634 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:01,634 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 1 times [2023-11-26 10:50:01,655 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:01,655 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345618542] [2023-11-26 10:50:01,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:01,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:01,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:02,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:02,159 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:02,159 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345618542] [2023-11-26 10:50:02,160 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1345618542] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:02,160 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:02,160 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:02,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [107661574] [2023-11-26 10:50:02,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:02,169 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:02,171 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:02,171 INFO L85 PathProgramCache]: Analyzing trace with hash 1373381520, now seen corresponding path program 1 times [2023-11-26 10:50:02,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:02,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [586690396] [2023-11-26 10:50:02,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:02,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:02,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:02,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:02,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:02,277 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [586690396] [2023-11-26 10:50:02,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [586690396] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:02,278 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:02,278 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:50:02,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [748567845] [2023-11-26 10:50:02,279 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:02,280 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:02,281 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:02,322 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-26 10:50:02,323 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-26 10:50:02,330 INFO L87 Difference]: Start difference. First operand has 1709 states, 1708 states have (on average 1.4976580796252927) internal successors, (2558), 1708 states have internal predecessors, (2558), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 73.5) internal successors, (147), 2 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:02,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:02,420 INFO L93 Difference]: Finished difference Result 1707 states and 2523 transitions. [2023-11-26 10:50:02,422 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1707 states and 2523 transitions. [2023-11-26 10:50:02,444 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:02,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1707 states to 1701 states and 2517 transitions. [2023-11-26 10:50:02,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-26 10:50:02,474 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-26 10:50:02,474 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2517 transitions. [2023-11-26 10:50:02,486 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:02,486 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2517 transitions. [2023-11-26 10:50:02,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2517 transitions. [2023-11-26 10:50:02,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-26 10:50:02,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4797178130511464) internal successors, (2517), 1700 states have internal predecessors, (2517), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:02,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2517 transitions. [2023-11-26 10:50:02,624 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2517 transitions. [2023-11-26 10:50:02,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-26 10:50:02,629 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2517 transitions. [2023-11-26 10:50:02,629 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-26 10:50:02,629 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2517 transitions. [2023-11-26 10:50:02,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:02,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:02,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:02,646 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:02,646 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:02,647 INFO L748 eck$LassoCheckResult]: Stem: 3702#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 3703#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4495#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4496#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4363#L821 assume !(1 == ~m_i~0);~m_st~0 := 2; 4364#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4457#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4756#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4891#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4892#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3678#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3679#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4823#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4261#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4262#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4172#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4173#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4566#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3917#L1174 assume !(0 == ~M_E~0); 3918#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3769#L1179-1 assume !(0 == ~T2_E~0); 3675#L1184-1 assume !(0 == ~T3_E~0); 3676#L1189-1 assume !(0 == ~T4_E~0); 3718#L1194-1 assume !(0 == ~T5_E~0); 3811#L1199-1 assume !(0 == ~T6_E~0); 4690#L1204-1 assume !(0 == ~T7_E~0); 4611#L1209-1 assume !(0 == ~T8_E~0); 4612#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5035#L1219-1 assume !(0 == ~T10_E~0); 5120#L1224-1 assume !(0 == ~T11_E~0); 4034#L1229-1 assume !(0 == ~T12_E~0); 3605#L1234-1 assume !(0 == ~E_1~0); 3606#L1239-1 assume !(0 == ~E_2~0); 3638#L1244-1 assume !(0 == ~E_3~0); 3639#L1249-1 assume !(0 == ~E_4~0); 4281#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3535#L1259-1 assume !(0 == ~E_6~0); 3488#L1264-1 assume !(0 == ~E_7~0); 3489#L1269-1 assume !(0 == ~E_8~0); 5123#L1274-1 assume !(0 == ~E_9~0); 5062#L1279-1 assume !(0 == ~E_10~0); 3722#L1284-1 assume !(0 == ~E_11~0); 3723#L1289-1 assume !(0 == ~E_12~0); 4333#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4334#L566 assume 1 == ~m_pc~0; 3505#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3506#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4377#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4378#L1455 assume !(0 != activate_threads_~tmp~1#1); 3944#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3945#L585 assume 1 == ~t1_pc~0; 3602#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3603#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4746#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4747#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 5091#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5087#L604 assume !(1 == ~t2_pc~0); 4652#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4653#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3887#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3888#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4851#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4852#L623 assume 1 == ~t3_pc~0; 4118#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3464#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4721#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4722#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 4885#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3502#L642 assume !(1 == ~t4_pc~0); 3503#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3955#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3557#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3558#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 3579#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4665#L661 assume 1 == ~t5_pc~0; 3735#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3736#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4583#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4950#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 4697#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4698#L680 assume !(1 == ~t6_pc~0); 4151#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4152#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3878#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3879#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 4960#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5084#L699 assume 1 == ~t7_pc~0; 4546#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4547#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4779#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4439#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 4440#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4335#L718 assume !(1 == ~t8_pc~0); 4336#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3716#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3717#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3751#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 3752#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3884#L737 assume 1 == ~t9_pc~0; 4735#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4015#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3924#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3925#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 4192#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4193#L756 assume 1 == ~t10_pc~0; 4769#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4430#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4685#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4370#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 3994#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3995#L775 assume !(1 == ~t11_pc~0); 4253#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4254#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5028#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3650#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3651#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3832#L794 assume 1 == ~t12_pc~0; 3673#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3653#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3508#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3509#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 3797#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4265#L1307 assume !(1 == ~M_E~0); 4266#L1307-2 assume !(1 == ~T1_E~0); 4374#L1312-1 assume !(1 == ~T2_E~0); 4294#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4295#L1322-1 assume !(1 == ~T4_E~0); 4005#L1327-1 assume !(1 == ~T5_E~0); 4006#L1332-1 assume !(1 == ~T6_E~0); 4551#L1337-1 assume !(1 == ~T7_E~0); 4508#L1342-1 assume !(1 == ~T8_E~0); 4509#L1347-1 assume !(1 == ~T9_E~0); 4921#L1352-1 assume !(1 == ~T10_E~0); 4780#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4170#L1362-1 assume !(1 == ~T12_E~0); 4171#L1367-1 assume !(1 == ~E_1~0); 3812#L1372-1 assume !(1 == ~E_2~0); 3813#L1377-1 assume !(1 == ~E_3~0); 4103#L1382-1 assume !(1 == ~E_4~0); 4104#L1387-1 assume !(1 == ~E_5~0); 4654#L1392-1 assume !(1 == ~E_6~0); 4121#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4122#L1402-1 assume !(1 == ~E_8~0); 3827#L1407-1 assume !(1 == ~E_9~0); 3828#L1412-1 assume !(1 == ~E_10~0); 4846#L1417-1 assume !(1 == ~E_11~0); 4847#L1422-1 assume !(1 == ~E_12~0); 5081#L1427-1 assume { :end_inline_reset_delta_events } true; 3634#L1768-2 [2023-11-26 10:50:02,648 INFO L750 eck$LassoCheckResult]: Loop: 3634#L1768-2 assume !false; 3635#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4298#L1149-1 assume !false; 4676#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4903#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4012#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4828#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4898#L976 assume !(0 != eval_~tmp~0#1); 4326#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4055#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4056#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4856#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4594#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4595#L1184-3 assume !(0 == ~T3_E~0); 4781#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4425#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3788#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3789#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4025#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3448#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3449#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4205#L1224-3 assume !(0 == ~T11_E~0); 4206#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4220#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3644#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3645#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4080#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4538#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5031#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4637#L1264-3 assume !(0 == ~E_7~0); 3648#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3649#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5061#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4201#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4202#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4189#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3868#L566-39 assume 1 == ~m_pc~0; 3869#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4468#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4469#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4521#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4712#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4713#L585-39 assume !(1 == ~t1_pc~0); 3876#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 3877#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4077#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5025#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4750#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4445#L604-39 assume 1 == ~t2_pc~0; 4446#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4084#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4085#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4264#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4498#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4066#L623-39 assume 1 == ~t3_pc~0; 3465#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3466#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4730#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3919#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3920#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4672#L642-39 assume !(1 == ~t4_pc~0); 4257#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 4256#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4420#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4421#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4902#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3838#L661-39 assume !(1 == ~t5_pc~0); 3473#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 3474#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4452#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4453#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4732#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4733#L680-39 assume 1 == ~t6_pc~0; 3540#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3541#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4981#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3992#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 3993#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5037#L699-39 assume 1 == ~t7_pc~0; 4427#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4154#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4155#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4737#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4977#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4974#L718-39 assume 1 == ~t8_pc~0; 4339#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4340#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4833#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4834#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4582#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4559#L737-39 assume 1 == ~t9_pc~0; 3973#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3974#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3568#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3569#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4949#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4886#L756-39 assume !(1 == ~t10_pc~0); 4353#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 4354#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5024#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4238#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4239#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3589#L775-39 assume 1 == ~t11_pc~0; 3590#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4229#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4230#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4479#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4630#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4280#L794-39 assume !(1 == ~t12_pc~0); 3969#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 3970#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4063#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4064#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3531#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3532#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5008#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5009#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5122#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4699#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4700#L1327-3 assume !(1 == ~T5_E~0); 3665#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3640#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3641#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4368#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4501#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4502#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4957#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5117#L1367-3 assume !(1 == ~E_1~0); 5108#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3461#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3462#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4087#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4088#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4807#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5075#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4467#L1407-3 assume !(1 == ~E_9~0); 3747#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3748#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4382#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4383#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3755#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3756#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3823#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 3824#L1787 assume !(0 == start_simulation_~tmp~3#1); 4471#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 5017#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3732#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3480#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 3481#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4073#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4074#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4984#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 3634#L1768-2 [2023-11-26 10:50:02,649 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:02,649 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 2 times [2023-11-26 10:50:02,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:02,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760637318] [2023-11-26 10:50:02,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:02,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:02,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:02,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:02,726 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:02,726 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1760637318] [2023-11-26 10:50:02,726 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1760637318] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:02,727 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:02,727 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:02,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012318492] [2023-11-26 10:50:02,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:02,728 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:02,728 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:02,729 INFO L85 PathProgramCache]: Analyzing trace with hash -1137085798, now seen corresponding path program 1 times [2023-11-26 10:50:02,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:02,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [603101489] [2023-11-26 10:50:02,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:02,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:02,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:02,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:02,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:02,870 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [603101489] [2023-11-26 10:50:02,870 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [603101489] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:02,871 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:02,871 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:02,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2054652183] [2023-11-26 10:50:02,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:02,873 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:02,874 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:02,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:02,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:02,875 INFO L87 Difference]: Start difference. First operand 1701 states and 2517 transitions. cyclomatic complexity: 817 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:02,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:02,940 INFO L93 Difference]: Finished difference Result 1701 states and 2516 transitions. [2023-11-26 10:50:02,941 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2516 transitions. [2023-11-26 10:50:02,957 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:02,972 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2516 transitions. [2023-11-26 10:50:02,972 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-26 10:50:02,974 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-26 10:50:02,975 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2516 transitions. [2023-11-26 10:50:02,978 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:02,979 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2516 transitions. [2023-11-26 10:50:02,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2516 transitions. [2023-11-26 10:50:03,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-26 10:50:03,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.479129923574368) internal successors, (2516), 1700 states have internal predecessors, (2516), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:03,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2516 transitions. [2023-11-26 10:50:03,026 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2516 transitions. [2023-11-26 10:50:03,027 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:03,029 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2516 transitions. [2023-11-26 10:50:03,029 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-26 10:50:03,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2516 transitions. [2023-11-26 10:50:03,046 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:03,046 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:03,046 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:03,049 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:03,049 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:03,052 INFO L748 eck$LassoCheckResult]: Stem: 7111#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 7112#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 7904#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7905#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7772#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 7773#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7866#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8165#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8300#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8301#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7087#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7088#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8232#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7670#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7671#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7581#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7582#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 7975#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7326#L1174 assume !(0 == ~M_E~0); 7327#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7178#L1179-1 assume !(0 == ~T2_E~0); 7084#L1184-1 assume !(0 == ~T3_E~0); 7085#L1189-1 assume !(0 == ~T4_E~0); 7127#L1194-1 assume !(0 == ~T5_E~0); 7220#L1199-1 assume !(0 == ~T6_E~0); 8099#L1204-1 assume !(0 == ~T7_E~0); 8020#L1209-1 assume !(0 == ~T8_E~0); 8021#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8444#L1219-1 assume !(0 == ~T10_E~0); 8529#L1224-1 assume !(0 == ~T11_E~0); 7443#L1229-1 assume !(0 == ~T12_E~0); 7014#L1234-1 assume !(0 == ~E_1~0); 7015#L1239-1 assume !(0 == ~E_2~0); 7047#L1244-1 assume !(0 == ~E_3~0); 7048#L1249-1 assume !(0 == ~E_4~0); 7690#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6944#L1259-1 assume !(0 == ~E_6~0); 6897#L1264-1 assume !(0 == ~E_7~0); 6898#L1269-1 assume !(0 == ~E_8~0); 8532#L1274-1 assume !(0 == ~E_9~0); 8471#L1279-1 assume !(0 == ~E_10~0); 7131#L1284-1 assume !(0 == ~E_11~0); 7132#L1289-1 assume !(0 == ~E_12~0); 7742#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7743#L566 assume 1 == ~m_pc~0; 6914#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6915#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7786#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7787#L1455 assume !(0 != activate_threads_~tmp~1#1); 7353#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7354#L585 assume 1 == ~t1_pc~0; 7011#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7012#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8155#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8156#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 8500#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8496#L604 assume !(1 == ~t2_pc~0); 8061#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8062#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7296#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7297#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8260#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8261#L623 assume 1 == ~t3_pc~0; 7527#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6873#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8130#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8131#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 8294#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6911#L642 assume !(1 == ~t4_pc~0); 6912#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7364#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6966#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6967#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 6988#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8074#L661 assume 1 == ~t5_pc~0; 7144#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7145#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7992#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8359#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 8106#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8107#L680 assume !(1 == ~t6_pc~0); 7560#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7561#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7287#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7288#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 8369#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8493#L699 assume 1 == ~t7_pc~0; 7955#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7956#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8188#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7848#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 7849#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7744#L718 assume !(1 == ~t8_pc~0); 7745#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7125#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7126#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7160#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 7161#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7293#L737 assume 1 == ~t9_pc~0; 8144#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7424#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7333#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7334#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 7601#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7602#L756 assume 1 == ~t10_pc~0; 8178#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7839#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8094#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7779#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 7403#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7404#L775 assume !(1 == ~t11_pc~0); 7662#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 7663#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8437#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7059#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7060#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7241#L794 assume 1 == ~t12_pc~0; 7082#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7062#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 6917#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6918#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 7206#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7674#L1307 assume !(1 == ~M_E~0); 7675#L1307-2 assume !(1 == ~T1_E~0); 7783#L1312-1 assume !(1 == ~T2_E~0); 7703#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7704#L1322-1 assume !(1 == ~T4_E~0); 7414#L1327-1 assume !(1 == ~T5_E~0); 7415#L1332-1 assume !(1 == ~T6_E~0); 7960#L1337-1 assume !(1 == ~T7_E~0); 7917#L1342-1 assume !(1 == ~T8_E~0); 7918#L1347-1 assume !(1 == ~T9_E~0); 8330#L1352-1 assume !(1 == ~T10_E~0); 8189#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7579#L1362-1 assume !(1 == ~T12_E~0); 7580#L1367-1 assume !(1 == ~E_1~0); 7221#L1372-1 assume !(1 == ~E_2~0); 7222#L1377-1 assume !(1 == ~E_3~0); 7512#L1382-1 assume !(1 == ~E_4~0); 7513#L1387-1 assume !(1 == ~E_5~0); 8063#L1392-1 assume !(1 == ~E_6~0); 7530#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7531#L1402-1 assume !(1 == ~E_8~0); 7236#L1407-1 assume !(1 == ~E_9~0); 7237#L1412-1 assume !(1 == ~E_10~0); 8255#L1417-1 assume !(1 == ~E_11~0); 8256#L1422-1 assume !(1 == ~E_12~0); 8490#L1427-1 assume { :end_inline_reset_delta_events } true; 7043#L1768-2 [2023-11-26 10:50:03,052 INFO L750 eck$LassoCheckResult]: Loop: 7043#L1768-2 assume !false; 7044#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7707#L1149-1 assume !false; 8085#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8312#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7421#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8237#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8307#L976 assume !(0 != eval_~tmp~0#1); 7735#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7464#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7465#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8265#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8003#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8004#L1184-3 assume !(0 == ~T3_E~0); 8190#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7834#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7197#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7198#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7434#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6857#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6858#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7614#L1224-3 assume !(0 == ~T11_E~0); 7615#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7629#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7053#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7054#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7489#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7947#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8440#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8046#L1264-3 assume !(0 == ~E_7~0); 7057#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7058#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8470#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7610#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7611#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7598#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7277#L566-39 assume 1 == ~m_pc~0; 7278#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7877#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7878#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7930#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8121#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8122#L585-39 assume !(1 == ~t1_pc~0); 7285#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 7286#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7486#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8434#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8159#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7854#L604-39 assume !(1 == ~t2_pc~0); 7856#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 7493#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7494#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7673#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7907#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7475#L623-39 assume 1 == ~t3_pc~0; 6874#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6875#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8139#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7328#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7329#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8081#L642-39 assume 1 == ~t4_pc~0; 7664#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7665#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7829#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7830#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8311#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7247#L661-39 assume 1 == ~t5_pc~0; 7248#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6883#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7861#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7862#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8141#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8142#L680-39 assume 1 == ~t6_pc~0; 6949#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6950#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8390#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7401#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 7402#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8446#L699-39 assume 1 == ~t7_pc~0; 7836#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7563#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7564#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8146#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8386#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8383#L718-39 assume 1 == ~t8_pc~0; 7748#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7749#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8242#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8243#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7991#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7968#L737-39 assume 1 == ~t9_pc~0; 7382#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7383#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6977#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6978#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8358#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8295#L756-39 assume !(1 == ~t10_pc~0); 7762#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 7763#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8433#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7647#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7648#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6998#L775-39 assume 1 == ~t11_pc~0; 6999#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7638#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7639#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7888#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8039#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7689#L794-39 assume !(1 == ~t12_pc~0); 7378#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 7379#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7472#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7473#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 6940#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6941#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8417#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8418#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8531#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8108#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8109#L1327-3 assume !(1 == ~T5_E~0); 7074#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7049#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7050#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7777#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7910#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7911#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8366#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8526#L1367-3 assume !(1 == ~E_1~0); 8517#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6870#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6871#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7496#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7497#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8216#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8484#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7876#L1407-3 assume !(1 == ~E_9~0); 7156#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7157#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7791#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 7792#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7164#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7165#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7232#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 7233#L1787 assume !(0 == start_simulation_~tmp~3#1); 7880#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8426#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7141#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 6889#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 6890#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7482#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7483#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 8393#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 7043#L1768-2 [2023-11-26 10:50:03,053 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:03,054 INFO L85 PathProgramCache]: Analyzing trace with hash -1760586097, now seen corresponding path program 1 times [2023-11-26 10:50:03,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:03,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1429410144] [2023-11-26 10:50:03,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:03,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:03,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:03,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:03,187 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:03,187 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1429410144] [2023-11-26 10:50:03,187 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1429410144] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:03,188 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:03,189 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:03,189 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [644683934] [2023-11-26 10:50:03,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:03,190 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:03,191 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:03,191 INFO L85 PathProgramCache]: Analyzing trace with hash -1670129477, now seen corresponding path program 1 times [2023-11-26 10:50:03,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:03,192 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1792404188] [2023-11-26 10:50:03,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:03,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:03,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:03,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:03,305 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:03,306 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1792404188] [2023-11-26 10:50:03,306 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1792404188] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:03,306 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:03,307 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:03,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999286771] [2023-11-26 10:50:03,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:03,309 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:03,309 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:03,309 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:03,309 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:03,310 INFO L87 Difference]: Start difference. First operand 1701 states and 2516 transitions. cyclomatic complexity: 816 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:03,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:03,362 INFO L93 Difference]: Finished difference Result 1701 states and 2515 transitions. [2023-11-26 10:50:03,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2515 transitions. [2023-11-26 10:50:03,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:03,393 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2515 transitions. [2023-11-26 10:50:03,393 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-26 10:50:03,395 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-26 10:50:03,395 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2515 transitions. [2023-11-26 10:50:03,398 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:03,398 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2515 transitions. [2023-11-26 10:50:03,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2515 transitions. [2023-11-26 10:50:03,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-26 10:50:03,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4785420340975897) internal successors, (2515), 1700 states have internal predecessors, (2515), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:03,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2515 transitions. [2023-11-26 10:50:03,442 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2515 transitions. [2023-11-26 10:50:03,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:03,444 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2515 transitions. [2023-11-26 10:50:03,445 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-26 10:50:03,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2515 transitions. [2023-11-26 10:50:03,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:03,456 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:03,458 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:03,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:03,461 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:03,462 INFO L748 eck$LassoCheckResult]: Stem: 10520#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 10521#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11313#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11314#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11181#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 11182#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11275#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11574#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 11709#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11710#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10496#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10497#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11641#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11079#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11080#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10990#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10991#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11384#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10735#L1174 assume !(0 == ~M_E~0); 10736#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10587#L1179-1 assume !(0 == ~T2_E~0); 10493#L1184-1 assume !(0 == ~T3_E~0); 10494#L1189-1 assume !(0 == ~T4_E~0); 10536#L1194-1 assume !(0 == ~T5_E~0); 10629#L1199-1 assume !(0 == ~T6_E~0); 11508#L1204-1 assume !(0 == ~T7_E~0); 11429#L1209-1 assume !(0 == ~T8_E~0); 11430#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11853#L1219-1 assume !(0 == ~T10_E~0); 11938#L1224-1 assume !(0 == ~T11_E~0); 10852#L1229-1 assume !(0 == ~T12_E~0); 10423#L1234-1 assume !(0 == ~E_1~0); 10424#L1239-1 assume !(0 == ~E_2~0); 10456#L1244-1 assume !(0 == ~E_3~0); 10457#L1249-1 assume !(0 == ~E_4~0); 11099#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10353#L1259-1 assume !(0 == ~E_6~0); 10306#L1264-1 assume !(0 == ~E_7~0); 10307#L1269-1 assume !(0 == ~E_8~0); 11941#L1274-1 assume !(0 == ~E_9~0); 11880#L1279-1 assume !(0 == ~E_10~0); 10540#L1284-1 assume !(0 == ~E_11~0); 10541#L1289-1 assume !(0 == ~E_12~0); 11151#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11152#L566 assume 1 == ~m_pc~0; 10323#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10324#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11195#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11196#L1455 assume !(0 != activate_threads_~tmp~1#1); 10762#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10763#L585 assume 1 == ~t1_pc~0; 10420#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10421#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11564#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11565#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 11909#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11905#L604 assume !(1 == ~t2_pc~0); 11470#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11471#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10705#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10706#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11669#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11670#L623 assume 1 == ~t3_pc~0; 10936#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10282#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11539#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11540#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 11703#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10320#L642 assume !(1 == ~t4_pc~0); 10321#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10773#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10375#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10376#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 10397#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11483#L661 assume 1 == ~t5_pc~0; 10553#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10554#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11401#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11768#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 11515#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11516#L680 assume !(1 == ~t6_pc~0); 10969#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10970#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10696#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10697#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 11778#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11902#L699 assume 1 == ~t7_pc~0; 11364#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11365#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11597#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11257#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 11258#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11153#L718 assume !(1 == ~t8_pc~0); 11154#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10534#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10535#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10569#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 10570#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10702#L737 assume 1 == ~t9_pc~0; 11553#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10833#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10742#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10743#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 11010#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11011#L756 assume 1 == ~t10_pc~0; 11587#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11248#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11503#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11188#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 10812#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10813#L775 assume !(1 == ~t11_pc~0); 11071#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 11072#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11846#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10468#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10469#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 10650#L794 assume 1 == ~t12_pc~0; 10491#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10471#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10326#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10327#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 10615#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11083#L1307 assume !(1 == ~M_E~0); 11084#L1307-2 assume !(1 == ~T1_E~0); 11192#L1312-1 assume !(1 == ~T2_E~0); 11112#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11113#L1322-1 assume !(1 == ~T4_E~0); 10823#L1327-1 assume !(1 == ~T5_E~0); 10824#L1332-1 assume !(1 == ~T6_E~0); 11369#L1337-1 assume !(1 == ~T7_E~0); 11326#L1342-1 assume !(1 == ~T8_E~0); 11327#L1347-1 assume !(1 == ~T9_E~0); 11739#L1352-1 assume !(1 == ~T10_E~0); 11598#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10988#L1362-1 assume !(1 == ~T12_E~0); 10989#L1367-1 assume !(1 == ~E_1~0); 10630#L1372-1 assume !(1 == ~E_2~0); 10631#L1377-1 assume !(1 == ~E_3~0); 10921#L1382-1 assume !(1 == ~E_4~0); 10922#L1387-1 assume !(1 == ~E_5~0); 11472#L1392-1 assume !(1 == ~E_6~0); 10939#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10940#L1402-1 assume !(1 == ~E_8~0); 10645#L1407-1 assume !(1 == ~E_9~0); 10646#L1412-1 assume !(1 == ~E_10~0); 11664#L1417-1 assume !(1 == ~E_11~0); 11665#L1422-1 assume !(1 == ~E_12~0); 11899#L1427-1 assume { :end_inline_reset_delta_events } true; 10452#L1768-2 [2023-11-26 10:50:03,463 INFO L750 eck$LassoCheckResult]: Loop: 10452#L1768-2 assume !false; 10453#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11116#L1149-1 assume !false; 11494#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11721#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10830#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11646#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11716#L976 assume !(0 != eval_~tmp~0#1); 11144#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10873#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10874#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11674#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11412#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11413#L1184-3 assume !(0 == ~T3_E~0); 11599#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11243#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10606#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10607#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10843#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10266#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10267#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11023#L1224-3 assume !(0 == ~T11_E~0); 11024#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11038#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10462#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10463#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10898#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11356#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11849#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11455#L1264-3 assume !(0 == ~E_7~0); 10466#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10467#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11879#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11019#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11020#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11007#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10686#L566-39 assume !(1 == ~m_pc~0); 10688#L566-41 is_master_triggered_~__retres1~0#1 := 0; 11286#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11287#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11339#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11530#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11531#L585-39 assume !(1 == ~t1_pc~0); 10694#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 10695#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10895#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11843#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11568#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11263#L604-39 assume 1 == ~t2_pc~0; 11264#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10902#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10903#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11082#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11316#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10884#L623-39 assume 1 == ~t3_pc~0; 10283#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10284#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11548#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10737#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10738#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11490#L642-39 assume 1 == ~t4_pc~0; 11073#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11074#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11238#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11239#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11720#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10656#L661-39 assume 1 == ~t5_pc~0; 10657#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10292#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11270#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11271#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11550#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11551#L680-39 assume 1 == ~t6_pc~0; 10358#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10359#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11799#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10810#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 10811#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11855#L699-39 assume 1 == ~t7_pc~0; 11245#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10972#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10973#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11555#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11795#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11792#L718-39 assume 1 == ~t8_pc~0; 11157#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11158#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11651#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11652#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11400#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11377#L737-39 assume 1 == ~t9_pc~0; 10791#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10792#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10386#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10387#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11767#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11704#L756-39 assume !(1 == ~t10_pc~0); 11171#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 11172#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11842#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11056#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11057#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10407#L775-39 assume 1 == ~t11_pc~0; 10408#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11047#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11048#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11297#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11448#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11098#L794-39 assume !(1 == ~t12_pc~0); 10787#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 10788#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10881#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10882#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10349#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10350#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11826#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11827#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11940#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11517#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11518#L1327-3 assume !(1 == ~T5_E~0); 10483#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10458#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10459#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11186#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11319#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11320#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11775#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11935#L1367-3 assume !(1 == ~E_1~0); 11926#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10279#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10280#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10905#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10906#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11625#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11893#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11285#L1407-3 assume !(1 == ~E_9~0); 10565#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10566#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 11200#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 11201#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 10573#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10574#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10641#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 10642#L1787 assume !(0 == start_simulation_~tmp~3#1); 11289#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11835#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10550#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10298#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 10299#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10891#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10892#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 11802#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 10452#L1768-2 [2023-11-26 10:50:03,464 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:03,464 INFO L85 PathProgramCache]: Analyzing trace with hash -1220156591, now seen corresponding path program 1 times [2023-11-26 10:50:03,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:03,466 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1383727790] [2023-11-26 10:50:03,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:03,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:03,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:03,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:03,539 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:03,539 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1383727790] [2023-11-26 10:50:03,540 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1383727790] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:03,540 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:03,540 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:03,544 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1764859981] [2023-11-26 10:50:03,545 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:03,545 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:03,546 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:03,546 INFO L85 PathProgramCache]: Analyzing trace with hash 2042585659, now seen corresponding path program 1 times [2023-11-26 10:50:03,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:03,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184238666] [2023-11-26 10:50:03,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:03,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:03,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:03,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:03,666 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:03,667 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184238666] [2023-11-26 10:50:03,667 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184238666] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:03,667 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:03,667 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:03,668 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721058406] [2023-11-26 10:50:03,668 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:03,668 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:03,669 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:03,669 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:03,669 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:03,670 INFO L87 Difference]: Start difference. First operand 1701 states and 2515 transitions. cyclomatic complexity: 815 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:03,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:03,727 INFO L93 Difference]: Finished difference Result 1701 states and 2514 transitions. [2023-11-26 10:50:03,727 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2514 transitions. [2023-11-26 10:50:03,744 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:03,759 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2514 transitions. [2023-11-26 10:50:03,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-26 10:50:03,762 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-26 10:50:03,762 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2514 transitions. [2023-11-26 10:50:03,766 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:03,767 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2514 transitions. [2023-11-26 10:50:03,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2514 transitions. [2023-11-26 10:50:03,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-26 10:50:03,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4779541446208113) internal successors, (2514), 1700 states have internal predecessors, (2514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:03,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2514 transitions. [2023-11-26 10:50:03,822 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2514 transitions. [2023-11-26 10:50:03,822 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:03,824 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2514 transitions. [2023-11-26 10:50:03,825 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-26 10:50:03,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2514 transitions. [2023-11-26 10:50:03,837 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:03,838 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:03,838 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:03,842 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:03,843 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:03,843 INFO L748 eck$LassoCheckResult]: Stem: 13929#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 13930#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 14723#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14724#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14590#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 14591#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14684#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14988#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15118#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15119#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13905#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13906#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15050#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14488#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14489#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14401#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14402#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 14793#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14144#L1174 assume !(0 == ~M_E~0); 14145#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13998#L1179-1 assume !(0 == ~T2_E~0); 13902#L1184-1 assume !(0 == ~T3_E~0); 13903#L1189-1 assume !(0 == ~T4_E~0); 13945#L1194-1 assume !(0 == ~T5_E~0); 14040#L1199-1 assume !(0 == ~T6_E~0); 14917#L1204-1 assume !(0 == ~T7_E~0); 14838#L1209-1 assume !(0 == ~T8_E~0); 14839#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15262#L1219-1 assume !(0 == ~T10_E~0); 15347#L1224-1 assume !(0 == ~T11_E~0); 14263#L1229-1 assume !(0 == ~T12_E~0); 13832#L1234-1 assume !(0 == ~E_1~0); 13833#L1239-1 assume !(0 == ~E_2~0); 13867#L1244-1 assume !(0 == ~E_3~0); 13868#L1249-1 assume !(0 == ~E_4~0); 14508#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13762#L1259-1 assume !(0 == ~E_6~0); 13715#L1264-1 assume !(0 == ~E_7~0); 13716#L1269-1 assume !(0 == ~E_8~0); 15350#L1274-1 assume !(0 == ~E_9~0); 15290#L1279-1 assume !(0 == ~E_10~0); 13949#L1284-1 assume !(0 == ~E_11~0); 13950#L1289-1 assume !(0 == ~E_12~0); 14560#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14561#L566 assume 1 == ~m_pc~0; 13732#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13733#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14604#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14605#L1455 assume !(0 != activate_threads_~tmp~1#1); 14171#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14172#L585 assume 1 == ~t1_pc~0; 13829#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13830#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14973#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14974#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 15318#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15314#L604 assume !(1 == ~t2_pc~0); 14879#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14880#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14119#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14120#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15080#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15081#L623 assume 1 == ~t3_pc~0; 14345#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13691#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14951#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14952#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 15112#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13729#L642 assume !(1 == ~t4_pc~0); 13730#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14182#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13790#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13791#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 13806#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14892#L661 assume 1 == ~t5_pc~0; 13962#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13963#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14810#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15177#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 14926#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14927#L680 assume !(1 == ~t6_pc~0); 14378#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14379#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14108#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14109#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 15187#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15312#L699 assume 1 == ~t7_pc~0; 14773#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14774#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15006#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14666#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 14667#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14562#L718 assume !(1 == ~t8_pc~0); 14563#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13943#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13944#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13980#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 13981#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14111#L737 assume 1 == ~t9_pc~0; 14964#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14244#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14151#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14152#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 14419#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14420#L756 assume 1 == ~t10_pc~0; 14996#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14658#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14912#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14597#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 14221#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14222#L775 assume !(1 == ~t11_pc~0); 14480#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 14481#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15255#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13877#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13878#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14059#L794 assume 1 == ~t12_pc~0; 13901#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13880#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13737#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13738#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 14026#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14492#L1307 assume !(1 == ~M_E~0); 14493#L1307-2 assume !(1 == ~T1_E~0); 14601#L1312-1 assume !(1 == ~T2_E~0); 14521#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14522#L1322-1 assume !(1 == ~T4_E~0); 14232#L1327-1 assume !(1 == ~T5_E~0); 14233#L1332-1 assume !(1 == ~T6_E~0); 14778#L1337-1 assume !(1 == ~T7_E~0); 14736#L1342-1 assume !(1 == ~T8_E~0); 14737#L1347-1 assume !(1 == ~T9_E~0); 15148#L1352-1 assume !(1 == ~T10_E~0); 15007#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14397#L1362-1 assume !(1 == ~T12_E~0); 14398#L1367-1 assume !(1 == ~E_1~0); 14041#L1372-1 assume !(1 == ~E_2~0); 14042#L1377-1 assume !(1 == ~E_3~0); 14330#L1382-1 assume !(1 == ~E_4~0); 14331#L1387-1 assume !(1 == ~E_5~0); 14881#L1392-1 assume !(1 == ~E_6~0); 14350#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14351#L1402-1 assume !(1 == ~E_8~0); 14057#L1407-1 assume !(1 == ~E_9~0); 14058#L1412-1 assume !(1 == ~E_10~0); 15073#L1417-1 assume !(1 == ~E_11~0); 15074#L1422-1 assume !(1 == ~E_12~0); 15308#L1427-1 assume { :end_inline_reset_delta_events } true; 13861#L1768-2 [2023-11-26 10:50:03,844 INFO L750 eck$LassoCheckResult]: Loop: 13861#L1768-2 assume !false; 13862#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14525#L1149-1 assume !false; 14905#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15130#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14239#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15055#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15125#L976 assume !(0 != eval_~tmp~0#1); 14553#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14282#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14283#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15083#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14821#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14822#L1184-3 assume !(0 == ~T3_E~0); 15009#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14652#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14018#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14019#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14252#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13675#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13676#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14432#L1224-3 assume !(0 == ~T11_E~0); 14433#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14447#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13869#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13870#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14307#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14765#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15258#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14864#L1264-3 assume !(0 == ~E_7~0); 13875#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13876#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15288#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14428#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14429#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14416#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14095#L566-39 assume 1 == ~m_pc~0; 14096#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14695#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14696#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14748#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14939#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14940#L585-39 assume !(1 == ~t1_pc~0); 14103#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 14104#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14304#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15252#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14977#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14672#L604-39 assume 1 == ~t2_pc~0; 14673#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14311#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14312#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14491#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14725#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14293#L623-39 assume 1 == ~t3_pc~0; 13692#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13693#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14957#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14146#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14147#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14899#L642-39 assume 1 == ~t4_pc~0; 14482#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14483#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14647#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14648#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15129#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14065#L661-39 assume 1 == ~t5_pc~0; 14066#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13701#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14679#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14680#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14959#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14960#L680-39 assume 1 == ~t6_pc~0; 13767#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13768#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15208#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14219#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 14220#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15264#L699-39 assume 1 == ~t7_pc~0; 14654#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14381#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14382#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14963#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15204#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15201#L718-39 assume 1 == ~t8_pc~0; 14566#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14567#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15060#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15061#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14809#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14786#L737-39 assume 1 == ~t9_pc~0; 14200#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14201#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13795#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13796#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15176#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15113#L756-39 assume !(1 == ~t10_pc~0); 14580#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 14581#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15251#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14465#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14466#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13816#L775-39 assume 1 == ~t11_pc~0; 13817#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14456#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14457#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14706#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14857#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14507#L794-39 assume !(1 == ~t12_pc~0); 14196#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 14197#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14290#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14291#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13758#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13759#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15235#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15236#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15349#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14924#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14925#L1327-3 assume !(1 == ~T5_E~0); 13892#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13865#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13866#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14595#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14728#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14729#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15184#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15344#L1367-3 assume !(1 == ~E_1~0); 15335#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13685#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13686#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14314#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14315#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15034#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15302#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14694#L1407-3 assume !(1 == ~E_9~0); 13974#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13975#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 14609#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 14610#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 13982#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13983#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14050#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 14051#L1787 assume !(0 == start_simulation_~tmp~3#1); 14697#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15244#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13959#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 13704#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 13705#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14300#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14301#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 15211#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 13861#L1768-2 [2023-11-26 10:50:03,845 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:03,846 INFO L85 PathProgramCache]: Analyzing trace with hash -1064176049, now seen corresponding path program 1 times [2023-11-26 10:50:03,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:03,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582929282] [2023-11-26 10:50:03,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:03,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:03,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:03,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:03,918 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:03,919 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [582929282] [2023-11-26 10:50:03,919 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [582929282] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:03,919 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:03,919 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:03,920 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1291246653] [2023-11-26 10:50:03,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:03,920 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:03,921 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:03,921 INFO L85 PathProgramCache]: Analyzing trace with hash -432476388, now seen corresponding path program 1 times [2023-11-26 10:50:03,921 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:03,921 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519666101] [2023-11-26 10:50:03,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:03,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:03,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:03,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:03,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:03,996 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [519666101] [2023-11-26 10:50:03,996 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [519666101] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:03,996 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:03,996 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:03,996 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [472038708] [2023-11-26 10:50:03,997 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:03,997 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:03,997 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:03,998 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:03,998 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:03,998 INFO L87 Difference]: Start difference. First operand 1701 states and 2514 transitions. cyclomatic complexity: 814 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:04,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:04,048 INFO L93 Difference]: Finished difference Result 1701 states and 2513 transitions. [2023-11-26 10:50:04,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2513 transitions. [2023-11-26 10:50:04,065 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:04,081 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2513 transitions. [2023-11-26 10:50:04,081 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-26 10:50:04,083 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-26 10:50:04,083 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2513 transitions. [2023-11-26 10:50:04,086 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:04,086 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2513 transitions. [2023-11-26 10:50:04,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2513 transitions. [2023-11-26 10:50:04,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-26 10:50:04,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.477366255144033) internal successors, (2513), 1700 states have internal predecessors, (2513), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:04,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2513 transitions. [2023-11-26 10:50:04,129 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2513 transitions. [2023-11-26 10:50:04,129 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:04,132 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2513 transitions. [2023-11-26 10:50:04,132 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-26 10:50:04,132 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2513 transitions. [2023-11-26 10:50:04,141 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:04,141 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:04,142 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:04,145 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:04,145 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:04,145 INFO L748 eck$LassoCheckResult]: Stem: 17338#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 17339#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18131#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18132#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17999#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 18000#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18093#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18394#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18527#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18528#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17314#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17315#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18459#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17897#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17898#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17808#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17809#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18202#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17553#L1174 assume !(0 == ~M_E~0); 17554#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17407#L1179-1 assume !(0 == ~T2_E~0); 17311#L1184-1 assume !(0 == ~T3_E~0); 17312#L1189-1 assume !(0 == ~T4_E~0); 17354#L1194-1 assume !(0 == ~T5_E~0); 17449#L1199-1 assume !(0 == ~T6_E~0); 18326#L1204-1 assume !(0 == ~T7_E~0); 18247#L1209-1 assume !(0 == ~T8_E~0); 18248#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18671#L1219-1 assume !(0 == ~T10_E~0); 18756#L1224-1 assume !(0 == ~T11_E~0); 17670#L1229-1 assume !(0 == ~T12_E~0); 17241#L1234-1 assume !(0 == ~E_1~0); 17242#L1239-1 assume !(0 == ~E_2~0); 17276#L1244-1 assume !(0 == ~E_3~0); 17277#L1249-1 assume !(0 == ~E_4~0); 17917#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17171#L1259-1 assume !(0 == ~E_6~0); 17124#L1264-1 assume !(0 == ~E_7~0); 17125#L1269-1 assume !(0 == ~E_8~0); 18759#L1274-1 assume !(0 == ~E_9~0); 18699#L1279-1 assume !(0 == ~E_10~0); 17358#L1284-1 assume !(0 == ~E_11~0); 17359#L1289-1 assume !(0 == ~E_12~0); 17969#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17970#L566 assume 1 == ~m_pc~0; 17141#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17142#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18013#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18014#L1455 assume !(0 != activate_threads_~tmp~1#1); 17580#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17581#L585 assume 1 == ~t1_pc~0; 17238#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17239#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18382#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18383#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 18727#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18723#L604 assume !(1 == ~t2_pc~0); 18288#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18289#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17528#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17529#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18489#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18490#L623 assume 1 == ~t3_pc~0; 17754#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17100#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18360#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18361#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 18521#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17138#L642 assume !(1 == ~t4_pc~0); 17139#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17591#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17196#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17197#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 17215#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18301#L661 assume 1 == ~t5_pc~0; 17371#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17372#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18219#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18586#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 18335#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18336#L680 assume !(1 == ~t6_pc~0); 17787#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17788#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17514#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17515#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 18596#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18721#L699 assume 1 == ~t7_pc~0; 18182#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18183#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18415#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18075#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 18076#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17971#L718 assume !(1 == ~t8_pc~0); 17972#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17352#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17353#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17387#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 17388#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17520#L737 assume 1 == ~t9_pc~0; 18373#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17651#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17560#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17561#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 17828#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17829#L756 assume 1 == ~t10_pc~0; 18405#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18066#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18321#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18006#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 17630#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17631#L775 assume !(1 == ~t11_pc~0); 17889#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 17890#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18664#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17286#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17287#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17468#L794 assume 1 == ~t12_pc~0; 17310#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17289#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17146#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17147#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 17435#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17901#L1307 assume !(1 == ~M_E~0); 17902#L1307-2 assume !(1 == ~T1_E~0); 18010#L1312-1 assume !(1 == ~T2_E~0); 17930#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17931#L1322-1 assume !(1 == ~T4_E~0); 17641#L1327-1 assume !(1 == ~T5_E~0); 17642#L1332-1 assume !(1 == ~T6_E~0); 18187#L1337-1 assume !(1 == ~T7_E~0); 18144#L1342-1 assume !(1 == ~T8_E~0); 18145#L1347-1 assume !(1 == ~T9_E~0); 18557#L1352-1 assume !(1 == ~T10_E~0); 18416#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17806#L1362-1 assume !(1 == ~T12_E~0); 17807#L1367-1 assume !(1 == ~E_1~0); 17450#L1372-1 assume !(1 == ~E_2~0); 17451#L1377-1 assume !(1 == ~E_3~0); 17739#L1382-1 assume !(1 == ~E_4~0); 17740#L1387-1 assume !(1 == ~E_5~0); 18290#L1392-1 assume !(1 == ~E_6~0); 17759#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17760#L1402-1 assume !(1 == ~E_8~0); 17463#L1407-1 assume !(1 == ~E_9~0); 17464#L1412-1 assume !(1 == ~E_10~0); 18482#L1417-1 assume !(1 == ~E_11~0); 18483#L1422-1 assume !(1 == ~E_12~0); 18717#L1427-1 assume { :end_inline_reset_delta_events } true; 17270#L1768-2 [2023-11-26 10:50:04,146 INFO L750 eck$LassoCheckResult]: Loop: 17270#L1768-2 assume !false; 17271#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17934#L1149-1 assume !false; 18314#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18539#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17648#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18464#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18534#L976 assume !(0 != eval_~tmp~0#1); 17962#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17691#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17692#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18492#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18230#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18231#L1184-3 assume !(0 == ~T3_E~0); 18417#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18061#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17427#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17428#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17661#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17084#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17085#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17841#L1224-3 assume !(0 == ~T11_E~0); 17842#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17856#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17280#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17281#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17716#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18174#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18667#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18273#L1264-3 assume !(0 == ~E_7~0); 17284#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17285#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18697#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17837#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 17838#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 17825#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17504#L566-39 assume 1 == ~m_pc~0; 17505#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18104#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18105#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18157#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18348#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18349#L585-39 assume !(1 == ~t1_pc~0); 17512#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 17513#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17713#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18661#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18386#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18083#L604-39 assume 1 == ~t2_pc~0; 18084#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17720#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17721#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17900#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18138#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17702#L623-39 assume !(1 == ~t3_pc~0); 17105#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 17104#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18366#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17555#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17556#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18308#L642-39 assume 1 == ~t4_pc~0; 17893#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17894#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18056#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18057#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18538#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17473#L661-39 assume 1 == ~t5_pc~0; 17474#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17107#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18088#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18089#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18368#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18369#L680-39 assume 1 == ~t6_pc~0; 17176#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17177#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18617#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17628#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 17629#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18673#L699-39 assume !(1 == ~t7_pc~0); 18064#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 17790#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17791#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18372#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18611#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18610#L718-39 assume 1 == ~t8_pc~0; 17975#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17976#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18468#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18469#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18218#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18195#L737-39 assume 1 == ~t9_pc~0; 17609#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17610#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17203#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17204#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18585#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18522#L756-39 assume !(1 == ~t10_pc~0); 17989#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 17990#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18660#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17874#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17875#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17225#L775-39 assume 1 == ~t11_pc~0; 17226#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17865#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17866#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18115#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18266#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17916#L794-39 assume !(1 == ~t12_pc~0); 17605#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 17606#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17697#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17698#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17167#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17168#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18644#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18645#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18758#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18333#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18334#L1327-3 assume !(1 == ~T5_E~0); 17299#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17274#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17275#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18004#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18136#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18137#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18593#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18753#L1367-3 assume !(1 == ~E_1~0); 18744#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17094#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17095#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17723#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17724#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18443#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18711#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18103#L1407-3 assume !(1 == ~E_9~0); 17383#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17384#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18017#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 18018#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 17391#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17392#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 17459#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 17460#L1787 assume !(0 == start_simulation_~tmp~3#1); 18106#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18653#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17368#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 17113#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 17114#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17709#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17710#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 18620#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 17270#L1768-2 [2023-11-26 10:50:04,147 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:04,148 INFO L85 PathProgramCache]: Analyzing trace with hash -1474786415, now seen corresponding path program 1 times [2023-11-26 10:50:04,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:04,148 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [293177679] [2023-11-26 10:50:04,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:04,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:04,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:04,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:04,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:04,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [293177679] [2023-11-26 10:50:04,247 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [293177679] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:04,247 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:04,248 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:04,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [335305315] [2023-11-26 10:50:04,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:04,249 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:04,249 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:04,249 INFO L85 PathProgramCache]: Analyzing trace with hash -634554918, now seen corresponding path program 1 times [2023-11-26 10:50:04,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:04,250 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913591774] [2023-11-26 10:50:04,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:04,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:04,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:04,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:04,337 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:04,337 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [913591774] [2023-11-26 10:50:04,337 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [913591774] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:04,337 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:04,338 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:04,338 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1683994985] [2023-11-26 10:50:04,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:04,339 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:04,339 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:04,340 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:04,340 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:04,340 INFO L87 Difference]: Start difference. First operand 1701 states and 2513 transitions. cyclomatic complexity: 813 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:04,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:04,391 INFO L93 Difference]: Finished difference Result 1701 states and 2512 transitions. [2023-11-26 10:50:04,391 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2512 transitions. [2023-11-26 10:50:04,405 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:04,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2512 transitions. [2023-11-26 10:50:04,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-26 10:50:04,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-26 10:50:04,422 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2512 transitions. [2023-11-26 10:50:04,425 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:04,425 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2512 transitions. [2023-11-26 10:50:04,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2512 transitions. [2023-11-26 10:50:04,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-26 10:50:04,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4767783656672546) internal successors, (2512), 1700 states have internal predecessors, (2512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:04,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2512 transitions. [2023-11-26 10:50:04,468 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2512 transitions. [2023-11-26 10:50:04,468 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:04,470 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2512 transitions. [2023-11-26 10:50:04,471 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-26 10:50:04,471 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2512 transitions. [2023-11-26 10:50:04,479 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:04,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:04,479 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:04,482 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:04,482 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:04,483 INFO L748 eck$LassoCheckResult]: Stem: 20747#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 20748#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 21540#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21541#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21408#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 21409#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21502#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21801#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21936#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21937#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20723#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20724#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21868#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21306#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21307#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21217#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21218#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21611#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20962#L1174 assume !(0 == ~M_E~0); 20963#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20814#L1179-1 assume !(0 == ~T2_E~0); 20720#L1184-1 assume !(0 == ~T3_E~0); 20721#L1189-1 assume !(0 == ~T4_E~0); 20763#L1194-1 assume !(0 == ~T5_E~0); 20856#L1199-1 assume !(0 == ~T6_E~0); 21735#L1204-1 assume !(0 == ~T7_E~0); 21656#L1209-1 assume !(0 == ~T8_E~0); 21657#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22080#L1219-1 assume !(0 == ~T10_E~0); 22165#L1224-1 assume !(0 == ~T11_E~0); 21079#L1229-1 assume !(0 == ~T12_E~0); 20650#L1234-1 assume !(0 == ~E_1~0); 20651#L1239-1 assume !(0 == ~E_2~0); 20683#L1244-1 assume !(0 == ~E_3~0); 20684#L1249-1 assume !(0 == ~E_4~0); 21326#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 20580#L1259-1 assume !(0 == ~E_6~0); 20533#L1264-1 assume !(0 == ~E_7~0); 20534#L1269-1 assume !(0 == ~E_8~0); 22168#L1274-1 assume !(0 == ~E_9~0); 22107#L1279-1 assume !(0 == ~E_10~0); 20767#L1284-1 assume !(0 == ~E_11~0); 20768#L1289-1 assume !(0 == ~E_12~0); 21378#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21379#L566 assume 1 == ~m_pc~0; 20550#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20551#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21422#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21423#L1455 assume !(0 != activate_threads_~tmp~1#1); 20989#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20990#L585 assume 1 == ~t1_pc~0; 20647#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20648#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21791#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21792#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 22136#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22132#L604 assume !(1 == ~t2_pc~0); 21697#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21698#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20932#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20933#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21896#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21897#L623 assume 1 == ~t3_pc~0; 21163#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20509#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21766#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21767#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 21930#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20547#L642 assume !(1 == ~t4_pc~0); 20548#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21000#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20602#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20603#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 20624#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21710#L661 assume 1 == ~t5_pc~0; 20780#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20781#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21628#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21995#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 21742#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21743#L680 assume !(1 == ~t6_pc~0); 21196#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21197#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20923#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20924#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 22005#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22129#L699 assume 1 == ~t7_pc~0; 21591#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21592#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21824#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21484#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 21485#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21380#L718 assume !(1 == ~t8_pc~0); 21381#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20761#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20762#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20796#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 20797#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20929#L737 assume 1 == ~t9_pc~0; 21780#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21060#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20969#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20970#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 21237#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21238#L756 assume 1 == ~t10_pc~0; 21814#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21475#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21730#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21415#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 21039#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21040#L775 assume !(1 == ~t11_pc~0); 21298#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21299#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22073#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20695#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20696#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20877#L794 assume 1 == ~t12_pc~0; 20718#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20698#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20553#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20554#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 20842#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21310#L1307 assume !(1 == ~M_E~0); 21311#L1307-2 assume !(1 == ~T1_E~0); 21419#L1312-1 assume !(1 == ~T2_E~0); 21339#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21340#L1322-1 assume !(1 == ~T4_E~0); 21050#L1327-1 assume !(1 == ~T5_E~0); 21051#L1332-1 assume !(1 == ~T6_E~0); 21596#L1337-1 assume !(1 == ~T7_E~0); 21553#L1342-1 assume !(1 == ~T8_E~0); 21554#L1347-1 assume !(1 == ~T9_E~0); 21966#L1352-1 assume !(1 == ~T10_E~0); 21825#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21215#L1362-1 assume !(1 == ~T12_E~0); 21216#L1367-1 assume !(1 == ~E_1~0); 20857#L1372-1 assume !(1 == ~E_2~0); 20858#L1377-1 assume !(1 == ~E_3~0); 21148#L1382-1 assume !(1 == ~E_4~0); 21149#L1387-1 assume !(1 == ~E_5~0); 21699#L1392-1 assume !(1 == ~E_6~0); 21166#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 21167#L1402-1 assume !(1 == ~E_8~0); 20872#L1407-1 assume !(1 == ~E_9~0); 20873#L1412-1 assume !(1 == ~E_10~0); 21891#L1417-1 assume !(1 == ~E_11~0); 21892#L1422-1 assume !(1 == ~E_12~0); 22126#L1427-1 assume { :end_inline_reset_delta_events } true; 20679#L1768-2 [2023-11-26 10:50:04,484 INFO L750 eck$LassoCheckResult]: Loop: 20679#L1768-2 assume !false; 20680#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21343#L1149-1 assume !false; 21721#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21948#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21057#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21873#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21943#L976 assume !(0 != eval_~tmp~0#1); 21371#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21100#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21101#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21901#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21639#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21640#L1184-3 assume !(0 == ~T3_E~0); 21826#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21470#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20833#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20834#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21070#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20493#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20494#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21250#L1224-3 assume !(0 == ~T11_E~0); 21251#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21265#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20689#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20690#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21125#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21583#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22076#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21682#L1264-3 assume !(0 == ~E_7~0); 20693#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20694#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22106#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21246#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21247#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 21234#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20913#L566-39 assume 1 == ~m_pc~0; 20914#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21513#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21514#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21566#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21757#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21758#L585-39 assume !(1 == ~t1_pc~0); 20921#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 20922#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21122#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22070#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21795#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21490#L604-39 assume 1 == ~t2_pc~0; 21491#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21129#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21130#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21309#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21543#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21111#L623-39 assume !(1 == ~t3_pc~0); 20512#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 20511#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21775#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20964#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20965#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21717#L642-39 assume 1 == ~t4_pc~0; 21300#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21301#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21465#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21466#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21947#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20883#L661-39 assume 1 == ~t5_pc~0; 20884#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20519#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21497#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21498#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21777#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21778#L680-39 assume 1 == ~t6_pc~0; 20585#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20586#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22026#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21037#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 21038#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22082#L699-39 assume 1 == ~t7_pc~0; 21472#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21199#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21200#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21782#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22022#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22019#L718-39 assume 1 == ~t8_pc~0; 21384#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21385#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21878#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21879#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21627#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21604#L737-39 assume 1 == ~t9_pc~0; 21018#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21019#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20613#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20614#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21994#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21931#L756-39 assume !(1 == ~t10_pc~0); 21398#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 21399#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22069#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21283#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21284#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20634#L775-39 assume 1 == ~t11_pc~0; 20635#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21274#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21275#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21524#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21675#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21325#L794-39 assume !(1 == ~t12_pc~0); 21014#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 21015#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21108#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21109#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20576#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20577#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22053#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22054#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22167#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21744#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21745#L1327-3 assume !(1 == ~T5_E~0); 20710#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20685#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20686#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21413#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21546#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21547#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22002#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22162#L1367-3 assume !(1 == ~E_1~0); 22153#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20506#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20507#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21132#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21133#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21852#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22120#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21512#L1407-3 assume !(1 == ~E_9~0); 20792#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20793#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21427#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21428#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 20800#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20801#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 20868#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 20869#L1787 assume !(0 == start_simulation_~tmp~3#1); 21516#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22062#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20777#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 20525#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 20526#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21118#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21119#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 22029#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 20679#L1768-2 [2023-11-26 10:50:04,484 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:04,485 INFO L85 PathProgramCache]: Analyzing trace with hash 313083407, now seen corresponding path program 1 times [2023-11-26 10:50:04,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:04,485 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151862252] [2023-11-26 10:50:04,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:04,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:04,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:04,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:04,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:04,558 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151862252] [2023-11-26 10:50:04,558 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1151862252] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:04,558 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:04,559 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:04,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1619552668] [2023-11-26 10:50:04,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:04,559 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:04,560 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:04,560 INFO L85 PathProgramCache]: Analyzing trace with hash 1993292795, now seen corresponding path program 1 times [2023-11-26 10:50:04,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:04,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1888281911] [2023-11-26 10:50:04,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:04,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:04,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:04,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:04,659 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:04,660 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1888281911] [2023-11-26 10:50:04,660 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1888281911] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:04,660 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:04,660 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:04,660 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [29975414] [2023-11-26 10:50:04,661 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:04,661 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:04,661 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:04,662 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:04,662 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:04,662 INFO L87 Difference]: Start difference. First operand 1701 states and 2512 transitions. cyclomatic complexity: 812 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:04,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:04,713 INFO L93 Difference]: Finished difference Result 1701 states and 2511 transitions. [2023-11-26 10:50:04,714 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2511 transitions. [2023-11-26 10:50:04,726 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:04,742 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2511 transitions. [2023-11-26 10:50:04,742 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-26 10:50:04,747 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-26 10:50:04,747 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2511 transitions. [2023-11-26 10:50:04,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:04,750 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2511 transitions. [2023-11-26 10:50:04,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2511 transitions. [2023-11-26 10:50:04,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-26 10:50:04,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4761904761904763) internal successors, (2511), 1700 states have internal predecessors, (2511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:04,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2511 transitions. [2023-11-26 10:50:04,796 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2511 transitions. [2023-11-26 10:50:04,797 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:04,799 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2511 transitions. [2023-11-26 10:50:04,799 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-26 10:50:04,799 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2511 transitions. [2023-11-26 10:50:04,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:04,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:04,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:04,842 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:04,842 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:04,843 INFO L748 eck$LassoCheckResult]: Stem: 24156#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 24157#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 24949#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24950#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24817#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 24818#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24911#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25210#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25345#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25346#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24132#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24133#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25277#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24715#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24716#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24626#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24627#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25020#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24371#L1174 assume !(0 == ~M_E~0); 24372#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24223#L1179-1 assume !(0 == ~T2_E~0); 24129#L1184-1 assume !(0 == ~T3_E~0); 24130#L1189-1 assume !(0 == ~T4_E~0); 24172#L1194-1 assume !(0 == ~T5_E~0); 24265#L1199-1 assume !(0 == ~T6_E~0); 25144#L1204-1 assume !(0 == ~T7_E~0); 25065#L1209-1 assume !(0 == ~T8_E~0); 25066#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25489#L1219-1 assume !(0 == ~T10_E~0); 25574#L1224-1 assume !(0 == ~T11_E~0); 24488#L1229-1 assume !(0 == ~T12_E~0); 24059#L1234-1 assume !(0 == ~E_1~0); 24060#L1239-1 assume !(0 == ~E_2~0); 24092#L1244-1 assume !(0 == ~E_3~0); 24093#L1249-1 assume !(0 == ~E_4~0); 24735#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 23989#L1259-1 assume !(0 == ~E_6~0); 23942#L1264-1 assume !(0 == ~E_7~0); 23943#L1269-1 assume !(0 == ~E_8~0); 25577#L1274-1 assume !(0 == ~E_9~0); 25516#L1279-1 assume !(0 == ~E_10~0); 24176#L1284-1 assume !(0 == ~E_11~0); 24177#L1289-1 assume !(0 == ~E_12~0); 24787#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24788#L566 assume 1 == ~m_pc~0; 23959#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23960#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24831#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24832#L1455 assume !(0 != activate_threads_~tmp~1#1); 24398#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24399#L585 assume 1 == ~t1_pc~0; 24056#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24057#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25200#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25201#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 25545#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25541#L604 assume !(1 == ~t2_pc~0); 25106#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 25107#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24341#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24342#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25305#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25306#L623 assume 1 == ~t3_pc~0; 24572#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23918#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25175#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25176#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 25339#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23956#L642 assume !(1 == ~t4_pc~0); 23957#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24409#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24011#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24012#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 24033#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25119#L661 assume 1 == ~t5_pc~0; 24189#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24190#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25037#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25404#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 25151#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25152#L680 assume !(1 == ~t6_pc~0); 24605#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24606#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24332#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24333#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 25414#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25538#L699 assume 1 == ~t7_pc~0; 25000#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25001#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25233#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24893#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 24894#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24789#L718 assume !(1 == ~t8_pc~0); 24790#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 24170#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24171#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24205#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 24206#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24338#L737 assume 1 == ~t9_pc~0; 25189#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24469#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24378#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24379#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 24646#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24647#L756 assume 1 == ~t10_pc~0; 25223#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24884#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25139#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24824#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 24448#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24449#L775 assume !(1 == ~t11_pc~0); 24707#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24708#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25482#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24104#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24105#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24286#L794 assume 1 == ~t12_pc~0; 24127#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24107#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23962#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23963#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 24251#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24719#L1307 assume !(1 == ~M_E~0); 24720#L1307-2 assume !(1 == ~T1_E~0); 24828#L1312-1 assume !(1 == ~T2_E~0); 24748#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24749#L1322-1 assume !(1 == ~T4_E~0); 24459#L1327-1 assume !(1 == ~T5_E~0); 24460#L1332-1 assume !(1 == ~T6_E~0); 25005#L1337-1 assume !(1 == ~T7_E~0); 24962#L1342-1 assume !(1 == ~T8_E~0); 24963#L1347-1 assume !(1 == ~T9_E~0); 25375#L1352-1 assume !(1 == ~T10_E~0); 25234#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24624#L1362-1 assume !(1 == ~T12_E~0); 24625#L1367-1 assume !(1 == ~E_1~0); 24266#L1372-1 assume !(1 == ~E_2~0); 24267#L1377-1 assume !(1 == ~E_3~0); 24557#L1382-1 assume !(1 == ~E_4~0); 24558#L1387-1 assume !(1 == ~E_5~0); 25108#L1392-1 assume !(1 == ~E_6~0); 24575#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 24576#L1402-1 assume !(1 == ~E_8~0); 24281#L1407-1 assume !(1 == ~E_9~0); 24282#L1412-1 assume !(1 == ~E_10~0); 25300#L1417-1 assume !(1 == ~E_11~0); 25301#L1422-1 assume !(1 == ~E_12~0); 25535#L1427-1 assume { :end_inline_reset_delta_events } true; 24088#L1768-2 [2023-11-26 10:50:04,844 INFO L750 eck$LassoCheckResult]: Loop: 24088#L1768-2 assume !false; 24089#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24752#L1149-1 assume !false; 25130#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25357#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24466#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25282#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 25352#L976 assume !(0 != eval_~tmp~0#1); 24780#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24509#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24510#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25310#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25048#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25049#L1184-3 assume !(0 == ~T3_E~0); 25235#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24879#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24242#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24243#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24479#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23902#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23903#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24659#L1224-3 assume !(0 == ~T11_E~0); 24660#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24674#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24098#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24099#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24534#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24992#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25485#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25091#L1264-3 assume !(0 == ~E_7~0); 24102#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24103#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25515#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24655#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24656#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 24643#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24322#L566-39 assume 1 == ~m_pc~0; 24323#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24922#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24923#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24975#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25166#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25167#L585-39 assume 1 == ~t1_pc~0; 25296#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24331#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24531#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25479#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25204#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24899#L604-39 assume 1 == ~t2_pc~0; 24900#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24538#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24539#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24718#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24952#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24520#L623-39 assume !(1 == ~t3_pc~0); 23921#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 23920#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25184#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24373#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24374#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25126#L642-39 assume 1 == ~t4_pc~0; 24709#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24710#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24874#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24875#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25356#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24292#L661-39 assume 1 == ~t5_pc~0; 24293#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23928#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24906#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24907#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25186#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25187#L680-39 assume 1 == ~t6_pc~0; 23994#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23995#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25435#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24446#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 24447#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25491#L699-39 assume 1 == ~t7_pc~0; 24881#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24608#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24609#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25191#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25431#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25428#L718-39 assume 1 == ~t8_pc~0; 24793#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24794#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25287#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25288#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25036#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25013#L737-39 assume 1 == ~t9_pc~0; 24427#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24428#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24022#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24023#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25403#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25340#L756-39 assume !(1 == ~t10_pc~0); 24807#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 24808#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25478#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24692#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24693#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24043#L775-39 assume 1 == ~t11_pc~0; 24044#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24683#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24684#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24933#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25084#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24734#L794-39 assume !(1 == ~t12_pc~0); 24423#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 24424#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24517#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24518#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 23985#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23986#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25462#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25463#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25576#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25153#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25154#L1327-3 assume !(1 == ~T5_E~0); 24119#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24094#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24095#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24822#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24955#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24956#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25411#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25571#L1367-3 assume !(1 == ~E_1~0); 25562#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23915#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23916#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24541#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24542#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25261#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25529#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24921#L1407-3 assume !(1 == ~E_9~0); 24201#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24202#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24836#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24837#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 24209#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24210#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24277#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 24278#L1787 assume !(0 == start_simulation_~tmp~3#1); 24925#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25471#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24186#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 23934#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 23935#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24527#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24528#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 25438#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 24088#L1768-2 [2023-11-26 10:50:04,845 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:04,845 INFO L85 PathProgramCache]: Analyzing trace with hash -1846000687, now seen corresponding path program 1 times [2023-11-26 10:50:04,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:04,847 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [320414105] [2023-11-26 10:50:04,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:04,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:04,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:04,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:04,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:04,906 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [320414105] [2023-11-26 10:50:04,906 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [320414105] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:04,906 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:04,906 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:04,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1396666033] [2023-11-26 10:50:04,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:04,911 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:04,912 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:04,912 INFO L85 PathProgramCache]: Analyzing trace with hash 1831355804, now seen corresponding path program 1 times [2023-11-26 10:50:04,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:04,914 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1657666571] [2023-11-26 10:50:04,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:04,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:04,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:04,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:04,993 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:04,993 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1657666571] [2023-11-26 10:50:04,996 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1657666571] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:04,996 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:04,996 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:04,996 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766949350] [2023-11-26 10:50:04,997 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:04,997 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:04,997 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:04,998 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:04,998 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:04,998 INFO L87 Difference]: Start difference. First operand 1701 states and 2511 transitions. cyclomatic complexity: 811 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:05,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:05,048 INFO L93 Difference]: Finished difference Result 1701 states and 2510 transitions. [2023-11-26 10:50:05,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2510 transitions. [2023-11-26 10:50:05,060 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:05,074 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2510 transitions. [2023-11-26 10:50:05,074 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-26 10:50:05,076 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-26 10:50:05,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2510 transitions. [2023-11-26 10:50:05,079 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:05,080 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2510 transitions. [2023-11-26 10:50:05,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2510 transitions. [2023-11-26 10:50:05,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-26 10:50:05,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.475602586713698) internal successors, (2510), 1700 states have internal predecessors, (2510), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:05,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2510 transitions. [2023-11-26 10:50:05,122 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2510 transitions. [2023-11-26 10:50:05,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:05,125 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2510 transitions. [2023-11-26 10:50:05,125 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-26 10:50:05,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2510 transitions. [2023-11-26 10:50:05,133 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:05,133 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:05,133 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:05,136 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:05,136 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:05,137 INFO L748 eck$LassoCheckResult]: Stem: 27565#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 27566#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 28358#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28359#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28226#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 28227#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28320#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28619#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28754#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28755#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27541#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27542#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28686#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 28124#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28125#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28035#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28036#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28429#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27780#L1174 assume !(0 == ~M_E~0); 27781#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27632#L1179-1 assume !(0 == ~T2_E~0); 27538#L1184-1 assume !(0 == ~T3_E~0); 27539#L1189-1 assume !(0 == ~T4_E~0); 27581#L1194-1 assume !(0 == ~T5_E~0); 27674#L1199-1 assume !(0 == ~T6_E~0); 28553#L1204-1 assume !(0 == ~T7_E~0); 28474#L1209-1 assume !(0 == ~T8_E~0); 28475#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28898#L1219-1 assume !(0 == ~T10_E~0); 28983#L1224-1 assume !(0 == ~T11_E~0); 27897#L1229-1 assume !(0 == ~T12_E~0); 27468#L1234-1 assume !(0 == ~E_1~0); 27469#L1239-1 assume !(0 == ~E_2~0); 27501#L1244-1 assume !(0 == ~E_3~0); 27502#L1249-1 assume !(0 == ~E_4~0); 28144#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 27398#L1259-1 assume !(0 == ~E_6~0); 27351#L1264-1 assume !(0 == ~E_7~0); 27352#L1269-1 assume !(0 == ~E_8~0); 28986#L1274-1 assume !(0 == ~E_9~0); 28925#L1279-1 assume !(0 == ~E_10~0); 27585#L1284-1 assume !(0 == ~E_11~0); 27586#L1289-1 assume !(0 == ~E_12~0); 28196#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28197#L566 assume 1 == ~m_pc~0; 27368#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27369#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28240#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28241#L1455 assume !(0 != activate_threads_~tmp~1#1); 27807#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27808#L585 assume 1 == ~t1_pc~0; 27465#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27466#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28609#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28610#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 28954#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28950#L604 assume !(1 == ~t2_pc~0); 28515#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28516#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27750#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27751#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28714#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28715#L623 assume 1 == ~t3_pc~0; 27981#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27327#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28584#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28585#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 28748#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27365#L642 assume !(1 == ~t4_pc~0); 27366#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27818#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27420#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27421#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 27442#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28528#L661 assume 1 == ~t5_pc~0; 27598#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27599#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28446#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28813#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 28560#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28561#L680 assume !(1 == ~t6_pc~0); 28014#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 28015#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27741#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27742#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 28823#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28947#L699 assume 1 == ~t7_pc~0; 28409#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28410#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28642#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28302#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 28303#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28198#L718 assume !(1 == ~t8_pc~0); 28199#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27579#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27580#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27614#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 27615#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27747#L737 assume 1 == ~t9_pc~0; 28598#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27878#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27787#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27788#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 28055#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28056#L756 assume 1 == ~t10_pc~0; 28632#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28293#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28548#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28233#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 27857#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27858#L775 assume !(1 == ~t11_pc~0); 28116#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 28117#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28891#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27513#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27514#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27695#L794 assume 1 == ~t12_pc~0; 27536#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27516#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27371#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27372#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 27660#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28128#L1307 assume !(1 == ~M_E~0); 28129#L1307-2 assume !(1 == ~T1_E~0); 28237#L1312-1 assume !(1 == ~T2_E~0); 28157#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28158#L1322-1 assume !(1 == ~T4_E~0); 27868#L1327-1 assume !(1 == ~T5_E~0); 27869#L1332-1 assume !(1 == ~T6_E~0); 28414#L1337-1 assume !(1 == ~T7_E~0); 28371#L1342-1 assume !(1 == ~T8_E~0); 28372#L1347-1 assume !(1 == ~T9_E~0); 28784#L1352-1 assume !(1 == ~T10_E~0); 28643#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28033#L1362-1 assume !(1 == ~T12_E~0); 28034#L1367-1 assume !(1 == ~E_1~0); 27675#L1372-1 assume !(1 == ~E_2~0); 27676#L1377-1 assume !(1 == ~E_3~0); 27966#L1382-1 assume !(1 == ~E_4~0); 27967#L1387-1 assume !(1 == ~E_5~0); 28517#L1392-1 assume !(1 == ~E_6~0); 27984#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27985#L1402-1 assume !(1 == ~E_8~0); 27690#L1407-1 assume !(1 == ~E_9~0); 27691#L1412-1 assume !(1 == ~E_10~0); 28709#L1417-1 assume !(1 == ~E_11~0); 28710#L1422-1 assume !(1 == ~E_12~0); 28944#L1427-1 assume { :end_inline_reset_delta_events } true; 27497#L1768-2 [2023-11-26 10:50:05,138 INFO L750 eck$LassoCheckResult]: Loop: 27497#L1768-2 assume !false; 27498#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28161#L1149-1 assume !false; 28539#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28766#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27875#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28691#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28761#L976 assume !(0 != eval_~tmp~0#1); 28189#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27918#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27919#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28719#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28457#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28458#L1184-3 assume !(0 == ~T3_E~0); 28644#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28288#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27651#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27652#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27888#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27311#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27312#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28068#L1224-3 assume !(0 == ~T11_E~0); 28069#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28083#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27507#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27508#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27943#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28401#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28894#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28500#L1264-3 assume !(0 == ~E_7~0); 27511#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27512#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28924#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28064#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28065#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 28052#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27731#L566-39 assume 1 == ~m_pc~0; 27732#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28331#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28332#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28384#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28575#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28576#L585-39 assume 1 == ~t1_pc~0; 28705#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27740#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27940#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28888#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28613#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28308#L604-39 assume 1 == ~t2_pc~0; 28309#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27947#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27948#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28127#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28361#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27929#L623-39 assume 1 == ~t3_pc~0; 27328#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27329#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28593#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27782#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27783#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28535#L642-39 assume 1 == ~t4_pc~0; 28118#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28119#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28283#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28284#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28765#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27701#L661-39 assume 1 == ~t5_pc~0; 27702#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27337#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28315#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28316#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28595#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28596#L680-39 assume 1 == ~t6_pc~0; 27403#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27404#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28844#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27855#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 27856#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28900#L699-39 assume 1 == ~t7_pc~0; 28290#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28017#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28018#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28600#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28840#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28837#L718-39 assume 1 == ~t8_pc~0; 28202#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28203#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28696#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28697#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28445#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28422#L737-39 assume 1 == ~t9_pc~0; 27836#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27837#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27431#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27432#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28812#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28749#L756-39 assume !(1 == ~t10_pc~0); 28216#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 28217#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28887#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28101#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28102#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27452#L775-39 assume 1 == ~t11_pc~0; 27453#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28092#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28093#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28342#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28493#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28143#L794-39 assume !(1 == ~t12_pc~0); 27832#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 27833#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27926#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27927#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 27394#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27395#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28871#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28872#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28985#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28562#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28563#L1327-3 assume !(1 == ~T5_E~0); 27528#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27503#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27504#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28231#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28364#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28365#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28820#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28980#L1367-3 assume !(1 == ~E_1~0); 28971#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27324#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27325#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27950#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27951#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28670#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28938#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28330#L1407-3 assume !(1 == ~E_9~0); 27610#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27611#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28245#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28246#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 27618#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27619#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 27686#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 27687#L1787 assume !(0 == start_simulation_~tmp~3#1); 28334#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28880#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27595#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 27343#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 27344#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27936#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27937#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 28847#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 27497#L1768-2 [2023-11-26 10:50:05,138 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:05,139 INFO L85 PathProgramCache]: Analyzing trace with hash -1915648561, now seen corresponding path program 1 times [2023-11-26 10:50:05,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:05,139 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1783762029] [2023-11-26 10:50:05,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:05,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:05,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:05,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:05,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:05,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1783762029] [2023-11-26 10:50:05,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1783762029] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:05,196 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:05,197 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:05,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2094598196] [2023-11-26 10:50:05,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:05,198 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:05,198 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:05,198 INFO L85 PathProgramCache]: Analyzing trace with hash -594413379, now seen corresponding path program 1 times [2023-11-26 10:50:05,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:05,199 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2057593779] [2023-11-26 10:50:05,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:05,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:05,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:05,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:05,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:05,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2057593779] [2023-11-26 10:50:05,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2057593779] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:05,273 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:05,273 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:05,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2073086276] [2023-11-26 10:50:05,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:05,274 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:05,274 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:05,274 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:05,274 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:05,275 INFO L87 Difference]: Start difference. First operand 1701 states and 2510 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:05,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:05,325 INFO L93 Difference]: Finished difference Result 1701 states and 2509 transitions. [2023-11-26 10:50:05,325 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2509 transitions. [2023-11-26 10:50:05,339 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:05,353 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2509 transitions. [2023-11-26 10:50:05,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-26 10:50:05,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-26 10:50:05,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2509 transitions. [2023-11-26 10:50:05,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:05,358 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2509 transitions. [2023-11-26 10:50:05,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2509 transitions. [2023-11-26 10:50:05,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-26 10:50:05,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4750146972369194) internal successors, (2509), 1700 states have internal predecessors, (2509), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:05,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2509 transitions. [2023-11-26 10:50:05,427 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2509 transitions. [2023-11-26 10:50:05,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:05,428 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2509 transitions. [2023-11-26 10:50:05,428 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-26 10:50:05,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2509 transitions. [2023-11-26 10:50:05,437 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:05,437 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:05,437 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:05,440 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:05,441 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:05,441 INFO L748 eck$LassoCheckResult]: Stem: 30974#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 30975#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 31767#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31768#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31635#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 31636#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31729#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32028#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32163#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32164#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30950#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30951#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32095#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31533#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31534#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31444#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31445#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 31838#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31189#L1174 assume !(0 == ~M_E~0); 31190#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31041#L1179-1 assume !(0 == ~T2_E~0); 30947#L1184-1 assume !(0 == ~T3_E~0); 30948#L1189-1 assume !(0 == ~T4_E~0); 30990#L1194-1 assume !(0 == ~T5_E~0); 31083#L1199-1 assume !(0 == ~T6_E~0); 31962#L1204-1 assume !(0 == ~T7_E~0); 31883#L1209-1 assume !(0 == ~T8_E~0); 31884#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32307#L1219-1 assume !(0 == ~T10_E~0); 32392#L1224-1 assume !(0 == ~T11_E~0); 31306#L1229-1 assume !(0 == ~T12_E~0); 30877#L1234-1 assume !(0 == ~E_1~0); 30878#L1239-1 assume !(0 == ~E_2~0); 30910#L1244-1 assume !(0 == ~E_3~0); 30911#L1249-1 assume !(0 == ~E_4~0); 31553#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 30807#L1259-1 assume !(0 == ~E_6~0); 30760#L1264-1 assume !(0 == ~E_7~0); 30761#L1269-1 assume !(0 == ~E_8~0); 32395#L1274-1 assume !(0 == ~E_9~0); 32334#L1279-1 assume !(0 == ~E_10~0); 30994#L1284-1 assume !(0 == ~E_11~0); 30995#L1289-1 assume !(0 == ~E_12~0); 31605#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31606#L566 assume 1 == ~m_pc~0; 30777#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30778#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31649#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31650#L1455 assume !(0 != activate_threads_~tmp~1#1); 31216#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31217#L585 assume 1 == ~t1_pc~0; 30874#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30875#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32018#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32019#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 32363#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32359#L604 assume !(1 == ~t2_pc~0); 31924#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31925#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31159#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31160#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32123#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32124#L623 assume 1 == ~t3_pc~0; 31390#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30736#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31993#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31994#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 32157#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30774#L642 assume !(1 == ~t4_pc~0); 30775#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31227#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30829#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30830#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 30851#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31937#L661 assume 1 == ~t5_pc~0; 31007#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31008#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31855#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32222#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 31969#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31970#L680 assume !(1 == ~t6_pc~0); 31423#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31424#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31150#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31151#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 32232#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32356#L699 assume 1 == ~t7_pc~0; 31818#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31819#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32051#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31711#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 31712#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31607#L718 assume !(1 == ~t8_pc~0); 31608#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30988#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30989#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31023#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 31024#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31156#L737 assume 1 == ~t9_pc~0; 32007#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31287#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31196#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31197#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 31464#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31465#L756 assume 1 == ~t10_pc~0; 32041#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31702#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31957#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31642#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 31266#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31267#L775 assume !(1 == ~t11_pc~0); 31525#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 31526#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32300#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30922#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30923#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31104#L794 assume 1 == ~t12_pc~0; 30945#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30925#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30780#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30781#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 31069#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31537#L1307 assume !(1 == ~M_E~0); 31538#L1307-2 assume !(1 == ~T1_E~0); 31646#L1312-1 assume !(1 == ~T2_E~0); 31566#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31567#L1322-1 assume !(1 == ~T4_E~0); 31277#L1327-1 assume !(1 == ~T5_E~0); 31278#L1332-1 assume !(1 == ~T6_E~0); 31823#L1337-1 assume !(1 == ~T7_E~0); 31780#L1342-1 assume !(1 == ~T8_E~0); 31781#L1347-1 assume !(1 == ~T9_E~0); 32193#L1352-1 assume !(1 == ~T10_E~0); 32052#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31442#L1362-1 assume !(1 == ~T12_E~0); 31443#L1367-1 assume !(1 == ~E_1~0); 31084#L1372-1 assume !(1 == ~E_2~0); 31085#L1377-1 assume !(1 == ~E_3~0); 31375#L1382-1 assume !(1 == ~E_4~0); 31376#L1387-1 assume !(1 == ~E_5~0); 31926#L1392-1 assume !(1 == ~E_6~0); 31393#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 31394#L1402-1 assume !(1 == ~E_8~0); 31099#L1407-1 assume !(1 == ~E_9~0); 31100#L1412-1 assume !(1 == ~E_10~0); 32118#L1417-1 assume !(1 == ~E_11~0); 32119#L1422-1 assume !(1 == ~E_12~0); 32353#L1427-1 assume { :end_inline_reset_delta_events } true; 30906#L1768-2 [2023-11-26 10:50:05,442 INFO L750 eck$LassoCheckResult]: Loop: 30906#L1768-2 assume !false; 30907#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31570#L1149-1 assume !false; 31948#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32175#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31284#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32100#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 32170#L976 assume !(0 != eval_~tmp~0#1); 31598#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31327#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31328#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32128#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31866#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31867#L1184-3 assume !(0 == ~T3_E~0); 32053#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31697#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31060#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31061#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31297#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30720#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30721#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31477#L1224-3 assume !(0 == ~T11_E~0); 31478#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31492#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30916#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30917#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31352#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31810#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32303#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31909#L1264-3 assume !(0 == ~E_7~0); 30920#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30921#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32333#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31473#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31474#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 31461#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31140#L566-39 assume 1 == ~m_pc~0; 31141#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31740#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31741#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31793#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31984#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31985#L585-39 assume 1 == ~t1_pc~0; 32114#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31149#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31349#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32297#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32022#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31717#L604-39 assume 1 == ~t2_pc~0; 31718#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31356#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31357#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31536#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31770#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31338#L623-39 assume 1 == ~t3_pc~0; 30737#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30738#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32002#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31191#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31192#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31944#L642-39 assume 1 == ~t4_pc~0; 31527#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31528#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31692#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31693#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32174#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31110#L661-39 assume 1 == ~t5_pc~0; 31111#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30746#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31724#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31725#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32004#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32005#L680-39 assume 1 == ~t6_pc~0; 30812#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30813#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32253#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31264#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 31265#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32309#L699-39 assume 1 == ~t7_pc~0; 31699#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31426#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31427#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32009#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32249#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32246#L718-39 assume 1 == ~t8_pc~0; 31611#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31612#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32105#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32106#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31854#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31831#L737-39 assume 1 == ~t9_pc~0; 31245#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31246#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30840#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30841#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32221#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32158#L756-39 assume !(1 == ~t10_pc~0); 31625#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 31626#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32296#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31510#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31511#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30861#L775-39 assume 1 == ~t11_pc~0; 30862#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31501#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31502#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31751#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31902#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31552#L794-39 assume 1 == ~t12_pc~0; 31248#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31242#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31335#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31336#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30803#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30804#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32280#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32281#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32394#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31971#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31972#L1327-3 assume !(1 == ~T5_E~0); 30937#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30912#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30913#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31640#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31773#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 31774#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32229#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32389#L1367-3 assume !(1 == ~E_1~0); 32380#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30733#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30734#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31359#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31360#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32079#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32347#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31739#L1407-3 assume !(1 == ~E_9~0); 31019#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 31020#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 31654#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31655#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 31027#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31028#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 31095#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 31096#L1787 assume !(0 == start_simulation_~tmp~3#1); 31743#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32289#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31004#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30752#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 30753#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31345#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31346#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 32256#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 30906#L1768-2 [2023-11-26 10:50:05,443 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:05,444 INFO L85 PathProgramCache]: Analyzing trace with hash 1961430033, now seen corresponding path program 1 times [2023-11-26 10:50:05,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:05,444 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230345767] [2023-11-26 10:50:05,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:05,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:05,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:05,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:05,511 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:05,512 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [230345767] [2023-11-26 10:50:05,512 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [230345767] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:05,512 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:05,512 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:05,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285947648] [2023-11-26 10:50:05,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:05,514 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:05,514 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:05,515 INFO L85 PathProgramCache]: Analyzing trace with hash 680689310, now seen corresponding path program 1 times [2023-11-26 10:50:05,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:05,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272765362] [2023-11-26 10:50:05,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:05,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:05,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:05,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:05,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:05,590 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1272765362] [2023-11-26 10:50:05,590 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1272765362] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:05,590 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:05,590 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:05,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193949562] [2023-11-26 10:50:05,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:05,591 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:05,591 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:05,592 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:05,592 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:05,592 INFO L87 Difference]: Start difference. First operand 1701 states and 2509 transitions. cyclomatic complexity: 809 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:05,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:05,640 INFO L93 Difference]: Finished difference Result 1701 states and 2508 transitions. [2023-11-26 10:50:05,640 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2508 transitions. [2023-11-26 10:50:05,651 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:05,664 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2508 transitions. [2023-11-26 10:50:05,664 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-26 10:50:05,666 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-26 10:50:05,667 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2508 transitions. [2023-11-26 10:50:05,669 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:05,669 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2508 transitions. [2023-11-26 10:50:05,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2508 transitions. [2023-11-26 10:50:05,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-26 10:50:05,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.474426807760141) internal successors, (2508), 1700 states have internal predecessors, (2508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:05,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2508 transitions. [2023-11-26 10:50:05,711 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2508 transitions. [2023-11-26 10:50:05,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:05,712 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2508 transitions. [2023-11-26 10:50:05,712 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-26 10:50:05,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2508 transitions. [2023-11-26 10:50:05,720 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:05,721 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:05,721 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:05,724 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:05,724 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:05,724 INFO L748 eck$LassoCheckResult]: Stem: 34383#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 34384#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 35177#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35178#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35044#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 35045#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35138#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35442#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35572#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35573#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34359#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34360#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35504#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34942#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34943#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34855#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 34856#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35247#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34598#L1174 assume !(0 == ~M_E~0); 34599#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34452#L1179-1 assume !(0 == ~T2_E~0); 34356#L1184-1 assume !(0 == ~T3_E~0); 34357#L1189-1 assume !(0 == ~T4_E~0); 34399#L1194-1 assume !(0 == ~T5_E~0); 34494#L1199-1 assume !(0 == ~T6_E~0); 35371#L1204-1 assume !(0 == ~T7_E~0); 35292#L1209-1 assume !(0 == ~T8_E~0); 35293#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35716#L1219-1 assume !(0 == ~T10_E~0); 35801#L1224-1 assume !(0 == ~T11_E~0); 34717#L1229-1 assume !(0 == ~T12_E~0); 34286#L1234-1 assume !(0 == ~E_1~0); 34287#L1239-1 assume !(0 == ~E_2~0); 34321#L1244-1 assume !(0 == ~E_3~0); 34322#L1249-1 assume !(0 == ~E_4~0); 34962#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 34216#L1259-1 assume !(0 == ~E_6~0); 34169#L1264-1 assume !(0 == ~E_7~0); 34170#L1269-1 assume !(0 == ~E_8~0); 35804#L1274-1 assume !(0 == ~E_9~0); 35744#L1279-1 assume !(0 == ~E_10~0); 34403#L1284-1 assume !(0 == ~E_11~0); 34404#L1289-1 assume !(0 == ~E_12~0); 35014#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35015#L566 assume 1 == ~m_pc~0; 34186#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34187#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35058#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35059#L1455 assume !(0 != activate_threads_~tmp~1#1); 34625#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34626#L585 assume 1 == ~t1_pc~0; 34283#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34284#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35427#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35428#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 35772#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35768#L604 assume !(1 == ~t2_pc~0); 35333#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35334#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34573#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34574#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35534#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35535#L623 assume 1 == ~t3_pc~0; 34799#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34145#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35405#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35406#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 35566#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34183#L642 assume !(1 == ~t4_pc~0); 34184#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34636#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34244#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34245#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 34260#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35346#L661 assume 1 == ~t5_pc~0; 34416#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34417#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35264#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35631#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 35380#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35381#L680 assume !(1 == ~t6_pc~0); 34832#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34833#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34562#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34563#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 35641#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35766#L699 assume 1 == ~t7_pc~0; 35227#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35228#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35460#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35120#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 35121#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35016#L718 assume !(1 == ~t8_pc~0); 35017#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34397#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34398#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34434#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 34435#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34565#L737 assume 1 == ~t9_pc~0; 35418#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34698#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34605#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34606#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 34873#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34874#L756 assume 1 == ~t10_pc~0; 35450#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35112#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35366#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35051#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 34675#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34676#L775 assume !(1 == ~t11_pc~0); 34934#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 34935#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35709#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34331#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34332#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34513#L794 assume 1 == ~t12_pc~0; 34355#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34334#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34191#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34192#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 34480#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34946#L1307 assume !(1 == ~M_E~0); 34947#L1307-2 assume !(1 == ~T1_E~0); 35055#L1312-1 assume !(1 == ~T2_E~0); 34975#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34976#L1322-1 assume !(1 == ~T4_E~0); 34686#L1327-1 assume !(1 == ~T5_E~0); 34687#L1332-1 assume !(1 == ~T6_E~0); 35232#L1337-1 assume !(1 == ~T7_E~0); 35190#L1342-1 assume !(1 == ~T8_E~0); 35191#L1347-1 assume !(1 == ~T9_E~0); 35602#L1352-1 assume !(1 == ~T10_E~0); 35461#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34851#L1362-1 assume !(1 == ~T12_E~0); 34852#L1367-1 assume !(1 == ~E_1~0); 34495#L1372-1 assume !(1 == ~E_2~0); 34496#L1377-1 assume !(1 == ~E_3~0); 34784#L1382-1 assume !(1 == ~E_4~0); 34785#L1387-1 assume !(1 == ~E_5~0); 35335#L1392-1 assume !(1 == ~E_6~0); 34804#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34805#L1402-1 assume !(1 == ~E_8~0); 34511#L1407-1 assume !(1 == ~E_9~0); 34512#L1412-1 assume !(1 == ~E_10~0); 35527#L1417-1 assume !(1 == ~E_11~0); 35528#L1422-1 assume !(1 == ~E_12~0); 35762#L1427-1 assume { :end_inline_reset_delta_events } true; 34315#L1768-2 [2023-11-26 10:50:05,725 INFO L750 eck$LassoCheckResult]: Loop: 34315#L1768-2 assume !false; 34316#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34979#L1149-1 assume !false; 35359#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35584#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34693#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 35509#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35579#L976 assume !(0 != eval_~tmp~0#1); 35007#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34736#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34737#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35537#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35275#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35276#L1184-3 assume !(0 == ~T3_E~0); 35463#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35106#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34472#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34473#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34706#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 34129#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34130#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34886#L1224-3 assume !(0 == ~T11_E~0); 34887#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 34901#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34323#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34324#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34761#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35219#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35712#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35318#L1264-3 assume !(0 == ~E_7~0); 34329#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34330#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35742#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34882#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34883#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 34870#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34546#L566-39 assume 1 == ~m_pc~0; 34547#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35149#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35150#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35202#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35393#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35394#L585-39 assume 1 == ~t1_pc~0; 35523#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34558#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34758#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35706#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35431#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35126#L604-39 assume 1 == ~t2_pc~0; 35127#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34765#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34766#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34945#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35179#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34747#L623-39 assume 1 == ~t3_pc~0; 34146#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34147#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35411#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34600#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34601#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35353#L642-39 assume 1 == ~t4_pc~0; 34936#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34937#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35101#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35102#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35583#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34519#L661-39 assume 1 == ~t5_pc~0; 34520#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34155#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35133#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35134#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35413#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35414#L680-39 assume 1 == ~t6_pc~0; 34221#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34222#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35662#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34673#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 34674#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35718#L699-39 assume 1 == ~t7_pc~0; 35108#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34835#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34836#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35417#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35658#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35655#L718-39 assume 1 == ~t8_pc~0; 35020#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35021#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35514#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35515#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35263#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35240#L737-39 assume !(1 == ~t9_pc~0); 34656#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 34655#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34249#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34250#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35630#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35567#L756-39 assume 1 == ~t10_pc~0; 35568#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35035#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35705#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34919#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34920#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34270#L775-39 assume !(1 == ~t11_pc~0); 34272#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 34910#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34911#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35160#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35311#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34961#L794-39 assume 1 == ~t12_pc~0; 34657#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34651#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34744#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34745#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 34212#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34213#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35689#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35690#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35803#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35378#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35379#L1327-3 assume !(1 == ~T5_E~0); 34346#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34319#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34320#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35049#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35182#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35183#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35638#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35798#L1367-3 assume !(1 == ~E_1~0); 35789#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34139#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34140#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34768#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34769#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35488#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35756#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35148#L1407-3 assume !(1 == ~E_9~0); 34428#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 34429#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35063#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35064#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 34436#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34437#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34504#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 34505#L1787 assume !(0 == start_simulation_~tmp~3#1); 35151#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35698#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34413#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34158#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 34159#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34754#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34755#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 35665#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 34315#L1768-2 [2023-11-26 10:50:05,726 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:05,727 INFO L85 PathProgramCache]: Analyzing trace with hash -716096813, now seen corresponding path program 1 times [2023-11-26 10:50:05,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:05,727 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [93410162] [2023-11-26 10:50:05,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:05,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:05,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:05,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:05,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:05,784 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [93410162] [2023-11-26 10:50:05,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [93410162] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:05,784 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:05,785 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:05,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [570903589] [2023-11-26 10:50:05,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:05,785 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:05,786 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:05,786 INFO L85 PathProgramCache]: Analyzing trace with hash 762327613, now seen corresponding path program 1 times [2023-11-26 10:50:05,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:05,786 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753710696] [2023-11-26 10:50:05,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:05,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:05,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:05,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:05,858 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:05,859 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [753710696] [2023-11-26 10:50:05,859 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [753710696] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:05,859 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:05,859 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:05,859 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264238730] [2023-11-26 10:50:05,860 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:05,860 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:05,860 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:05,861 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:05,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:05,864 INFO L87 Difference]: Start difference. First operand 1701 states and 2508 transitions. cyclomatic complexity: 808 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:05,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:05,949 INFO L93 Difference]: Finished difference Result 1701 states and 2507 transitions. [2023-11-26 10:50:05,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2507 transitions. [2023-11-26 10:50:05,963 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:05,985 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2507 transitions. [2023-11-26 10:50:05,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-26 10:50:05,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-26 10:50:05,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2507 transitions. [2023-11-26 10:50:05,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:05,991 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2507 transitions. [2023-11-26 10:50:05,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2507 transitions. [2023-11-26 10:50:06,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-26 10:50:06,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4738389182833627) internal successors, (2507), 1700 states have internal predecessors, (2507), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:06,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2507 transitions. [2023-11-26 10:50:06,057 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2507 transitions. [2023-11-26 10:50:06,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:06,058 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2507 transitions. [2023-11-26 10:50:06,058 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-26 10:50:06,059 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2507 transitions. [2023-11-26 10:50:06,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:06,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:06,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:06,073 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:06,073 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:06,073 INFO L748 eck$LassoCheckResult]: Stem: 37792#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 37793#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 38585#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38586#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38453#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 38454#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38547#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38848#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38981#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38982#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37768#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37769#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38913#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38351#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38352#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 38262#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 38263#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38656#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38007#L1174 assume !(0 == ~M_E~0); 38008#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37861#L1179-1 assume !(0 == ~T2_E~0); 37765#L1184-1 assume !(0 == ~T3_E~0); 37766#L1189-1 assume !(0 == ~T4_E~0); 37808#L1194-1 assume !(0 == ~T5_E~0); 37901#L1199-1 assume !(0 == ~T6_E~0); 38780#L1204-1 assume !(0 == ~T7_E~0); 38701#L1209-1 assume !(0 == ~T8_E~0); 38702#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39125#L1219-1 assume !(0 == ~T10_E~0); 39210#L1224-1 assume !(0 == ~T11_E~0); 38124#L1229-1 assume !(0 == ~T12_E~0); 37695#L1234-1 assume !(0 == ~E_1~0); 37696#L1239-1 assume !(0 == ~E_2~0); 37730#L1244-1 assume !(0 == ~E_3~0); 37731#L1249-1 assume !(0 == ~E_4~0); 38371#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 37625#L1259-1 assume !(0 == ~E_6~0); 37578#L1264-1 assume !(0 == ~E_7~0); 37579#L1269-1 assume !(0 == ~E_8~0); 39213#L1274-1 assume !(0 == ~E_9~0); 39153#L1279-1 assume !(0 == ~E_10~0); 37812#L1284-1 assume !(0 == ~E_11~0); 37813#L1289-1 assume !(0 == ~E_12~0); 38423#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38424#L566 assume 1 == ~m_pc~0; 37595#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 37596#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38467#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38468#L1455 assume !(0 != activate_threads_~tmp~1#1); 38034#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38035#L585 assume 1 == ~t1_pc~0; 37692#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37693#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38836#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38837#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 39181#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39177#L604 assume !(1 == ~t2_pc~0); 38742#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38743#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37982#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37983#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38943#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38944#L623 assume 1 == ~t3_pc~0; 38208#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37554#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38814#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38815#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 38975#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37592#L642 assume !(1 == ~t4_pc~0); 37593#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 38045#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37650#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37651#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 37669#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38755#L661 assume 1 == ~t5_pc~0; 37825#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37826#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38673#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39040#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 38789#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38790#L680 assume !(1 == ~t6_pc~0); 38241#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38242#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37968#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37969#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 39050#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39175#L699 assume 1 == ~t7_pc~0; 38636#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38637#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38869#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38529#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 38530#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38425#L718 assume !(1 == ~t8_pc~0); 38426#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 37806#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37807#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37841#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 37842#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37974#L737 assume 1 == ~t9_pc~0; 38827#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38105#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38014#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38015#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 38282#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38283#L756 assume 1 == ~t10_pc~0; 38859#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38520#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38775#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38460#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 38084#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38085#L775 assume !(1 == ~t11_pc~0); 38343#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 38344#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39118#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37740#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 37741#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37922#L794 assume 1 == ~t12_pc~0; 37764#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37743#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37600#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37601#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 37889#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38355#L1307 assume !(1 == ~M_E~0); 38356#L1307-2 assume !(1 == ~T1_E~0); 38464#L1312-1 assume !(1 == ~T2_E~0); 38384#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38385#L1322-1 assume !(1 == ~T4_E~0); 38095#L1327-1 assume !(1 == ~T5_E~0); 38096#L1332-1 assume !(1 == ~T6_E~0); 38641#L1337-1 assume !(1 == ~T7_E~0); 38598#L1342-1 assume !(1 == ~T8_E~0); 38599#L1347-1 assume !(1 == ~T9_E~0); 39011#L1352-1 assume !(1 == ~T10_E~0); 38870#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38260#L1362-1 assume !(1 == ~T12_E~0); 38261#L1367-1 assume !(1 == ~E_1~0); 37902#L1372-1 assume !(1 == ~E_2~0); 37903#L1377-1 assume !(1 == ~E_3~0); 38193#L1382-1 assume !(1 == ~E_4~0); 38194#L1387-1 assume !(1 == ~E_5~0); 38744#L1392-1 assume !(1 == ~E_6~0); 38213#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38214#L1402-1 assume !(1 == ~E_8~0); 37917#L1407-1 assume !(1 == ~E_9~0); 37918#L1412-1 assume !(1 == ~E_10~0); 38936#L1417-1 assume !(1 == ~E_11~0); 38937#L1422-1 assume !(1 == ~E_12~0); 39171#L1427-1 assume { :end_inline_reset_delta_events } true; 37724#L1768-2 [2023-11-26 10:50:06,075 INFO L750 eck$LassoCheckResult]: Loop: 37724#L1768-2 assume !false; 37725#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38388#L1149-1 assume !false; 38768#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38993#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 38102#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38918#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38988#L976 assume !(0 != eval_~tmp~0#1); 38416#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38145#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38146#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38946#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38684#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38685#L1184-3 assume !(0 == ~T3_E~0); 38871#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38515#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37881#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37882#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38115#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37538#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37539#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38295#L1224-3 assume !(0 == ~T11_E~0); 38296#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38310#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37734#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37735#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38170#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38628#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39121#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38727#L1264-3 assume !(0 == ~E_7~0); 37738#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37739#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39151#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38291#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38292#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 38279#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37958#L566-39 assume 1 == ~m_pc~0; 37959#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38558#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38559#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38611#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38802#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38803#L585-39 assume 1 == ~t1_pc~0; 38932#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37967#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38167#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39115#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38840#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38535#L604-39 assume 1 == ~t2_pc~0; 38536#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38174#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38175#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38354#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38592#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38156#L623-39 assume 1 == ~t3_pc~0; 37557#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37558#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38820#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38009#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38010#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38762#L642-39 assume 1 == ~t4_pc~0; 38347#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38348#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38510#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38511#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38992#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37930#L661-39 assume !(1 == ~t5_pc~0); 37560#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 37561#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38542#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38543#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38822#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38823#L680-39 assume !(1 == ~t6_pc~0); 37632#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 37631#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39071#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38082#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 38083#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39127#L699-39 assume 1 == ~t7_pc~0; 38517#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38244#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38245#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38826#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39065#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39064#L718-39 assume 1 == ~t8_pc~0; 38429#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38430#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38922#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38923#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 38672#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38649#L737-39 assume !(1 == ~t9_pc~0); 38065#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 38064#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37657#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37658#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39039#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38976#L756-39 assume 1 == ~t10_pc~0; 38977#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38444#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39114#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38328#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38329#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37679#L775-39 assume 1 == ~t11_pc~0; 37680#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38319#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38320#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38569#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38720#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38370#L794-39 assume 1 == ~t12_pc~0; 38066#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38060#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38151#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38152#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37621#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37622#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39098#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39099#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39212#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38787#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38788#L1327-3 assume !(1 == ~T5_E~0); 37753#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37728#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37729#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38458#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38590#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38591#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39047#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39207#L1367-3 assume !(1 == ~E_1~0); 39198#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37548#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37549#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38177#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38178#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38897#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39165#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38557#L1407-3 assume !(1 == ~E_9~0); 37837#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37838#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 38471#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38472#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37845#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37846#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37913#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 37914#L1787 assume !(0 == start_simulation_~tmp~3#1); 38560#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 39107#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37822#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37567#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 37568#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38163#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38164#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 39074#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 37724#L1768-2 [2023-11-26 10:50:06,076 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:06,076 INFO L85 PathProgramCache]: Analyzing trace with hash -1079563311, now seen corresponding path program 1 times [2023-11-26 10:50:06,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:06,077 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223989648] [2023-11-26 10:50:06,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:06,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:06,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:06,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:06,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:06,159 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1223989648] [2023-11-26 10:50:06,159 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1223989648] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:06,159 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:06,159 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:06,161 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206167375] [2023-11-26 10:50:06,161 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:06,161 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:06,162 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:06,162 INFO L85 PathProgramCache]: Analyzing trace with hash 136545628, now seen corresponding path program 1 times [2023-11-26 10:50:06,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:06,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308276788] [2023-11-26 10:50:06,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:06,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:06,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:06,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:06,256 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:06,256 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308276788] [2023-11-26 10:50:06,257 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308276788] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:06,257 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:06,257 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:06,257 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1770209839] [2023-11-26 10:50:06,257 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:06,258 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:06,258 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:06,258 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:06,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:06,259 INFO L87 Difference]: Start difference. First operand 1701 states and 2507 transitions. cyclomatic complexity: 807 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:06,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:06,306 INFO L93 Difference]: Finished difference Result 1701 states and 2506 transitions. [2023-11-26 10:50:06,306 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2506 transitions. [2023-11-26 10:50:06,317 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:06,328 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2506 transitions. [2023-11-26 10:50:06,328 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-26 10:50:06,330 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-26 10:50:06,331 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2506 transitions. [2023-11-26 10:50:06,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:06,333 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2506 transitions. [2023-11-26 10:50:06,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2506 transitions. [2023-11-26 10:50:06,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-26 10:50:06,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4732510288065843) internal successors, (2506), 1700 states have internal predecessors, (2506), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:06,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2506 transitions. [2023-11-26 10:50:06,373 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2506 transitions. [2023-11-26 10:50:06,373 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:06,374 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2506 transitions. [2023-11-26 10:50:06,374 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-26 10:50:06,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2506 transitions. [2023-11-26 10:50:06,382 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:06,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:06,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:06,386 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:06,386 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:06,386 INFO L748 eck$LassoCheckResult]: Stem: 41201#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 41202#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 41994#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41995#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41862#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 41863#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41956#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42255#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42390#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42391#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41177#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41178#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42322#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41760#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41761#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41671#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 41672#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 42065#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41416#L1174 assume !(0 == ~M_E~0); 41417#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41268#L1179-1 assume !(0 == ~T2_E~0); 41174#L1184-1 assume !(0 == ~T3_E~0); 41175#L1189-1 assume !(0 == ~T4_E~0); 41217#L1194-1 assume !(0 == ~T5_E~0); 41310#L1199-1 assume !(0 == ~T6_E~0); 42189#L1204-1 assume !(0 == ~T7_E~0); 42110#L1209-1 assume !(0 == ~T8_E~0); 42111#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42534#L1219-1 assume !(0 == ~T10_E~0); 42619#L1224-1 assume !(0 == ~T11_E~0); 41533#L1229-1 assume !(0 == ~T12_E~0); 41104#L1234-1 assume !(0 == ~E_1~0); 41105#L1239-1 assume !(0 == ~E_2~0); 41137#L1244-1 assume !(0 == ~E_3~0); 41138#L1249-1 assume !(0 == ~E_4~0); 41780#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 41034#L1259-1 assume !(0 == ~E_6~0); 40987#L1264-1 assume !(0 == ~E_7~0); 40988#L1269-1 assume !(0 == ~E_8~0); 42622#L1274-1 assume !(0 == ~E_9~0); 42561#L1279-1 assume !(0 == ~E_10~0); 41221#L1284-1 assume !(0 == ~E_11~0); 41222#L1289-1 assume !(0 == ~E_12~0); 41832#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41833#L566 assume 1 == ~m_pc~0; 41004#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 41005#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41876#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41877#L1455 assume !(0 != activate_threads_~tmp~1#1); 41443#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41444#L585 assume 1 == ~t1_pc~0; 41101#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41102#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42245#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42246#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 42590#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42586#L604 assume !(1 == ~t2_pc~0); 42151#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42152#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41386#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41387#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42350#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42351#L623 assume 1 == ~t3_pc~0; 41617#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40963#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42220#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42221#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 42384#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41001#L642 assume !(1 == ~t4_pc~0); 41002#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41454#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41056#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41057#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 41078#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42164#L661 assume 1 == ~t5_pc~0; 41234#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41235#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42082#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42449#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 42196#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42197#L680 assume !(1 == ~t6_pc~0); 41650#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41651#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41377#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41378#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 42459#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42583#L699 assume 1 == ~t7_pc~0; 42045#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42046#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42278#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41938#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 41939#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41834#L718 assume !(1 == ~t8_pc~0); 41835#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 41215#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41216#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41250#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 41251#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41383#L737 assume 1 == ~t9_pc~0; 42234#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41514#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41423#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41424#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 41691#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41692#L756 assume 1 == ~t10_pc~0; 42268#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41929#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42184#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41869#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 41493#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41494#L775 assume !(1 == ~t11_pc~0); 41752#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 41753#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42527#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41149#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41150#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41331#L794 assume 1 == ~t12_pc~0; 41172#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 41152#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41007#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41008#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 41296#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41764#L1307 assume !(1 == ~M_E~0); 41765#L1307-2 assume !(1 == ~T1_E~0); 41873#L1312-1 assume !(1 == ~T2_E~0); 41793#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41794#L1322-1 assume !(1 == ~T4_E~0); 41504#L1327-1 assume !(1 == ~T5_E~0); 41505#L1332-1 assume !(1 == ~T6_E~0); 42050#L1337-1 assume !(1 == ~T7_E~0); 42007#L1342-1 assume !(1 == ~T8_E~0); 42008#L1347-1 assume !(1 == ~T9_E~0); 42420#L1352-1 assume !(1 == ~T10_E~0); 42279#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41669#L1362-1 assume !(1 == ~T12_E~0); 41670#L1367-1 assume !(1 == ~E_1~0); 41311#L1372-1 assume !(1 == ~E_2~0); 41312#L1377-1 assume !(1 == ~E_3~0); 41602#L1382-1 assume !(1 == ~E_4~0); 41603#L1387-1 assume !(1 == ~E_5~0); 42153#L1392-1 assume !(1 == ~E_6~0); 41620#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 41621#L1402-1 assume !(1 == ~E_8~0); 41326#L1407-1 assume !(1 == ~E_9~0); 41327#L1412-1 assume !(1 == ~E_10~0); 42345#L1417-1 assume !(1 == ~E_11~0); 42346#L1422-1 assume !(1 == ~E_12~0); 42580#L1427-1 assume { :end_inline_reset_delta_events } true; 41133#L1768-2 [2023-11-26 10:50:06,387 INFO L750 eck$LassoCheckResult]: Loop: 41133#L1768-2 assume !false; 41134#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41797#L1149-1 assume !false; 42175#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42402#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41511#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 42327#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42397#L976 assume !(0 != eval_~tmp~0#1); 41825#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41554#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41555#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42355#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42093#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42094#L1184-3 assume !(0 == ~T3_E~0); 42280#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41924#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41287#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41288#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41524#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40947#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40948#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41704#L1224-3 assume !(0 == ~T11_E~0); 41705#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41719#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41143#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41144#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41579#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42037#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42530#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42136#L1264-3 assume !(0 == ~E_7~0); 41147#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41148#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42560#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41700#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41701#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 41688#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41367#L566-39 assume 1 == ~m_pc~0; 41368#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 41967#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41968#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42020#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42211#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42212#L585-39 assume 1 == ~t1_pc~0; 42341#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41376#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41576#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42524#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42249#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41944#L604-39 assume 1 == ~t2_pc~0; 41945#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41583#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41584#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41763#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41997#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41565#L623-39 assume 1 == ~t3_pc~0; 40964#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40965#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42229#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41418#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41419#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42171#L642-39 assume 1 == ~t4_pc~0; 41754#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41755#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41919#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41920#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42401#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41337#L661-39 assume 1 == ~t5_pc~0; 41338#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40973#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41951#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41952#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42231#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42232#L680-39 assume !(1 == ~t6_pc~0); 41041#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 41040#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42480#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41491#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 41492#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42536#L699-39 assume 1 == ~t7_pc~0; 41926#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41653#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41654#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42236#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42476#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42473#L718-39 assume !(1 == ~t8_pc~0); 41840#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 41839#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42332#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42333#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 42081#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 42058#L737-39 assume 1 == ~t9_pc~0; 41472#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41473#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41067#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41068#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42448#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42385#L756-39 assume 1 == ~t10_pc~0; 42386#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41853#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42523#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41737#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41738#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41088#L775-39 assume 1 == ~t11_pc~0; 41089#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41728#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41729#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41978#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42129#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41779#L794-39 assume 1 == ~t12_pc~0; 41475#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 41469#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41562#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41563#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41030#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41031#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42507#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42508#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42621#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42198#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42199#L1327-3 assume !(1 == ~T5_E~0); 41164#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41139#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41140#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41867#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42000#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42001#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42456#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42616#L1367-3 assume !(1 == ~E_1~0); 42607#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40960#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40961#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41586#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41587#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42306#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42574#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41966#L1407-3 assume !(1 == ~E_9~0); 41246#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41247#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41881#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41882#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 41254#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41255#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41322#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 41323#L1787 assume !(0 == start_simulation_~tmp~3#1); 41970#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42516#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41231#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40979#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 40980#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41572#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41573#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 42483#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 41133#L1768-2 [2023-11-26 10:50:06,388 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:06,389 INFO L85 PathProgramCache]: Analyzing trace with hash -1368382701, now seen corresponding path program 1 times [2023-11-26 10:50:06,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:06,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437047993] [2023-11-26 10:50:06,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:06,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:06,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:06,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:06,465 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:06,465 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437047993] [2023-11-26 10:50:06,465 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437047993] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:06,465 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:06,466 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:50:06,466 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1939075819] [2023-11-26 10:50:06,466 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:06,467 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:06,467 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:06,468 INFO L85 PathProgramCache]: Analyzing trace with hash -767287619, now seen corresponding path program 1 times [2023-11-26 10:50:06,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:06,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66492321] [2023-11-26 10:50:06,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:06,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:06,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:06,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:06,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:06,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [66492321] [2023-11-26 10:50:06,544 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [66492321] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:06,545 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:06,545 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:06,545 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [683539857] [2023-11-26 10:50:06,545 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:06,546 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:06,546 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:06,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:06,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:06,547 INFO L87 Difference]: Start difference. First operand 1701 states and 2506 transitions. cyclomatic complexity: 806 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:06,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:06,620 INFO L93 Difference]: Finished difference Result 1701 states and 2501 transitions. [2023-11-26 10:50:06,620 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2501 transitions. [2023-11-26 10:50:06,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:06,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2501 transitions. [2023-11-26 10:50:06,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2023-11-26 10:50:06,645 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2023-11-26 10:50:06,645 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2501 transitions. [2023-11-26 10:50:06,648 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:06,648 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2501 transitions. [2023-11-26 10:50:06,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2501 transitions. [2023-11-26 10:50:06,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2023-11-26 10:50:06,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4703115814226926) internal successors, (2501), 1700 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:06,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2501 transitions. [2023-11-26 10:50:06,708 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2501 transitions. [2023-11-26 10:50:06,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:06,709 INFO L428 stractBuchiCegarLoop]: Abstraction has 1701 states and 2501 transitions. [2023-11-26 10:50:06,710 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-26 10:50:06,710 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2501 transitions. [2023-11-26 10:50:06,719 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2023-11-26 10:50:06,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:06,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:06,722 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:06,722 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:06,723 INFO L748 eck$LassoCheckResult]: Stem: 44610#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 44611#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 45403#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45404#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45271#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 45272#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45365#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45664#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45799#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45800#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44586#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44587#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45731#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45169#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45170#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45080#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45081#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 45474#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44825#L1174 assume !(0 == ~M_E~0); 44826#L1174-2 assume !(0 == ~T1_E~0); 44677#L1179-1 assume !(0 == ~T2_E~0); 44583#L1184-1 assume !(0 == ~T3_E~0); 44584#L1189-1 assume !(0 == ~T4_E~0); 44626#L1194-1 assume !(0 == ~T5_E~0); 44719#L1199-1 assume !(0 == ~T6_E~0); 45598#L1204-1 assume !(0 == ~T7_E~0); 45519#L1209-1 assume !(0 == ~T8_E~0); 45520#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45943#L1219-1 assume !(0 == ~T10_E~0); 46028#L1224-1 assume !(0 == ~T11_E~0); 44942#L1229-1 assume !(0 == ~T12_E~0); 44513#L1234-1 assume !(0 == ~E_1~0); 44514#L1239-1 assume !(0 == ~E_2~0); 44546#L1244-1 assume !(0 == ~E_3~0); 44547#L1249-1 assume !(0 == ~E_4~0); 45189#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 44443#L1259-1 assume !(0 == ~E_6~0); 44396#L1264-1 assume !(0 == ~E_7~0); 44397#L1269-1 assume !(0 == ~E_8~0); 46031#L1274-1 assume !(0 == ~E_9~0); 45970#L1279-1 assume !(0 == ~E_10~0); 44630#L1284-1 assume !(0 == ~E_11~0); 44631#L1289-1 assume !(0 == ~E_12~0); 45241#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45242#L566 assume 1 == ~m_pc~0; 44413#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 44414#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45285#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45286#L1455 assume !(0 != activate_threads_~tmp~1#1); 44852#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44853#L585 assume 1 == ~t1_pc~0; 44510#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44511#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45654#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45655#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 45999#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45995#L604 assume !(1 == ~t2_pc~0); 45560#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45561#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44795#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44796#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45759#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45760#L623 assume 1 == ~t3_pc~0; 45026#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44372#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45629#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45630#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 45793#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44410#L642 assume !(1 == ~t4_pc~0); 44411#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44863#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44465#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44466#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 44487#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45573#L661 assume 1 == ~t5_pc~0; 44643#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44644#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45491#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45858#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 45605#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45606#L680 assume !(1 == ~t6_pc~0); 45059#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 45060#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44786#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44787#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 45868#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45992#L699 assume 1 == ~t7_pc~0; 45454#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45455#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45687#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45347#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 45348#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45243#L718 assume !(1 == ~t8_pc~0); 45244#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44624#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44625#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44659#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 44660#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44792#L737 assume 1 == ~t9_pc~0; 45643#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44923#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44832#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44833#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 45100#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45101#L756 assume 1 == ~t10_pc~0; 45677#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45338#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45593#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45278#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 44902#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44903#L775 assume !(1 == ~t11_pc~0); 45161#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 45162#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45936#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44558#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44559#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44740#L794 assume 1 == ~t12_pc~0; 44581#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44561#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44416#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44417#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 44705#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45173#L1307 assume !(1 == ~M_E~0); 45174#L1307-2 assume !(1 == ~T1_E~0); 45282#L1312-1 assume !(1 == ~T2_E~0); 45202#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45203#L1322-1 assume !(1 == ~T4_E~0); 44913#L1327-1 assume !(1 == ~T5_E~0); 44914#L1332-1 assume !(1 == ~T6_E~0); 45459#L1337-1 assume !(1 == ~T7_E~0); 45416#L1342-1 assume !(1 == ~T8_E~0); 45417#L1347-1 assume !(1 == ~T9_E~0); 45829#L1352-1 assume !(1 == ~T10_E~0); 45688#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45078#L1362-1 assume !(1 == ~T12_E~0); 45079#L1367-1 assume !(1 == ~E_1~0); 44720#L1372-1 assume !(1 == ~E_2~0); 44721#L1377-1 assume !(1 == ~E_3~0); 45011#L1382-1 assume !(1 == ~E_4~0); 45012#L1387-1 assume !(1 == ~E_5~0); 45562#L1392-1 assume !(1 == ~E_6~0); 45029#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 45030#L1402-1 assume !(1 == ~E_8~0); 44735#L1407-1 assume !(1 == ~E_9~0); 44736#L1412-1 assume !(1 == ~E_10~0); 45754#L1417-1 assume !(1 == ~E_11~0); 45755#L1422-1 assume !(1 == ~E_12~0); 45989#L1427-1 assume { :end_inline_reset_delta_events } true; 44542#L1768-2 [2023-11-26 10:50:06,724 INFO L750 eck$LassoCheckResult]: Loop: 44542#L1768-2 assume !false; 44543#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45206#L1149-1 assume !false; 45584#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45811#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44920#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 45736#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 45806#L976 assume !(0 != eval_~tmp~0#1); 45234#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44963#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44964#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45764#L1174-5 assume !(0 == ~T1_E~0); 45502#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45503#L1184-3 assume !(0 == ~T3_E~0); 45689#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45333#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44696#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44697#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44933#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44356#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44357#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 45113#L1224-3 assume !(0 == ~T11_E~0); 45114#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45128#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44552#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44553#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44988#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 45446#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45939#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45545#L1264-3 assume !(0 == ~E_7~0); 44556#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44557#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45969#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45109#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 45110#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 45097#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44776#L566-39 assume 1 == ~m_pc~0; 44777#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 45376#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45377#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45429#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45620#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45621#L585-39 assume !(1 == ~t1_pc~0); 44784#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 44785#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44985#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45933#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45658#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45353#L604-39 assume 1 == ~t2_pc~0; 45354#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44992#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44993#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45172#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45406#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44974#L623-39 assume 1 == ~t3_pc~0; 44373#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44374#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45638#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44827#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44828#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45580#L642-39 assume 1 == ~t4_pc~0; 45163#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45164#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45328#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45329#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45810#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44746#L661-39 assume 1 == ~t5_pc~0; 44747#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44382#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45360#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45361#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45640#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45641#L680-39 assume 1 == ~t6_pc~0; 44448#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44449#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45889#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44900#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 44901#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45945#L699-39 assume 1 == ~t7_pc~0; 45335#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45062#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45063#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45645#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45885#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45882#L718-39 assume !(1 == ~t8_pc~0); 45249#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 45248#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45741#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45742#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45490#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45467#L737-39 assume 1 == ~t9_pc~0; 44881#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44882#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44476#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44477#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45857#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45794#L756-39 assume 1 == ~t10_pc~0; 45795#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45262#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45932#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45146#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45147#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44497#L775-39 assume 1 == ~t11_pc~0; 44498#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45137#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45138#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45387#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 45538#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45188#L794-39 assume 1 == ~t12_pc~0; 44884#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44878#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44971#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44972#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44439#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44440#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 45916#L1307-5 assume !(1 == ~T1_E~0); 45917#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46030#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45607#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45608#L1327-3 assume !(1 == ~T5_E~0); 44573#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44548#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44549#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45276#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45409#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 45410#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45865#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46025#L1367-3 assume !(1 == ~E_1~0); 46016#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44369#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44370#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44995#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44996#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 45715#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45983#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45375#L1407-3 assume !(1 == ~E_9~0); 44655#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44656#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45290#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 45291#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44663#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44664#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44731#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 44732#L1787 assume !(0 == start_simulation_~tmp~3#1); 45379#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45925#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44640#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44388#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 44389#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44981#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44982#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 45892#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 44542#L1768-2 [2023-11-26 10:50:06,725 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:06,725 INFO L85 PathProgramCache]: Analyzing trace with hash 1978532629, now seen corresponding path program 1 times [2023-11-26 10:50:06,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:06,726 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2131747470] [2023-11-26 10:50:06,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:06,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:06,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:06,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:06,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:06,825 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2131747470] [2023-11-26 10:50:06,825 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2131747470] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:06,826 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:06,826 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:06,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [466376055] [2023-11-26 10:50:06,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:06,828 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:06,829 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:06,829 INFO L85 PathProgramCache]: Analyzing trace with hash -1118727551, now seen corresponding path program 1 times [2023-11-26 10:50:06,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:06,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116308604] [2023-11-26 10:50:06,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:06,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:06,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:06,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:06,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:06,899 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [116308604] [2023-11-26 10:50:06,899 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [116308604] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:06,899 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:06,900 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:06,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [331829767] [2023-11-26 10:50:06,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:06,901 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:06,901 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:06,902 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:50:06,902 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:50:06,902 INFO L87 Difference]: Start difference. First operand 1701 states and 2501 transitions. cyclomatic complexity: 801 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:07,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:07,136 INFO L93 Difference]: Finished difference Result 3264 states and 4792 transitions. [2023-11-26 10:50:07,136 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3264 states and 4792 transitions. [2023-11-26 10:50:07,158 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3080 [2023-11-26 10:50:07,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3264 states to 3264 states and 4792 transitions. [2023-11-26 10:50:07,187 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3264 [2023-11-26 10:50:07,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3264 [2023-11-26 10:50:07,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3264 states and 4792 transitions. [2023-11-26 10:50:07,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:07,197 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3264 states and 4792 transitions. [2023-11-26 10:50:07,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3264 states and 4792 transitions. [2023-11-26 10:50:07,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3264 to 3264. [2023-11-26 10:50:07,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3264 states, 3264 states have (on average 1.4681372549019607) internal successors, (4792), 3263 states have internal predecessors, (4792), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:07,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3264 states to 3264 states and 4792 transitions. [2023-11-26 10:50:07,285 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3264 states and 4792 transitions. [2023-11-26 10:50:07,285 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:50:07,286 INFO L428 stractBuchiCegarLoop]: Abstraction has 3264 states and 4792 transitions. [2023-11-26 10:50:07,286 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-26 10:50:07,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3264 states and 4792 transitions. [2023-11-26 10:50:07,302 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3080 [2023-11-26 10:50:07,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:07,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:07,306 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:07,306 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:07,306 INFO L748 eck$LassoCheckResult]: Stem: 49587#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 49588#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 50398#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50399#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50259#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 50260#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50358#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50669#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50824#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50825#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49563#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49564#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50746#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50154#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50155#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50064#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 50065#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50473#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49802#L1174 assume !(0 == ~M_E~0); 49803#L1174-2 assume !(0 == ~T1_E~0); 49654#L1179-1 assume !(0 == ~T2_E~0); 49560#L1184-1 assume !(0 == ~T3_E~0); 49561#L1189-1 assume !(0 == ~T4_E~0); 49603#L1194-1 assume !(0 == ~T5_E~0); 49696#L1199-1 assume !(0 == ~T6_E~0); 50601#L1204-1 assume !(0 == ~T7_E~0); 50518#L1209-1 assume !(0 == ~T8_E~0); 50519#L1214-1 assume !(0 == ~T9_E~0); 50993#L1219-1 assume !(0 == ~T10_E~0); 51129#L1224-1 assume !(0 == ~T11_E~0); 49921#L1229-1 assume !(0 == ~T12_E~0); 49489#L1234-1 assume !(0 == ~E_1~0); 49490#L1239-1 assume !(0 == ~E_2~0); 49522#L1244-1 assume !(0 == ~E_3~0); 49523#L1249-1 assume !(0 == ~E_4~0); 50175#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 49419#L1259-1 assume !(0 == ~E_6~0); 49371#L1264-1 assume !(0 == ~E_7~0); 49372#L1269-1 assume !(0 == ~E_8~0); 51139#L1274-1 assume !(0 == ~E_9~0); 51037#L1279-1 assume !(0 == ~E_10~0); 49607#L1284-1 assume !(0 == ~E_11~0); 49608#L1289-1 assume !(0 == ~E_12~0); 50229#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50230#L566 assume 1 == ~m_pc~0; 49388#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49389#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50274#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50275#L1455 assume !(0 != activate_threads_~tmp~1#1); 49829#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49830#L585 assume 1 == ~t1_pc~0; 49486#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49487#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50659#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50660#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 51080#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51073#L604 assume !(1 == ~t2_pc~0); 50559#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 50560#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49772#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49773#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50781#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50782#L623 assume 1 == ~t3_pc~0; 50009#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49347#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50634#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50635#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 50818#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49385#L642 assume !(1 == ~t4_pc~0); 49386#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49840#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49441#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49442#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 49463#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50573#L661 assume 1 == ~t5_pc~0; 49620#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49621#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50490#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50888#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 50609#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50610#L680 assume !(1 == ~t6_pc~0); 50043#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50044#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49763#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49764#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 50900#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51070#L699 assume 1 == ~t7_pc~0; 50450#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50451#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50694#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50340#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 50341#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50231#L718 assume !(1 == ~t8_pc~0); 50232#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49601#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49602#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49636#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 49637#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49769#L737 assume 1 == ~t9_pc~0; 50648#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49902#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49809#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49810#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 50084#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50085#L756 assume 1 == ~t10_pc~0; 50682#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50331#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50596#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50267#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 49880#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49881#L775 assume !(1 == ~t11_pc~0); 50146#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 50147#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50984#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49534#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 49535#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49717#L794 assume 1 == ~t12_pc~0; 49559#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 49537#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49394#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49395#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 49682#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50158#L1307 assume !(1 == ~M_E~0); 50159#L1307-2 assume !(1 == ~T1_E~0); 50271#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51094#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51386#L1322-1 assume !(1 == ~T4_E~0); 51385#L1327-1 assume !(1 == ~T5_E~0); 50455#L1332-1 assume !(1 == ~T6_E~0); 50456#L1337-1 assume !(1 == ~T7_E~0); 51384#L1342-1 assume !(1 == ~T8_E~0); 51034#L1347-1 assume !(1 == ~T9_E~0); 51035#L1352-1 assume !(1 == ~T10_E~0); 50695#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50062#L1362-1 assume !(1 == ~T12_E~0); 50063#L1367-1 assume !(1 == ~E_1~0); 51382#L1372-1 assume !(1 == ~E_2~0); 51381#L1377-1 assume !(1 == ~E_3~0); 51380#L1382-1 assume !(1 == ~E_4~0); 50561#L1387-1 assume !(1 == ~E_5~0); 50562#L1392-1 assume !(1 == ~E_6~0); 50012#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 50013#L1402-1 assume !(1 == ~E_8~0); 49712#L1407-1 assume !(1 == ~E_9~0); 49713#L1412-1 assume !(1 == ~E_10~0); 51115#L1417-1 assume !(1 == ~E_11~0); 51196#L1422-1 assume !(1 == ~E_12~0); 51189#L1427-1 assume { :end_inline_reset_delta_events } true; 51183#L1768-2 [2023-11-26 10:50:07,307 INFO L750 eck$LassoCheckResult]: Loop: 51183#L1768-2 assume !false; 51178#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51174#L1149-1 assume !false; 51173#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 51165#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51159#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51158#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 51157#L976 assume !(0 != eval_~tmp~0#1); 51156#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51155#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51154#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51153#L1174-5 assume !(0 == ~T1_E~0); 51151#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51152#L1184-3 assume !(0 == ~T3_E~0); 51776#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51775#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51774#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51773#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 51772#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51771#L1214-3 assume !(0 == ~T9_E~0); 51770#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51769#L1224-3 assume !(0 == ~T11_E~0); 51768#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51767#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 51766#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51765#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51764#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51763#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51762#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51761#L1264-3 assume !(0 == ~E_7~0); 51760#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 51759#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 51758#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51757#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51756#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 51755#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51754#L566-39 assume 1 == ~m_pc~0; 51752#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 51751#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51750#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51749#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51748#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51747#L585-39 assume !(1 == ~t1_pc~0); 51745#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 51744#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51743#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51742#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51741#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51740#L604-39 assume 1 == ~t2_pc~0; 51738#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51737#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51736#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51735#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51734#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51733#L623-39 assume !(1 == ~t3_pc~0); 51731#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 51730#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51729#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51728#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51727#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51726#L642-39 assume 1 == ~t4_pc~0; 51724#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51723#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51722#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51721#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51720#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51719#L661-39 assume !(1 == ~t5_pc~0); 51717#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 51716#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51715#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51714#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51713#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51712#L680-39 assume 1 == ~t6_pc~0; 51710#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 51709#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51708#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51707#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 51706#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51705#L699-39 assume 1 == ~t7_pc~0; 51703#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51702#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51701#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51700#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 51699#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50918#L718-39 assume !(1 == ~t8_pc~0); 50919#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 51692#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51691#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51690#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51689#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51688#L737-39 assume 1 == ~t9_pc~0; 51686#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51685#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51684#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51683#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51682#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51681#L756-39 assume 1 == ~t10_pc~0; 51680#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51678#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51677#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51676#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50310#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49473#L775-39 assume 1 == ~t11_pc~0; 49474#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51654#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51653#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51652#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 51651#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51650#L794-39 assume !(1 == ~t12_pc~0); 51648#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 51647#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51646#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50588#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 50589#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51024#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51025#L1307-5 assume !(1 == ~T1_E~0); 51644#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51138#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50611#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50612#L1327-3 assume !(1 == ~T5_E~0); 49549#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49550#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50264#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50265#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50404#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50405#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50897#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51122#L1367-3 assume !(1 == ~E_1~0); 51110#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49344#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49345#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49976#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49977#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50729#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51057#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50368#L1407-3 assume !(1 == ~E_9~0); 49632#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49633#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 50280#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50281#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 51550#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51544#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51543#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 51541#L1787 assume !(0 == start_simulation_~tmp~3#1); 51539#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 51538#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51525#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51524#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 51523#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51203#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51197#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 51190#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 51183#L1768-2 [2023-11-26 10:50:07,308 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:07,308 INFO L85 PathProgramCache]: Analyzing trace with hash -1694374055, now seen corresponding path program 1 times [2023-11-26 10:50:07,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:07,308 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984727844] [2023-11-26 10:50:07,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:07,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:07,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:07,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:07,398 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:07,398 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [984727844] [2023-11-26 10:50:07,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [984727844] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:07,398 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:07,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:07,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1055470846] [2023-11-26 10:50:07,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:07,399 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:07,400 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:07,400 INFO L85 PathProgramCache]: Analyzing trace with hash 1317325792, now seen corresponding path program 1 times [2023-11-26 10:50:07,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:07,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1479271704] [2023-11-26 10:50:07,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:07,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:07,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:07,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:07,489 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:07,489 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1479271704] [2023-11-26 10:50:07,489 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1479271704] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:07,489 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:07,489 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:07,490 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2086286204] [2023-11-26 10:50:07,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:07,490 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:07,490 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:07,491 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:50:07,491 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:50:07,491 INFO L87 Difference]: Start difference. First operand 3264 states and 4792 transitions. cyclomatic complexity: 1530 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:07,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:07,759 INFO L93 Difference]: Finished difference Result 6184 states and 9069 transitions. [2023-11-26 10:50:07,759 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6184 states and 9069 transitions. [2023-11-26 10:50:07,798 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5974 [2023-11-26 10:50:07,823 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6184 states to 6184 states and 9069 transitions. [2023-11-26 10:50:07,823 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6184 [2023-11-26 10:50:07,830 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6184 [2023-11-26 10:50:07,831 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6184 states and 9069 transitions. [2023-11-26 10:50:07,839 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:07,840 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6184 states and 9069 transitions. [2023-11-26 10:50:07,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6184 states and 9069 transitions. [2023-11-26 10:50:07,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6184 to 6182. [2023-11-26 10:50:07,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6182 states, 6182 states have (on average 1.4666774506632159) internal successors, (9067), 6181 states have internal predecessors, (9067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:07,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6182 states to 6182 states and 9067 transitions. [2023-11-26 10:50:07,972 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6182 states and 9067 transitions. [2023-11-26 10:50:07,973 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:50:07,973 INFO L428 stractBuchiCegarLoop]: Abstraction has 6182 states and 9067 transitions. [2023-11-26 10:50:07,973 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-26 10:50:07,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6182 states and 9067 transitions. [2023-11-26 10:50:08,002 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5974 [2023-11-26 10:50:08,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:08,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:08,005 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:08,006 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:08,006 INFO L748 eck$LassoCheckResult]: Stem: 59044#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 59045#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 59842#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59843#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59709#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 59710#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59803#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60110#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60256#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60257#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59020#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59021#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60182#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59607#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59608#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59517#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59518#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59914#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59259#L1174 assume !(0 == ~M_E~0); 59260#L1174-2 assume !(0 == ~T1_E~0); 59111#L1179-1 assume !(0 == ~T2_E~0); 59017#L1184-1 assume !(0 == ~T3_E~0); 59018#L1189-1 assume !(0 == ~T4_E~0); 59060#L1194-1 assume !(0 == ~T5_E~0); 59153#L1199-1 assume !(0 == ~T6_E~0); 60044#L1204-1 assume !(0 == ~T7_E~0); 59960#L1209-1 assume !(0 == ~T8_E~0); 59961#L1214-1 assume !(0 == ~T9_E~0); 60405#L1219-1 assume !(0 == ~T10_E~0); 60504#L1224-1 assume !(0 == ~T11_E~0); 59378#L1229-1 assume !(0 == ~T12_E~0); 58947#L1234-1 assume !(0 == ~E_1~0); 58948#L1239-1 assume !(0 == ~E_2~0); 58980#L1244-1 assume !(0 == ~E_3~0); 58981#L1249-1 assume !(0 == ~E_4~0); 59627#L1254-1 assume !(0 == ~E_5~0); 58877#L1259-1 assume !(0 == ~E_6~0); 58829#L1264-1 assume !(0 == ~E_7~0); 58830#L1269-1 assume !(0 == ~E_8~0); 60509#L1274-1 assume !(0 == ~E_9~0); 60437#L1279-1 assume !(0 == ~E_10~0); 59064#L1284-1 assume !(0 == ~E_11~0); 59065#L1289-1 assume !(0 == ~E_12~0); 59679#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59680#L566 assume 1 == ~m_pc~0; 58846#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58847#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59723#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59724#L1455 assume !(0 != activate_threads_~tmp~1#1); 59286#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59287#L585 assume 1 == ~t1_pc~0; 58944#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58945#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60100#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 60101#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 60467#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60463#L604 assume !(1 == ~t2_pc~0); 60004#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 60005#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59229#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59230#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60213#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60214#L623 assume 1 == ~t3_pc~0; 59462#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58805#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60075#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60076#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 60249#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58843#L642 assume !(1 == ~t4_pc~0); 58844#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 59299#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58899#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58900#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 58921#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60019#L661 assume 1 == ~t5_pc~0; 59077#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59078#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59932#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60316#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 60051#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60052#L680 assume !(1 == ~t6_pc~0); 59495#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 59496#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59220#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59221#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 60326#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60460#L699 assume 1 == ~t7_pc~0; 59894#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59895#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60134#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59785#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 59786#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59681#L718 assume !(1 == ~t8_pc~0); 59682#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 59058#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59059#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59093#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 59094#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59226#L737 assume 1 == ~t9_pc~0; 60089#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59359#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59266#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59267#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 59537#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59538#L756 assume 1 == ~t10_pc~0; 60124#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59776#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60039#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59716#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 59338#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59339#L775 assume !(1 == ~t11_pc~0); 59599#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 59600#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60397#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58992#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58993#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59174#L794 assume 1 == ~t12_pc~0; 59015#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58995#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58849#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58850#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 59139#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59611#L1307 assume !(1 == ~M_E~0); 59612#L1307-2 assume !(1 == ~T1_E~0); 59720#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59640#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59641#L1322-1 assume !(1 == ~T4_E~0); 59349#L1327-1 assume !(1 == ~T5_E~0); 59350#L1332-1 assume !(1 == ~T6_E~0); 59899#L1337-1 assume !(1 == ~T7_E~0); 59855#L1342-1 assume !(1 == ~T8_E~0); 59856#L1347-1 assume !(1 == ~T9_E~0); 60436#L1352-1 assume !(1 == ~T10_E~0); 61137#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59515#L1362-1 assume !(1 == ~T12_E~0); 59516#L1367-1 assume !(1 == ~E_1~0); 59154#L1372-1 assume !(1 == ~E_2~0); 59155#L1377-1 assume !(1 == ~E_3~0); 59447#L1382-1 assume !(1 == ~E_4~0); 59448#L1387-1 assume !(1 == ~E_5~0); 60608#L1392-1 assume !(1 == ~E_6~0); 60606#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 60604#L1402-1 assume !(1 == ~E_8~0); 60601#L1407-1 assume !(1 == ~E_9~0); 60587#L1412-1 assume !(1 == ~E_10~0); 60575#L1417-1 assume !(1 == ~E_11~0); 60565#L1422-1 assume !(1 == ~E_12~0); 60556#L1427-1 assume { :end_inline_reset_delta_events } true; 60549#L1768-2 [2023-11-26 10:50:08,007 INFO L750 eck$LassoCheckResult]: Loop: 60549#L1768-2 assume !false; 60543#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60539#L1149-1 assume !false; 60538#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60530#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60524#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60523#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 60521#L976 assume !(0 != eval_~tmp~0#1); 60520#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60519#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60518#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 60517#L1174-5 assume !(0 == ~T1_E~0); 60515#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60516#L1184-3 assume !(0 == ~T3_E~0); 62500#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62498#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62496#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62493#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 62491#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62490#L1214-3 assume !(0 == ~T9_E~0); 62489#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 62488#L1224-3 assume !(0 == ~T11_E~0); 62487#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 62485#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62483#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62481#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62479#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62477#L1254-3 assume !(0 == ~E_5~0); 62475#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62473#L1264-3 assume !(0 == ~E_7~0); 62471#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62469#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 62467#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 62465#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62463#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 62461#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62459#L566-39 assume 1 == ~m_pc~0; 62456#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 62455#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62454#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62453#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62452#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62451#L585-39 assume !(1 == ~t1_pc~0); 62448#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 62446#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62444#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 62441#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62439#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62437#L604-39 assume 1 == ~t2_pc~0; 62434#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62432#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62430#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62429#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62426#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62424#L623-39 assume !(1 == ~t3_pc~0); 62358#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 62351#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62347#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62341#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62336#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62331#L642-39 assume 1 == ~t4_pc~0; 62324#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62318#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62312#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62306#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62301#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62296#L661-39 assume !(1 == ~t5_pc~0); 62289#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 62283#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62277#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62271#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62266#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62261#L680-39 assume 1 == ~t6_pc~0; 62254#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62248#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62242#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62236#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 62231#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62226#L699-39 assume 1 == ~t7_pc~0; 62219#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62213#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62207#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62201#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 62196#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62191#L718-39 assume 1 == ~t8_pc~0; 62184#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 62178#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62172#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62166#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62161#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62156#L737-39 assume 1 == ~t9_pc~0; 62149#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62143#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62137#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62132#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 62058#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62055#L756-39 assume !(1 == ~t10_pc~0); 62052#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 62050#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62048#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62046#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 62044#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 62043#L775-39 assume 1 == ~t11_pc~0; 62039#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62037#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62035#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62033#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 62031#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62029#L794-39 assume !(1 == ~t12_pc~0); 61982#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 61973#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61965#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 61958#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61950#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61943#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 61928#L1307-5 assume !(1 == ~T1_E~0); 61920#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60508#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61907#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61900#L1327-3 assume !(1 == ~T5_E~0); 61892#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 61883#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 61874#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 61866#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60195#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 61851#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 61844#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 61836#L1367-3 assume !(1 == ~E_1~0); 61824#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 61814#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61807#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61798#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61789#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 61781#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 61772#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 61764#L1407-3 assume !(1 == ~E_9~0); 61759#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 61025#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 61023#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 61021#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60768#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60761#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60759#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 60757#L1787 assume !(0 == start_simulation_~tmp~3#1); 60755#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60621#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60607#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60605#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 60588#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60576#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60566#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 60557#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 60549#L1768-2 [2023-11-26 10:50:08,007 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:08,008 INFO L85 PathProgramCache]: Analyzing trace with hash 32770907, now seen corresponding path program 1 times [2023-11-26 10:50:08,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:08,008 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2001035045] [2023-11-26 10:50:08,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:08,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:08,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:08,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:08,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:08,075 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2001035045] [2023-11-26 10:50:08,075 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2001035045] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:08,075 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:08,075 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:50:08,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1151057852] [2023-11-26 10:50:08,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:08,076 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:08,077 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:08,077 INFO L85 PathProgramCache]: Analyzing trace with hash -1219333278, now seen corresponding path program 1 times [2023-11-26 10:50:08,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:08,077 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [996048552] [2023-11-26 10:50:08,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:08,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:08,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:08,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:08,144 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:08,144 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [996048552] [2023-11-26 10:50:08,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [996048552] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:08,145 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:08,145 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:08,145 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [739646414] [2023-11-26 10:50:08,145 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:08,146 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:08,146 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:08,146 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:08,146 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:08,147 INFO L87 Difference]: Start difference. First operand 6182 states and 9067 transitions. cyclomatic complexity: 2889 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:08,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:08,365 INFO L93 Difference]: Finished difference Result 12097 states and 17623 transitions. [2023-11-26 10:50:08,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12097 states and 17623 transitions. [2023-11-26 10:50:08,432 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11882 [2023-11-26 10:50:08,476 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12097 states to 12097 states and 17623 transitions. [2023-11-26 10:50:08,476 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12097 [2023-11-26 10:50:08,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12097 [2023-11-26 10:50:08,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12097 states and 17623 transitions. [2023-11-26 10:50:08,503 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:08,503 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12097 states and 17623 transitions. [2023-11-26 10:50:08,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12097 states and 17623 transitions. [2023-11-26 10:50:08,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12097 to 11729. [2023-11-26 10:50:08,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11729 states, 11729 states have (on average 1.4585216130957457) internal successors, (17107), 11728 states have internal predecessors, (17107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:08,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11729 states to 11729 states and 17107 transitions. [2023-11-26 10:50:08,731 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11729 states and 17107 transitions. [2023-11-26 10:50:08,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:08,733 INFO L428 stractBuchiCegarLoop]: Abstraction has 11729 states and 17107 transitions. [2023-11-26 10:50:08,733 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-26 10:50:08,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11729 states and 17107 transitions. [2023-11-26 10:50:08,841 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11514 [2023-11-26 10:50:08,842 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:08,842 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:08,845 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:08,845 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:08,846 INFO L748 eck$LassoCheckResult]: Stem: 77327#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 77328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 78139#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 78140#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 78002#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 78003#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 78097#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78425#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78573#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78574#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77303#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 77304#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 78493#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 77897#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77898#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77808#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 77809#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 78213#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77544#L1174 assume !(0 == ~M_E~0); 77545#L1174-2 assume !(0 == ~T1_E~0); 77398#L1179-1 assume !(0 == ~T2_E~0); 77301#L1184-1 assume !(0 == ~T3_E~0); 77302#L1189-1 assume !(0 == ~T4_E~0); 77345#L1194-1 assume !(0 == ~T5_E~0); 77441#L1199-1 assume !(0 == ~T6_E~0); 78349#L1204-1 assume !(0 == ~T7_E~0); 78260#L1209-1 assume !(0 == ~T8_E~0); 78261#L1214-1 assume !(0 == ~T9_E~0); 78740#L1219-1 assume !(0 == ~T10_E~0); 78886#L1224-1 assume !(0 == ~T11_E~0); 77665#L1229-1 assume !(0 == ~T12_E~0); 77230#L1234-1 assume !(0 == ~E_1~0); 77231#L1239-1 assume !(0 == ~E_2~0); 77265#L1244-1 assume !(0 == ~E_3~0); 77266#L1249-1 assume !(0 == ~E_4~0); 77918#L1254-1 assume !(0 == ~E_5~0); 77160#L1259-1 assume !(0 == ~E_6~0); 77115#L1264-1 assume !(0 == ~E_7~0); 77116#L1269-1 assume !(0 == ~E_8~0); 78898#L1274-1 assume !(0 == ~E_9~0); 78774#L1279-1 assume !(0 == ~E_10~0); 77349#L1284-1 assume !(0 == ~E_11~0); 77350#L1289-1 assume !(0 == ~E_12~0); 77972#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77973#L566 assume !(1 == ~m_pc~0); 78416#L566-2 is_master_triggered_~__retres1~0#1 := 0; 78417#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78017#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 78018#L1455 assume !(0 != activate_threads_~tmp~1#1); 77571#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77572#L585 assume 1 == ~t1_pc~0; 77227#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77228#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78408#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 78409#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 78820#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78815#L604 assume !(1 == ~t2_pc~0); 78306#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 78307#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77518#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77519#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78531#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78532#L623 assume 1 == ~t3_pc~0; 77752#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 77091#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78384#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78385#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 78565#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77129#L642 assume !(1 == ~t4_pc~0); 77130#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 77584#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77188#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77189#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 77204#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78321#L661 assume 1 == ~t5_pc~0; 77362#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77363#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78231#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78635#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 78359#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78360#L680 assume !(1 == ~t6_pc~0); 77785#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 77786#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77507#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77508#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 78646#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78813#L699 assume 1 == ~t7_pc~0; 78192#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 78193#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78444#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78079#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 78080#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77974#L718 assume !(1 == ~t8_pc~0); 77975#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 77343#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77344#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77380#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 77381#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77510#L737 assume 1 == ~t9_pc~0; 78399#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77647#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77551#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77552#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 77828#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77829#L756 assume 1 == ~t10_pc~0; 78434#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 78071#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78344#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78009#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 77623#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77624#L775 assume !(1 == ~t11_pc~0); 77889#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 77890#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 78732#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 77275#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 77276#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77460#L794 assume 1 == ~t12_pc~0; 77299#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 77278#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77135#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77136#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 77426#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77901#L1307 assume !(1 == ~M_E~0); 77902#L1307-2 assume !(1 == ~T1_E~0); 78014#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77931#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77932#L1322-1 assume !(1 == ~T4_E~0); 77635#L1327-1 assume !(1 == ~T5_E~0); 77636#L1332-1 assume !(1 == ~T6_E~0); 78197#L1337-1 assume !(1 == ~T7_E~0); 78152#L1342-1 assume !(1 == ~T8_E~0); 78153#L1347-1 assume !(1 == ~T9_E~0); 78605#L1352-1 assume !(1 == ~T10_E~0); 78445#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77804#L1362-1 assume !(1 == ~T12_E~0); 77805#L1367-1 assume !(1 == ~E_1~0); 86263#L1372-1 assume !(1 == ~E_2~0); 86260#L1377-1 assume !(1 == ~E_3~0); 86258#L1382-1 assume !(1 == ~E_4~0); 86254#L1387-1 assume !(1 == ~E_5~0); 86251#L1392-1 assume !(1 == ~E_6~0); 84669#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 84667#L1402-1 assume !(1 == ~E_8~0); 84665#L1407-1 assume !(1 == ~E_9~0); 84334#L1412-1 assume !(1 == ~E_10~0); 84320#L1417-1 assume !(1 == ~E_11~0); 84318#L1422-1 assume !(1 == ~E_12~0); 84310#L1427-1 assume { :end_inline_reset_delta_events } true; 84303#L1768-2 [2023-11-26 10:50:08,846 INFO L750 eck$LassoCheckResult]: Loop: 84303#L1768-2 assume !false; 84297#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 84293#L1149-1 assume !false; 84292#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 84284#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 84278#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 84277#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 84275#L976 assume !(0 != eval_~tmp~0#1); 84276#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 87697#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 87696#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 87695#L1174-5 assume !(0 == ~T1_E~0); 87693#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 87694#L1184-3 assume !(0 == ~T3_E~0); 87995#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 87993#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 87991#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 87988#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 87986#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 87984#L1214-3 assume !(0 == ~T9_E~0); 87982#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 87981#L1224-3 assume !(0 == ~T11_E~0); 87980#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 87979#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 87978#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 87421#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 87420#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 78841#L1254-3 assume !(0 == ~E_5~0); 78736#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 78291#L1264-3 assume !(0 == ~E_7~0); 77273#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 77274#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 78771#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 77837#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 77838#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 77825#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77492#L566-39 assume !(1 == ~m_pc~0); 77493#L566-41 is_master_triggered_~__retres1~0#1 := 0; 78108#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78109#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 78164#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 78372#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78373#L585-39 assume 1 == ~t1_pc~0; 78518#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77503#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77708#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 78728#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78412#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78085#L604-39 assume !(1 == ~t2_pc~0); 78087#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 77717#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77718#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77900#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78141#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77696#L623-39 assume 1 == ~t3_pc~0; 77092#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 77093#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78392#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77546#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77547#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78328#L642-39 assume 1 == ~t4_pc~0; 77891#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 77892#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78060#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78061#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78584#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77466#L661-39 assume 1 == ~t5_pc~0; 77467#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77101#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78092#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78093#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 78394#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78395#L680-39 assume 1 == ~t6_pc~0; 77165#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77166#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78674#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77621#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 77622#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78742#L699-39 assume 1 == ~t7_pc~0; 78067#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 77788#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77789#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78398#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 78670#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78667#L718-39 assume 1 == ~t8_pc~0; 77978#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 77979#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78506#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78507#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 78230#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78206#L737-39 assume 1 == ~t9_pc~0; 77602#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77603#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77193#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77194#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 78634#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78567#L756-39 assume !(1 == ~t10_pc~0); 77992#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 77993#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78727#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77874#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77875#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77214#L775-39 assume !(1 == ~t11_pc~0); 77216#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 77865#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77866#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78120#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 78284#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77917#L794-39 assume 1 == ~t12_pc~0; 77605#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 77599#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77693#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77694#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 77156#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77157#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 78709#L1307-5 assume !(1 == ~T1_E~0); 78710#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78897#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78357#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78358#L1327-3 assume !(1 == ~T5_E~0); 77290#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 77263#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77264#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78007#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78144#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78145#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78643#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 78878#L1367-3 assume !(1 == ~E_1~0); 78860#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77088#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77089#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77720#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77721#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86487#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 86252#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 86250#L1407-3 assume !(1 == ~E_9~0); 86249#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 86247#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 86246#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 86244#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 84655#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 84648#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 84646#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 84643#L1787 assume !(0 == start_simulation_~tmp~3#1); 84640#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 84333#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 84319#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 84317#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 84316#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 84315#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 84313#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 84311#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 84303#L1768-2 [2023-11-26 10:50:08,847 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:08,847 INFO L85 PathProgramCache]: Analyzing trace with hash -1204882182, now seen corresponding path program 1 times [2023-11-26 10:50:08,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:08,848 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1374911251] [2023-11-26 10:50:08,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:08,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:08,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:08,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:08,942 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:08,942 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1374911251] [2023-11-26 10:50:08,942 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1374911251] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:08,942 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:08,942 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:50:08,943 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1016462836] [2023-11-26 10:50:08,943 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:08,943 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:08,944 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:08,944 INFO L85 PathProgramCache]: Analyzing trace with hash 348182083, now seen corresponding path program 1 times [2023-11-26 10:50:08,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:08,944 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444140434] [2023-11-26 10:50:08,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:08,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:08,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:09,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:09,034 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:09,034 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [444140434] [2023-11-26 10:50:09,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [444140434] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:09,034 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:09,034 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:09,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [857327648] [2023-11-26 10:50:09,035 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:09,035 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:09,035 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:09,036 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:09,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:09,036 INFO L87 Difference]: Start difference. First operand 11729 states and 17107 transitions. cyclomatic complexity: 5386 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:09,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:09,285 INFO L93 Difference]: Finished difference Result 22406 states and 32528 transitions. [2023-11-26 10:50:09,285 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22406 states and 32528 transitions. [2023-11-26 10:50:09,405 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22168 [2023-11-26 10:50:09,491 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22406 states to 22406 states and 32528 transitions. [2023-11-26 10:50:09,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22406 [2023-11-26 10:50:09,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22406 [2023-11-26 10:50:09,514 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22406 states and 32528 transitions. [2023-11-26 10:50:09,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:09,536 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22406 states and 32528 transitions. [2023-11-26 10:50:09,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22406 states and 32528 transitions. [2023-11-26 10:50:10,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22406 to 22390. [2023-11-26 10:50:10,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22390 states, 22390 states have (on average 1.4520768200089325) internal successors, (32512), 22389 states have internal predecessors, (32512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:10,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22390 states to 22390 states and 32512 transitions. [2023-11-26 10:50:10,161 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22390 states and 32512 transitions. [2023-11-26 10:50:10,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:10,163 INFO L428 stractBuchiCegarLoop]: Abstraction has 22390 states and 32512 transitions. [2023-11-26 10:50:10,163 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-26 10:50:10,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22390 states and 32512 transitions. [2023-11-26 10:50:10,410 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22152 [2023-11-26 10:50:10,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:10,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:10,413 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:10,413 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:10,414 INFO L748 eck$LassoCheckResult]: Stem: 111464#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 111465#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 112279#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 112280#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112141#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 112142#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 112237#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 112559#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 112709#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112710#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 111440#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 111441#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 112631#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 112034#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 112035#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 111948#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 111949#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 112350#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 111683#L1174 assume !(0 == ~M_E~0); 111684#L1174-2 assume !(0 == ~T1_E~0); 111535#L1179-1 assume !(0 == ~T2_E~0); 111438#L1184-1 assume !(0 == ~T3_E~0); 111439#L1189-1 assume !(0 == ~T4_E~0); 111481#L1194-1 assume !(0 == ~T5_E~0); 111577#L1199-1 assume !(0 == ~T6_E~0); 112482#L1204-1 assume !(0 == ~T7_E~0); 112398#L1209-1 assume !(0 == ~T8_E~0); 112399#L1214-1 assume !(0 == ~T9_E~0); 112878#L1219-1 assume !(0 == ~T10_E~0); 113007#L1224-1 assume !(0 == ~T11_E~0); 111806#L1229-1 assume !(0 == ~T12_E~0); 111368#L1234-1 assume !(0 == ~E_1~0); 111369#L1239-1 assume !(0 == ~E_2~0); 111403#L1244-1 assume !(0 == ~E_3~0); 111404#L1249-1 assume !(0 == ~E_4~0); 112053#L1254-1 assume !(0 == ~E_5~0); 111301#L1259-1 assume !(0 == ~E_6~0); 111256#L1264-1 assume !(0 == ~E_7~0); 111257#L1269-1 assume !(0 == ~E_8~0); 113016#L1274-1 assume !(0 == ~E_9~0); 112913#L1279-1 assume !(0 == ~E_10~0); 111484#L1284-1 assume !(0 == ~E_11~0); 111485#L1289-1 assume !(0 == ~E_12~0); 112110#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112111#L566 assume !(1 == ~m_pc~0); 112550#L566-2 is_master_triggered_~__retres1~0#1 := 0; 112551#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112155#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 112156#L1455 assume !(0 != activate_threads_~tmp~1#1); 111710#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111711#L585 assume !(1 == ~t1_pc~0); 111889#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 111890#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112542#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 112543#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 112958#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112953#L604 assume !(1 == ~t2_pc~0); 112441#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 112442#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111658#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 111659#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 112667#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112668#L623 assume 1 == ~t3_pc~0; 111888#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 111232#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112520#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 112521#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 112703#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111270#L642 assume !(1 == ~t4_pc~0); 111271#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 111721#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 111329#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 111330#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 111345#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112455#L661 assume 1 == ~t5_pc~0; 111499#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 111500#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112368#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 112777#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 112492#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112493#L680 assume !(1 == ~t6_pc~0); 111923#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 111924#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111647#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 111648#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 112788#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 112949#L699 assume 1 == ~t7_pc~0; 112330#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 112331#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 112579#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 112219#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 112220#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 112112#L718 assume !(1 == ~t8_pc~0); 112113#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 111479#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 111480#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 111517#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 111518#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 111650#L737 assume 1 == ~t9_pc~0; 112533#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 111788#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 111690#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111691#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 111966#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 111967#L756 assume 1 == ~t10_pc~0; 112568#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 112209#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 112476#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 112148#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 111763#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 111764#L775 assume !(1 == ~t11_pc~0); 112026#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 112027#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112871#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 111413#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 111414#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 111596#L794 assume 1 == ~t12_pc~0; 111436#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 111416#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 111276#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 111277#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 111563#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112038#L1307 assume !(1 == ~M_E~0); 112039#L1307-2 assume !(1 == ~T1_E~0); 112152#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 112067#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112068#L1322-1 assume !(1 == ~T4_E~0); 111776#L1327-1 assume !(1 == ~T5_E~0); 111777#L1332-1 assume !(1 == ~T6_E~0); 112335#L1337-1 assume !(1 == ~T7_E~0); 112292#L1342-1 assume !(1 == ~T8_E~0); 112293#L1347-1 assume !(1 == ~T9_E~0); 112742#L1352-1 assume !(1 == ~T10_E~0); 112743#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 126922#L1362-1 assume !(1 == ~T12_E~0); 126915#L1367-1 assume !(1 == ~E_1~0); 126909#L1372-1 assume !(1 == ~E_2~0); 126901#L1377-1 assume !(1 == ~E_3~0); 126895#L1382-1 assume !(1 == ~E_4~0); 126888#L1387-1 assume !(1 == ~E_5~0); 112443#L1392-1 assume !(1 == ~E_6~0); 124775#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 124773#L1402-1 assume !(1 == ~E_8~0); 123675#L1407-1 assume !(1 == ~E_9~0); 123673#L1412-1 assume !(1 == ~E_10~0); 123360#L1417-1 assume !(1 == ~E_11~0); 123358#L1422-1 assume !(1 == ~E_12~0); 123220#L1427-1 assume { :end_inline_reset_delta_events } true; 123218#L1768-2 [2023-11-26 10:50:10,414 INFO L750 eck$LassoCheckResult]: Loop: 123218#L1768-2 assume !false; 123215#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 123210#L1149-1 assume !false; 123208#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 123174#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 123164#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 123157#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 123149#L976 assume !(0 != eval_~tmp~0#1); 123150#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 129626#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 129621#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 129615#L1174-5 assume !(0 == ~T1_E~0); 129610#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 129602#L1184-3 assume !(0 == ~T3_E~0); 129597#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 129592#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 129586#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 129579#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 129573#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 129564#L1214-3 assume !(0 == ~T9_E~0); 129558#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 129552#L1224-3 assume !(0 == ~T11_E~0); 129546#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 129539#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 129533#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 129524#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 129518#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 129511#L1254-3 assume !(0 == ~E_5~0); 129506#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 129500#L1264-3 assume !(0 == ~E_7~0); 129495#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 129488#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 129483#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 129477#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 129473#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 129468#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 129463#L566-39 assume !(1 == ~m_pc~0); 129457#L566-41 is_master_triggered_~__retres1~0#1 := 0; 129453#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 129448#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 129443#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 129436#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129430#L585-39 assume !(1 == ~t1_pc~0); 129422#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 129417#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 129412#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 129406#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 129402#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 129399#L604-39 assume 1 == ~t2_pc~0; 129393#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 129392#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 129391#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 129390#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 129389#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 129322#L623-39 assume 1 == ~t3_pc~0; 129317#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 129311#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 127900#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 127897#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 127895#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127893#L642-39 assume !(1 == ~t4_pc~0); 127891#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 127838#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 127827#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 127818#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 127814#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 127811#L661-39 assume 1 == ~t5_pc~0; 127695#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 127692#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 127689#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 127670#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 127663#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 127653#L680-39 assume 1 == ~t6_pc~0; 127651#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 127642#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 127631#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 127620#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 127610#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 127602#L699-39 assume 1 == ~t7_pc~0; 127595#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 127589#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 127584#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 127578#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 127574#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 127568#L718-39 assume !(1 == ~t8_pc~0); 127563#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 127557#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 127552#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 127547#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 127540#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 127534#L737-39 assume !(1 == ~t9_pc~0); 127529#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 127523#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 127518#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 127513#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 127506#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 127500#L756-39 assume !(1 == ~t10_pc~0); 127493#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 127488#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 127483#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 127478#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 127471#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 127465#L775-39 assume 1 == ~t11_pc~0; 127457#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 127451#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 127445#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 127440#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 127434#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 127429#L794-39 assume 1 == ~t12_pc~0; 127425#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 127421#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 127417#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 127413#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 127407#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127402#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 127397#L1307-5 assume !(1 == ~T1_E~0); 127394#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 124478#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 127387#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 127382#L1327-3 assume !(1 == ~T5_E~0); 127376#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 127370#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 127365#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 125083#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 125079#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 125077#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 125075#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 125073#L1367-3 assume !(1 == ~E_1~0); 125071#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 125068#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 125066#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 125064#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 125060#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 124152#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 124149#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 124147#L1407-3 assume !(1 == ~E_9~0); 124145#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 124143#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 124141#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 124139#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 123704#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 123697#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 123695#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 123693#L1787 assume !(0 == start_simulation_~tmp~3#1); 123691#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 123382#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 123368#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 123366#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 123364#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 123363#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123362#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 123221#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 123218#L1768-2 [2023-11-26 10:50:10,414 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:10,415 INFO L85 PathProgramCache]: Analyzing trace with hash 1220887001, now seen corresponding path program 1 times [2023-11-26 10:50:10,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:10,415 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149261698] [2023-11-26 10:50:10,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:10,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:10,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:10,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:10,499 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:10,499 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1149261698] [2023-11-26 10:50:10,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1149261698] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:10,499 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:10,499 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-26 10:50:10,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1128256333] [2023-11-26 10:50:10,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:10,500 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:10,500 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:10,500 INFO L85 PathProgramCache]: Analyzing trace with hash 1214151105, now seen corresponding path program 1 times [2023-11-26 10:50:10,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:10,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341775150] [2023-11-26 10:50:10,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:10,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:10,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:10,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:10,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:10,567 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341775150] [2023-11-26 10:50:10,567 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341775150] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:10,567 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:10,567 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:10,567 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1852320380] [2023-11-26 10:50:10,567 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:10,568 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:10,568 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:10,568 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-26 10:50:10,569 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-26 10:50:10,569 INFO L87 Difference]: Start difference. First operand 22390 states and 32512 transitions. cyclomatic complexity: 10138 Second operand has 5 states, 5 states have (on average 29.6) internal successors, (148), 5 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:11,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:11,399 INFO L93 Difference]: Finished difference Result 58392 states and 84038 transitions. [2023-11-26 10:50:11,399 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 58392 states and 84038 transitions. [2023-11-26 10:50:11,720 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 57904 [2023-11-26 10:50:12,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 58392 states to 58392 states and 84038 transitions. [2023-11-26 10:50:12,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 58392 [2023-11-26 10:50:12,148 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 58392 [2023-11-26 10:50:12,148 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58392 states and 84038 transitions. [2023-11-26 10:50:12,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:12,195 INFO L218 hiAutomatonCegarLoop]: Abstraction has 58392 states and 84038 transitions. [2023-11-26 10:50:12,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58392 states and 84038 transitions. [2023-11-26 10:50:12,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58392 to 22993. [2023-11-26 10:50:12,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22993 states, 22993 states have (on average 1.4402209368068544) internal successors, (33115), 22992 states have internal predecessors, (33115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:12,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22993 states to 22993 states and 33115 transitions. [2023-11-26 10:50:12,867 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22993 states and 33115 transitions. [2023-11-26 10:50:12,868 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-26 10:50:12,868 INFO L428 stractBuchiCegarLoop]: Abstraction has 22993 states and 33115 transitions. [2023-11-26 10:50:12,868 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-26 10:50:12,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22993 states and 33115 transitions. [2023-11-26 10:50:12,943 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22752 [2023-11-26 10:50:12,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:12,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:12,947 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:12,947 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:12,947 INFO L748 eck$LassoCheckResult]: Stem: 192260#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 192261#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 193090#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 193091#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 192944#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 192945#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 193048#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 193392#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 193562#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 193563#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 192236#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 192237#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 193472#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 192839#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 192840#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 192749#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 192750#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 193175#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 192480#L1174 assume !(0 == ~M_E~0); 192481#L1174-2 assume !(0 == ~T1_E~0); 192329#L1179-1 assume !(0 == ~T2_E~0); 192233#L1184-1 assume !(0 == ~T3_E~0); 192234#L1189-1 assume !(0 == ~T4_E~0); 192277#L1194-1 assume !(0 == ~T5_E~0); 192373#L1199-1 assume !(0 == ~T6_E~0); 193315#L1204-1 assume !(0 == ~T7_E~0); 193225#L1209-1 assume !(0 == ~T8_E~0); 193226#L1214-1 assume !(0 == ~T9_E~0); 193756#L1219-1 assume !(0 == ~T10_E~0); 193930#L1224-1 assume !(0 == ~T11_E~0); 192604#L1229-1 assume !(0 == ~T12_E~0); 192164#L1234-1 assume !(0 == ~E_1~0); 192165#L1239-1 assume !(0 == ~E_2~0); 192197#L1244-1 assume !(0 == ~E_3~0); 192198#L1249-1 assume !(0 == ~E_4~0); 192859#L1254-1 assume !(0 == ~E_5~0); 192097#L1259-1 assume !(0 == ~E_6~0); 192052#L1264-1 assume !(0 == ~E_7~0); 192053#L1269-1 assume !(0 == ~E_8~0); 193948#L1274-1 assume !(0 == ~E_9~0); 193809#L1279-1 assume !(0 == ~E_10~0); 192280#L1284-1 assume !(0 == ~E_11~0); 192281#L1289-1 assume !(0 == ~E_12~0); 192914#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 192915#L566 assume !(1 == ~m_pc~0); 193387#L566-2 is_master_triggered_~__retres1~0#1 := 0; 193388#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 192963#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 192964#L1455 assume !(0 != activate_threads_~tmp~1#1); 192507#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 192508#L585 assume !(1 == ~t1_pc~0); 192693#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 192694#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 193378#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 193379#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 193866#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 193861#L604 assume !(1 == ~t2_pc~0); 193270#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 193271#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 193831#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 193721#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 193516#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 193517#L623 assume 1 == ~t3_pc~0; 192692#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 192027#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 193352#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 193353#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 193556#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 192066#L642 assume !(1 == ~t4_pc~0); 192067#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 192520#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 192119#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 192120#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 192141#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 193286#L661 assume 1 == ~t5_pc~0; 192295#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 192296#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 193193#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 193646#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 193323#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 193324#L680 assume !(1 == ~t6_pc~0); 192727#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 192728#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 192441#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 192442#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 193658#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 193858#L699 assume 1 == ~t7_pc~0; 193149#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 193150#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 193420#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 193028#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 193029#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 192916#L718 assume !(1 == ~t8_pc~0); 192917#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 192275#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 192276#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 192311#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 192312#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 192447#L737 assume 1 == ~t9_pc~0; 193367#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 192586#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 192487#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 192488#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 192769#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 192770#L756 assume 1 == ~t10_pc~0; 193408#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 193019#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 193310#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 192951#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 192562#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 192563#L775 assume !(1 == ~t11_pc~0); 192831#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 192832#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 193747#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 192209#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 192210#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 192394#L794 assume 1 == ~t12_pc~0; 192231#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 192212#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 192069#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 192070#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 192357#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 192843#L1307 assume !(1 == ~M_E~0); 192844#L1307-2 assume !(1 == ~T1_E~0); 192957#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 193891#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 198329#L1322-1 assume !(1 == ~T4_E~0); 198328#L1327-1 assume !(1 == ~T5_E~0); 198327#L1332-1 assume !(1 == ~T6_E~0); 198326#L1337-1 assume !(1 == ~T7_E~0); 193104#L1342-1 assume !(1 == ~T8_E~0); 193105#L1347-1 assume !(1 == ~T9_E~0); 193808#L1352-1 assume !(1 == ~T10_E~0); 198325#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 198324#L1362-1 assume !(1 == ~T12_E~0); 198286#L1367-1 assume !(1 == ~E_1~0); 192374#L1372-1 assume !(1 == ~E_2~0); 192375#L1377-1 assume !(1 == ~E_3~0); 192677#L1382-1 assume !(1 == ~E_4~0); 192678#L1387-1 assume !(1 == ~E_5~0); 198254#L1392-1 assume !(1 == ~E_6~0); 198229#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 198201#L1402-1 assume !(1 == ~E_8~0); 198177#L1407-1 assume !(1 == ~E_9~0); 198175#L1412-1 assume !(1 == ~E_10~0); 198157#L1417-1 assume !(1 == ~E_11~0); 198125#L1422-1 assume !(1 == ~E_12~0); 198119#L1427-1 assume { :end_inline_reset_delta_events } true; 198106#L1768-2 [2023-11-26 10:50:12,948 INFO L750 eck$LassoCheckResult]: Loop: 198106#L1768-2 assume !false; 198097#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 198092#L1149-1 assume !false; 198090#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 198040#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 198031#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 198025#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 198020#L976 assume !(0 != eval_~tmp~0#1); 198021#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 202821#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 202820#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 202819#L1174-5 assume !(0 == ~T1_E~0); 202818#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 202817#L1184-3 assume !(0 == ~T3_E~0); 202816#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 202815#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 202814#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 202813#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 202812#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 202811#L1214-3 assume !(0 == ~T9_E~0); 202810#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 202809#L1224-3 assume !(0 == ~T11_E~0); 202808#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 202807#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 202806#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 202805#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 202804#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 202803#L1254-3 assume !(0 == ~E_5~0); 202802#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 202801#L1264-3 assume !(0 == ~E_7~0); 202800#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 202799#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 202798#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 202797#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 202796#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 202795#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 202794#L566-39 assume !(1 == ~m_pc~0); 202793#L566-41 is_master_triggered_~__retres1~0#1 := 0; 202792#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 202791#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 202790#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 202789#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 202788#L585-39 assume !(1 == ~t1_pc~0); 202787#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 202786#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 202785#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 202784#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 202783#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 202782#L604-39 assume !(1 == ~t2_pc~0); 202781#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 202779#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 202777#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 202775#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 202771#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 202770#L623-39 assume 1 == ~t3_pc~0; 202769#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 202746#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 202744#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 202742#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 202739#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 202737#L642-39 assume !(1 == ~t4_pc~0); 202735#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 202732#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 202730#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 202728#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 202725#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 202723#L661-39 assume 1 == ~t5_pc~0; 202721#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 202718#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 202716#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 202714#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 202711#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 202709#L680-39 assume !(1 == ~t6_pc~0); 202707#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 202704#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 202702#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 202700#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 202697#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 202695#L699-39 assume !(1 == ~t7_pc~0); 202693#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 202690#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 202688#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 202686#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 202683#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 202681#L718-39 assume !(1 == ~t8_pc~0); 202679#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 202676#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 202674#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 202672#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 202669#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 202667#L737-39 assume !(1 == ~t9_pc~0); 202665#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 202662#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 202660#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 202658#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 202655#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 202653#L756-39 assume 1 == ~t10_pc~0; 202651#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 202648#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 202646#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 202644#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 202641#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 202639#L775-39 assume !(1 == ~t11_pc~0); 199035#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 199032#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 199031#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 199030#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 199029#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 199028#L794-39 assume 1 == ~t12_pc~0; 198663#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 198660#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 198659#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 198657#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 198655#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 198653#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 198651#L1307-5 assume !(1 == ~T1_E~0); 198649#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 194824#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 198644#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 198641#L1327-3 assume !(1 == ~T5_E~0); 198639#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 198636#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 198629#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 198470#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 198465#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 198463#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 198458#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 198455#L1367-3 assume !(1 == ~E_1~0); 198452#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 198449#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 198446#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 198444#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 198367#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 198364#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 198357#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 198350#L1407-3 assume !(1 == ~E_9~0); 198345#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 198340#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 198335#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 198333#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 198303#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 198296#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 198295#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 198273#L1787 assume !(0 == start_simulation_~tmp~3#1); 198266#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 198253#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 198222#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 198200#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 198176#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 198158#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 198126#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 198120#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 198106#L1768-2 [2023-11-26 10:50:12,949 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:12,949 INFO L85 PathProgramCache]: Analyzing trace with hash 226193303, now seen corresponding path program 1 times [2023-11-26 10:50:12,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:12,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184632889] [2023-11-26 10:50:12,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:12,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:12,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:13,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:13,148 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:13,148 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184632889] [2023-11-26 10:50:13,148 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [184632889] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:13,149 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:13,149 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:50:13,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [711896063] [2023-11-26 10:50:13,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:13,150 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:13,150 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:13,150 INFO L85 PathProgramCache]: Analyzing trace with hash -1475012644, now seen corresponding path program 1 times [2023-11-26 10:50:13,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:13,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [149806055] [2023-11-26 10:50:13,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:13,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:13,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:13,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:13,211 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:13,211 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [149806055] [2023-11-26 10:50:13,211 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [149806055] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:13,211 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:13,211 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:13,212 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [954329092] [2023-11-26 10:50:13,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:13,212 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:13,212 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:13,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:13,213 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:13,213 INFO L87 Difference]: Start difference. First operand 22993 states and 33115 transitions. cyclomatic complexity: 10138 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:13,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:13,470 INFO L93 Difference]: Finished difference Result 44040 states and 63164 transitions. [2023-11-26 10:50:13,470 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44040 states and 63164 transitions. [2023-11-26 10:50:13,927 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43752 [2023-11-26 10:50:14,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44040 states to 44040 states and 63164 transitions. [2023-11-26 10:50:14,220 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44040 [2023-11-26 10:50:14,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44040 [2023-11-26 10:50:14,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44040 states and 63164 transitions. [2023-11-26 10:50:14,274 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:14,274 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44040 states and 63164 transitions. [2023-11-26 10:50:14,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44040 states and 63164 transitions. [2023-11-26 10:50:14,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44040 to 44008. [2023-11-26 10:50:14,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44008 states, 44008 states have (on average 1.4345573532085076) internal successors, (63132), 44007 states have internal predecessors, (63132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:15,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44008 states to 44008 states and 63132 transitions. [2023-11-26 10:50:15,139 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44008 states and 63132 transitions. [2023-11-26 10:50:15,139 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:15,140 INFO L428 stractBuchiCegarLoop]: Abstraction has 44008 states and 63132 transitions. [2023-11-26 10:50:15,140 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-26 10:50:15,140 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44008 states and 63132 transitions. [2023-11-26 10:50:15,332 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43720 [2023-11-26 10:50:15,332 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:15,332 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:15,335 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:15,335 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:15,336 INFO L748 eck$LassoCheckResult]: Stem: 259299#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 259300#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 260145#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 260146#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 260002#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 260003#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 260105#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 260440#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 260603#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 260604#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 259275#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 259276#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 260523#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 259889#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 259890#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 259795#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 259796#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 260229#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 259516#L1174 assume !(0 == ~M_E~0); 259517#L1174-2 assume !(0 == ~T1_E~0); 259367#L1179-1 assume !(0 == ~T2_E~0); 259272#L1184-1 assume !(0 == ~T3_E~0); 259273#L1189-1 assume !(0 == ~T4_E~0); 259314#L1194-1 assume !(0 == ~T5_E~0); 259411#L1199-1 assume !(0 == ~T6_E~0); 260367#L1204-1 assume !(0 == ~T7_E~0); 260279#L1209-1 assume !(0 == ~T8_E~0); 260280#L1214-1 assume !(0 == ~T9_E~0); 260796#L1219-1 assume !(0 == ~T10_E~0); 260960#L1224-1 assume !(0 == ~T11_E~0); 259647#L1229-1 assume !(0 == ~T12_E~0); 259201#L1234-1 assume !(0 == ~E_1~0); 259202#L1239-1 assume !(0 == ~E_2~0); 259234#L1244-1 assume !(0 == ~E_3~0); 259235#L1249-1 assume !(0 == ~E_4~0); 259916#L1254-1 assume !(0 == ~E_5~0); 259134#L1259-1 assume !(0 == ~E_6~0); 259091#L1264-1 assume !(0 == ~E_7~0); 259092#L1269-1 assume !(0 == ~E_8~0); 260980#L1274-1 assume !(0 == ~E_9~0); 260844#L1279-1 assume !(0 == ~E_10~0); 259318#L1284-1 assume !(0 == ~E_11~0); 259319#L1289-1 assume !(0 == ~E_12~0); 259972#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 259973#L566 assume !(1 == ~m_pc~0); 260435#L566-2 is_master_triggered_~__retres1~0#1 := 0; 260436#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 260021#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 260022#L1455 assume !(0 != activate_threads_~tmp~1#1); 259543#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 259544#L585 assume !(1 == ~t1_pc~0); 259737#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 259738#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 260426#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 260427#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 260893#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 260889#L604 assume !(1 == ~t2_pc~0); 260325#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 260326#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 259486#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 259487#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 260555#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 260556#L623 assume !(1 == ~t3_pc~0); 259066#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 259067#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 260399#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 260400#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 260596#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 259105#L642 assume !(1 == ~t4_pc~0); 259106#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 259559#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 259156#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 259157#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 259178#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 260340#L661 assume 1 == ~t5_pc~0; 259333#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 259334#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 260246#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 260668#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 260374#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 260375#L680 assume !(1 == ~t6_pc~0); 259773#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 259774#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 259477#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 259478#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 260681#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 260886#L699 assume 1 == ~t7_pc~0; 260205#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 260206#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 260465#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 260086#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 260087#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 259974#L718 assume !(1 == ~t8_pc~0); 259975#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 259312#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 259313#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 259349#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 259350#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 259483#L737 assume 1 == ~t9_pc~0; 260414#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 259627#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 259523#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 259524#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 259816#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 259817#L756 assume 1 == ~t10_pc~0; 260454#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 260077#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 260361#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 260013#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 259604#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 259605#L775 assume !(1 == ~t11_pc~0); 259881#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 259882#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 260789#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 259246#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 259247#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 259431#L794 assume 1 == ~t12_pc~0; 259270#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 259249#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 259108#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 259109#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 259396#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 259896#L1307 assume !(1 == ~M_E~0); 259897#L1307-2 assume !(1 == ~T1_E~0); 260018#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 259931#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 259932#L1322-1 assume !(1 == ~T4_E~0); 259616#L1327-1 assume !(1 == ~T5_E~0); 259617#L1332-1 assume !(1 == ~T6_E~0); 260210#L1337-1 assume !(1 == ~T7_E~0); 260160#L1342-1 assume !(1 == ~T8_E~0); 260161#L1347-1 assume !(1 == ~T9_E~0); 260636#L1352-1 assume !(1 == ~T10_E~0); 260466#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 259793#L1362-1 assume !(1 == ~T12_E~0); 259794#L1367-1 assume !(1 == ~E_1~0); 265363#L1372-1 assume !(1 == ~E_2~0); 265358#L1377-1 assume !(1 == ~E_3~0); 265356#L1382-1 assume !(1 == ~E_4~0); 265354#L1387-1 assume !(1 == ~E_5~0); 265351#L1392-1 assume !(1 == ~E_6~0); 265350#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 265349#L1402-1 assume !(1 == ~E_8~0); 265348#L1407-1 assume !(1 == ~E_9~0); 265347#L1412-1 assume !(1 == ~E_10~0); 265346#L1417-1 assume !(1 == ~E_11~0); 265345#L1422-1 assume !(1 == ~E_12~0); 265303#L1427-1 assume { :end_inline_reset_delta_events } true; 265301#L1768-2 [2023-11-26 10:50:15,337 INFO L750 eck$LassoCheckResult]: Loop: 265301#L1768-2 assume !false; 265299#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 265293#L1149-1 assume !false; 265291#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 264922#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 264914#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 264911#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 264908#L976 assume !(0 != eval_~tmp~0#1); 264909#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 272112#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 272111#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 272110#L1174-5 assume !(0 == ~T1_E~0); 272109#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 272108#L1184-3 assume !(0 == ~T3_E~0); 272107#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 272106#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 272105#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 272104#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 272103#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 272102#L1214-3 assume !(0 == ~T9_E~0); 272101#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 272100#L1224-3 assume !(0 == ~T11_E~0); 272099#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 272098#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 272097#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 272096#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 272095#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 272094#L1254-3 assume !(0 == ~E_5~0); 272093#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 272092#L1264-3 assume !(0 == ~E_7~0); 272091#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 272090#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 272089#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 272088#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 272087#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 272086#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 272085#L566-39 assume !(1 == ~m_pc~0); 272084#L566-41 is_master_triggered_~__retres1~0#1 := 0; 272083#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 272082#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 272081#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 272080#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 272079#L585-39 assume !(1 == ~t1_pc~0); 272078#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 272077#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 272076#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 272075#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 272074#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 272073#L604-39 assume 1 == ~t2_pc~0; 272071#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 272069#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 272067#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 272064#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 272062#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 272060#L623-39 assume !(1 == ~t3_pc~0); 272058#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 272056#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 272054#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 272052#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 272050#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 272048#L642-39 assume 1 == ~t4_pc~0; 272045#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 272043#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 272041#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 272039#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 272036#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 272033#L661-39 assume !(1 == ~t5_pc~0); 272029#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 272026#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 272024#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 272022#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 272020#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 272018#L680-39 assume !(1 == ~t6_pc~0); 272016#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 272013#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 272011#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 272009#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 272006#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 272004#L699-39 assume 1 == ~t7_pc~0; 272001#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 271999#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 271997#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 271995#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 271992#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 271990#L718-39 assume !(1 == ~t8_pc~0); 271988#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 271985#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 271983#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 271981#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 271978#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 271975#L737-39 assume !(1 == ~t9_pc~0); 271972#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 271968#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 271965#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 271962#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 271958#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 271955#L756-39 assume !(1 == ~t10_pc~0); 271950#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 271947#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 271944#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 271941#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 271937#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 271934#L775-39 assume 1 == ~t11_pc~0; 271929#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 271925#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 271921#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 271917#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 271913#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 271910#L794-39 assume !(1 == ~t12_pc~0); 271906#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 271903#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 271900#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 271897#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 271893#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 271890#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 271886#L1307-5 assume !(1 == ~T1_E~0); 271883#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 265485#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 271878#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 271874#L1327-3 assume !(1 == ~T5_E~0); 271871#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 271867#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 271864#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 271861#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 271215#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 271855#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 271852#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 271848#L1367-3 assume !(1 == ~E_1~0); 271845#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 271843#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 271841#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 271839#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 265432#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 271835#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 270463#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 270462#L1407-3 assume !(1 == ~E_9~0); 270458#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 270454#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 270450#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 270449#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 270374#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 270365#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 270360#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 270355#L1787 assume !(0 == start_simulation_~tmp~3#1); 270351#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 265328#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 265314#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 265312#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 265310#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 265308#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 265306#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 265304#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 265301#L1768-2 [2023-11-26 10:50:15,337 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:15,338 INFO L85 PathProgramCache]: Analyzing trace with hash 1148113654, now seen corresponding path program 1 times [2023-11-26 10:50:15,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:15,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92828535] [2023-11-26 10:50:15,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:15,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:15,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:15,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:15,403 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:15,403 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [92828535] [2023-11-26 10:50:15,403 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [92828535] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:15,403 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:15,404 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:50:15,404 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2002350380] [2023-11-26 10:50:15,404 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:15,404 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:15,405 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:15,405 INFO L85 PathProgramCache]: Analyzing trace with hash 1635228318, now seen corresponding path program 1 times [2023-11-26 10:50:15,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:15,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [57365924] [2023-11-26 10:50:15,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:15,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:15,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:15,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:15,657 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:15,658 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [57365924] [2023-11-26 10:50:15,658 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [57365924] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:15,658 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:15,658 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:15,658 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320067069] [2023-11-26 10:50:15,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:15,659 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:15,659 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:15,660 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:15,660 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:15,660 INFO L87 Difference]: Start difference. First operand 44008 states and 63132 transitions. cyclomatic complexity: 19156 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:16,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:16,123 INFO L93 Difference]: Finished difference Result 84399 states and 120633 transitions. [2023-11-26 10:50:16,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84399 states and 120633 transitions. [2023-11-26 10:50:16,863 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 83968 [2023-11-26 10:50:17,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84399 states to 84399 states and 120633 transitions. [2023-11-26 10:50:17,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 84399 [2023-11-26 10:50:17,204 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 84399 [2023-11-26 10:50:17,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84399 states and 120633 transitions. [2023-11-26 10:50:17,275 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:17,275 INFO L218 hiAutomatonCegarLoop]: Abstraction has 84399 states and 120633 transitions. [2023-11-26 10:50:17,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84399 states and 120633 transitions. [2023-11-26 10:50:18,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84399 to 84335. [2023-11-26 10:50:18,620 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84335 states, 84335 states have (on average 1.4296436829311674) internal successors, (120569), 84334 states have internal predecessors, (120569), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:18,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84335 states to 84335 states and 120569 transitions. [2023-11-26 10:50:18,823 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84335 states and 120569 transitions. [2023-11-26 10:50:18,824 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:18,824 INFO L428 stractBuchiCegarLoop]: Abstraction has 84335 states and 120569 transitions. [2023-11-26 10:50:18,824 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-26 10:50:18,824 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84335 states and 120569 transitions. [2023-11-26 10:50:19,352 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 83904 [2023-11-26 10:50:19,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:19,352 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:19,355 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:19,356 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:19,356 INFO L748 eck$LassoCheckResult]: Stem: 387716#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 387717#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 388533#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 388534#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 388394#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 388395#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 388491#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 388833#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 389005#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 389006#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 387692#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 387693#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 388916#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 388287#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 388288#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 388195#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 388196#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 388614#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 387928#L1174 assume !(0 == ~M_E~0); 387929#L1174-2 assume !(0 == ~T1_E~0); 387779#L1179-1 assume !(0 == ~T2_E~0); 387687#L1184-1 assume !(0 == ~T3_E~0); 387688#L1189-1 assume !(0 == ~T4_E~0); 387732#L1194-1 assume !(0 == ~T5_E~0); 387822#L1199-1 assume !(0 == ~T6_E~0); 388759#L1204-1 assume !(0 == ~T7_E~0); 388666#L1209-1 assume !(0 == ~T8_E~0); 388667#L1214-1 assume !(0 == ~T9_E~0); 389201#L1219-1 assume !(0 == ~T10_E~0); 389394#L1224-1 assume !(0 == ~T11_E~0); 388053#L1229-1 assume !(0 == ~T12_E~0); 387617#L1234-1 assume !(0 == ~E_1~0); 387618#L1239-1 assume !(0 == ~E_2~0); 387650#L1244-1 assume !(0 == ~E_3~0); 387651#L1249-1 assume !(0 == ~E_4~0); 388307#L1254-1 assume !(0 == ~E_5~0); 387550#L1259-1 assume !(0 == ~E_6~0); 387505#L1264-1 assume !(0 == ~E_7~0); 387506#L1269-1 assume !(0 == ~E_8~0); 389416#L1274-1 assume !(0 == ~E_9~0); 389245#L1279-1 assume !(0 == ~E_10~0); 387736#L1284-1 assume !(0 == ~E_11~0); 387737#L1289-1 assume !(0 == ~E_12~0); 388363#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 388364#L566 assume !(1 == ~m_pc~0); 388828#L566-2 is_master_triggered_~__retres1~0#1 := 0; 388829#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 388410#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 388411#L1455 assume !(0 != activate_threads_~tmp~1#1); 387955#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 387956#L585 assume !(1 == ~t1_pc~0); 388140#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 388141#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 388819#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 388820#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 389305#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 389300#L604 assume !(1 == ~t2_pc~0); 388715#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 388716#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 387897#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 387898#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 388960#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 388961#L623 assume !(1 == ~t3_pc~0); 387480#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 387481#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 388794#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 388795#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 388998#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 387519#L642 assume !(1 == ~t4_pc~0); 387520#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 387968#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 387572#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 387573#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 387594#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 388731#L661 assume !(1 == ~t5_pc~0); 388922#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 388632#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 388633#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 389084#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 388767#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 388768#L680 assume !(1 == ~t6_pc~0); 388175#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 388176#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 387888#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 387889#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 389095#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 389297#L699 assume 1 == ~t7_pc~0; 388592#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 388593#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 388861#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 388472#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 388473#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 388365#L718 assume !(1 == ~t8_pc~0); 388366#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 387730#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 387731#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 387761#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 387762#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 387894#L737 assume 1 == ~t9_pc~0; 388808#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 388034#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 387935#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 387936#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 388218#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 388219#L756 assume 1 == ~t10_pc~0; 388849#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 388463#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 388754#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 388401#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 388010#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 388011#L775 assume !(1 == ~t11_pc~0); 388279#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 388280#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 389194#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 387662#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 387663#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 387843#L794 assume 1 == ~t12_pc~0; 387685#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 387665#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 387522#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 387523#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 387807#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 388291#L1307 assume !(1 == ~M_E~0); 388292#L1307-2 assume !(1 == ~T1_E~0); 388406#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 388320#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 388321#L1322-1 assume !(1 == ~T4_E~0); 388022#L1327-1 assume !(1 == ~T5_E~0); 388023#L1332-1 assume !(1 == ~T6_E~0); 388597#L1337-1 assume !(1 == ~T7_E~0); 388546#L1342-1 assume !(1 == ~T8_E~0); 388547#L1347-1 assume !(1 == ~T9_E~0); 389244#L1352-1 assume !(1 == ~T10_E~0); 403773#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 403771#L1362-1 assume !(1 == ~T12_E~0); 403769#L1367-1 assume !(1 == ~E_1~0); 403768#L1372-1 assume !(1 == ~E_2~0); 403764#L1377-1 assume !(1 == ~E_3~0); 403762#L1382-1 assume !(1 == ~E_4~0); 403760#L1387-1 assume !(1 == ~E_5~0); 388717#L1392-1 assume !(1 == ~E_6~0); 403757#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 403756#L1402-1 assume !(1 == ~E_8~0); 403752#L1407-1 assume !(1 == ~E_9~0); 403748#L1412-1 assume !(1 == ~E_10~0); 403744#L1417-1 assume !(1 == ~E_11~0); 403740#L1422-1 assume !(1 == ~E_12~0); 403737#L1427-1 assume { :end_inline_reset_delta_events } true; 403735#L1768-2 [2023-11-26 10:50:19,357 INFO L750 eck$LassoCheckResult]: Loop: 403735#L1768-2 assume !false; 403733#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 401256#L1149-1 assume !false; 401251#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 401234#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 401220#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 401211#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 401197#L976 assume !(0 != eval_~tmp~0#1); 401198#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 408710#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 408705#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 408700#L1174-5 assume !(0 == ~T1_E~0); 408695#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 408690#L1184-3 assume !(0 == ~T3_E~0); 408684#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 408677#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 408670#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 408663#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 408657#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 408652#L1214-3 assume !(0 == ~T9_E~0); 408646#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 408641#L1224-3 assume !(0 == ~T11_E~0); 408636#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 408630#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 408624#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 408618#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 408611#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 408605#L1254-3 assume !(0 == ~E_5~0); 408600#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 408596#L1264-3 assume !(0 == ~E_7~0); 408592#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 408588#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 408584#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 408580#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 408576#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 408571#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 408567#L566-39 assume !(1 == ~m_pc~0); 408563#L566-41 is_master_triggered_~__retres1~0#1 := 0; 408558#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 408553#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 408549#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 408545#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 408541#L585-39 assume !(1 == ~t1_pc~0); 408537#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 408532#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 408526#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 408521#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 408515#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 408510#L604-39 assume 1 == ~t2_pc~0; 408504#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 408497#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 408490#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 408484#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 408478#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 408473#L623-39 assume !(1 == ~t3_pc~0); 408469#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 408464#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 408460#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 408455#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 408449#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 408444#L642-39 assume 1 == ~t4_pc~0; 408438#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 408433#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 408429#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 408425#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 408420#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 408416#L661-39 assume !(1 == ~t5_pc~0); 408412#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 408407#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 408403#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 408399#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 408394#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 408391#L680-39 assume 1 == ~t6_pc~0; 408382#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 408381#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 408380#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 408379#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 408378#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 408377#L699-39 assume 1 == ~t7_pc~0; 408375#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 408374#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 408373#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 408372#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 408371#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 408370#L718-39 assume 1 == ~t8_pc~0; 408368#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 408366#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 408364#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 408362#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 408360#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 408358#L737-39 assume !(1 == ~t9_pc~0); 408356#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 408353#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 408351#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 408349#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 408347#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 408345#L756-39 assume !(1 == ~t10_pc~0); 408330#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 408328#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 408326#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 408324#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 408322#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 408320#L775-39 assume !(1 == ~t11_pc~0); 408318#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 408314#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 408312#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 408310#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 408308#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 408306#L794-39 assume 1 == ~t12_pc~0; 408304#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 408301#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 408299#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 408297#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 408295#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 408293#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 408291#L1307-5 assume !(1 == ~T1_E~0); 408288#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 399042#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 408285#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 408283#L1327-3 assume !(1 == ~T5_E~0); 408281#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 408279#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 408276#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 408274#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 399026#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 408271#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 408269#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 408267#L1367-3 assume !(1 == ~E_1~0); 408264#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 408262#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 408260#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 408258#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 407156#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 408255#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 408252#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 408250#L1407-3 assume !(1 == ~E_9~0); 408248#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 408246#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 408244#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 408242#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 408151#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 408141#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 408136#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 408129#L1787 assume !(0 == start_simulation_~tmp~3#1); 408124#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 408009#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 407988#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 407980#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 407972#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 407966#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 407858#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 403738#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 403735#L1768-2 [2023-11-26 10:50:19,358 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:19,358 INFO L85 PathProgramCache]: Analyzing trace with hash -1479734059, now seen corresponding path program 1 times [2023-11-26 10:50:19,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:19,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2122796231] [2023-11-26 10:50:19,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:19,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:19,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:19,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:19,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:19,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2122796231] [2023-11-26 10:50:19,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2122796231] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:19,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:19,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:19,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1365555511] [2023-11-26 10:50:19,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:19,469 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:19,469 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:19,469 INFO L85 PathProgramCache]: Analyzing trace with hash -1674746976, now seen corresponding path program 1 times [2023-11-26 10:50:19,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:19,470 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847501217] [2023-11-26 10:50:19,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:19,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:19,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:19,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:19,543 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:19,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1847501217] [2023-11-26 10:50:19,544 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1847501217] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:19,544 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:19,544 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:19,544 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [227070421] [2023-11-26 10:50:19,545 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:19,545 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:19,546 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:19,546 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-26 10:50:19,546 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-26 10:50:19,547 INFO L87 Difference]: Start difference. First operand 84335 states and 120569 transitions. cyclomatic complexity: 36298 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:20,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:20,604 INFO L93 Difference]: Finished difference Result 201366 states and 286422 transitions. [2023-11-26 10:50:20,604 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 201366 states and 286422 transitions. [2023-11-26 10:50:21,905 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 200392 [2023-11-26 10:50:22,937 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 201366 states to 201366 states and 286422 transitions. [2023-11-26 10:50:22,937 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201366 [2023-11-26 10:50:23,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201366 [2023-11-26 10:50:23,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201366 states and 286422 transitions. [2023-11-26 10:50:23,245 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:23,245 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201366 states and 286422 transitions. [2023-11-26 10:50:23,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201366 states and 286422 transitions. [2023-11-26 10:50:24,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201366 to 161582. [2023-11-26 10:50:25,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 161582 states, 161582 states have (on average 1.4251463653129681) internal successors, (230278), 161581 states have internal predecessors, (230278), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:26,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161582 states to 161582 states and 230278 transitions. [2023-11-26 10:50:26,330 INFO L240 hiAutomatonCegarLoop]: Abstraction has 161582 states and 230278 transitions. [2023-11-26 10:50:26,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-26 10:50:26,331 INFO L428 stractBuchiCegarLoop]: Abstraction has 161582 states and 230278 transitions. [2023-11-26 10:50:26,331 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-26 10:50:26,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 161582 states and 230278 transitions. [2023-11-26 10:50:26,804 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 160928 [2023-11-26 10:50:26,804 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:26,804 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:26,808 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:26,808 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:26,809 INFO L748 eck$LassoCheckResult]: Stem: 673424#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 673425#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 674252#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 674253#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 674108#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 674109#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 674209#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 674554#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 674718#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 674719#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 673400#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 673401#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 674634#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 674000#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 674001#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 673907#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 673908#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 674336#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 673636#L1174 assume !(0 == ~M_E~0); 673637#L1174-2 assume !(0 == ~T1_E~0); 673490#L1179-1 assume !(0 == ~T2_E~0); 673398#L1184-1 assume !(0 == ~T3_E~0); 673399#L1189-1 assume !(0 == ~T4_E~0); 673440#L1194-1 assume !(0 == ~T5_E~0); 673531#L1199-1 assume !(0 == ~T6_E~0); 674473#L1204-1 assume !(0 == ~T7_E~0); 674387#L1209-1 assume !(0 == ~T8_E~0); 674388#L1214-1 assume !(0 == ~T9_E~0); 674906#L1219-1 assume !(0 == ~T10_E~0); 675054#L1224-1 assume !(0 == ~T11_E~0); 673758#L1229-1 assume !(0 == ~T12_E~0); 673326#L1234-1 assume !(0 == ~E_1~0); 673327#L1239-1 assume !(0 == ~E_2~0); 673361#L1244-1 assume !(0 == ~E_3~0); 673362#L1249-1 assume !(0 == ~E_4~0); 674023#L1254-1 assume !(0 == ~E_5~0); 673259#L1259-1 assume !(0 == ~E_6~0); 673215#L1264-1 assume !(0 == ~E_7~0); 673216#L1269-1 assume !(0 == ~E_8~0); 675070#L1274-1 assume !(0 == ~E_9~0); 674947#L1279-1 assume !(0 == ~E_10~0); 673444#L1284-1 assume !(0 == ~E_11~0); 673445#L1289-1 assume !(0 == ~E_12~0); 674079#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 674080#L566 assume !(1 == ~m_pc~0); 674545#L566-2 is_master_triggered_~__retres1~0#1 := 0; 674546#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 674125#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 674126#L1455 assume !(0 != activate_threads_~tmp~1#1); 673663#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 673664#L585 assume !(1 == ~t1_pc~0); 673844#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 673845#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 674535#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 674536#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 674988#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 674981#L604 assume !(1 == ~t2_pc~0); 674432#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 674433#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 673610#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 673611#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 674674#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 674675#L623 assume !(1 == ~t3_pc~0); 673190#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 673191#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 674510#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 674511#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 674712#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 673229#L642 assume !(1 == ~t4_pc~0); 673230#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 673674#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 673287#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 673288#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 673303#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 674448#L661 assume !(1 == ~t5_pc~0); 674639#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 674354#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 674355#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 674792#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 674482#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 674483#L680 assume !(1 == ~t6_pc~0); 673883#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 673884#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 673598#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 673599#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 674806#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 674978#L699 assume !(1 == ~t7_pc~0); 674979#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 674573#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 674574#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 674191#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 674192#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 674081#L718 assume !(1 == ~t8_pc~0); 674082#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 673438#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 673439#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 673472#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 673473#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 673602#L737 assume 1 == ~t9_pc~0; 674526#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 673739#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 673643#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 673644#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 673927#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 673928#L756 assume 1 == ~t10_pc~0; 674563#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 674183#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 674468#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 674118#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 673715#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 673716#L775 assume !(1 == ~t11_pc~0); 673992#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 673993#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 674898#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 673371#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 673372#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 673550#L794 assume 1 == ~t12_pc~0; 673396#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 673374#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 673235#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 673236#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 673518#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 674004#L1307 assume !(1 == ~M_E~0); 674005#L1307-2 assume !(1 == ~T1_E~0); 674122#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 674036#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 674037#L1322-1 assume !(1 == ~T4_E~0); 673726#L1327-1 assume !(1 == ~T5_E~0); 673727#L1332-1 assume !(1 == ~T6_E~0); 674996#L1337-1 assume !(1 == ~T7_E~0); 674997#L1342-1 assume !(1 == ~T8_E~0); 674945#L1347-1 assume !(1 == ~T9_E~0); 674758#L1352-1 assume !(1 == ~T10_E~0); 674759#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 673903#L1362-1 assume !(1 == ~T12_E~0); 673904#L1367-1 assume !(1 == ~E_1~0); 673532#L1372-1 assume !(1 == ~E_2~0); 673533#L1377-1 assume !(1 == ~E_3~0); 673828#L1382-1 assume !(1 == ~E_4~0); 673829#L1387-1 assume !(1 == ~E_5~0); 683111#L1392-1 assume !(1 == ~E_6~0); 683110#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 683109#L1402-1 assume !(1 == ~E_8~0); 683108#L1407-1 assume !(1 == ~E_9~0); 683107#L1412-1 assume !(1 == ~E_10~0); 683106#L1417-1 assume !(1 == ~E_11~0); 683105#L1422-1 assume !(1 == ~E_12~0); 683101#L1427-1 assume { :end_inline_reset_delta_events } true; 683098#L1768-2 [2023-11-26 10:50:26,810 INFO L750 eck$LassoCheckResult]: Loop: 683098#L1768-2 assume !false; 683076#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 683068#L1149-1 assume !false; 683067#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 683053#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 683046#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 683044#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 683041#L976 assume !(0 != eval_~tmp~0#1); 683042#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 684716#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 684714#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 684712#L1174-5 assume !(0 == ~T1_E~0); 684711#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 684710#L1184-3 assume !(0 == ~T3_E~0); 684708#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 684706#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 684704#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 684702#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 684700#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 684698#L1214-3 assume !(0 == ~T9_E~0); 684697#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 684696#L1224-3 assume !(0 == ~T11_E~0); 684694#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 684692#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 684690#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 684688#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 684684#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 684682#L1254-3 assume !(0 == ~E_5~0); 684680#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 684678#L1264-3 assume !(0 == ~E_7~0); 684676#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 684674#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 684672#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 684670#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 684668#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 684667#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 684597#L566-39 assume !(1 == ~m_pc~0); 684588#L566-41 is_master_triggered_~__retres1~0#1 := 0; 684580#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 684575#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 684565#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 684564#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 684563#L585-39 assume !(1 == ~t1_pc~0); 684562#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 684561#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 684560#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 684558#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 684557#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 684556#L604-39 assume 1 == ~t2_pc~0; 684554#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 684555#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 684559#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 684546#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 684544#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 684542#L623-39 assume !(1 == ~t3_pc~0); 684540#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 684538#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 684536#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 684426#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 684419#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 684413#L642-39 assume !(1 == ~t4_pc~0); 684406#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 684000#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 683997#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 683995#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 683993#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 683991#L661-39 assume !(1 == ~t5_pc~0); 683989#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 683987#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 683985#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 683983#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 683981#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 683979#L680-39 assume 1 == ~t6_pc~0; 683976#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 683974#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 683971#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 683969#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 683967#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 683965#L699-39 assume !(1 == ~t7_pc~0); 680556#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 683962#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 683961#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 683959#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 683957#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 683955#L718-39 assume !(1 == ~t8_pc~0); 683950#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 683947#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 683945#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 683943#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 683941#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 683939#L737-39 assume 1 == ~t9_pc~0; 683935#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 683933#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 683931#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 683929#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 683927#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 683925#L756-39 assume 1 == ~t10_pc~0; 683832#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 683829#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 683827#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 683825#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 683823#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 683821#L775-39 assume 1 == ~t11_pc~0; 683818#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 683816#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 683814#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 683812#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 683810#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 683808#L794-39 assume 1 == ~t12_pc~0; 683798#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 683788#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 683782#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 683776#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 683770#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 683765#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 683760#L1307-5 assume !(1 == ~T1_E~0); 683756#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 683749#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 683741#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 683735#L1327-3 assume !(1 == ~T5_E~0); 683729#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 683723#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 683716#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 683711#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 683704#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 683695#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 683690#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 683685#L1367-3 assume !(1 == ~E_1~0); 683679#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 683674#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 683669#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 683663#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 683656#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 683629#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 683592#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 683587#L1407-3 assume !(1 == ~E_9~0); 683583#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 683579#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 683575#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 683569#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 683168#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 683161#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 683160#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 683158#L1787 assume !(0 == start_simulation_~tmp~3#1); 683154#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 683151#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 683138#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 683135#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 683134#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 683133#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 683115#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 683102#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 683098#L1768-2 [2023-11-26 10:50:26,811 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:26,811 INFO L85 PathProgramCache]: Analyzing trace with hash 339991860, now seen corresponding path program 1 times [2023-11-26 10:50:26,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:26,812 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1701273484] [2023-11-26 10:50:26,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:26,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:26,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:26,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:26,901 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:26,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1701273484] [2023-11-26 10:50:26,901 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1701273484] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:26,901 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:26,902 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:50:26,902 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [255298556] [2023-11-26 10:50:26,902 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:26,903 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:26,903 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:26,903 INFO L85 PathProgramCache]: Analyzing trace with hash 106516448, now seen corresponding path program 1 times [2023-11-26 10:50:26,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:26,904 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1633447283] [2023-11-26 10:50:26,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:26,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:26,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:26,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:26,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:26,985 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1633447283] [2023-11-26 10:50:26,985 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1633447283] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:26,985 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:26,985 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:26,985 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556426295] [2023-11-26 10:50:26,986 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:26,986 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:26,986 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:26,987 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:26,987 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:26,987 INFO L87 Difference]: Start difference. First operand 161582 states and 230278 transitions. cyclomatic complexity: 68760 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:28,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-26 10:50:28,846 INFO L93 Difference]: Finished difference Result 309581 states and 439811 transitions. [2023-11-26 10:50:28,846 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 309581 states and 439811 transitions. [2023-11-26 10:50:30,646 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 308224 [2023-11-26 10:50:31,247 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 309581 states to 309581 states and 439811 transitions. [2023-11-26 10:50:31,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 309581 [2023-11-26 10:50:31,381 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 309581 [2023-11-26 10:50:31,381 INFO L73 IsDeterministic]: Start isDeterministic. Operand 309581 states and 439811 transitions. [2023-11-26 10:50:31,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-26 10:50:31,497 INFO L218 hiAutomatonCegarLoop]: Abstraction has 309581 states and 439811 transitions. [2023-11-26 10:50:31,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309581 states and 439811 transitions. [2023-11-26 10:50:35,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309581 to 309325. [2023-11-26 10:50:36,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 309325 states, 309325 states have (on average 1.4210134971308495) internal successors, (439555), 309324 states have internal predecessors, (439555), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-26 10:50:37,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 309325 states to 309325 states and 439555 transitions. [2023-11-26 10:50:37,280 INFO L240 hiAutomatonCegarLoop]: Abstraction has 309325 states and 439555 transitions. [2023-11-26 10:50:37,281 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-26 10:50:37,281 INFO L428 stractBuchiCegarLoop]: Abstraction has 309325 states and 439555 transitions. [2023-11-26 10:50:37,281 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-26 10:50:37,281 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 309325 states and 439555 transitions. [2023-11-26 10:50:38,928 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 307968 [2023-11-26 10:50:38,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-26 10:50:38,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-26 10:50:38,931 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:38,931 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-26 10:50:38,932 INFO L748 eck$LassoCheckResult]: Stem: 1144591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1144592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1145432#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1145433#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1145282#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 1145283#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1145391#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1145761#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1145933#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1145934#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1144568#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1144569#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1145840#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1145167#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1145168#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1145072#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1145073#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1145529#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1144804#L1174 assume !(0 == ~M_E~0); 1144805#L1174-2 assume !(0 == ~T1_E~0); 1144658#L1179-1 assume !(0 == ~T2_E~0); 1144565#L1184-1 assume !(0 == ~T3_E~0); 1144566#L1189-1 assume !(0 == ~T4_E~0); 1144608#L1194-1 assume !(0 == ~T5_E~0); 1144701#L1199-1 assume !(0 == ~T6_E~0); 1145674#L1204-1 assume !(0 == ~T7_E~0); 1145583#L1209-1 assume !(0 == ~T8_E~0); 1145584#L1214-1 assume !(0 == ~T9_E~0); 1146128#L1219-1 assume !(0 == ~T10_E~0); 1146320#L1224-1 assume !(0 == ~T11_E~0); 1144930#L1229-1 assume !(0 == ~T12_E~0); 1144496#L1234-1 assume !(0 == ~E_1~0); 1144497#L1239-1 assume !(0 == ~E_2~0); 1144530#L1244-1 assume !(0 == ~E_3~0); 1144531#L1249-1 assume !(0 == ~E_4~0); 1145198#L1254-1 assume !(0 == ~E_5~0); 1144429#L1259-1 assume !(0 == ~E_6~0); 1144386#L1264-1 assume !(0 == ~E_7~0); 1144387#L1269-1 assume !(0 == ~E_8~0); 1146349#L1274-1 assume !(0 == ~E_9~0); 1146182#L1279-1 assume !(0 == ~E_10~0); 1144611#L1284-1 assume !(0 == ~E_11~0); 1144612#L1289-1 assume !(0 == ~E_12~0); 1145253#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1145254#L566 assume !(1 == ~m_pc~0); 1145755#L566-2 is_master_triggered_~__retres1~0#1 := 0; 1145756#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1145299#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1145300#L1455 assume !(0 != activate_threads_~tmp~1#1); 1144831#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1144832#L585 assume !(1 == ~t1_pc~0); 1145015#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1145016#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1145745#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1145746#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 1146224#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1146220#L604 assume !(1 == ~t2_pc~0); 1145634#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1145635#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1144778#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1144779#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 1145885#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1145886#L623 assume !(1 == ~t3_pc~0); 1144361#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1144362#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1145718#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1145719#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 1145925#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1144400#L642 assume !(1 == ~t4_pc~0); 1144401#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1144844#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1144457#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1144458#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 1144473#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1145648#L661 assume !(1 == ~t5_pc~0); 1145846#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1145547#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1145548#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1146003#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 1145687#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1145688#L680 assume !(1 == ~t6_pc~0); 1145052#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1145053#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1144764#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1144765#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 1146017#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1146216#L699 assume !(1 == ~t7_pc~0); 1146217#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1145785#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1145786#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1145372#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 1145373#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1145255#L718 assume !(1 == ~t8_pc~0); 1145256#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1144606#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1144607#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1144638#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 1144639#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1144770#L737 assume !(1 == ~t9_pc~0); 1144909#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1144910#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1144811#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1144812#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 1145094#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1145095#L756 assume 1 == ~t10_pc~0; 1145773#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1145362#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1145668#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1145292#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 1144888#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1144889#L775 assume !(1 == ~t11_pc~0); 1145159#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1145160#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1146119#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1144540#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1144541#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1144719#L794 assume 1 == ~t12_pc~0; 1144564#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1144543#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1144405#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1144406#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 1144686#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1145175#L1307 assume !(1 == ~M_E~0); 1145176#L1307-2 assume !(1 == ~T1_E~0); 1145296#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1145210#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1145211#L1322-1 assume !(1 == ~T4_E~0); 1144899#L1327-1 assume !(1 == ~T5_E~0); 1144900#L1332-1 assume !(1 == ~T6_E~0); 1145505#L1337-1 assume !(1 == ~T7_E~0); 1145448#L1342-1 assume !(1 == ~T8_E~0); 1145449#L1347-1 assume !(1 == ~T9_E~0); 1145967#L1352-1 assume !(1 == ~T10_E~0); 1145787#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1145070#L1362-1 assume !(1 == ~T12_E~0); 1145071#L1367-1 assume !(1 == ~E_1~0); 1144702#L1372-1 assume !(1 == ~E_2~0); 1144703#L1377-1 assume !(1 == ~E_3~0); 1145000#L1382-1 assume !(1 == ~E_4~0); 1145001#L1387-1 assume !(1 == ~E_5~0); 1145636#L1392-1 assume !(1 == ~E_6~0); 1290788#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1290786#L1402-1 assume !(1 == ~E_8~0); 1290784#L1407-1 assume !(1 == ~E_9~0); 1290781#L1412-1 assume !(1 == ~E_10~0); 1216888#L1417-1 assume !(1 == ~E_11~0); 1216886#L1422-1 assume !(1 == ~E_12~0); 1192259#L1427-1 assume { :end_inline_reset_delta_events } true; 1192257#L1768-2 [2023-11-26 10:50:38,933 INFO L750 eck$LassoCheckResult]: Loop: 1192257#L1768-2 assume !false; 1192254#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1192249#L1149-1 assume !false; 1192247#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1192223#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1192217#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1192216#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1192214#L976 assume !(0 != eval_~tmp~0#1); 1192215#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1220727#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1220725#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1220723#L1174-5 assume !(0 == ~T1_E~0); 1220720#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1220718#L1184-3 assume !(0 == ~T3_E~0); 1220716#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1220714#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1220712#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1220710#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1220708#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1220706#L1214-3 assume !(0 == ~T9_E~0); 1220704#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1220702#L1224-3 assume !(0 == ~T11_E~0); 1220700#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1220698#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1220695#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1220693#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1220691#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1220689#L1254-3 assume !(0 == ~E_5~0); 1220687#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1220686#L1264-3 assume !(0 == ~E_7~0); 1220685#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1220684#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1220683#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1220682#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1220681#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1220680#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1220679#L566-39 assume !(1 == ~m_pc~0); 1220678#L566-41 is_master_triggered_~__retres1~0#1 := 0; 1220677#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1220676#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1220675#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1220674#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1220673#L585-39 assume !(1 == ~t1_pc~0); 1220672#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1220671#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1220670#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1220669#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1220667#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1220666#L604-39 assume !(1 == ~t2_pc~0); 1220664#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1220662#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1220660#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1220659#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 1220657#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1220656#L623-39 assume !(1 == ~t3_pc~0); 1220655#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1220653#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1220651#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1220649#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1220647#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1220645#L642-39 assume 1 == ~t4_pc~0; 1220642#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1220640#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1220638#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1220636#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1220634#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1220632#L661-39 assume !(1 == ~t5_pc~0); 1220630#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1220626#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1220624#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1220622#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1220620#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1220617#L680-39 assume 1 == ~t6_pc~0; 1220614#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1220612#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1220610#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1220608#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 1220606#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1220604#L699-39 assume !(1 == ~t7_pc~0); 1217429#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1220601#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1220598#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1220596#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1220594#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1220592#L718-39 assume !(1 == ~t8_pc~0); 1220590#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 1220587#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1220585#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1220583#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1220581#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1220579#L737-39 assume !(1 == ~t9_pc~0); 1220577#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1220575#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1220572#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1220570#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1220568#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1220566#L756-39 assume !(1 == ~t10_pc~0); 1220563#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1220561#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1220560#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1220558#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1220556#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1220554#L775-39 assume 1 == ~t11_pc~0; 1220551#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1220549#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1220546#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1220544#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1220542#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1220540#L794-39 assume 1 == ~t12_pc~0; 1220538#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1220535#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1220533#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1220531#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1220529#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1220527#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1220525#L1307-5 assume !(1 == ~T1_E~0); 1220523#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1192778#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1220519#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1220517#L1327-3 assume !(1 == ~T5_E~0); 1220515#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1220513#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1220511#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1220508#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1192762#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1220505#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1220504#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1220503#L1367-3 assume !(1 == ~E_1~0); 1220502#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1220501#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1220500#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1220499#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1216523#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1220497#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1220495#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1220493#L1407-3 assume !(1 == ~E_9~0); 1220491#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1220489#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1220487#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1220485#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1192305#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1192296#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1192294#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1192291#L1787 assume !(0 == start_simulation_~tmp~3#1); 1192289#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1192285#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1192271#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1192268#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1192266#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1192264#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1192262#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1192260#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 1192257#L1768-2 [2023-11-26 10:50:38,934 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:38,934 INFO L85 PathProgramCache]: Analyzing trace with hash -1390345197, now seen corresponding path program 1 times [2023-11-26 10:50:38,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:38,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381196851] [2023-11-26 10:50:38,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:38,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:38,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:39,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:39,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:39,009 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1381196851] [2023-11-26 10:50:39,009 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1381196851] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:39,009 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:39,009 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-26 10:50:39,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1565467245] [2023-11-26 10:50:39,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:39,010 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-26 10:50:39,010 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-26 10:50:39,011 INFO L85 PathProgramCache]: Analyzing trace with hash -74600932, now seen corresponding path program 1 times [2023-11-26 10:50:39,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-26 10:50:39,011 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684669535] [2023-11-26 10:50:39,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-26 10:50:39,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-26 10:50:39,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-26 10:50:39,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-26 10:50:39,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-26 10:50:39,065 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684669535] [2023-11-26 10:50:39,065 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684669535] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-26 10:50:39,065 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-26 10:50:39,065 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-26 10:50:39,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845138015] [2023-11-26 10:50:39,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-26 10:50:39,066 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-26 10:50:39,066 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-26 10:50:39,067 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-26 10:50:39,067 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-26 10:50:39,067 INFO L87 Difference]: Start difference. First operand 309325 states and 439555 transitions. cyclomatic complexity: 130358 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)