./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/kundu.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/kundu.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-29 02:22:53,692 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-29 02:22:53,764 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-29 02:22:53,768 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-29 02:22:53,769 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-29 02:22:53,790 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-29 02:22:53,791 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-29 02:22:53,791 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-29 02:22:53,792 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-29 02:22:53,792 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-29 02:22:53,793 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-29 02:22:53,794 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-29 02:22:53,794 INFO L153 SettingsManager]: * Use SBE=true [2023-11-29 02:22:53,795 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-29 02:22:53,795 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-29 02:22:53,796 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-29 02:22:53,796 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-29 02:22:53,797 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-29 02:22:53,797 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-29 02:22:53,798 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-29 02:22:53,798 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-29 02:22:53,799 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-29 02:22:53,800 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-29 02:22:53,800 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-29 02:22:53,800 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-29 02:22:53,801 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-29 02:22:53,801 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-29 02:22:53,802 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-29 02:22:53,802 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-29 02:22:53,802 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-29 02:22:53,803 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-29 02:22:53,803 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-29 02:22:53,803 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-29 02:22:53,804 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-29 02:22:53,804 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-29 02:22:53,804 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-29 02:22:53,804 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-29 02:22:53,805 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-29 02:22:53,805 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb [2023-11-29 02:22:54,044 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-29 02:22:54,063 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-29 02:22:54,066 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-29 02:22:54,067 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-29 02:22:54,067 INFO L274 PluginConnector]: CDTParser initialized [2023-11-29 02:22:54,068 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/kundu.cil.c [2023-11-29 02:22:56,816 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-29 02:22:56,996 INFO L384 CDTParser]: Found 1 translation units. [2023-11-29 02:22:56,996 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/sv-benchmarks/c/systemc/kundu.cil.c [2023-11-29 02:22:57,007 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/data/4e111df19/bf2b1e1194c64cff94794e931ea807ac/FLAG2eb26ff40 [2023-11-29 02:22:57,020 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/data/4e111df19/bf2b1e1194c64cff94794e931ea807ac [2023-11-29 02:22:57,022 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-29 02:22:57,023 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-29 02:22:57,024 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-29 02:22:57,024 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-29 02:22:57,028 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-29 02:22:57,029 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 02:22:57" (1/1) ... [2023-11-29 02:22:57,030 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@37aa725c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57, skipping insertion in model container [2023-11-29 02:22:57,030 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 02:22:57" (1/1) ... [2023-11-29 02:22:57,068 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-29 02:22:57,262 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 02:22:57,276 INFO L202 MainTranslator]: Completed pre-run [2023-11-29 02:22:57,311 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 02:22:57,326 INFO L206 MainTranslator]: Completed translation [2023-11-29 02:22:57,326 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57 WrapperNode [2023-11-29 02:22:57,326 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-29 02:22:57,327 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-29 02:22:57,327 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-29 02:22:57,327 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-29 02:22:57,334 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57" (1/1) ... [2023-11-29 02:22:57,342 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57" (1/1) ... [2023-11-29 02:22:57,373 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 49, statements flattened = 540 [2023-11-29 02:22:57,374 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-29 02:22:57,375 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-29 02:22:57,375 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-29 02:22:57,375 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-29 02:22:57,386 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57" (1/1) ... [2023-11-29 02:22:57,386 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57" (1/1) ... [2023-11-29 02:22:57,390 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57" (1/1) ... [2023-11-29 02:22:57,401 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-29 02:22:57,401 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57" (1/1) ... [2023-11-29 02:22:57,401 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57" (1/1) ... [2023-11-29 02:22:57,408 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57" (1/1) ... [2023-11-29 02:22:57,415 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57" (1/1) ... [2023-11-29 02:22:57,417 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57" (1/1) ... [2023-11-29 02:22:57,420 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57" (1/1) ... [2023-11-29 02:22:57,424 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-29 02:22:57,425 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-29 02:22:57,425 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-29 02:22:57,426 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-29 02:22:57,426 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57" (1/1) ... [2023-11-29 02:22:57,432 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:22:57,445 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:22:57,459 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:22:57,464 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-29 02:22:57,494 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-29 02:22:57,494 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-29 02:22:57,494 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-29 02:22:57,494 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-29 02:22:57,573 INFO L241 CfgBuilder]: Building ICFG [2023-11-29 02:22:57,575 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-29 02:22:57,988 INFO L282 CfgBuilder]: Performing block encoding [2023-11-29 02:22:58,002 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-29 02:22:58,002 INFO L309 CfgBuilder]: Removed 5 assume(true) statements. [2023-11-29 02:22:58,004 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 02:22:58 BoogieIcfgContainer [2023-11-29 02:22:58,004 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-29 02:22:58,005 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-29 02:22:58,005 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-29 02:22:58,009 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-29 02:22:58,010 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 02:22:58,010 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.11 02:22:57" (1/3) ... [2023-11-29 02:22:58,011 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@779352c0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 02:22:58, skipping insertion in model container [2023-11-29 02:22:58,011 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 02:22:58,011 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:22:57" (2/3) ... [2023-11-29 02:22:58,012 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@779352c0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 02:22:58, skipping insertion in model container [2023-11-29 02:22:58,012 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 02:22:58,012 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 02:22:58" (3/3) ... [2023-11-29 02:22:58,013 INFO L332 chiAutomizerObserver]: Analyzing ICFG kundu.cil.c [2023-11-29 02:22:58,068 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-29 02:22:58,068 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-29 02:22:58,068 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-29 02:22:58,068 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-29 02:22:58,068 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-29 02:22:58,068 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-29 02:22:58,069 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-29 02:22:58,069 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-29 02:22:58,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 195 states, 194 states have (on average 1.4948453608247423) internal successors, (290), 194 states have internal predecessors, (290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:22:58,101 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 158 [2023-11-29 02:22:58,101 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:22:58,101 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:22:58,109 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:58,109 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:58,109 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-29 02:22:58,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 195 states, 194 states have (on average 1.4948453608247423) internal successors, (290), 194 states have internal predecessors, (290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:22:58,121 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 158 [2023-11-29 02:22:58,121 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:22:58,121 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:22:58,123 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:58,124 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:58,132 INFO L748 eck$LassoCheckResult]: Stem: 128#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 136#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 190#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 134#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 146#L305true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 184#L305-2true assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 152#L310-1true assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 186#L315-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76#fire_delta_events_returnLabel#1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 165#L118true assume !(1 == ~P_1_pc~0); 54#L118-2true is_P_1_triggered_~__retres1~0#1 := 0; 181#L129true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 47#is_P_1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4#L491true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 185#L491-2true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 58#L186true assume 1 == ~P_2_pc~0; 95#L187true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 60#L197true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 89#is_P_2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 45#L499true assume !(0 != activate_threads_~tmp___0~1#1); 143#L499-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 120#L268true assume 1 == ~C_1_pc~0; 56#L269true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 132#L289true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 189#is_C_1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 121#L507true assume !(0 != activate_threads_~tmp___1~1#1); 30#L507-2true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 179#reset_delta_events_returnLabel#1true assume { :end_inline_reset_delta_events } true; 39#L561-2true [2023-11-29 02:22:58,133 INFO L750 eck$LassoCheckResult]: Loop: 39#L561-2true assume !false; 157#L562true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 97#L397true assume false; 67#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 90#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40#fire_delta_events_returnLabel#2true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 182#L118-6true assume !(1 == ~P_1_pc~0); 5#L118-8true is_P_1_triggered_~__retres1~0#1 := 0; 16#L129-2true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 42#is_P_1_triggered_returnLabel#3true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 83#L491-6true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 28#L491-8true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 57#L186-6true assume !(1 == ~P_2_pc~0); 29#L186-8true is_P_2_triggered_~__retres1~1#1 := 0; 178#L197-2true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 193#is_P_2_triggered_returnLabel#3true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 129#L499-6true assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 127#L499-8true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 11#L268-6true assume 1 == ~C_1_pc~0; 102#L269-2true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 117#L289-2true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 99#is_C_1_triggered_returnLabel#3true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22#L507-6true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 161#L507-8true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78#reset_delta_events_returnLabel#2true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 62#L328-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 66#L345-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 167#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2#L580true assume !(0 == start_simulation_~tmp~3#1); 13#L580-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 59#L328-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 183#L345-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 35#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 160#L535true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 111#L542true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 104#stop_simulation_returnLabel#1true start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 63#L593true assume !(0 != start_simulation_~tmp___0~2#1); 39#L561-2true [2023-11-29 02:22:58,139 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:22:58,139 INFO L85 PathProgramCache]: Analyzing trace with hash 1332213672, now seen corresponding path program 1 times [2023-11-29 02:22:58,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:22:58,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322566114] [2023-11-29 02:22:58,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:22:58,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:22:58,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:22:58,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:22:58,332 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:22:58,332 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [322566114] [2023-11-29 02:22:58,333 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [322566114] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:22:58,333 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:22:58,333 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:22:58,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [884609941] [2023-11-29 02:22:58,337 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:22:58,342 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:22:58,343 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:22:58,343 INFO L85 PathProgramCache]: Analyzing trace with hash -1388386939, now seen corresponding path program 1 times [2023-11-29 02:22:58,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:22:58,343 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [711270333] [2023-11-29 02:22:58,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:22:58,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:22:58,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:22:58,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:22:58,370 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:22:58,370 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [711270333] [2023-11-29 02:22:58,370 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [711270333] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:22:58,371 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:22:58,371 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 02:22:58,371 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96708133] [2023-11-29 02:22:58,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:22:58,372 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:22:58,373 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:22:58,401 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:22:58,401 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:22:58,404 INFO L87 Difference]: Start difference. First operand has 195 states, 194 states have (on average 1.4948453608247423) internal successors, (290), 194 states have internal predecessors, (290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:22:58,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:22:58,436 INFO L93 Difference]: Finished difference Result 187 states and 270 transitions. [2023-11-29 02:22:58,437 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 187 states and 270 transitions. [2023-11-29 02:22:58,442 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2023-11-29 02:22:58,449 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 187 states to 179 states and 262 transitions. [2023-11-29 02:22:58,450 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179 [2023-11-29 02:22:58,451 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179 [2023-11-29 02:22:58,451 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179 states and 262 transitions. [2023-11-29 02:22:58,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:22:58,453 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179 states and 262 transitions. [2023-11-29 02:22:58,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states and 262 transitions. [2023-11-29 02:22:58,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2023-11-29 02:22:58,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 179 states have (on average 1.4636871508379887) internal successors, (262), 178 states have internal predecessors, (262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:22:58,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 262 transitions. [2023-11-29 02:22:58,492 INFO L240 hiAutomatonCegarLoop]: Abstraction has 179 states and 262 transitions. [2023-11-29 02:22:58,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:22:58,496 INFO L428 stractBuchiCegarLoop]: Abstraction has 179 states and 262 transitions. [2023-11-29 02:22:58,497 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-29 02:22:58,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179 states and 262 transitions. [2023-11-29 02:22:58,499 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2023-11-29 02:22:58,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:22:58,500 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:22:58,501 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:58,501 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:58,502 INFO L748 eck$LassoCheckResult]: Stem: 490#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 491#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 516#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 508#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 509#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 536#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 549#L310-1 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 550#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 561#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 559#L118 assume !(1 == ~P_1_pc~0); 530#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 531#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 526#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 400#L491 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 401#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 538#L186 assume 1 == ~P_2_pc~0; 539#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 423#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 543#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 522#L499 assume !(0 != activate_threads_~tmp___0~1#1); 523#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 465#L268 assume 1 == ~C_1_pc~0; 467#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 500#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 501#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 468#L507 assume !(0 != activate_threads_~tmp___1~1#1); 469#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 482#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 511#L561-2 [2023-11-29 02:22:58,502 INFO L750 eck$LassoCheckResult]: Loop: 511#L561-2 assume !false; 512#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 418#L397 assume !false; 441#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 442#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 484#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 437#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 438#L362 assume !(0 != eval_~tmp___2~0#1); 554#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 513#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 514#L118-6 assume !(1 == ~P_1_pc~0); 402#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 403#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 436#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 518#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 476#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 477#L186-6 assume 1 == ~P_2_pc~0; 537#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 479#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 569#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 492#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 489#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 426#L268-6 assume 1 == ~C_1_pc~0; 427#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 443#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 444#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 458#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 459#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 556#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 547#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 405#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 552#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 391#L580 assume !(0 == start_simulation_~tmp~3#1); 392#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 433#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 541#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 502#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 503#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 411#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 412#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 548#L593 assume !(0 != start_simulation_~tmp___0~2#1); 511#L561-2 [2023-11-29 02:22:58,503 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:22:58,503 INFO L85 PathProgramCache]: Analyzing trace with hash 1466227178, now seen corresponding path program 1 times [2023-11-29 02:22:58,503 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:22:58,504 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [733611861] [2023-11-29 02:22:58,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:22:58,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:22:58,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:22:58,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:22:58,567 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:22:58,567 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [733611861] [2023-11-29 02:22:58,568 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [733611861] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:22:58,568 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:22:58,568 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:22:58,568 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [797092890] [2023-11-29 02:22:58,568 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:22:58,569 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:22:58,569 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:22:58,570 INFO L85 PathProgramCache]: Analyzing trace with hash 169210142, now seen corresponding path program 1 times [2023-11-29 02:22:58,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:22:58,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964763770] [2023-11-29 02:22:58,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:22:58,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:22:58,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:22:58,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:22:58,666 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:22:58,666 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1964763770] [2023-11-29 02:22:58,667 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1964763770] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:22:58,667 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:22:58,667 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:22:58,667 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1384791376] [2023-11-29 02:22:58,667 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:22:58,668 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:22:58,668 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:22:58,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:22:58,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:22:58,669 INFO L87 Difference]: Start difference. First operand 179 states and 262 transitions. cyclomatic complexity: 84 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:22:58,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:22:58,687 INFO L93 Difference]: Finished difference Result 179 states and 261 transitions. [2023-11-29 02:22:58,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179 states and 261 transitions. [2023-11-29 02:22:58,689 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2023-11-29 02:22:58,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179 states to 179 states and 261 transitions. [2023-11-29 02:22:58,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179 [2023-11-29 02:22:58,692 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179 [2023-11-29 02:22:58,693 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179 states and 261 transitions. [2023-11-29 02:22:58,694 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:22:58,694 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179 states and 261 transitions. [2023-11-29 02:22:58,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states and 261 transitions. [2023-11-29 02:22:58,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2023-11-29 02:22:58,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 179 states have (on average 1.458100558659218) internal successors, (261), 178 states have internal predecessors, (261), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:22:58,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 261 transitions. [2023-11-29 02:22:58,704 INFO L240 hiAutomatonCegarLoop]: Abstraction has 179 states and 261 transitions. [2023-11-29 02:22:58,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:22:58,705 INFO L428 stractBuchiCegarLoop]: Abstraction has 179 states and 261 transitions. [2023-11-29 02:22:58,706 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-29 02:22:58,706 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179 states and 261 transitions. [2023-11-29 02:22:58,707 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 146 [2023-11-29 02:22:58,707 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:22:58,708 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:22:58,709 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:58,709 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:58,709 INFO L748 eck$LassoCheckResult]: Stem: 857#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 882#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 874#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 875#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 903#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 916#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 917#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 928#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 926#L118 assume !(1 == ~P_1_pc~0); 897#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 898#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 893#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 765#L491 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 766#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 905#L186 assume 1 == ~P_2_pc~0; 906#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 785#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 910#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 888#L499 assume !(0 != activate_threads_~tmp___0~1#1); 889#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 831#L268 assume 1 == ~C_1_pc~0; 833#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 867#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 868#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 834#L507 assume !(0 != activate_threads_~tmp___1~1#1); 835#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 847#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 877#L561-2 [2023-11-29 02:22:58,710 INFO L750 eck$LassoCheckResult]: Loop: 877#L561-2 assume !false; 878#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 787#L397 assume !false; 806#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 807#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 849#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 803#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 804#L362 assume !(0 != eval_~tmp___2~0#1); 921#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 922#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 880#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 881#L118-6 assume !(1 == ~P_1_pc~0); 769#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 770#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 805#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 885#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 843#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 844#L186-6 assume 1 == ~P_2_pc~0; 904#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 846#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 936#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 859#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 856#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 793#L268-6 assume 1 == ~C_1_pc~0; 794#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 810#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 811#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 825#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 826#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 923#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 914#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 772#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 919#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 758#L580 assume !(0 == start_simulation_~tmp~3#1); 759#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 800#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 908#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 869#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 870#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 778#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 779#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 915#L593 assume !(0 != start_simulation_~tmp___0~2#1); 877#L561-2 [2023-11-29 02:22:58,710 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:22:58,710 INFO L85 PathProgramCache]: Analyzing trace with hash 1247372460, now seen corresponding path program 1 times [2023-11-29 02:22:58,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:22:58,711 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782515] [2023-11-29 02:22:58,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:22:58,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:22:58,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:22:58,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:22:58,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:22:58,791 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782515] [2023-11-29 02:22:58,791 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [782515] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:22:58,792 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:22:58,792 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:22:58,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [124418471] [2023-11-29 02:22:58,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:22:58,793 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:22:58,793 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:22:58,794 INFO L85 PathProgramCache]: Analyzing trace with hash 169210142, now seen corresponding path program 2 times [2023-11-29 02:22:58,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:22:58,794 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [484733194] [2023-11-29 02:22:58,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:22:58,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:22:58,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:22:58,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:22:58,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:22:58,906 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [484733194] [2023-11-29 02:22:58,906 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [484733194] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:22:58,907 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:22:58,907 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:22:58,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1130355373] [2023-11-29 02:22:58,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:22:58,907 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:22:58,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:22:58,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 02:22:58,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 02:22:58,909 INFO L87 Difference]: Start difference. First operand 179 states and 261 transitions. cyclomatic complexity: 83 Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:22:59,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:22:59,056 INFO L93 Difference]: Finished difference Result 405 states and 588 transitions. [2023-11-29 02:22:59,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 405 states and 588 transitions. [2023-11-29 02:22:59,061 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 334 [2023-11-29 02:22:59,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 405 states to 405 states and 588 transitions. [2023-11-29 02:22:59,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 405 [2023-11-29 02:22:59,066 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 405 [2023-11-29 02:22:59,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 405 states and 588 transitions. [2023-11-29 02:22:59,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:22:59,069 INFO L218 hiAutomatonCegarLoop]: Abstraction has 405 states and 588 transitions. [2023-11-29 02:22:59,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 405 states and 588 transitions. [2023-11-29 02:22:59,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 405 to 191. [2023-11-29 02:22:59,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191 states, 191 states have (on average 1.4293193717277486) internal successors, (273), 190 states have internal predecessors, (273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:22:59,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 273 transitions. [2023-11-29 02:22:59,083 INFO L240 hiAutomatonCegarLoop]: Abstraction has 191 states and 273 transitions. [2023-11-29 02:22:59,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 02:22:59,084 INFO L428 stractBuchiCegarLoop]: Abstraction has 191 states and 273 transitions. [2023-11-29 02:22:59,084 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-29 02:22:59,084 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191 states and 273 transitions. [2023-11-29 02:22:59,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 155 [2023-11-29 02:22:59,086 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:22:59,086 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:22:59,087 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:59,087 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:59,088 INFO L748 eck$LassoCheckResult]: Stem: 1456#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1457#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1484#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1475#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1476#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1507#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1521#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1522#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1533#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1531#L118 assume !(1 == ~P_1_pc~0); 1501#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 1502#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1546#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1366#L491 assume !(0 != activate_threads_~tmp~1#1); 1367#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1509#L186 assume 1 == ~P_2_pc~0; 1510#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1389#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1515#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1492#L499 assume !(0 != activate_threads_~tmp___0~1#1); 1493#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1431#L268 assume 1 == ~C_1_pc~0; 1433#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1467#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1468#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1434#L507 assume !(0 != activate_threads_~tmp___1~1#1); 1435#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1451#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 1478#L561-2 [2023-11-29 02:22:59,088 INFO L750 eck$LassoCheckResult]: Loop: 1478#L561-2 assume !false; 1479#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1384#L397 assume !false; 1405#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1406#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1447#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1402#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1403#L362 assume !(0 != eval_~tmp___2~0#1); 1526#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1527#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1481#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1482#L118-6 assume 1 == ~P_1_pc~0; 1490#L119-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 1491#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1486#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1487#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 1442#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1443#L186-6 assume !(1 == ~P_2_pc~0); 1444#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 1445#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1545#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1458#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1455#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1392#L268-6 assume 1 == ~C_1_pc~0; 1393#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1409#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1410#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1424#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1425#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1528#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1519#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1371#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1524#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1357#L580 assume !(0 == start_simulation_~tmp~3#1); 1358#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1399#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1513#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1469#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1470#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1377#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1378#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1520#L593 assume !(0 != start_simulation_~tmp___0~2#1); 1478#L561-2 [2023-11-29 02:22:59,088 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:22:59,088 INFO L85 PathProgramCache]: Analyzing trace with hash -32491218, now seen corresponding path program 1 times [2023-11-29 02:22:59,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:22:59,089 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715920895] [2023-11-29 02:22:59,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:22:59,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:22:59,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:22:59,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:22:59,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:22:59,142 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715920895] [2023-11-29 02:22:59,142 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1715920895] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:22:59,142 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:22:59,142 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 02:22:59,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [510591620] [2023-11-29 02:22:59,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:22:59,143 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:22:59,143 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:22:59,143 INFO L85 PathProgramCache]: Analyzing trace with hash -116922914, now seen corresponding path program 1 times [2023-11-29 02:22:59,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:22:59,144 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10674856] [2023-11-29 02:22:59,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:22:59,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:22:59,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:22:59,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:22:59,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:22:59,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10674856] [2023-11-29 02:22:59,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10674856] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:22:59,197 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:22:59,197 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:22:59,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [157768611] [2023-11-29 02:22:59,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:22:59,198 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:22:59,198 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:22:59,199 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 02:22:59,199 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 02:22:59,199 INFO L87 Difference]: Start difference. First operand 191 states and 273 transitions. cyclomatic complexity: 83 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:22:59,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:22:59,315 INFO L93 Difference]: Finished difference Result 478 states and 671 transitions. [2023-11-29 02:22:59,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 478 states and 671 transitions. [2023-11-29 02:22:59,321 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 415 [2023-11-29 02:22:59,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 478 states to 478 states and 671 transitions. [2023-11-29 02:22:59,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 478 [2023-11-29 02:22:59,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 478 [2023-11-29 02:22:59,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 478 states and 671 transitions. [2023-11-29 02:22:59,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:22:59,328 INFO L218 hiAutomatonCegarLoop]: Abstraction has 478 states and 671 transitions. [2023-11-29 02:22:59,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states and 671 transitions. [2023-11-29 02:22:59,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 436. [2023-11-29 02:22:59,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 436 states, 436 states have (on average 1.4128440366972477) internal successors, (616), 435 states have internal predecessors, (616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:22:59,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 616 transitions. [2023-11-29 02:22:59,351 INFO L240 hiAutomatonCegarLoop]: Abstraction has 436 states and 616 transitions. [2023-11-29 02:22:59,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 02:22:59,352 INFO L428 stractBuchiCegarLoop]: Abstraction has 436 states and 616 transitions. [2023-11-29 02:22:59,352 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-29 02:22:59,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 436 states and 616 transitions. [2023-11-29 02:22:59,356 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 399 [2023-11-29 02:22:59,356 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:22:59,356 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:22:59,358 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:59,358 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:59,358 INFO L748 eck$LassoCheckResult]: Stem: 2140#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 2141#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 2165#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2157#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2158#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 2190#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 2202#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 2203#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2217#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2216#L118 assume !(1 == ~P_1_pc~0); 2184#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 2185#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2178#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2046#L491 assume !(0 != activate_threads_~tmp~1#1); 2047#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2191#L186 assume !(1 == ~P_2_pc~0); 2065#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 2066#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2195#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2171#L499 assume !(0 != activate_threads_~tmp___0~1#1); 2172#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2114#L268 assume 1 == ~C_1_pc~0; 2116#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2150#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2151#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2117#L507 assume !(0 != activate_threads_~tmp___1~1#1); 2118#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2130#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 2160#L561-2 [2023-11-29 02:22:59,359 INFO L750 eck$LassoCheckResult]: Loop: 2160#L561-2 assume !false; 2161#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2068#L397 assume !false; 2089#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2090#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2132#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2086#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2087#L362 assume !(0 != eval_~tmp___2~0#1); 2210#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2211#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2163#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2164#L118-6 assume !(1 == ~P_1_pc~0); 2050#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 2051#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2088#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2168#L491-6 assume !(0 != activate_threads_~tmp~1#1); 2126#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2127#L186-6 assume !(1 == ~P_2_pc~0); 2128#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 2129#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2229#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2142#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 2139#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2075#L268-6 assume 1 == ~C_1_pc~0; 2076#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2093#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2094#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2108#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 2109#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2212#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2199#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2053#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2205#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2039#L580 assume !(0 == start_simulation_~tmp~3#1); 2040#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2457#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2453#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2152#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2153#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2059#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2060#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2200#L593 assume !(0 != start_simulation_~tmp___0~2#1); 2160#L561-2 [2023-11-29 02:22:59,359 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:22:59,359 INFO L85 PathProgramCache]: Analyzing trace with hash -1311815953, now seen corresponding path program 1 times [2023-11-29 02:22:59,360 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:22:59,360 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965750615] [2023-11-29 02:22:59,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:22:59,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:22:59,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:22:59,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:22:59,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:22:59,419 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1965750615] [2023-11-29 02:22:59,420 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1965750615] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:22:59,420 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:22:59,420 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 02:22:59,420 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443027013] [2023-11-29 02:22:59,420 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:22:59,421 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:22:59,421 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:22:59,421 INFO L85 PathProgramCache]: Analyzing trace with hash 34834145, now seen corresponding path program 1 times [2023-11-29 02:22:59,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:22:59,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265706610] [2023-11-29 02:22:59,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:22:59,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:22:59,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:22:59,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:22:59,478 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:22:59,478 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265706610] [2023-11-29 02:22:59,478 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1265706610] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:22:59,478 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:22:59,479 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:22:59,479 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435507642] [2023-11-29 02:22:59,479 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:22:59,479 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:22:59,479 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:22:59,480 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 02:22:59,480 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 02:22:59,480 INFO L87 Difference]: Start difference. First operand 436 states and 616 transitions. cyclomatic complexity: 182 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:22:59,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:22:59,633 INFO L93 Difference]: Finished difference Result 1188 states and 1642 transitions. [2023-11-29 02:22:59,634 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1188 states and 1642 transitions. [2023-11-29 02:22:59,647 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1108 [2023-11-29 02:22:59,659 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1188 states to 1188 states and 1642 transitions. [2023-11-29 02:22:59,660 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1188 [2023-11-29 02:22:59,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1188 [2023-11-29 02:22:59,662 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1188 states and 1642 transitions. [2023-11-29 02:22:59,664 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:22:59,664 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1188 states and 1642 transitions. [2023-11-29 02:22:59,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1188 states and 1642 transitions. [2023-11-29 02:22:59,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1188 to 1129. [2023-11-29 02:22:59,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1129 states, 1129 states have (on average 1.3906111603188662) internal successors, (1570), 1128 states have internal predecessors, (1570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:22:59,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1129 states to 1129 states and 1570 transitions. [2023-11-29 02:22:59,700 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1129 states and 1570 transitions. [2023-11-29 02:22:59,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 02:22:59,701 INFO L428 stractBuchiCegarLoop]: Abstraction has 1129 states and 1570 transitions. [2023-11-29 02:22:59,702 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-29 02:22:59,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1129 states and 1570 transitions. [2023-11-29 02:22:59,711 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1087 [2023-11-29 02:22:59,711 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:22:59,711 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:22:59,712 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:59,712 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:59,713 INFO L748 eck$LassoCheckResult]: Stem: 3777#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 3778#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 3804#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3796#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3797#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3831#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 3844#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3845#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3862#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3861#L118 assume !(1 == ~P_1_pc~0); 3825#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 3826#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3819#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3683#L491 assume !(0 != activate_threads_~tmp~1#1); 3684#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3832#L186 assume !(1 == ~P_2_pc~0); 3702#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 3703#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3836#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3812#L499 assume !(0 != activate_threads_~tmp___0~1#1); 3813#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3751#L268 assume !(1 == ~C_1_pc~0); 3752#L268-2 assume 2 == ~C_1_pc~0; 3822#L279 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3788#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3789#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3753#L507 assume !(0 != activate_threads_~tmp___1~1#1); 3754#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3767#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 3880#L561-2 [2023-11-29 02:22:59,713 INFO L750 eck$LassoCheckResult]: Loop: 3880#L561-2 assume !false; 4652#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 3705#L397 assume !false; 4645#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3871#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3769#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3722#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3723#L362 assume !(0 != eval_~tmp___2~0#1); 3888#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4774#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4772#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4770#L118-6 assume !(1 == ~P_1_pc~0); 4768#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 4767#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 4766#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4759#L491-6 assume !(0 != activate_threads_~tmp~1#1); 4758#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 4748#L186-6 assume !(1 == ~P_2_pc~0); 4747#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 4746#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 4745#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4744#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 4743#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 4742#L268-6 assume !(1 == ~C_1_pc~0); 4741#L268-8 assume !(2 == ~C_1_pc~0); 4739#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 4738#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 4737#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4736#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 4735#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4734#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4731#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3847#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3848#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3676#L580 assume !(0 == start_simulation_~tmp~3#1); 3677#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3719#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3834#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3790#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3791#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3696#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3697#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4659#L593 assume !(0 != start_simulation_~tmp___0~2#1); 3880#L561-2 [2023-11-29 02:22:59,714 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:22:59,714 INFO L85 PathProgramCache]: Analyzing trace with hash -122788309, now seen corresponding path program 1 times [2023-11-29 02:22:59,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:22:59,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808100829] [2023-11-29 02:22:59,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:22:59,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:22:59,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:22:59,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:22:59,779 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:22:59,779 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808100829] [2023-11-29 02:22:59,779 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [808100829] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:22:59,779 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:22:59,779 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:22:59,780 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1975113745] [2023-11-29 02:22:59,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:22:59,780 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:22:59,780 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:22:59,781 INFO L85 PathProgramCache]: Analyzing trace with hash -597585727, now seen corresponding path program 1 times [2023-11-29 02:22:59,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:22:59,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2090444427] [2023-11-29 02:22:59,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:22:59,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:22:59,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:22:59,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:22:59,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:22:59,833 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2090444427] [2023-11-29 02:22:59,833 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2090444427] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:22:59,833 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:22:59,833 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:22:59,833 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1874390240] [2023-11-29 02:22:59,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:22:59,834 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:22:59,834 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:22:59,835 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:22:59,835 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:22:59,835 INFO L87 Difference]: Start difference. First operand 1129 states and 1570 transitions. cyclomatic complexity: 445 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:22:59,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:22:59,899 INFO L93 Difference]: Finished difference Result 1500 states and 2055 transitions. [2023-11-29 02:22:59,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1500 states and 2055 transitions. [2023-11-29 02:22:59,914 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1453 [2023-11-29 02:22:59,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1500 states to 1500 states and 2055 transitions. [2023-11-29 02:22:59,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1500 [2023-11-29 02:22:59,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1500 [2023-11-29 02:22:59,932 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1500 states and 2055 transitions. [2023-11-29 02:22:59,935 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:22:59,936 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1500 states and 2055 transitions. [2023-11-29 02:22:59,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1500 states and 2055 transitions. [2023-11-29 02:22:59,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1500 to 1476. [2023-11-29 02:22:59,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.3719512195121952) internal successors, (2025), 1475 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:22:59,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2025 transitions. [2023-11-29 02:22:59,976 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1476 states and 2025 transitions. [2023-11-29 02:22:59,977 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:22:59,978 INFO L428 stractBuchiCegarLoop]: Abstraction has 1476 states and 2025 transitions. [2023-11-29 02:22:59,978 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-29 02:22:59,978 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2025 transitions. [2023-11-29 02:22:59,988 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1429 [2023-11-29 02:22:59,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:22:59,989 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:22:59,990 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:59,990 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:22:59,990 INFO L748 eck$LassoCheckResult]: Stem: 6410#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 6411#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 6439#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6430#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6431#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 6468#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 6484#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 6485#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6500#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6499#L118 assume !(1 == ~P_1_pc~0); 6463#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 6464#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6455#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6321#L491 assume !(0 != activate_threads_~tmp~1#1); 6322#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6470#L186 assume !(1 == ~P_2_pc~0); 6339#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 6340#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6476#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6448#L499 assume !(0 != activate_threads_~tmp___0~1#1); 6449#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6384#L268 assume !(1 == ~C_1_pc~0); 6385#L268-2 assume !(2 == ~C_1_pc~0); 6508#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 6423#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6424#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6386#L507 assume !(0 != activate_threads_~tmp___1~1#1); 6387#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6399#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 6480#L561-2 [2023-11-29 02:22:59,991 INFO L750 eck$LassoCheckResult]: Loop: 6480#L561-2 assume !false; 6488#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 6342#L397 assume !false; 6359#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6360#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6401#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6356#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6357#L362 assume !(0 != eval_~tmp___2~0#1); 7716#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7787#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7786#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 7785#L118-6 assume !(1 == ~P_1_pc~0); 7784#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 7783#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 7782#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7781#L491-6 assume !(0 != activate_threads_~tmp~1#1); 7780#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 7779#L186-6 assume !(1 == ~P_2_pc~0); 7778#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 7777#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 7776#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7775#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 7774#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6347#L268-6 assume !(1 == ~C_1_pc~0); 6348#L268-8 assume !(2 == ~C_1_pc~0); 6459#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 6363#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6364#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7681#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 7682#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7748#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7744#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7741#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7740#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7738#L580 assume !(0 == start_simulation_~tmp~3#1); 7736#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6473#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6474#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6425#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6426#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 6333#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6334#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 6479#L593 assume !(0 != start_simulation_~tmp___0~2#1); 6480#L561-2 [2023-11-29 02:22:59,991 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:22:59,991 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 1 times [2023-11-29 02:22:59,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:22:59,992 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303068504] [2023-11-29 02:22:59,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:22:59,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:00,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:00,003 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:23:00,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:00,040 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:23:00,041 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:23:00,041 INFO L85 PathProgramCache]: Analyzing trace with hash -597585727, now seen corresponding path program 2 times [2023-11-29 02:23:00,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:23:00,041 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [211931246] [2023-11-29 02:23:00,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:23:00,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:00,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:23:00,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:23:00,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:23:00,101 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [211931246] [2023-11-29 02:23:00,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [211931246] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:23:00,102 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:23:00,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:23:00,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095956749] [2023-11-29 02:23:00,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:23:00,102 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:23:00,103 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:23:00,103 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 02:23:00,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 02:23:00,104 INFO L87 Difference]: Start difference. First operand 1476 states and 2025 transitions. cyclomatic complexity: 553 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:23:00,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:23:00,233 INFO L93 Difference]: Finished difference Result 2613 states and 3559 transitions. [2023-11-29 02:23:00,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2613 states and 3559 transitions. [2023-11-29 02:23:00,258 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2548 [2023-11-29 02:23:00,282 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2613 states to 2613 states and 3559 transitions. [2023-11-29 02:23:00,282 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2613 [2023-11-29 02:23:00,286 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2613 [2023-11-29 02:23:00,287 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2613 states and 3559 transitions. [2023-11-29 02:23:00,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:23:00,292 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2613 states and 3559 transitions. [2023-11-29 02:23:00,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2613 states and 3559 transitions. [2023-11-29 02:23:00,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2613 to 1512. [2023-11-29 02:23:00,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1512 states, 1512 states have (on average 1.3630952380952381) internal successors, (2061), 1511 states have internal predecessors, (2061), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:23:00,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1512 states to 1512 states and 2061 transitions. [2023-11-29 02:23:00,340 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1512 states and 2061 transitions. [2023-11-29 02:23:00,341 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-29 02:23:00,341 INFO L428 stractBuchiCegarLoop]: Abstraction has 1512 states and 2061 transitions. [2023-11-29 02:23:00,342 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-29 02:23:00,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1512 states and 2061 transitions. [2023-11-29 02:23:00,352 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1465 [2023-11-29 02:23:00,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:23:00,352 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:23:00,353 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:23:00,353 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:23:00,353 INFO L748 eck$LassoCheckResult]: Stem: 10519#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 10520#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 10549#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10540#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10541#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 10578#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 10594#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 10595#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10613#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10612#L118 assume !(1 == ~P_1_pc~0); 10573#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 10574#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10562#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10429#L491 assume !(0 != activate_threads_~tmp~1#1); 10430#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10582#L186 assume !(1 == ~P_2_pc~0); 10450#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 10451#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10587#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10558#L499 assume !(0 != activate_threads_~tmp___0~1#1); 10559#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10494#L268 assume !(1 == ~C_1_pc~0); 10495#L268-2 assume !(2 == ~C_1_pc~0); 10621#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 10532#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10533#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10496#L507 assume !(0 != activate_threads_~tmp___1~1#1); 10497#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10513#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 10636#L561-2 [2023-11-29 02:23:00,353 INFO L750 eck$LassoCheckResult]: Loop: 10636#L561-2 assume !false; 11892#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 10448#L397 assume !false; 11881#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11879#L328 assume !(0 == ~P_1_st~0); 11880#L332 assume !(0 == ~P_2_st~0); 11878#L336 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 11875#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11870#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11756#L362 assume !(0 != eval_~tmp___2~0#1); 10606#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10607#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10546#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10547#L118-6 assume !(1 == ~P_1_pc~0); 10431#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 10432#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10551#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10552#L491-6 assume !(0 != activate_threads_~tmp~1#1); 10504#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10505#L186-6 assume !(1 == ~P_2_pc~0); 10506#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 10507#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10660#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10661#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 10517#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10518#L268-6 assume !(1 == ~C_1_pc~0); 10604#L268-8 assume !(2 == ~C_1_pc~0); 10605#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 10471#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10472#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10486#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 10487#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10615#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10616#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11903#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11902#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 11901#L580 assume !(0 == start_simulation_~tmp~3#1); 10456#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10457#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11898#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11897#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 11896#L535 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 11895#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11894#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 11893#L593 assume !(0 != start_simulation_~tmp___0~2#1); 10636#L561-2 [2023-11-29 02:23:00,354 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:23:00,354 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 2 times [2023-11-29 02:23:00,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:23:00,354 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901955309] [2023-11-29 02:23:00,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:23:00,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:00,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:00,364 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:23:00,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:00,379 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:23:00,379 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:23:00,380 INFO L85 PathProgramCache]: Analyzing trace with hash 162746408, now seen corresponding path program 1 times [2023-11-29 02:23:00,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:23:00,380 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954537292] [2023-11-29 02:23:00,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:23:00,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:00,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:23:00,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:23:00,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:23:00,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [954537292] [2023-11-29 02:23:00,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [954537292] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:23:00,415 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:23:00,415 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:23:00,415 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [612534405] [2023-11-29 02:23:00,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:23:00,415 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:23:00,416 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:23:00,416 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:23:00,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:23:00,416 INFO L87 Difference]: Start difference. First operand 1512 states and 2061 transitions. cyclomatic complexity: 553 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:23:00,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:23:00,497 INFO L93 Difference]: Finished difference Result 2343 states and 3154 transitions. [2023-11-29 02:23:00,497 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2343 states and 3154 transitions. [2023-11-29 02:23:00,514 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2246 [2023-11-29 02:23:00,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2343 states to 2343 states and 3154 transitions. [2023-11-29 02:23:00,532 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2343 [2023-11-29 02:23:00,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2343 [2023-11-29 02:23:00,535 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2343 states and 3154 transitions. [2023-11-29 02:23:00,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:23:00,539 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2023-11-29 02:23:00,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2343 states and 3154 transitions. [2023-11-29 02:23:00,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2343 to 2343. [2023-11-29 02:23:00,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2343 states, 2343 states have (on average 1.3461374306444729) internal successors, (3154), 2342 states have internal predecessors, (3154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:23:00,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2343 states to 2343 states and 3154 transitions. [2023-11-29 02:23:00,595 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2023-11-29 02:23:00,596 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:23:00,596 INFO L428 stractBuchiCegarLoop]: Abstraction has 2343 states and 3154 transitions. [2023-11-29 02:23:00,597 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-29 02:23:00,597 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2343 states and 3154 transitions. [2023-11-29 02:23:00,611 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2246 [2023-11-29 02:23:00,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:23:00,611 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:23:00,612 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:23:00,612 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:23:00,612 INFO L748 eck$LassoCheckResult]: Stem: 14378#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 14379#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 14406#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14398#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14399#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 14433#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 14448#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 14449#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14470#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 14469#L118 assume !(1 == ~P_1_pc~0); 14428#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 14429#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 14420#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14290#L491 assume !(0 != activate_threads_~tmp~1#1); 14291#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 14436#L186 assume !(1 == ~P_2_pc~0); 14311#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 14312#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 14441#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14416#L499 assume !(0 != activate_threads_~tmp___0~1#1); 14417#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 14354#L268 assume !(1 == ~C_1_pc~0); 14355#L268-2 assume !(2 == ~C_1_pc~0); 14476#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 14390#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 14391#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14356#L507 assume !(0 != activate_threads_~tmp___1~1#1); 14357#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14373#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 14489#L561-2 assume !false; 16128#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 16123#L397 [2023-11-29 02:23:00,612 INFO L750 eck$LassoCheckResult]: Loop: 16123#L397 assume !false; 16118#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16115#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 16113#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16111#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16110#L362 assume 0 != eval_~tmp___2~0#1; 16104#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 16101#L371 assume !(0 != eval_~tmp~0#1); 16097#L367 assume !(0 == ~P_2_st~0); 16094#L382 assume !(0 == ~C_1_st~0); 16123#L397 [2023-11-29 02:23:00,613 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:23:00,613 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 1 times [2023-11-29 02:23:00,613 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:23:00,613 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367205886] [2023-11-29 02:23:00,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:23:00,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:00,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:00,621 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:23:00,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:00,633 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:23:00,633 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:23:00,633 INFO L85 PathProgramCache]: Analyzing trace with hash -658298241, now seen corresponding path program 1 times [2023-11-29 02:23:00,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:23:00,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065146736] [2023-11-29 02:23:00,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:23:00,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:00,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:00,637 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:23:00,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:00,641 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:23:00,642 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:23:00,642 INFO L85 PathProgramCache]: Analyzing trace with hash -1216568596, now seen corresponding path program 1 times [2023-11-29 02:23:00,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:23:00,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989926671] [2023-11-29 02:23:00,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:23:00,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:00,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:23:00,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:23:00,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:23:00,671 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [989926671] [2023-11-29 02:23:00,671 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [989926671] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:23:00,671 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:23:00,671 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:23:00,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1909966663] [2023-11-29 02:23:00,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:23:00,737 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:23:00,738 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:23:00,738 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:23:00,738 INFO L87 Difference]: Start difference. First operand 2343 states and 3154 transitions. cyclomatic complexity: 818 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:23:00,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:23:00,789 INFO L93 Difference]: Finished difference Result 3913 states and 5192 transitions. [2023-11-29 02:23:00,789 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3913 states and 5192 transitions. [2023-11-29 02:23:00,818 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3761 [2023-11-29 02:23:00,849 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3913 states to 3913 states and 5192 transitions. [2023-11-29 02:23:00,849 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3913 [2023-11-29 02:23:00,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3913 [2023-11-29 02:23:00,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3913 states and 5192 transitions. [2023-11-29 02:23:00,860 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:23:00,860 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3913 states and 5192 transitions. [2023-11-29 02:23:00,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3913 states and 5192 transitions. [2023-11-29 02:23:00,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3913 to 3829. [2023-11-29 02:23:00,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3829 states, 3829 states have (on average 1.329328806476887) internal successors, (5090), 3828 states have internal predecessors, (5090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:23:00,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3829 states to 3829 states and 5090 transitions. [2023-11-29 02:23:00,954 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3829 states and 5090 transitions. [2023-11-29 02:23:00,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:23:00,955 INFO L428 stractBuchiCegarLoop]: Abstraction has 3829 states and 5090 transitions. [2023-11-29 02:23:00,955 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-29 02:23:00,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3829 states and 5090 transitions. [2023-11-29 02:23:00,973 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2023-11-29 02:23:00,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:23:00,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:23:00,974 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:23:00,974 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:23:00,974 INFO L748 eck$LassoCheckResult]: Stem: 20642#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 20643#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 20671#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20662#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20663#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 20699#L305-2 assume !(1 == ~P_2_i~0);~P_2_st~0 := 2; 20764#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 22851#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22850#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 22849#L118 assume !(1 == ~P_1_pc~0); 22848#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 22847#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 22846#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 22845#L491 assume !(0 != activate_threads_~tmp~1#1); 22844#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 22843#L186 assume !(1 == ~P_2_pc~0); 22842#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 22841#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 22840#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22839#L499 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 20679#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 20617#L268 assume !(1 == ~C_1_pc~0); 20618#L268-2 assume !(2 == ~C_1_pc~0); 20747#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 20655#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 20656#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20619#L507 assume !(0 != activate_threads_~tmp___1~1#1); 20620#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20633#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 20761#L561-2 assume !false; 23706#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 23707#L397 [2023-11-29 02:23:00,975 INFO L750 eck$LassoCheckResult]: Loop: 23707#L397 assume !false; 23745#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 23744#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 23699#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 23700#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23365#L362 assume 0 != eval_~tmp___2~0#1; 23366#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 23521#L371 assume !(0 != eval_~tmp~0#1); 23560#L367 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 23553#L386 assume !(0 != eval_~tmp___0~0#1); 23559#L382 assume !(0 == ~C_1_st~0); 23707#L397 [2023-11-29 02:23:00,975 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:23:00,975 INFO L85 PathProgramCache]: Analyzing trace with hash -131921874, now seen corresponding path program 1 times [2023-11-29 02:23:00,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:23:00,976 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080927100] [2023-11-29 02:23:00,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:23:00,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:01,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:23:01,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:23:01,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:23:01,029 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2080927100] [2023-11-29 02:23:01,029 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2080927100] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:23:01,029 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:23:01,029 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:23:01,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1776587161] [2023-11-29 02:23:01,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:23:01,030 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:23:01,030 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:23:01,031 INFO L85 PathProgramCache]: Analyzing trace with hash 1067448397, now seen corresponding path program 1 times [2023-11-29 02:23:01,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:23:01,031 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [16610341] [2023-11-29 02:23:01,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:23:01,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:01,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:01,036 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:23:01,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:01,042 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:23:01,120 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:23:01,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:23:01,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:23:01,121 INFO L87 Difference]: Start difference. First operand 3829 states and 5090 transitions. cyclomatic complexity: 1268 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:23:01,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:23:01,143 INFO L93 Difference]: Finished difference Result 3804 states and 5062 transitions. [2023-11-29 02:23:01,143 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3804 states and 5062 transitions. [2023-11-29 02:23:01,160 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2023-11-29 02:23:01,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3804 states to 3804 states and 5062 transitions. [2023-11-29 02:23:01,184 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3804 [2023-11-29 02:23:01,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3804 [2023-11-29 02:23:01,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3804 states and 5062 transitions. [2023-11-29 02:23:01,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:23:01,192 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2023-11-29 02:23:01,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3804 states and 5062 transitions. [2023-11-29 02:23:01,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3804 to 3804. [2023-11-29 02:23:01,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3804 states, 3804 states have (on average 1.3307045215562565) internal successors, (5062), 3803 states have internal predecessors, (5062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:23:01,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3804 states to 3804 states and 5062 transitions. [2023-11-29 02:23:01,250 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2023-11-29 02:23:01,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:23:01,251 INFO L428 stractBuchiCegarLoop]: Abstraction has 3804 states and 5062 transitions. [2023-11-29 02:23:01,251 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-29 02:23:01,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3804 states and 5062 transitions. [2023-11-29 02:23:01,261 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3677 [2023-11-29 02:23:01,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:23:01,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:23:01,262 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:23:01,262 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:23:01,262 INFO L748 eck$LassoCheckResult]: Stem: 28281#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 28282#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 28310#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28302#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28303#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 28338#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 28354#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 28355#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28373#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 28372#L118 assume !(1 == ~P_1_pc~0); 28333#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 28334#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 28324#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28193#L491 assume !(0 != activate_threads_~tmp~1#1); 28194#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 28342#L186 assume !(1 == ~P_2_pc~0); 28214#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 28215#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 28346#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28320#L499 assume !(0 != activate_threads_~tmp___0~1#1); 28321#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 28257#L268 assume !(1 == ~C_1_pc~0); 28258#L268-2 assume !(2 == ~C_1_pc~0); 28379#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 28293#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 28294#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28259#L507 assume !(0 != activate_threads_~tmp___1~1#1); 28260#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28276#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 28390#L561-2 assume !false; 31242#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 31237#L397 [2023-11-29 02:23:01,262 INFO L750 eck$LassoCheckResult]: Loop: 31237#L397 assume !false; 31235#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31234#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 31233#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 31231#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31225#L362 assume 0 != eval_~tmp___2~0#1; 31222#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 31217#L371 assume !(0 != eval_~tmp~0#1); 31215#L367 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 31192#L386 assume !(0 != eval_~tmp___0~0#1); 31211#L382 assume !(0 == ~C_1_st~0); 31237#L397 [2023-11-29 02:23:01,263 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:23:01,263 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 2 times [2023-11-29 02:23:01,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:23:01,263 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565188854] [2023-11-29 02:23:01,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:23:01,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:01,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:01,269 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:23:01,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:01,279 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:23:01,279 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:23:01,279 INFO L85 PathProgramCache]: Analyzing trace with hash 1067448397, now seen corresponding path program 2 times [2023-11-29 02:23:01,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:23:01,280 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406589438] [2023-11-29 02:23:01,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:23:01,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:01,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:01,283 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:23:01,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:01,287 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:23:01,287 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:23:01,287 INFO L85 PathProgramCache]: Analyzing trace with hash 940936576, now seen corresponding path program 1 times [2023-11-29 02:23:01,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:23:01,287 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589323254] [2023-11-29 02:23:01,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:23:01,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:01,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:23:01,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:23:01,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:23:01,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1589323254] [2023-11-29 02:23:01,311 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1589323254] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:23:01,311 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:23:01,311 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 02:23:01,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [207691110] [2023-11-29 02:23:01,311 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:23:01,374 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:23:01,375 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:23:01,375 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:23:01,375 INFO L87 Difference]: Start difference. First operand 3804 states and 5062 transitions. cyclomatic complexity: 1265 Second operand has 3 states, 2 states have (on average 21.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:23:01,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:23:01,429 INFO L93 Difference]: Finished difference Result 6650 states and 8776 transitions. [2023-11-29 02:23:01,429 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6650 states and 8776 transitions. [2023-11-29 02:23:01,453 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6427 [2023-11-29 02:23:01,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6650 states to 6650 states and 8776 transitions. [2023-11-29 02:23:01,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6650 [2023-11-29 02:23:01,500 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6650 [2023-11-29 02:23:01,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6650 states and 8776 transitions. [2023-11-29 02:23:01,508 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:23:01,508 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2023-11-29 02:23:01,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6650 states and 8776 transitions. [2023-11-29 02:23:01,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6650 to 6650. [2023-11-29 02:23:01,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6650 states, 6650 states have (on average 1.3196992481203007) internal successors, (8776), 6649 states have internal predecessors, (8776), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:23:01,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6650 states to 6650 states and 8776 transitions. [2023-11-29 02:23:01,624 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2023-11-29 02:23:01,624 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:23:01,625 INFO L428 stractBuchiCegarLoop]: Abstraction has 6650 states and 8776 transitions. [2023-11-29 02:23:01,625 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-29 02:23:01,625 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6650 states and 8776 transitions. [2023-11-29 02:23:01,643 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6427 [2023-11-29 02:23:01,643 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:23:01,643 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:23:01,644 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:23:01,644 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:23:01,644 INFO L748 eck$LassoCheckResult]: Stem: 38742#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 38743#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 38774#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38765#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38766#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 38799#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 38812#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 38813#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38837#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 38836#L118 assume !(1 == ~P_1_pc~0); 38794#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 38795#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 38785#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 38655#L491 assume !(0 != activate_threads_~tmp~1#1); 38656#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 38803#L186 assume !(1 == ~P_2_pc~0); 38676#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 38677#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 38806#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38781#L499 assume !(0 != activate_threads_~tmp___0~1#1); 38782#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 38718#L268 assume !(1 == ~C_1_pc~0); 38719#L268-2 assume !(2 == ~C_1_pc~0); 38848#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 38756#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 38757#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38720#L507 assume !(0 != activate_threads_~tmp___1~1#1); 38721#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38737#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 38860#L561-2 assume !false; 39668#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 39669#L397 [2023-11-29 02:23:01,644 INFO L750 eck$LassoCheckResult]: Loop: 39669#L397 assume !false; 42520#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 42518#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 42517#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 42516#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 42515#L362 assume 0 != eval_~tmp___2~0#1; 42513#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 42511#L371 assume !(0 != eval_~tmp~0#1); 42510#L367 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 42496#L386 assume !(0 != eval_~tmp___0~0#1); 42443#L382 assume 0 == ~C_1_st~0;havoc eval_#t~nondet8#1;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 42442#L401 assume !(0 != eval_~tmp___1~0#1); 39669#L397 [2023-11-29 02:23:01,644 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:23:01,645 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 3 times [2023-11-29 02:23:01,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:23:01,645 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74715764] [2023-11-29 02:23:01,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:23:01,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:01,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:01,652 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:23:01,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:01,662 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:23:01,663 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:23:01,663 INFO L85 PathProgramCache]: Analyzing trace with hash -1268840153, now seen corresponding path program 1 times [2023-11-29 02:23:01,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:23:01,663 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1226671648] [2023-11-29 02:23:01,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:23:01,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:01,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:01,668 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:23:01,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:01,671 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:23:01,672 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:23:01,672 INFO L85 PathProgramCache]: Analyzing trace with hash -895739308, now seen corresponding path program 1 times [2023-11-29 02:23:01,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:23:01,672 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [375824112] [2023-11-29 02:23:01,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:23:01,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:23:01,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:01,679 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:23:01,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:01,687 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:23:02,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:02,722 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:23:02,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:23:02,832 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 29.11 02:23:02 BoogieIcfgContainer [2023-11-29 02:23:02,832 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-29 02:23:02,833 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-29 02:23:02,833 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-29 02:23:02,833 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-29 02:23:02,833 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 02:22:58" (3/4) ... [2023-11-29 02:23:02,835 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-29 02:23:02,898 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/witness.graphml [2023-11-29 02:23:02,898 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-29 02:23:02,899 INFO L158 Benchmark]: Toolchain (without parser) took 5876.13ms. Allocated memory was 172.0MB in the beginning and 211.8MB in the end (delta: 39.8MB). Free memory was 133.5MB in the beginning and 132.6MB in the end (delta: 862.8kB). Peak memory consumption was 40.7MB. Max. memory is 16.1GB. [2023-11-29 02:23:02,899 INFO L158 Benchmark]: CDTParser took 0.13ms. Allocated memory is still 119.5MB. Free memory is still 87.8MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-29 02:23:02,900 INFO L158 Benchmark]: CACSL2BoogieTranslator took 302.79ms. Allocated memory is still 172.0MB. Free memory was 132.7MB in the beginning and 135.1MB in the end (delta: -2.4MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-29 02:23:02,900 INFO L158 Benchmark]: Boogie Procedure Inliner took 46.90ms. Allocated memory is still 172.0MB. Free memory was 135.1MB in the beginning and 132.3MB in the end (delta: 2.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-29 02:23:02,900 INFO L158 Benchmark]: Boogie Preprocessor took 49.99ms. Allocated memory is still 172.0MB. Free memory was 132.3MB in the beginning and 128.8MB in the end (delta: 3.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-29 02:23:02,901 INFO L158 Benchmark]: RCFGBuilder took 578.80ms. Allocated memory is still 172.0MB. Free memory was 128.8MB in the beginning and 101.6MB in the end (delta: 27.3MB). Peak memory consumption was 27.3MB. Max. memory is 16.1GB. [2023-11-29 02:23:02,901 INFO L158 Benchmark]: BuchiAutomizer took 4827.21ms. Allocated memory was 172.0MB in the beginning and 211.8MB in the end (delta: 39.8MB). Free memory was 101.6MB in the beginning and 137.9MB in the end (delta: -36.3MB). Peak memory consumption was 6.7MB. Max. memory is 16.1GB. [2023-11-29 02:23:02,901 INFO L158 Benchmark]: Witness Printer took 65.74ms. Allocated memory is still 211.8MB. Free memory was 137.9MB in the beginning and 132.6MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-29 02:23:02,903 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13ms. Allocated memory is still 119.5MB. Free memory is still 87.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 302.79ms. Allocated memory is still 172.0MB. Free memory was 132.7MB in the beginning and 135.1MB in the end (delta: -2.4MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 46.90ms. Allocated memory is still 172.0MB. Free memory was 135.1MB in the beginning and 132.3MB in the end (delta: 2.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 49.99ms. Allocated memory is still 172.0MB. Free memory was 132.3MB in the beginning and 128.8MB in the end (delta: 3.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 578.80ms. Allocated memory is still 172.0MB. Free memory was 128.8MB in the beginning and 101.6MB in the end (delta: 27.3MB). Peak memory consumption was 27.3MB. Max. memory is 16.1GB. * BuchiAutomizer took 4827.21ms. Allocated memory was 172.0MB in the beginning and 211.8MB in the end (delta: 39.8MB). Free memory was 101.6MB in the beginning and 137.9MB in the end (delta: -36.3MB). Peak memory consumption was 6.7MB. Max. memory is 16.1GB. * Witness Printer took 65.74ms. Allocated memory is still 211.8MB. Free memory was 137.9MB in the beginning and 132.6MB in the end (delta: 5.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 6650 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.7s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 2.6s. Construction of modules took 0.3s. Büchi inclusion checks took 1.4s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.5s AutomataMinimizationTime, 11 MinimizatonAttempts, 1524 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3338 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3338 mSDsluCounter, 6273 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3359 mSDsCounter, 115 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 309 IncrementalHoareTripleChecker+Invalid, 424 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 115 mSolverCounterUnsat, 2914 mSDtfsCounter, 309 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 357]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int clk ; [L27] int num ; [L28] int i ; [L29] int e ; [L30] int timer ; [L31] char data_0 ; [L32] char data_1 ; [L75] int P_1_pc; [L76] int P_1_st ; [L77] int P_1_i ; [L78] int P_1_ev ; [L133] int P_2_pc ; [L134] int P_2_st ; [L135] int P_2_i ; [L136] int P_2_ev ; [L201] int C_1_pc ; [L202] int C_1_st ; [L203] int C_1_i ; [L204] int C_1_ev ; [L205] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L617] int count ; [L618] int __retres2 ; [L622] num = 0 [L623] i = 0 [L624] clk = 0 [L625] max_loop = 8 [L627] timer = 0 [L628] P_1_pc = 0 [L629] P_2_pc = 0 [L630] C_1_pc = 0 [L632] count = 0 [L633] CALL init_model() [L609] P_1_i = 1 [L610] P_2_i = 1 [L611] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L633] RET init_model() [L634] CALL start_simulation() [L547] int kernel_st ; [L548] int tmp ; [L549] int tmp___0 ; [L553] kernel_st = 0 [L554] FCALL update_channels() [L555] CALL init_threads() [L305] COND TRUE (int )P_1_i == 1 [L306] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L310] COND TRUE (int )P_2_i == 1 [L311] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L315] COND TRUE (int )C_1_i == 1 [L316] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L555] RET init_threads() [L556] FCALL fire_delta_events() [L557] CALL activate_threads() [L483] int tmp ; [L484] int tmp___0 ; [L485] int tmp___1 ; [L489] CALL, EXPR is_P_1_triggered() [L115] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L118] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L128] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L130] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L489] RET, EXPR is_P_1_triggered() [L489] tmp = is_P_1_triggered() [L491] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0, tmp=0] [L497] CALL, EXPR is_P_2_triggered() [L183] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L186] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L196] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L198] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L497] RET, EXPR is_P_2_triggered() [L497] tmp___0 = is_P_2_triggered() [L499] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0, tmp=0, tmp___0=0] [L505] CALL, EXPR is_C_1_triggered() [L265] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L268] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L278] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L288] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L290] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L505] RET, EXPR is_C_1_triggered() [L505] tmp___1 = is_C_1_triggered() [L507] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0, tmp=0, tmp___0=0, tmp___1=0] [L557] RET activate_threads() [L558] FCALL reset_delta_events() [L561] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=8, num=0, timer=0] [L564] kernel_st = 1 [L565] CALL eval() [L350] int tmp ; [L351] int tmp___0 ; [L352] int tmp___1 ; [L353] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] Loop: [L357] COND TRUE 1 [L360] CALL, EXPR exists_runnable_thread() [L325] int __retres1 ; [L328] COND TRUE (int )P_1_st == 0 [L329] __retres1 = 1 [L346] return (__retres1); [L360] RET, EXPR exists_runnable_thread() [L360] tmp___2 = exists_runnable_thread() [L362] COND TRUE \read(tmp___2) [L367] COND TRUE (int )P_1_st == 0 [L369] tmp = __VERIFIER_nondet_int() [L371] COND FALSE !(\read(tmp)) [L382] COND TRUE (int )P_2_st == 0 [L384] tmp___0 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp___0)) [L397] COND TRUE (int )C_1_st == 0 [L399] tmp___1 = __VERIFIER_nondet_int() [L401] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 357]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int clk ; [L27] int num ; [L28] int i ; [L29] int e ; [L30] int timer ; [L31] char data_0 ; [L32] char data_1 ; [L75] int P_1_pc; [L76] int P_1_st ; [L77] int P_1_i ; [L78] int P_1_ev ; [L133] int P_2_pc ; [L134] int P_2_st ; [L135] int P_2_i ; [L136] int P_2_ev ; [L201] int C_1_pc ; [L202] int C_1_st ; [L203] int C_1_i ; [L204] int C_1_ev ; [L205] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L617] int count ; [L618] int __retres2 ; [L622] num = 0 [L623] i = 0 [L624] clk = 0 [L625] max_loop = 8 [L627] timer = 0 [L628] P_1_pc = 0 [L629] P_2_pc = 0 [L630] C_1_pc = 0 [L632] count = 0 [L633] CALL init_model() [L609] P_1_i = 1 [L610] P_2_i = 1 [L611] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L633] RET init_model() [L634] CALL start_simulation() [L547] int kernel_st ; [L548] int tmp ; [L549] int tmp___0 ; [L553] kernel_st = 0 [L554] FCALL update_channels() [L555] CALL init_threads() [L305] COND TRUE (int )P_1_i == 1 [L306] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L310] COND TRUE (int )P_2_i == 1 [L311] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L315] COND TRUE (int )C_1_i == 1 [L316] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L555] RET init_threads() [L556] FCALL fire_delta_events() [L557] CALL activate_threads() [L483] int tmp ; [L484] int tmp___0 ; [L485] int tmp___1 ; [L489] CALL, EXPR is_P_1_triggered() [L115] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L118] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L128] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L130] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L489] RET, EXPR is_P_1_triggered() [L489] tmp = is_P_1_triggered() [L491] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0, tmp=0] [L497] CALL, EXPR is_P_2_triggered() [L183] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L186] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L196] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L198] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L497] RET, EXPR is_P_2_triggered() [L497] tmp___0 = is_P_2_triggered() [L499] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0, tmp=0, tmp___0=0] [L505] CALL, EXPR is_C_1_triggered() [L265] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L268] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L278] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L288] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L290] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] [L505] RET, EXPR is_C_1_triggered() [L505] tmp___1 = is_C_1_triggered() [L507] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0, tmp=0, tmp___0=0, tmp___1=0] [L557] RET activate_threads() [L558] FCALL reset_delta_events() [L561] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=8, num=0, timer=0] [L564] kernel_st = 1 [L565] CALL eval() [L350] int tmp ; [L351] int tmp___0 ; [L352] int tmp___1 ; [L353] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0] Loop: [L357] COND TRUE 1 [L360] CALL, EXPR exists_runnable_thread() [L325] int __retres1 ; [L328] COND TRUE (int )P_1_st == 0 [L329] __retres1 = 1 [L346] return (__retres1); [L360] RET, EXPR exists_runnable_thread() [L360] tmp___2 = exists_runnable_thread() [L362] COND TRUE \read(tmp___2) [L367] COND TRUE (int )P_1_st == 0 [L369] tmp = __VERIFIER_nondet_int() [L371] COND FALSE !(\read(tmp)) [L382] COND TRUE (int )P_2_st == 0 [L384] tmp___0 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp___0)) [L397] COND TRUE (int )C_1_st == 0 [L399] tmp___1 = __VERIFIER_nondet_int() [L401] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-29 02:23:02,957 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0367c01c-8397-440a-8d89-592860b8d822/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)