./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/pipeline.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/pipeline.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c42f0f019aa30bac52b753d657fd0a7a27ad0fcef5ea61d179259276789b8861 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-29 01:22:47,129 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-29 01:22:47,211 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-29 01:22:47,217 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-29 01:22:47,218 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-29 01:22:47,249 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-29 01:22:47,250 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-29 01:22:47,251 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-29 01:22:47,252 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-29 01:22:47,252 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-29 01:22:47,253 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-29 01:22:47,254 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-29 01:22:47,254 INFO L153 SettingsManager]: * Use SBE=true [2023-11-29 01:22:47,255 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-29 01:22:47,256 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-29 01:22:47,256 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-29 01:22:47,257 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-29 01:22:47,257 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-29 01:22:47,258 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-29 01:22:47,259 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-29 01:22:47,259 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-29 01:22:47,266 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-29 01:22:47,267 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-29 01:22:47,267 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-29 01:22:47,268 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-29 01:22:47,268 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-29 01:22:47,269 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-29 01:22:47,269 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-29 01:22:47,269 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-29 01:22:47,270 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-29 01:22:47,270 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-29 01:22:47,271 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-29 01:22:47,271 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-29 01:22:47,271 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-29 01:22:47,272 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-29 01:22:47,272 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-29 01:22:47,272 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-29 01:22:47,273 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-29 01:22:47,273 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c42f0f019aa30bac52b753d657fd0a7a27ad0fcef5ea61d179259276789b8861 [2023-11-29 01:22:47,566 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-29 01:22:47,593 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-29 01:22:47,596 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-29 01:22:47,598 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-29 01:22:47,599 INFO L274 PluginConnector]: CDTParser initialized [2023-11-29 01:22:47,600 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/pipeline.cil-2.c [2023-11-29 01:22:51,070 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-29 01:22:51,302 INFO L384 CDTParser]: Found 1 translation units. [2023-11-29 01:22:51,303 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/sv-benchmarks/c/systemc/pipeline.cil-2.c [2023-11-29 01:22:51,319 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya/data/ffb88486a/c8dc96bbf6be47f9adffb858f02b8c1b/FLAG2cab152fa [2023-11-29 01:22:51,338 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya/data/ffb88486a/c8dc96bbf6be47f9adffb858f02b8c1b [2023-11-29 01:22:51,341 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-29 01:22:51,343 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-29 01:22:51,345 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-29 01:22:51,345 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-29 01:22:51,352 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-29 01:22:51,353 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 01:22:51" (1/1) ... [2023-11-29 01:22:51,355 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@327518ef and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51, skipping insertion in model container [2023-11-29 01:22:51,355 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 01:22:51" (1/1) ... [2023-11-29 01:22:51,416 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-29 01:22:51,670 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 01:22:51,686 INFO L202 MainTranslator]: Completed pre-run [2023-11-29 01:22:51,738 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 01:22:51,754 INFO L206 MainTranslator]: Completed translation [2023-11-29 01:22:51,755 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51 WrapperNode [2023-11-29 01:22:51,755 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-29 01:22:51,757 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-29 01:22:51,757 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-29 01:22:51,757 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-29 01:22:51,765 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51" (1/1) ... [2023-11-29 01:22:51,778 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51" (1/1) ... [2023-11-29 01:22:51,831 INFO L138 Inliner]: procedures = 20, calls = 18, calls flagged for inlining = 13, calls inlined = 25, statements flattened = 1052 [2023-11-29 01:22:51,831 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-29 01:22:51,832 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-29 01:22:51,832 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-29 01:22:51,832 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-29 01:22:51,847 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51" (1/1) ... [2023-11-29 01:22:51,847 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51" (1/1) ... [2023-11-29 01:22:51,853 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51" (1/1) ... [2023-11-29 01:22:51,879 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-29 01:22:51,879 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51" (1/1) ... [2023-11-29 01:22:51,880 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51" (1/1) ... [2023-11-29 01:22:51,899 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51" (1/1) ... [2023-11-29 01:22:51,923 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51" (1/1) ... [2023-11-29 01:22:51,927 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51" (1/1) ... [2023-11-29 01:22:51,933 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51" (1/1) ... [2023-11-29 01:22:51,943 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-29 01:22:51,944 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-29 01:22:51,945 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-29 01:22:51,945 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-29 01:22:51,946 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51" (1/1) ... [2023-11-29 01:22:51,955 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:22:51,971 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:22:51,985 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:22:51,988 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c23a3234-534a-4d30-9b51-d8bedc7b395a/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-29 01:22:52,029 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-29 01:22:52,029 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-29 01:22:52,029 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-29 01:22:52,030 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-29 01:22:52,149 INFO L241 CfgBuilder]: Building ICFG [2023-11-29 01:22:52,151 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-29 01:22:53,257 INFO L282 CfgBuilder]: Performing block encoding [2023-11-29 01:22:53,283 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-29 01:22:53,283 INFO L309 CfgBuilder]: Removed 7 assume(true) statements. [2023-11-29 01:22:53,286 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 01:22:53 BoogieIcfgContainer [2023-11-29 01:22:53,286 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-29 01:22:53,287 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-29 01:22:53,287 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-29 01:22:53,292 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-29 01:22:53,293 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:22:53,294 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.11 01:22:51" (1/3) ... [2023-11-29 01:22:53,295 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4f5f9ca4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 01:22:53, skipping insertion in model container [2023-11-29 01:22:53,295 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:22:53,295 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:22:51" (2/3) ... [2023-11-29 01:22:53,296 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4f5f9ca4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 01:22:53, skipping insertion in model container [2023-11-29 01:22:53,296 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:22:53,296 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 01:22:53" (3/3) ... [2023-11-29 01:22:53,298 INFO L332 chiAutomizerObserver]: Analyzing ICFG pipeline.cil-2.c [2023-11-29 01:22:53,367 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-29 01:22:53,367 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-29 01:22:53,367 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-29 01:22:53,367 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-29 01:22:53,368 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-29 01:22:53,368 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-29 01:22:53,368 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-29 01:22:53,368 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-29 01:22:53,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 423 states, 422 states have (on average 1.8127962085308056) internal successors, (765), 422 states have internal predecessors, (765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:53,424 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 361 [2023-11-29 01:22:53,425 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:22:53,425 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:22:53,435 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:53,436 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:53,436 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-29 01:22:53,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 423 states, 422 states have (on average 1.8127962085308056) internal successors, (765), 422 states have internal predecessors, (765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:53,452 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 361 [2023-11-29 01:22:53,452 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:22:53,452 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:22:53,454 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:53,455 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:53,465 INFO L748 eck$LassoCheckResult]: Stem: 127#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 358#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 32#L256true assume !(1 == ~main_in1_req_up~0); 9#L256-2true assume !(1 == ~main_in2_req_up~0); 26#L267-1true assume !(1 == ~main_sum_req_up~0); 304#L278-1true assume !(1 == ~main_diff_req_up~0); 2#L289-1true assume !(1 == ~main_pres_req_up~0); 255#L300-1true assume !(1 == ~main_dbl_req_up~0); 150#L311-1true assume !(1 == ~main_zero_req_up~0); 328#L322-1true assume !(1 == ~main_clk_req_up~0); 195#L333-1true assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 125#L351-1true assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 19#L356-1true assume 1 == ~S2_presdbl_i~0;~S2_presdbl_st~0 := 0; 119#L361-1true assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 341#L366-1true assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 114#L371-1true assume !(0 == ~main_in1_ev~0); 44#L376-1true assume !(0 == ~main_in2_ev~0); 306#L381-1true assume !(0 == ~main_sum_ev~0); 134#L386-1true assume !(0 == ~main_diff_ev~0); 323#L391-1true assume !(0 == ~main_pres_ev~0); 232#L396-1true assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 82#L401-1true assume !(0 == ~main_zero_ev~0); 87#L406-1true assume !(0 == ~main_clk_ev~0); 353#L411-1true assume !(0 == ~main_clk_pos_edge~0); 338#L416-1true assume !(0 == ~main_clk_neg_edge~0); 395#L421-1true assume !(1 == ~main_clk_pos_edge~0); 291#L426-1true assume !(1 == ~main_clk_pos_edge~0); 107#L431-1true assume !(1 == ~main_clk_pos_edge~0); 236#L436-1true assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 95#L441-1true assume !(1 == ~main_clk_pos_edge~0); 386#L446-1true assume !(1 == ~main_in1_ev~0); 280#L451-1true assume !(1 == ~main_in2_ev~0); 396#L456-1true assume !(1 == ~main_sum_ev~0); 138#L461-1true assume !(1 == ~main_diff_ev~0); 380#L466-1true assume !(1 == ~main_pres_ev~0); 407#L471-1true assume !(1 == ~main_dbl_ev~0); 27#L476-1true assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 196#L481-1true assume !(1 == ~main_clk_ev~0); 92#L486-1true assume !(1 == ~main_clk_pos_edge~0); 29#L491-1true assume !(1 == ~main_clk_neg_edge~0); 250#L742-1true [2023-11-29 01:22:53,466 INFO L750 eck$LassoCheckResult]: Loop: 250#L742-1true assume !false; 376#L503true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 209#L229true assume false; 63#eval_returnLabel#1true havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 256#L509true assume !(1 == ~main_in1_req_up~0); 175#L509-2true assume !(1 == ~main_in2_req_up~0); 339#L520-1true assume !(1 == ~main_sum_req_up~0); 223#L531-1true assume !(1 == ~main_diff_req_up~0); 144#L542-1true assume !(1 == ~main_pres_req_up~0); 394#L553-1true assume !(1 == ~main_dbl_req_up~0); 161#L564-1true assume !(1 == ~main_zero_req_up~0); 245#L575-1true assume !(1 == ~main_clk_req_up~0); 343#L586-1true start_simulation_~kernel_st~0#1 := 3; 370#L605true assume !(0 == ~main_in1_ev~0); 287#L605-2true assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 17#L610-1true assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 194#L615-1true assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 191#L620-1true assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 188#L625-1true assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 271#L630-1true assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 329#L635-1true assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 327#L640-1true assume !(0 == ~main_clk_pos_edge~0); 85#L645-1true assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 113#L650-1true assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 132#L655-1true assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 207#L660-1true assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 241#L665-1true assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 290#L670-1true assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 184#L675-1true assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 239#L680-1true assume !(1 == ~main_in2_ev~0); 313#L685-1true assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 218#L690-1true assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 406#L695-1true assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 277#L700-1true assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 269#L705-1true assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 375#L710-1true assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 180#L715-1true assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 136#L720-1true assume !(1 == ~main_clk_neg_edge~0); 167#L725-1true assume 0 == ~N_generate_st~0; 250#L742-1true [2023-11-29 01:22:53,473 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:53,474 INFO L85 PathProgramCache]: Analyzing trace with hash 1291793407, now seen corresponding path program 1 times [2023-11-29 01:22:53,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:53,483 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776289873] [2023-11-29 01:22:53,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:53,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:53,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:53,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:53,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:53,862 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776289873] [2023-11-29 01:22:53,863 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776289873] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:53,863 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:53,863 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:22:53,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [963753002] [2023-11-29 01:22:53,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:53,870 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:22:53,871 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:53,871 INFO L85 PathProgramCache]: Analyzing trace with hash -727719859, now seen corresponding path program 1 times [2023-11-29 01:22:53,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:53,872 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997091922] [2023-11-29 01:22:53,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:53,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:53,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:53,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:53,901 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:53,902 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1997091922] [2023-11-29 01:22:53,902 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1997091922] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:53,902 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:53,903 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:22:53,903 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [153804763] [2023-11-29 01:22:53,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:53,905 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:22:53,906 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:22:53,942 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-29 01:22:53,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-29 01:22:53,945 INFO L87 Difference]: Start difference. First operand has 423 states, 422 states have (on average 1.8127962085308056) internal successors, (765), 422 states have internal predecessors, (765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 19.5) internal successors, (39), 2 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:53,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:22:53,989 INFO L93 Difference]: Finished difference Result 417 states and 745 transitions. [2023-11-29 01:22:53,991 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 417 states and 745 transitions. [2023-11-29 01:22:53,997 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 358 [2023-11-29 01:22:54,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 417 states to 416 states and 744 transitions. [2023-11-29 01:22:54,009 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 416 [2023-11-29 01:22:54,011 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 416 [2023-11-29 01:22:54,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 416 states and 744 transitions. [2023-11-29 01:22:54,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:22:54,016 INFO L218 hiAutomatonCegarLoop]: Abstraction has 416 states and 744 transitions. [2023-11-29 01:22:54,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416 states and 744 transitions. [2023-11-29 01:22:54,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416 to 416. [2023-11-29 01:22:54,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 416 states, 416 states have (on average 1.7884615384615385) internal successors, (744), 415 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:54,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 416 states to 416 states and 744 transitions. [2023-11-29 01:22:54,074 INFO L240 hiAutomatonCegarLoop]: Abstraction has 416 states and 744 transitions. [2023-11-29 01:22:54,075 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-29 01:22:54,080 INFO L428 stractBuchiCegarLoop]: Abstraction has 416 states and 744 transitions. [2023-11-29 01:22:54,080 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-29 01:22:54,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 416 states and 744 transitions. [2023-11-29 01:22:54,084 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 358 [2023-11-29 01:22:54,084 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:22:54,084 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:22:54,087 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:54,087 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:54,088 INFO L748 eck$LassoCheckResult]: Stem: 1071#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1072#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 912#L256 assume !(1 == ~main_in1_req_up~0); 867#L256-2 assume !(1 == ~main_in2_req_up~0); 869#L267-1 assume !(1 == ~main_sum_req_up~0); 900#L278-1 assume !(1 == ~main_diff_req_up~0); 850#L289-1 assume !(1 == ~main_pres_req_up~0); 851#L300-1 assume !(1 == ~main_dbl_req_up~0); 960#L311-1 assume !(1 == ~main_zero_req_up~0); 1103#L322-1 assume !(1 == ~main_clk_req_up~0); 1078#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1069#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 889#L356-1 assume 1 == ~S2_presdbl_i~0;~S2_presdbl_st~0 := 0; 890#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 1063#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 1058#L371-1 assume !(0 == ~main_in1_ev~0); 938#L376-1 assume !(0 == ~main_in2_ev~0); 939#L381-1 assume !(0 == ~main_sum_ev~0); 1080#L386-1 assume !(0 == ~main_diff_ev~0); 1081#L391-1 assume !(0 == ~main_pres_ev~0); 1190#L396-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 1008#L401-1 assume !(0 == ~main_zero_ev~0); 1009#L406-1 assume !(0 == ~main_clk_ev~0); 1016#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1249#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1250#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1236#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1047#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1048#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 1025#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1026#L446-1 assume !(1 == ~main_in1_ev~0); 1228#L451-1 assume !(1 == ~main_in2_ev~0); 1229#L456-1 assume !(1 == ~main_sum_ev~0); 1087#L461-1 assume !(1 == ~main_diff_ev~0); 1088#L466-1 assume !(1 == ~main_pres_ev~0); 1263#L471-1 assume !(1 == ~main_dbl_ev~0); 902#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 903#L481-1 assume !(1 == ~main_clk_ev~0); 1023#L486-1 assume !(1 == ~main_clk_pos_edge~0); 907#L491-1 assume !(1 == ~main_clk_neg_edge~0); 908#L742-1 [2023-11-29 01:22:54,088 INFO L750 eck$LassoCheckResult]: Loop: 908#L742-1 assume !false; 1206#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 942#L229 assume !false; 1168#L147 assume !(0 == ~N_generate_st~0); 973#L151 assume !(0 == ~S1_addsub_st~0); 974#L154 assume !(0 == ~S2_presdbl_st~0); 860#L157 assume !(0 == ~S3_zero_st~0); 862#L160 assume !(0 == ~D_print_st~0); 976#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 977#L509 assume !(1 == ~main_in1_req_up~0); 864#L509-2 assume !(1 == ~main_in2_req_up~0); 1133#L520-1 assume !(1 == ~main_sum_req_up~0); 1181#L531-1 assume !(1 == ~main_diff_req_up~0); 1095#L542-1 assume !(1 == ~main_pres_req_up~0); 871#L553-1 assume !(1 == ~main_dbl_req_up~0); 1107#L564-1 assume !(1 == ~main_zero_req_up~0); 1117#L575-1 assume !(1 == ~main_clk_req_up~0); 1201#L586-1 start_simulation_~kernel_st~0#1 := 3; 1251#L605 assume !(0 == ~main_in1_ev~0); 1235#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 886#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 887#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 1158#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 1153#L625-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 1154#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 1222#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 1246#L640-1 assume !(0 == ~main_clk_pos_edge~0); 1014#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 1015#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 1057#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 1079#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 1167#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 1198#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 1146#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 1147#L680-1 assume !(1 == ~main_in2_ev~0); 1196#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 1176#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 1177#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 1223#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 1220#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 1221#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 1140#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 1083#L720-1 assume !(1 == ~main_clk_neg_edge~0); 1084#L725-1 assume 0 == ~N_generate_st~0; 908#L742-1 [2023-11-29 01:22:54,089 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:54,089 INFO L85 PathProgramCache]: Analyzing trace with hash 1291793407, now seen corresponding path program 2 times [2023-11-29 01:22:54,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:54,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925073763] [2023-11-29 01:22:54,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:54,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:54,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:54,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:54,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:54,207 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [925073763] [2023-11-29 01:22:54,207 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [925073763] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:54,207 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:54,207 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:22:54,208 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [222283179] [2023-11-29 01:22:54,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:54,209 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:22:54,209 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:54,210 INFO L85 PathProgramCache]: Analyzing trace with hash 1802774254, now seen corresponding path program 1 times [2023-11-29 01:22:54,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:54,210 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864965647] [2023-11-29 01:22:54,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:54,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:54,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:54,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:54,254 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:54,254 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [864965647] [2023-11-29 01:22:54,254 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [864965647] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:54,255 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:54,255 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:22:54,255 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1925779416] [2023-11-29 01:22:54,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:54,256 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:22:54,256 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:22:54,257 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:22:54,257 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:22:54,257 INFO L87 Difference]: Start difference. First operand 416 states and 744 transitions. cyclomatic complexity: 330 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:54,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:22:54,413 INFO L93 Difference]: Finished difference Result 760 states and 1352 transitions. [2023-11-29 01:22:54,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 760 states and 1352 transitions. [2023-11-29 01:22:54,423 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 703 [2023-11-29 01:22:54,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 760 states to 760 states and 1352 transitions. [2023-11-29 01:22:54,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 760 [2023-11-29 01:22:54,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 760 [2023-11-29 01:22:54,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 760 states and 1352 transitions. [2023-11-29 01:22:54,438 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:22:54,438 INFO L218 hiAutomatonCegarLoop]: Abstraction has 760 states and 1352 transitions. [2023-11-29 01:22:54,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 760 states and 1352 transitions. [2023-11-29 01:22:54,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 760 to 760. [2023-11-29 01:22:54,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 760 states, 760 states have (on average 1.7789473684210526) internal successors, (1352), 759 states have internal predecessors, (1352), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:54,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 760 states to 760 states and 1352 transitions. [2023-11-29 01:22:54,476 INFO L240 hiAutomatonCegarLoop]: Abstraction has 760 states and 1352 transitions. [2023-11-29 01:22:54,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:22:54,477 INFO L428 stractBuchiCegarLoop]: Abstraction has 760 states and 1352 transitions. [2023-11-29 01:22:54,477 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-29 01:22:54,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 760 states and 1352 transitions. [2023-11-29 01:22:54,484 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 703 [2023-11-29 01:22:54,485 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:22:54,485 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:22:54,487 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:54,487 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:54,487 INFO L748 eck$LassoCheckResult]: Stem: 2262#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2263#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2100#L256 assume !(1 == ~main_in1_req_up~0); 2054#L256-2 assume !(1 == ~main_in2_req_up~0); 2056#L267-1 assume !(1 == ~main_sum_req_up~0); 2088#L278-1 assume !(1 == ~main_diff_req_up~0); 2037#L289-1 assume !(1 == ~main_pres_req_up~0); 2038#L300-1 assume !(1 == ~main_dbl_req_up~0); 2146#L311-1 assume !(1 == ~main_zero_req_up~0); 2296#L322-1 assume !(1 == ~main_clk_req_up~0); 2270#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2259#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2076#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2077#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2253#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2248#L371-1 assume !(0 == ~main_in1_ev~0); 2124#L376-1 assume !(0 == ~main_in2_ev~0); 2125#L381-1 assume !(0 == ~main_sum_ev~0); 2272#L386-1 assume !(0 == ~main_diff_ev~0); 2273#L391-1 assume !(0 == ~main_pres_ev~0); 2391#L396-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 2196#L401-1 assume !(0 == ~main_zero_ev~0); 2197#L406-1 assume !(0 == ~main_clk_ev~0); 2205#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2472#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2473#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2442#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2236#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2237#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 2213#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2214#L446-1 assume !(1 == ~main_in1_ev~0); 2433#L451-1 assume !(1 == ~main_in2_ev~0); 2434#L456-1 assume !(1 == ~main_sum_ev~0); 2280#L461-1 assume !(1 == ~main_diff_ev~0); 2281#L466-1 assume !(1 == ~main_pres_ev~0); 2492#L471-1 assume !(1 == ~main_dbl_ev~0); 2090#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 2091#L481-1 assume !(1 == ~main_clk_ev~0); 2212#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2095#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2096#L742-1 [2023-11-29 01:22:54,488 INFO L750 eck$LassoCheckResult]: Loop: 2096#L742-1 assume !false; 2408#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2128#L229 assume !false; 2366#L147 assume !(0 == ~N_generate_st~0); 2160#L151 assume !(0 == ~S1_addsub_st~0); 2161#L154 assume !(0 == ~S2_presdbl_st~0); 2047#L157 assume !(0 == ~S3_zero_st~0); 2049#L160 assume !(0 == ~D_print_st~0); 2163#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2164#L509 assume !(1 == ~main_in1_req_up~0); 2328#L509-2 assume !(1 == ~main_in2_req_up~0); 2329#L520-1 assume !(1 == ~main_sum_req_up~0); 2379#L531-1 assume !(1 == ~main_diff_req_up~0); 2288#L542-1 assume !(1 == ~main_pres_req_up~0); 2058#L553-1 assume !(1 == ~main_dbl_req_up~0); 2300#L564-1 assume !(1 == ~main_zero_req_up~0); 2311#L575-1 assume !(1 == ~main_clk_req_up~0); 2403#L586-1 start_simulation_~kernel_st~0#1 := 3; 2474#L605 assume !(0 == ~main_in1_ev~0); 2440#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 2073#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2074#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2356#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2351#L625-1 assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1; 2352#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 2426#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2467#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2202#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 2203#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 2247#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 2271#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 2365#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 2400#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 2344#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 2345#L680-1 assume !(1 == ~main_in2_ev~0); 2398#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2374#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2375#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2428#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 2424#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 2425#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2338#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 2275#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2276#L725-1 assume 0 == ~N_generate_st~0; 2096#L742-1 [2023-11-29 01:22:54,488 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:54,488 INFO L85 PathProgramCache]: Analyzing trace with hash 782320317, now seen corresponding path program 1 times [2023-11-29 01:22:54,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:54,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865660958] [2023-11-29 01:22:54,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:54,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:54,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:54,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:54,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:54,582 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865660958] [2023-11-29 01:22:54,583 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1865660958] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:54,583 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:54,583 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:22:54,583 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758247945] [2023-11-29 01:22:54,584 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:54,584 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:22:54,585 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:54,585 INFO L85 PathProgramCache]: Analyzing trace with hash 1802774254, now seen corresponding path program 2 times [2023-11-29 01:22:54,585 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:54,585 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607909547] [2023-11-29 01:22:54,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:54,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:54,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:54,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:54,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:54,628 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1607909547] [2023-11-29 01:22:54,628 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1607909547] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:54,628 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:54,629 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:22:54,629 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137001452] [2023-11-29 01:22:54,629 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:54,629 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:22:54,630 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:22:54,630 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:22:54,630 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:22:54,631 INFO L87 Difference]: Start difference. First operand 760 states and 1352 transitions. cyclomatic complexity: 596 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:54,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:22:54,951 INFO L93 Difference]: Finished difference Result 1669 states and 2937 transitions. [2023-11-29 01:22:54,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1669 states and 2937 transitions. [2023-11-29 01:22:54,970 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1572 [2023-11-29 01:22:54,988 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1669 states to 1669 states and 2937 transitions. [2023-11-29 01:22:54,989 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1669 [2023-11-29 01:22:54,991 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1669 [2023-11-29 01:22:54,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1669 states and 2937 transitions. [2023-11-29 01:22:54,995 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:22:54,995 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2023-11-29 01:22:54,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1669 states and 2937 transitions. [2023-11-29 01:22:55,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1669 to 1669. [2023-11-29 01:22:55,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1669 states, 1669 states have (on average 1.7597363690832835) internal successors, (2937), 1668 states have internal predecessors, (2937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:55,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1669 states to 1669 states and 2937 transitions. [2023-11-29 01:22:55,048 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2023-11-29 01:22:55,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-29 01:22:55,049 INFO L428 stractBuchiCegarLoop]: Abstraction has 1669 states and 2937 transitions. [2023-11-29 01:22:55,049 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-29 01:22:55,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1669 states and 2937 transitions. [2023-11-29 01:22:55,062 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1572 [2023-11-29 01:22:55,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:22:55,063 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:22:55,064 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:55,064 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:55,065 INFO L748 eck$LassoCheckResult]: Stem: 4704#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 4705#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 4538#L256 assume !(1 == ~main_in1_req_up~0); 4493#L256-2 assume !(1 == ~main_in2_req_up~0); 4495#L267-1 assume !(1 == ~main_sum_req_up~0); 4526#L278-1 assume !(1 == ~main_diff_req_up~0); 4476#L289-1 assume !(1 == ~main_pres_req_up~0); 4477#L300-1 assume !(1 == ~main_dbl_req_up~0); 4738#L311-1 assume !(1 == ~main_zero_req_up~0); 4737#L322-1 assume !(1 == ~main_clk_req_up~0); 4709#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 4699#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 4700#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 4954#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 4953#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 4952#L371-1 assume !(0 == ~main_in1_ev~0); 4951#L376-1 assume !(0 == ~main_in2_ev~0); 4895#L381-1 assume !(0 == ~main_sum_ev~0); 4896#L386-1 assume !(0 == ~main_diff_ev~0); 4904#L391-1 assume !(0 == ~main_pres_ev~0); 4836#L396-1 assume !(0 == ~main_dbl_ev~0); 4837#L401-1 assume !(0 == ~main_zero_ev~0); 4644#L406-1 assume !(0 == ~main_clk_ev~0); 4645#L411-1 assume !(0 == ~main_clk_pos_edge~0); 4910#L416-1 assume !(0 == ~main_clk_neg_edge~0); 4911#L421-1 assume !(1 == ~main_clk_pos_edge~0); 4889#L426-1 assume !(1 == ~main_clk_pos_edge~0); 4677#L431-1 assume !(1 == ~main_clk_pos_edge~0); 4678#L436-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 4654#L441-1 assume !(1 == ~main_clk_pos_edge~0); 4655#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 4934#L451-1 assume !(1 == ~main_in2_ev~0); 5227#L456-1 assume !(1 == ~main_sum_ev~0); 5226#L461-1 assume !(1 == ~main_diff_ev~0); 5225#L466-1 assume !(1 == ~main_pres_ev~0); 5224#L471-1 assume !(1 == ~main_dbl_ev~0); 4944#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 5223#L481-1 assume !(1 == ~main_clk_ev~0); 4653#L486-1 assume !(1 == ~main_clk_pos_edge~0); 4533#L491-1 assume !(1 == ~main_clk_neg_edge~0); 4534#L742-1 [2023-11-29 01:22:55,065 INFO L750 eck$LassoCheckResult]: Loop: 4534#L742-1 assume !false; 4854#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 5204#L229 assume !false; 5202#L147 assume !(0 == ~N_generate_st~0); 5198#L151 assume !(0 == ~S1_addsub_st~0); 5199#L154 assume !(0 == ~S2_presdbl_st~0); 5200#L157 assume !(0 == ~S3_zero_st~0); 5201#L160 assume !(0 == ~D_print_st~0); 4605#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 4606#L509 assume !(1 == ~main_in1_req_up~0); 4857#L509-2 assume !(1 == ~main_in2_req_up~0); 5269#L520-1 assume !(1 == ~main_sum_req_up~0); 5265#L531-1 assume !(1 == ~main_diff_req_up~0); 5263#L542-1 assume !(1 == ~main_pres_req_up~0); 4936#L553-1 assume !(1 == ~main_dbl_req_up~0); 4741#L564-1 assume !(1 == ~main_zero_req_up~0); 4753#L575-1 assume !(1 == ~main_clk_req_up~0); 4849#L586-1 start_simulation_~kernel_st~0#1 := 3; 4912#L605 assume !(0 == ~main_in1_ev~0); 4887#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 4512#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 4513#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 4798#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 4793#L625-1 assume !(0 == ~main_dbl_ev~0); 4794#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 4873#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 4905#L640-1 assume !(0 == ~main_clk_pos_edge~0); 4641#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 4642#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 4687#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 4710#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 4809#L665-1 assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0; 4845#L670-1 assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0; 4888#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 4786#L680-1 assume !(1 == ~main_in2_ev~0); 5236#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 5235#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 5234#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 4874#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 4871#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 4872#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 4778#L715-1 assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2; 4716#L720-1 assume !(1 == ~main_clk_neg_edge~0); 4717#L725-1 assume 0 == ~N_generate_st~0; 4534#L742-1 [2023-11-29 01:22:55,065 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:55,066 INFO L85 PathProgramCache]: Analyzing trace with hash 357698877, now seen corresponding path program 1 times [2023-11-29 01:22:55,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:55,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1918411002] [2023-11-29 01:22:55,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:55,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:55,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:55,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:55,112 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:55,113 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1918411002] [2023-11-29 01:22:55,113 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1918411002] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:55,113 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:55,113 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:22:55,114 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1232817944] [2023-11-29 01:22:55,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:55,114 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:22:55,115 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:55,115 INFO L85 PathProgramCache]: Analyzing trace with hash -2069491216, now seen corresponding path program 1 times [2023-11-29 01:22:55,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:55,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192648530] [2023-11-29 01:22:55,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:55,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:55,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:55,151 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:55,152 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:55,152 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192648530] [2023-11-29 01:22:55,152 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192648530] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:55,152 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:55,153 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:22:55,153 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615261244] [2023-11-29 01:22:55,153 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:55,153 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:22:55,154 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:22:55,154 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:22:55,154 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:22:55,154 INFO L87 Difference]: Start difference. First operand 1669 states and 2937 transitions. cyclomatic complexity: 1276 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:55,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:22:55,418 INFO L93 Difference]: Finished difference Result 1999 states and 3465 transitions. [2023-11-29 01:22:55,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1999 states and 3465 transitions. [2023-11-29 01:22:55,436 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1872 [2023-11-29 01:22:55,453 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1999 states to 1999 states and 3465 transitions. [2023-11-29 01:22:55,454 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1999 [2023-11-29 01:22:55,456 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1999 [2023-11-29 01:22:55,456 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1999 states and 3465 transitions. [2023-11-29 01:22:55,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:22:55,460 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2023-11-29 01:22:55,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1999 states and 3465 transitions. [2023-11-29 01:22:55,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1999 to 1999. [2023-11-29 01:22:55,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1999 states, 1999 states have (on average 1.7333666833416708) internal successors, (3465), 1998 states have internal predecessors, (3465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:55,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1999 states to 1999 states and 3465 transitions. [2023-11-29 01:22:55,510 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2023-11-29 01:22:55,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:22:55,513 INFO L428 stractBuchiCegarLoop]: Abstraction has 1999 states and 3465 transitions. [2023-11-29 01:22:55,513 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-29 01:22:55,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1999 states and 3465 transitions. [2023-11-29 01:22:55,524 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1872 [2023-11-29 01:22:55,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:22:55,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:22:55,526 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:55,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:55,526 INFO L748 eck$LassoCheckResult]: Stem: 8385#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 8386#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 8216#L256 assume !(1 == ~main_in1_req_up~0); 8168#L256-2 assume !(1 == ~main_in2_req_up~0); 8170#L267-1 assume !(1 == ~main_sum_req_up~0); 8203#L278-1 assume !(1 == ~main_diff_req_up~0); 8151#L289-1 assume !(1 == ~main_pres_req_up~0); 8152#L300-1 assume !(1 == ~main_dbl_req_up~0); 8422#L311-1 assume !(1 == ~main_zero_req_up~0); 8419#L322-1 assume !(1 == ~main_clk_req_up~0); 8643#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 8642#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 8190#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 8191#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 8375#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 8640#L371-1 assume !(0 == ~main_in1_ev~0); 8639#L376-1 assume !(0 == ~main_in2_ev~0); 8584#L381-1 assume !(0 == ~main_sum_ev~0); 8585#L386-1 assume !(0 == ~main_diff_ev~0); 8593#L391-1 assume !(0 == ~main_pres_ev~0); 8522#L396-1 assume !(0 == ~main_dbl_ev~0); 8523#L401-1 assume !(0 == ~main_zero_ev~0); 9930#L406-1 assume !(0 == ~main_clk_ev~0); 9927#L411-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 9928#L416-1 assume !(0 == ~main_clk_neg_edge~0); 9920#L421-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 9921#L426-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 9912#L431-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 9911#L436-1 assume !(1 == ~main_clk_pos_edge~0); 9909#L441-1 assume !(1 == ~main_clk_pos_edge~0); 9906#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 8568#L451-1 assume !(1 == ~main_in2_ev~0); 8569#L456-1 assume !(1 == ~main_sum_ev~0); 8402#L461-1 assume !(1 == ~main_diff_ev~0); 8403#L466-1 assume !(1 == ~main_pres_ev~0); 8623#L471-1 assume !(1 == ~main_dbl_ev~0); 8205#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 8206#L481-1 assume !(1 == ~main_clk_ev~0); 8332#L486-1 assume !(1 == ~main_clk_pos_edge~0); 8210#L491-1 assume !(1 == ~main_clk_neg_edge~0); 8211#L742-1 [2023-11-29 01:22:55,527 INFO L750 eck$LassoCheckResult]: Loop: 8211#L742-1 assume !false; 8621#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 8245#L229 assume !false; 9421#L147 assume !(0 == ~N_generate_st~0); 9419#L151 assume !(0 == ~S1_addsub_st~0); 9417#L154 assume !(0 == ~S2_presdbl_st~0); 9415#L157 assume !(0 == ~S3_zero_st~0); 9413#L160 assume !(0 == ~D_print_st~0); 9411#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 9409#L509 assume !(1 == ~main_in1_req_up~0); 9406#L509-2 assume !(1 == ~main_in2_req_up~0); 9402#L520-1 assume !(1 == ~main_sum_req_up~0); 9388#L531-1 assume !(1 == ~main_diff_req_up~0); 9385#L542-1 assume !(1 == ~main_pres_req_up~0); 9381#L553-1 assume !(1 == ~main_dbl_req_up~0); 9377#L564-1 assume !(1 == ~main_zero_req_up~0); 9373#L575-1 assume !(1 == ~main_clk_req_up~0); 9370#L586-1 start_simulation_~kernel_st~0#1 := 3; 9368#L605 assume !(0 == ~main_in1_ev~0); 9367#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 9366#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 9364#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 9362#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 9360#L625-1 assume !(0 == ~main_dbl_ev~0); 9358#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 9356#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 9355#L640-1 assume !(0 == ~main_clk_pos_edge~0); 8320#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 8321#L650-1 assume !(1 == ~main_clk_pos_edge~0); 9349#L655-1 assume !(1 == ~main_clk_pos_edge~0); 9346#L660-1 assume !(1 == ~main_clk_pos_edge~0); 9343#L665-1 assume !(1 == ~main_clk_pos_edge~0); 9333#L670-1 assume !(1 == ~main_clk_pos_edge~0); 9332#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 9329#L680-1 assume !(1 == ~main_in2_ev~0); 9327#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 9325#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 9323#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 9322#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 9319#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 9318#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 9317#L715-1 assume !(1 == ~main_clk_pos_edge~0); 9315#L720-1 assume !(1 == ~main_clk_neg_edge~0); 9314#L725-1 assume 0 == ~N_generate_st~0; 8211#L742-1 [2023-11-29 01:22:55,527 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:55,527 INFO L85 PathProgramCache]: Analyzing trace with hash 787031863, now seen corresponding path program 1 times [2023-11-29 01:22:55,527 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:55,527 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705728551] [2023-11-29 01:22:55,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:55,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:55,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:55,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:55,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:55,626 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1705728551] [2023-11-29 01:22:55,626 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1705728551] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:55,626 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:55,626 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:22:55,626 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1018778877] [2023-11-29 01:22:55,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:55,627 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:22:55,627 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:55,628 INFO L85 PathProgramCache]: Analyzing trace with hash -1415211856, now seen corresponding path program 1 times [2023-11-29 01:22:55,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:55,628 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864250689] [2023-11-29 01:22:55,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:55,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:55,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:55,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:55,662 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:55,662 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [864250689] [2023-11-29 01:22:55,662 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [864250689] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:55,663 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:55,663 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:22:55,663 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [241060390] [2023-11-29 01:22:55,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:55,664 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:22:55,664 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:22:55,664 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:22:55,664 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:22:55,665 INFO L87 Difference]: Start difference. First operand 1999 states and 3465 transitions. cyclomatic complexity: 1474 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:56,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:22:56,056 INFO L93 Difference]: Finished difference Result 4015 states and 6814 transitions. [2023-11-29 01:22:56,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4015 states and 6814 transitions. [2023-11-29 01:22:56,096 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3762 [2023-11-29 01:22:56,137 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4015 states to 4015 states and 6814 transitions. [2023-11-29 01:22:56,137 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4015 [2023-11-29 01:22:56,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4015 [2023-11-29 01:22:56,143 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4015 states and 6814 transitions. [2023-11-29 01:22:56,152 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:22:56,152 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4015 states and 6814 transitions. [2023-11-29 01:22:56,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4015 states and 6814 transitions. [2023-11-29 01:22:56,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4015 to 3985. [2023-11-29 01:22:56,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3985 states, 3985 states have (on average 1.6948557089084064) internal successors, (6754), 3984 states have internal predecessors, (6754), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:56,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3985 states to 3985 states and 6754 transitions. [2023-11-29 01:22:56,270 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3985 states and 6754 transitions. [2023-11-29 01:22:56,270 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-29 01:22:56,271 INFO L428 stractBuchiCegarLoop]: Abstraction has 3985 states and 6754 transitions. [2023-11-29 01:22:56,271 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-29 01:22:56,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3985 states and 6754 transitions. [2023-11-29 01:22:56,298 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3762 [2023-11-29 01:22:56,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:22:56,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:22:56,300 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:56,300 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:56,300 INFO L748 eck$LassoCheckResult]: Stem: 14409#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 14410#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 14238#L256 assume !(1 == ~main_in1_req_up~0); 14192#L256-2 assume !(1 == ~main_in2_req_up~0); 14194#L267-1 assume !(1 == ~main_sum_req_up~0); 14225#L278-1 assume !(1 == ~main_diff_req_up~0); 14175#L289-1 assume !(1 == ~main_pres_req_up~0); 14176#L300-1 assume !(1 == ~main_dbl_req_up~0); 14286#L311-1 assume !(1 == ~main_zero_req_up~0); 16526#L322-1 assume !(1 == ~main_clk_req_up~0); 16527#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 16821#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 16819#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 16817#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 16815#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 16813#L371-1 assume !(0 == ~main_in1_ev~0); 16811#L376-1 assume !(0 == ~main_in2_ev~0); 16809#L381-1 assume !(0 == ~main_sum_ev~0); 16805#L386-1 assume !(0 == ~main_diff_ev~0); 16800#L391-1 assume !(0 == ~main_pres_ev~0); 16795#L396-1 assume !(0 == ~main_dbl_ev~0); 16793#L401-1 assume !(0 == ~main_zero_ev~0); 16791#L406-1 assume !(0 == ~main_clk_ev~0); 16788#L411-1 assume !(0 == ~main_clk_pos_edge~0); 16785#L416-1 assume !(0 == ~main_clk_neg_edge~0); 16782#L421-1 assume !(1 == ~main_clk_pos_edge~0); 16780#L426-1 assume !(1 == ~main_clk_pos_edge~0); 16778#L431-1 assume !(1 == ~main_clk_pos_edge~0); 16775#L436-1 assume !(1 == ~main_clk_pos_edge~0); 16771#L441-1 assume !(1 == ~main_clk_pos_edge~0); 16767#L446-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 14662#L451-1 assume !(1 == ~main_in2_ev~0); 16832#L456-1 assume !(1 == ~main_sum_ev~0); 14427#L461-1 assume !(1 == ~main_diff_ev~0); 14428#L466-1 assume !(1 == ~main_pres_ev~0); 14657#L471-1 assume !(1 == ~main_dbl_ev~0); 14227#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 14228#L481-1 assume !(1 == ~main_clk_ev~0); 14358#L486-1 assume !(1 == ~main_clk_pos_edge~0); 14232#L491-1 assume !(1 == ~main_clk_neg_edge~0); 14233#L742-1 [2023-11-29 01:22:56,300 INFO L750 eck$LassoCheckResult]: Loop: 14233#L742-1 assume !false; 14571#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 14267#L229 assume !false; 14522#L147 assume !(0 == ~N_generate_st~0); 14301#L151 assume !(0 == ~S1_addsub_st~0); 14302#L154 assume !(0 == ~S2_presdbl_st~0); 14185#L157 assume !(0 == ~S3_zero_st~0); 14187#L160 assume !(0 == ~D_print_st~0); 14305#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 14306#L509 assume !(1 == ~main_in1_req_up~0); 14574#L509-2 assume !(1 == ~main_in2_req_up~0); 16727#L520-1 assume !(1 == ~main_sum_req_up~0); 16723#L531-1 assume !(1 == ~main_diff_req_up~0); 16721#L542-1 assume !(1 == ~main_pres_req_up~0); 16717#L553-1 assume !(1 == ~main_dbl_req_up~0); 16718#L564-1 assume !(1 == ~main_zero_req_up~0); 16696#L575-1 assume !(1 == ~main_clk_req_up~0); 16694#L586-1 start_simulation_~kernel_st~0#1 := 3; 16692#L605 assume !(0 == ~main_in1_ev~0); 16691#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 16686#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 16684#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 16682#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 16680#L625-1 assume !(0 == ~main_dbl_ev~0); 16677#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 16675#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 16672#L640-1 assume !(0 == ~main_clk_pos_edge~0); 16596#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 16669#L650-1 assume !(1 == ~main_clk_pos_edge~0); 16591#L655-1 assume !(1 == ~main_clk_pos_edge~0); 16588#L660-1 assume !(1 == ~main_clk_pos_edge~0); 16585#L665-1 assume !(1 == ~main_clk_pos_edge~0); 16433#L670-1 assume !(1 == ~main_clk_pos_edge~0); 16428#L675-1 assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2; 16177#L680-1 assume !(1 == ~main_in2_ev~0); 16423#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 16421#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 16419#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 16417#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 16133#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 16413#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 16411#L715-1 assume !(1 == ~main_clk_pos_edge~0); 16409#L720-1 assume !(1 == ~main_clk_neg_edge~0); 16408#L725-1 assume 0 == ~N_generate_st~0; 14233#L742-1 [2023-11-29 01:22:56,301 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:56,301 INFO L85 PathProgramCache]: Analyzing trace with hash 615864315, now seen corresponding path program 1 times [2023-11-29 01:22:56,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:56,301 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254247745] [2023-11-29 01:22:56,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:56,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:56,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:56,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:56,405 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:56,405 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254247745] [2023-11-29 01:22:56,405 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [254247745] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:56,405 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:56,406 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:22:56,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692153162] [2023-11-29 01:22:56,406 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:56,407 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:22:56,407 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:56,407 INFO L85 PathProgramCache]: Analyzing trace with hash -1415211856, now seen corresponding path program 2 times [2023-11-29 01:22:56,408 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:56,408 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318384307] [2023-11-29 01:22:56,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:56,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:56,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:56,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:56,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:56,444 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1318384307] [2023-11-29 01:22:56,444 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1318384307] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:56,444 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:56,444 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:22:56,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585283522] [2023-11-29 01:22:56,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:56,445 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:22:56,445 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:22:56,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:22:56,446 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:22:56,446 INFO L87 Difference]: Start difference. First operand 3985 states and 6754 transitions. cyclomatic complexity: 2785 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:56,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:22:56,800 INFO L93 Difference]: Finished difference Result 4445 states and 7522 transitions. [2023-11-29 01:22:56,801 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4445 states and 7522 transitions. [2023-11-29 01:22:56,823 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4162 [2023-11-29 01:22:56,851 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4445 states to 4445 states and 7522 transitions. [2023-11-29 01:22:56,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4445 [2023-11-29 01:22:56,856 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4445 [2023-11-29 01:22:56,856 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4445 states and 7522 transitions. [2023-11-29 01:22:56,863 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:22:56,863 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4445 states and 7522 transitions. [2023-11-29 01:22:56,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4445 states and 7522 transitions. [2023-11-29 01:22:56,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4445 to 4415. [2023-11-29 01:22:56,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4415 states, 4415 states have (on average 1.6901472253680634) internal successors, (7462), 4414 states have internal predecessors, (7462), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:56,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4415 states to 4415 states and 7462 transitions. [2023-11-29 01:22:56,940 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4415 states and 7462 transitions. [2023-11-29 01:22:56,940 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:22:56,941 INFO L428 stractBuchiCegarLoop]: Abstraction has 4415 states and 7462 transitions. [2023-11-29 01:22:56,942 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-29 01:22:56,942 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4415 states and 7462 transitions. [2023-11-29 01:22:56,959 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4162 [2023-11-29 01:22:56,960 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:22:56,960 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:22:56,961 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:56,961 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:56,961 INFO L748 eck$LassoCheckResult]: Stem: 22849#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 22850#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 22679#L256 assume !(1 == ~main_in1_req_up~0); 22633#L256-2 assume !(1 == ~main_in2_req_up~0); 22635#L267-1 assume !(1 == ~main_sum_req_up~0); 22666#L278-1 assume !(1 == ~main_diff_req_up~0); 22616#L289-1 assume !(1 == ~main_pres_req_up~0); 22617#L300-1 assume !(1 == ~main_dbl_req_up~0); 23011#L311-1 assume !(1 == ~main_zero_req_up~0); 25232#L322-1 assume !(1 == ~main_clk_req_up~0); 25233#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 26482#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 26479#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 26476#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 26472#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 26468#L371-1 assume !(0 == ~main_in1_ev~0); 26466#L376-1 assume !(0 == ~main_in2_ev~0); 26464#L381-1 assume !(0 == ~main_sum_ev~0); 26462#L386-1 assume !(0 == ~main_diff_ev~0); 26460#L391-1 assume !(0 == ~main_pres_ev~0); 26458#L396-1 assume !(0 == ~main_dbl_ev~0); 26456#L401-1 assume !(0 == ~main_zero_ev~0); 26454#L406-1 assume !(0 == ~main_clk_ev~0); 26452#L411-1 assume !(0 == ~main_clk_pos_edge~0); 26450#L416-1 assume !(0 == ~main_clk_neg_edge~0); 26448#L421-1 assume !(1 == ~main_clk_pos_edge~0); 26446#L426-1 assume !(1 == ~main_clk_pos_edge~0); 26444#L431-1 assume !(1 == ~main_clk_pos_edge~0); 26442#L436-1 assume !(1 == ~main_clk_pos_edge~0); 26440#L441-1 assume !(1 == ~main_clk_pos_edge~0); 26438#L446-1 assume !(1 == ~main_in1_ev~0); 26436#L451-1 assume !(1 == ~main_in2_ev~0); 26434#L456-1 assume !(1 == ~main_sum_ev~0); 26432#L461-1 assume !(1 == ~main_diff_ev~0); 26430#L466-1 assume !(1 == ~main_pres_ev~0); 26428#L471-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 22668#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 22669#L481-1 assume !(1 == ~main_clk_ev~0); 22797#L486-1 assume !(1 == ~main_clk_pos_edge~0); 22673#L491-1 assume !(1 == ~main_clk_neg_edge~0); 22674#L742-1 [2023-11-29 01:22:56,962 INFO L750 eck$LassoCheckResult]: Loop: 22674#L742-1 assume !false; 23008#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 22708#L229 assume !false; 22966#L147 assume !(0 == ~N_generate_st~0); 22742#L151 assume !(0 == ~S1_addsub_st~0); 22743#L154 assume !(0 == ~S2_presdbl_st~0); 22626#L157 assume !(0 == ~S3_zero_st~0); 22628#L160 assume !(0 == ~D_print_st~0); 23053#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 26770#L509 assume !(1 == ~main_in1_req_up~0); 26768#L509-2 assume !(1 == ~main_in2_req_up~0); 26765#L520-1 assume !(1 == ~main_sum_req_up~0); 26761#L531-1 assume !(1 == ~main_diff_req_up~0); 26759#L542-1 assume !(1 == ~main_pres_req_up~0); 23099#L553-1 assume !(1 == ~main_dbl_req_up~0); 23100#L564-1 assume !(1 == ~main_zero_req_up~0); 26962#L575-1 assume !(1 == ~main_clk_req_up~0); 26960#L586-1 start_simulation_~kernel_st~0#1 := 3; 26959#L605 assume !(0 == ~main_in1_ev~0); 26958#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 26955#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 26951#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 26949#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 26947#L625-1 assume !(0 == ~main_dbl_ev~0); 26944#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 26647#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 26646#L640-1 assume !(0 == ~main_clk_pos_edge~0); 26645#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 26644#L650-1 assume !(1 == ~main_clk_pos_edge~0); 26643#L655-1 assume !(1 == ~main_clk_pos_edge~0); 26642#L660-1 assume !(1 == ~main_clk_pos_edge~0); 26641#L665-1 assume !(1 == ~main_clk_pos_edge~0); 26640#L670-1 assume !(1 == ~main_clk_pos_edge~0); 26639#L675-1 assume !(1 == ~main_in1_ev~0); 26637#L680-1 assume !(1 == ~main_in2_ev~0); 26636#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 26635#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 26632#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 26628#L700-1 assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2; 26425#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 26621#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 26100#L715-1 assume !(1 == ~main_clk_pos_edge~0); 22864#L720-1 assume !(1 == ~main_clk_neg_edge~0); 22865#L725-1 assume 0 == ~N_generate_st~0; 22674#L742-1 [2023-11-29 01:22:56,962 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:56,962 INFO L85 PathProgramCache]: Analyzing trace with hash 220990263, now seen corresponding path program 1 times [2023-11-29 01:22:56,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:56,963 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1786441465] [2023-11-29 01:22:56,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:56,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:56,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:57,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:57,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:57,016 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1786441465] [2023-11-29 01:22:57,016 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1786441465] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:57,016 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:57,016 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:22:57,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579725697] [2023-11-29 01:22:57,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:57,017 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:22:57,018 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:57,018 INFO L85 PathProgramCache]: Analyzing trace with hash -714147278, now seen corresponding path program 1 times [2023-11-29 01:22:57,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:57,018 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1001753278] [2023-11-29 01:22:57,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:57,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:57,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:57,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:57,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:57,084 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1001753278] [2023-11-29 01:22:57,084 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1001753278] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:57,084 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:57,085 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:22:57,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2136013233] [2023-11-29 01:22:57,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:57,085 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:22:57,085 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:22:57,086 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:22:57,086 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:22:57,086 INFO L87 Difference]: Start difference. First operand 4415 states and 7462 transitions. cyclomatic complexity: 3063 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:57,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:22:57,418 INFO L93 Difference]: Finished difference Result 5574 states and 9318 transitions. [2023-11-29 01:22:57,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5574 states and 9318 transitions. [2023-11-29 01:22:57,453 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 5240 [2023-11-29 01:22:57,501 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5574 states to 5574 states and 9318 transitions. [2023-11-29 01:22:57,501 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5574 [2023-11-29 01:22:57,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5574 [2023-11-29 01:22:57,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5574 states and 9318 transitions. [2023-11-29 01:22:57,520 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:22:57,520 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5574 states and 9318 transitions. [2023-11-29 01:22:57,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5574 states and 9318 transitions. [2023-11-29 01:22:57,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5574 to 5130. [2023-11-29 01:22:57,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5130 states, 5130 states have (on average 1.6754385964912282) internal successors, (8595), 5129 states have internal predecessors, (8595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:57,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5130 states to 5130 states and 8595 transitions. [2023-11-29 01:22:57,656 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5130 states and 8595 transitions. [2023-11-29 01:22:57,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:22:57,657 INFO L428 stractBuchiCegarLoop]: Abstraction has 5130 states and 8595 transitions. [2023-11-29 01:22:57,658 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-29 01:22:57,658 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5130 states and 8595 transitions. [2023-11-29 01:22:57,680 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4812 [2023-11-29 01:22:57,681 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:22:57,681 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:22:57,682 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:57,682 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:57,682 INFO L748 eck$LassoCheckResult]: Stem: 32846#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 32847#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 32679#L256 assume !(1 == ~main_in1_req_up~0); 32633#L256-2 assume !(1 == ~main_in2_req_up~0); 32635#L267-1 assume !(1 == ~main_sum_req_up~0); 32666#L278-1 assume !(1 == ~main_diff_req_up~0); 32616#L289-1 assume !(1 == ~main_pres_req_up~0); 32617#L300-1 assume !(1 == ~main_dbl_req_up~0); 32726#L311-1 assume !(1 == ~main_zero_req_up~0); 33068#L322-1 assume !(1 == ~main_clk_req_up~0); 32950#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 32842#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 32843#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 33273#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 33274#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 33269#L371-1 assume !(0 == ~main_in1_ev~0); 33270#L376-1 assume !(0 == ~main_in2_ev~0); 33053#L381-1 assume !(0 == ~main_sum_ev~0); 33054#L386-1 assume !(0 == ~main_diff_ev~0); 33065#L391-1 assume !(0 == ~main_pres_ev~0); 32987#L396-1 assume !(0 == ~main_dbl_ev~0); 32988#L401-1 assume !(0 == ~main_zero_ev~0); 33750#L406-1 assume !(0 == ~main_clk_ev~0); 33751#L411-1 assume !(0 == ~main_clk_pos_edge~0); 33741#L416-1 assume !(0 == ~main_clk_neg_edge~0); 33742#L421-1 assume !(1 == ~main_clk_pos_edge~0); 33730#L426-1 assume !(1 == ~main_clk_pos_edge~0); 33731#L431-1 assume !(1 == ~main_clk_pos_edge~0); 33720#L436-1 assume !(1 == ~main_clk_pos_edge~0); 33721#L441-1 assume !(1 == ~main_clk_pos_edge~0); 33703#L446-1 assume !(1 == ~main_in1_ev~0); 33704#L451-1 assume !(1 == ~main_in2_ev~0); 33112#L456-1 assume !(1 == ~main_sum_ev~0); 32866#L461-1 assume !(1 == ~main_diff_ev~0); 32867#L466-1 assume !(1 == ~main_pres_ev~0); 33657#L471-1 assume !(1 == ~main_dbl_ev~0); 33658#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 33612#L481-1 assume !(1 == ~main_clk_ev~0); 33613#L486-1 assume !(1 == ~main_clk_pos_edge~0); 33590#L491-1 assume !(1 == ~main_clk_neg_edge~0); 33591#L742-1 [2023-11-29 01:22:57,682 INFO L750 eck$LassoCheckResult]: Loop: 33591#L742-1 assume !false; 33577#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 33571#L229 assume !false; 33566#L147 assume !(0 == ~N_generate_st~0); 33559#L151 assume !(0 == ~S1_addsub_st~0); 33560#L154 assume !(0 == ~S2_presdbl_st~0); 33564#L157 assume !(0 == ~S3_zero_st~0); 33565#L160 assume !(0 == ~D_print_st~0); 33733#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 33734#L509 assume !(1 == ~main_in1_req_up~0); 33716#L509-2 assume !(1 == ~main_in2_req_up~0); 33708#L520-1 assume !(1 == ~main_sum_req_up~0); 33707#L531-1 assume !(1 == ~main_diff_req_up~0); 35147#L542-1 assume !(1 == ~main_pres_req_up~0); 33680#L553-1 assume !(1 == ~main_dbl_req_up~0); 33679#L564-1 assume !(1 == ~main_zero_req_up~0); 33661#L575-1 assume !(1 == ~main_clk_req_up~0); 33662#L586-1 start_simulation_~kernel_st~0#1 := 3; 33778#L605 assume !(0 == ~main_in1_ev~0); 33777#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 33776#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 33772#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 33768#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 33763#L625-1 assume !(0 == ~main_dbl_ev~0); 33759#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 33757#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 33752#L640-1 assume !(0 == ~main_clk_pos_edge~0); 33747#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 33743#L650-1 assume !(1 == ~main_clk_pos_edge~0); 33738#L655-1 assume !(1 == ~main_clk_pos_edge~0); 33732#L660-1 assume !(1 == ~main_clk_pos_edge~0); 33725#L665-1 assume !(1 == ~main_clk_pos_edge~0); 33722#L670-1 assume !(1 == ~main_clk_pos_edge~0); 33714#L675-1 assume !(1 == ~main_in1_ev~0); 33705#L680-1 assume !(1 == ~main_in2_ev~0); 33697#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 33685#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 33674#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 33675#L700-1 assume !(1 == ~main_dbl_ev~0); 33659#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 33660#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 33616#L715-1 assume !(1 == ~main_clk_pos_edge~0); 33617#L720-1 assume !(1 == ~main_clk_neg_edge~0); 33594#L725-1 assume 0 == ~N_generate_st~0; 33591#L742-1 [2023-11-29 01:22:57,683 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:57,683 INFO L85 PathProgramCache]: Analyzing trace with hash 222837305, now seen corresponding path program 1 times [2023-11-29 01:22:57,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:57,683 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338616361] [2023-11-29 01:22:57,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:57,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:57,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:57,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:57,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:57,746 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [338616361] [2023-11-29 01:22:57,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [338616361] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:57,747 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:57,747 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:22:57,747 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1422028528] [2023-11-29 01:22:57,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:57,748 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:22:57,748 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:57,748 INFO L85 PathProgramCache]: Analyzing trace with hash -656888976, now seen corresponding path program 1 times [2023-11-29 01:22:57,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:57,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1536832343] [2023-11-29 01:22:57,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:57,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:57,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:57,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:57,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:57,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1536832343] [2023-11-29 01:22:57,776 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1536832343] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:57,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:57,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:22:57,776 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579088476] [2023-11-29 01:22:57,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:57,777 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:22:57,777 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:22:57,777 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:22:57,777 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:22:57,778 INFO L87 Difference]: Start difference. First operand 5130 states and 8595 transitions. cyclomatic complexity: 3481 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:58,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:22:58,177 INFO L93 Difference]: Finished difference Result 9446 states and 15503 transitions. [2023-11-29 01:22:58,177 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9446 states and 15503 transitions. [2023-11-29 01:22:58,230 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 8840 [2023-11-29 01:22:58,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9446 states to 9446 states and 15503 transitions. [2023-11-29 01:22:58,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9446 [2023-11-29 01:22:58,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9446 [2023-11-29 01:22:58,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9446 states and 15503 transitions. [2023-11-29 01:22:58,321 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:22:58,321 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9446 states and 15503 transitions. [2023-11-29 01:22:58,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9446 states and 15503 transitions. [2023-11-29 01:22:58,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9446 to 6978. [2023-11-29 01:22:58,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6978 states, 6978 states have (on average 1.65262252794497) internal successors, (11532), 6977 states have internal predecessors, (11532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:58,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6978 states to 6978 states and 11532 transitions. [2023-11-29 01:22:58,561 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6978 states and 11532 transitions. [2023-11-29 01:22:58,562 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:22:58,566 INFO L428 stractBuchiCegarLoop]: Abstraction has 6978 states and 11532 transitions. [2023-11-29 01:22:58,567 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-29 01:22:58,567 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6978 states and 11532 transitions. [2023-11-29 01:22:58,587 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6492 [2023-11-29 01:22:58,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:22:58,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:22:58,588 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:58,588 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:58,588 INFO L748 eck$LassoCheckResult]: Stem: 47434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 47435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 47266#L256 assume !(1 == ~main_in1_req_up~0); 47220#L256-2 assume !(1 == ~main_in2_req_up~0); 47222#L267-1 assume !(1 == ~main_sum_req_up~0); 47253#L278-1 assume !(1 == ~main_diff_req_up~0); 47203#L289-1 assume !(1 == ~main_pres_req_up~0); 47204#L300-1 assume !(1 == ~main_dbl_req_up~0); 47313#L311-1 assume !(1 == ~main_zero_req_up~0); 47667#L322-1 assume !(1 == ~main_clk_req_up~0); 47444#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 47432#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 47242#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 47243#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 47426#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 47420#L371-1 assume !(0 == ~main_in1_ev~0); 47421#L376-1 assume !(0 == ~main_in2_ev~0); 47654#L381-1 assume !(0 == ~main_sum_ev~0); 47655#L386-1 assume !(0 == ~main_diff_ev~0); 47664#L391-1 assume !(0 == ~main_pres_ev~0); 47591#L396-1 assume !(0 == ~main_dbl_ev~0); 47363#L401-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 47364#L406-1 assume !(0 == ~main_clk_ev~0); 49731#L411-1 assume !(0 == ~main_clk_pos_edge~0); 49727#L416-1 assume !(0 == ~main_clk_neg_edge~0); 49728#L421-1 assume !(1 == ~main_clk_pos_edge~0); 49723#L426-1 assume !(1 == ~main_clk_pos_edge~0); 49724#L431-1 assume !(1 == ~main_clk_pos_edge~0); 49719#L436-1 assume !(1 == ~main_clk_pos_edge~0); 49720#L441-1 assume !(1 == ~main_clk_pos_edge~0); 49717#L446-1 assume !(1 == ~main_in1_ev~0); 49718#L451-1 assume !(1 == ~main_in2_ev~0); 49714#L456-1 assume !(1 == ~main_sum_ev~0); 49715#L461-1 assume !(1 == ~main_diff_ev~0); 49710#L466-1 assume !(1 == ~main_pres_ev~0); 49711#L471-1 assume !(1 == ~main_dbl_ev~0); 49708#L476-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 47547#L481-1 assume !(1 == ~main_clk_ev~0); 47382#L486-1 assume !(1 == ~main_clk_pos_edge~0); 47383#L491-1 assume !(1 == ~main_clk_neg_edge~0); 49523#L742-1 [2023-11-29 01:22:58,588 INFO L750 eck$LassoCheckResult]: Loop: 49523#L742-1 assume !false; 49686#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 49680#L229 assume !false; 49668#L147 assume !(0 == ~N_generate_st~0); 49664#L151 assume !(0 == ~S1_addsub_st~0); 49665#L154 assume !(0 == ~S2_presdbl_st~0); 49666#L157 assume !(0 == ~S3_zero_st~0); 49667#L160 assume !(0 == ~D_print_st~0); 49669#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 49682#L509 assume !(1 == ~main_in1_req_up~0); 49678#L509-2 assume !(1 == ~main_in2_req_up~0); 49674#L520-1 assume !(1 == ~main_sum_req_up~0); 49661#L531-1 assume !(1 == ~main_diff_req_up~0); 49656#L542-1 assume !(1 == ~main_pres_req_up~0); 49648#L553-1 assume !(1 == ~main_dbl_req_up~0); 49640#L564-1 assume !(1 == ~main_zero_req_up~0); 49607#L575-1 assume !(1 == ~main_clk_req_up~0); 49608#L586-1 start_simulation_~kernel_st~0#1 := 3; 49676#L605 assume !(0 == ~main_in1_ev~0); 49672#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 49671#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 49660#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 49653#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 49645#L625-1 assume !(0 == ~main_dbl_ev~0); 49646#L630-1 assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1; 49634#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 49635#L640-1 assume !(0 == ~main_clk_pos_edge~0); 49631#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 49632#L650-1 assume !(1 == ~main_clk_pos_edge~0); 49628#L655-1 assume !(1 == ~main_clk_pos_edge~0); 49629#L660-1 assume !(1 == ~main_clk_pos_edge~0); 49626#L665-1 assume !(1 == ~main_clk_pos_edge~0); 49627#L670-1 assume !(1 == ~main_clk_pos_edge~0); 49624#L675-1 assume !(1 == ~main_in1_ev~0); 49625#L680-1 assume !(1 == ~main_in2_ev~0); 49620#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 49621#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 49616#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 49617#L700-1 assume !(1 == ~main_dbl_ev~0); 49612#L705-1 assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2; 49606#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 49546#L715-1 assume !(1 == ~main_clk_pos_edge~0); 49540#L720-1 assume !(1 == ~main_clk_neg_edge~0); 49535#L725-1 assume 0 == ~N_generate_st~0; 49523#L742-1 [2023-11-29 01:22:58,589 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:58,589 INFO L85 PathProgramCache]: Analyzing trace with hash 1911781047, now seen corresponding path program 1 times [2023-11-29 01:22:58,589 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:58,589 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [723784351] [2023-11-29 01:22:58,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:58,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:58,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:58,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:58,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:58,636 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [723784351] [2023-11-29 01:22:58,636 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [723784351] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:58,636 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:58,637 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:22:58,637 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345533548] [2023-11-29 01:22:58,637 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:58,637 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:22:58,638 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:58,638 INFO L85 PathProgramCache]: Analyzing trace with hash -656888976, now seen corresponding path program 2 times [2023-11-29 01:22:58,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:58,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134134637] [2023-11-29 01:22:58,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:58,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:58,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:58,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:58,659 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:58,660 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [134134637] [2023-11-29 01:22:58,660 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [134134637] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:58,660 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:58,660 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:22:58,660 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [578136682] [2023-11-29 01:22:58,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:58,661 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:22:58,661 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:22:58,661 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:22:58,662 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:22:58,662 INFO L87 Difference]: Start difference. First operand 6978 states and 11532 transitions. cyclomatic complexity: 4570 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:58,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:22:58,854 INFO L93 Difference]: Finished difference Result 12839 states and 21043 transitions. [2023-11-29 01:22:58,855 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12839 states and 21043 transitions. [2023-11-29 01:22:58,983 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 12108 [2023-11-29 01:22:59,048 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12839 states to 12839 states and 21043 transitions. [2023-11-29 01:22:59,048 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12839 [2023-11-29 01:22:59,058 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12839 [2023-11-29 01:22:59,058 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12839 states and 21043 transitions. [2023-11-29 01:22:59,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:22:59,074 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2023-11-29 01:22:59,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12839 states and 21043 transitions. [2023-11-29 01:22:59,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12839 to 12839. [2023-11-29 01:22:59,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12839 states, 12839 states have (on average 1.6389905755899992) internal successors, (21043), 12838 states have internal predecessors, (21043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:59,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12839 states to 12839 states and 21043 transitions. [2023-11-29 01:22:59,353 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2023-11-29 01:22:59,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-29 01:22:59,354 INFO L428 stractBuchiCegarLoop]: Abstraction has 12839 states and 21043 transitions. [2023-11-29 01:22:59,355 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-29 01:22:59,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12839 states and 21043 transitions. [2023-11-29 01:22:59,401 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 12108 [2023-11-29 01:22:59,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:22:59,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:22:59,403 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:59,403 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:22:59,403 INFO L748 eck$LassoCheckResult]: Stem: 67266#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 67267#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 67094#L256 assume !(1 == ~main_in1_req_up~0); 67048#L256-2 assume !(1 == ~main_in2_req_up~0); 67050#L267-1 assume !(1 == ~main_sum_req_up~0); 67081#L278-1 assume !(1 == ~main_diff_req_up~0); 67030#L289-1 assume !(1 == ~main_pres_req_up~0); 67031#L300-1 assume !(1 == ~main_dbl_req_up~0); 67431#L311-1 assume !(1 == ~main_zero_req_up~0); 71691#L322-1 assume !(1 == ~main_clk_req_up~0); 71688#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 71686#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 71684#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 71682#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 71680#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 71678#L371-1 assume !(0 == ~main_in1_ev~0); 71676#L376-1 assume !(0 == ~main_in2_ev~0); 71674#L381-1 assume !(0 == ~main_sum_ev~0); 71672#L386-1 assume !(0 == ~main_diff_ev~0); 71670#L391-1 assume !(0 == ~main_pres_ev~0); 71668#L396-1 assume !(0 == ~main_dbl_ev~0); 71666#L401-1 assume !(0 == ~main_zero_ev~0); 71664#L406-1 assume !(0 == ~main_clk_ev~0); 71662#L411-1 assume !(0 == ~main_clk_pos_edge~0); 71660#L416-1 assume !(0 == ~main_clk_neg_edge~0); 71658#L421-1 assume !(1 == ~main_clk_pos_edge~0); 71657#L426-1 assume !(1 == ~main_clk_pos_edge~0); 71656#L431-1 assume !(1 == ~main_clk_pos_edge~0); 71655#L436-1 assume !(1 == ~main_clk_pos_edge~0); 71654#L441-1 assume !(1 == ~main_clk_pos_edge~0); 71653#L446-1 assume !(1 == ~main_in1_ev~0); 71652#L451-1 assume !(1 == ~main_in2_ev~0); 71651#L456-1 assume !(1 == ~main_sum_ev~0); 71650#L461-1 assume !(1 == ~main_diff_ev~0); 71649#L466-1 assume !(1 == ~main_pres_ev~0); 71648#L471-1 assume !(1 == ~main_dbl_ev~0); 71647#L476-1 assume !(1 == ~main_zero_ev~0); 71644#L481-1 assume !(1 == ~main_clk_ev~0); 71640#L486-1 assume !(1 == ~main_clk_pos_edge~0); 71636#L491-1 assume !(1 == ~main_clk_neg_edge~0); 71505#L742-1 [2023-11-29 01:22:59,403 INFO L750 eck$LassoCheckResult]: Loop: 71505#L742-1 assume !false; 71632#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 71624#L229 assume !false; 71622#L147 assume !(0 == ~N_generate_st~0); 71620#L151 assume !(0 == ~S1_addsub_st~0); 71618#L154 assume !(0 == ~S2_presdbl_st~0); 71616#L157 assume !(0 == ~S3_zero_st~0); 71613#L160 assume !(0 == ~D_print_st~0); 71610#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 71608#L509 assume !(1 == ~main_in1_req_up~0); 71605#L509-2 assume !(1 == ~main_in2_req_up~0); 71599#L520-1 assume !(1 == ~main_sum_req_up~0); 71595#L531-1 assume !(1 == ~main_diff_req_up~0); 71590#L542-1 assume !(1 == ~main_pres_req_up~0); 71584#L553-1 assume !(1 == ~main_dbl_req_up~0); 71578#L564-1 assume !(1 == ~main_zero_req_up~0); 71572#L575-1 assume !(1 == ~main_clk_req_up~0); 71567#L586-1 start_simulation_~kernel_st~0#1 := 3; 71563#L605 assume !(0 == ~main_in1_ev~0); 71561#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 71559#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 71557#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 71555#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 71553#L625-1 assume !(0 == ~main_dbl_ev~0); 71551#L630-1 assume !(0 == ~main_zero_ev~0); 71549#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 71547#L640-1 assume !(0 == ~main_clk_pos_edge~0); 71545#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 71543#L650-1 assume !(1 == ~main_clk_pos_edge~0); 71541#L655-1 assume !(1 == ~main_clk_pos_edge~0); 71539#L660-1 assume !(1 == ~main_clk_pos_edge~0); 71537#L665-1 assume !(1 == ~main_clk_pos_edge~0); 71535#L670-1 assume !(1 == ~main_clk_pos_edge~0); 71533#L675-1 assume !(1 == ~main_in1_ev~0); 71531#L680-1 assume !(1 == ~main_in2_ev~0); 71529#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 71527#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 71525#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 71523#L700-1 assume !(1 == ~main_dbl_ev~0); 71521#L705-1 assume !(1 == ~main_zero_ev~0); 71519#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 71517#L715-1 assume !(1 == ~main_clk_pos_edge~0); 71515#L720-1 assume !(1 == ~main_clk_neg_edge~0); 71513#L725-1 assume 0 == ~N_generate_st~0; 71505#L742-1 [2023-11-29 01:22:59,404 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:59,404 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 1 times [2023-11-29 01:22:59,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:59,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535602769] [2023-11-29 01:22:59,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:59,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:59,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:22:59,418 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:22:59,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:22:59,464 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:22:59,464 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:22:59,465 INFO L85 PathProgramCache]: Analyzing trace with hash -1472690384, now seen corresponding path program 1 times [2023-11-29 01:22:59,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:22:59,465 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844252581] [2023-11-29 01:22:59,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:22:59,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:22:59,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:22:59,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:22:59,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:22:59,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844252581] [2023-11-29 01:22:59,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [844252581] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:22:59,491 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:22:59,491 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:22:59,491 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1926914437] [2023-11-29 01:22:59,491 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:22:59,492 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:22:59,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:22:59,492 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:22:59,493 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:22:59,493 INFO L87 Difference]: Start difference. First operand 12839 states and 21043 transitions. cyclomatic complexity: 8236 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:22:59,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:22:59,644 INFO L93 Difference]: Finished difference Result 18429 states and 29722 transitions. [2023-11-29 01:22:59,644 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18429 states and 29722 transitions. [2023-11-29 01:22:59,769 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17278 [2023-11-29 01:22:59,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18429 states to 18429 states and 29722 transitions. [2023-11-29 01:22:59,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18429 [2023-11-29 01:22:59,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18429 [2023-11-29 01:22:59,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18429 states and 29722 transitions. [2023-11-29 01:22:59,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:22:59,908 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18429 states and 29722 transitions. [2023-11-29 01:22:59,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18429 states and 29722 transitions. [2023-11-29 01:23:00,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18429 to 18429. [2023-11-29 01:23:00,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18429 states, 18429 states have (on average 1.6127841988170817) internal successors, (29722), 18428 states have internal predecessors, (29722), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:00,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18429 states to 18429 states and 29722 transitions. [2023-11-29 01:23:00,184 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18429 states and 29722 transitions. [2023-11-29 01:23:00,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:23:00,185 INFO L428 stractBuchiCegarLoop]: Abstraction has 18429 states and 29722 transitions. [2023-11-29 01:23:00,185 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-29 01:23:00,185 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18429 states and 29722 transitions. [2023-11-29 01:23:00,232 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17278 [2023-11-29 01:23:00,232 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:00,232 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:00,233 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:00,233 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:00,233 INFO L748 eck$LassoCheckResult]: Stem: 98540#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 98541#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 98369#L256 assume !(1 == ~main_in1_req_up~0); 98322#L256-2 assume !(1 == ~main_in2_req_up~0); 98324#L267-1 assume !(1 == ~main_sum_req_up~0); 98356#L278-1 assume !(1 == ~main_diff_req_up~0); 98304#L289-1 assume !(1 == ~main_pres_req_up~0); 98305#L300-1 assume !(1 == ~main_dbl_req_up~0); 98417#L311-1 assume !(1 == ~main_zero_req_up~0); 102522#L322-1 assume !(1 == ~main_clk_req_up~0); 102523#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 102635#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 102634#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 102633#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 102618#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 102617#L371-1 assume !(0 == ~main_in1_ev~0); 102615#L376-1 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 102607#L381-1 assume !(0 == ~main_sum_ev~0); 102604#L386-1 assume !(0 == ~main_diff_ev~0); 102601#L391-1 assume !(0 == ~main_pres_ev~0); 102598#L396-1 assume !(0 == ~main_dbl_ev~0); 102595#L401-1 assume !(0 == ~main_zero_ev~0); 102590#L406-1 assume !(0 == ~main_clk_ev~0); 102584#L411-1 assume !(0 == ~main_clk_pos_edge~0); 102579#L416-1 assume !(0 == ~main_clk_neg_edge~0); 102572#L421-1 assume !(1 == ~main_clk_pos_edge~0); 102565#L426-1 assume !(1 == ~main_clk_pos_edge~0); 102558#L431-1 assume !(1 == ~main_clk_pos_edge~0); 102551#L436-1 assume !(1 == ~main_clk_pos_edge~0); 102544#L441-1 assume !(1 == ~main_clk_pos_edge~0); 102539#L446-1 assume !(1 == ~main_in1_ev~0); 102233#L451-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 102232#L456-1 assume !(1 == ~main_sum_ev~0); 102230#L461-1 assume !(1 == ~main_diff_ev~0); 102228#L466-1 assume !(1 == ~main_pres_ev~0); 102227#L471-1 assume !(1 == ~main_dbl_ev~0); 102226#L476-1 assume !(1 == ~main_zero_ev~0); 102224#L481-1 assume !(1 == ~main_clk_ev~0); 102223#L486-1 assume !(1 == ~main_clk_pos_edge~0); 102219#L491-1 assume !(1 == ~main_clk_neg_edge~0); 102052#L742-1 [2023-11-29 01:23:00,234 INFO L750 eck$LassoCheckResult]: Loop: 102052#L742-1 assume !false; 102215#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 102211#L229 assume !false; 102210#L147 assume !(0 == ~N_generate_st~0); 102209#L151 assume !(0 == ~S1_addsub_st~0); 102208#L154 assume !(0 == ~S2_presdbl_st~0); 102207#L157 assume !(0 == ~S3_zero_st~0); 102205#L160 assume !(0 == ~D_print_st~0); 102204#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 102203#L509 assume !(1 == ~main_in1_req_up~0); 102201#L509-2 assume !(1 == ~main_in2_req_up~0); 102198#L520-1 assume !(1 == ~main_sum_req_up~0); 102194#L531-1 assume !(1 == ~main_diff_req_up~0); 102192#L542-1 assume !(1 == ~main_pres_req_up~0); 102136#L553-1 assume !(1 == ~main_dbl_req_up~0); 102131#L564-1 assume !(1 == ~main_zero_req_up~0); 102127#L575-1 assume !(1 == ~main_clk_req_up~0); 102124#L586-1 start_simulation_~kernel_st~0#1 := 3; 102121#L605 assume !(0 == ~main_in1_ev~0); 102118#L605-2 assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1; 102116#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 102114#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 102112#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 102110#L625-1 assume !(0 == ~main_dbl_ev~0); 102108#L630-1 assume !(0 == ~main_zero_ev~0); 102106#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 102104#L640-1 assume !(0 == ~main_clk_pos_edge~0); 102102#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 102100#L650-1 assume !(1 == ~main_clk_pos_edge~0); 102098#L655-1 assume !(1 == ~main_clk_pos_edge~0); 102096#L660-1 assume !(1 == ~main_clk_pos_edge~0); 102094#L665-1 assume !(1 == ~main_clk_pos_edge~0); 102092#L670-1 assume !(1 == ~main_clk_pos_edge~0); 102091#L675-1 assume !(1 == ~main_in1_ev~0); 102088#L680-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 102085#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 102083#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 102081#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 102079#L700-1 assume !(1 == ~main_dbl_ev~0); 102077#L705-1 assume !(1 == ~main_zero_ev~0); 102074#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 102069#L715-1 assume !(1 == ~main_clk_pos_edge~0); 102064#L720-1 assume !(1 == ~main_clk_neg_edge~0); 102062#L725-1 assume 0 == ~N_generate_st~0; 102052#L742-1 [2023-11-29 01:23:00,234 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:00,234 INFO L85 PathProgramCache]: Analyzing trace with hash -323147977, now seen corresponding path program 1 times [2023-11-29 01:23:00,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:00,235 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810616643] [2023-11-29 01:23:00,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:00,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:00,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:00,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:00,340 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:00,340 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [810616643] [2023-11-29 01:23:00,341 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [810616643] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:00,341 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:00,341 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:23:00,341 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1669666601] [2023-11-29 01:23:00,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:00,341 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:23:00,342 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:00,342 INFO L85 PathProgramCache]: Analyzing trace with hash -1079663374, now seen corresponding path program 1 times [2023-11-29 01:23:00,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:00,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500152540] [2023-11-29 01:23:00,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:00,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:00,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:00,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:00,370 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:00,370 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500152540] [2023-11-29 01:23:00,370 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [500152540] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:00,370 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:00,370 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:23:00,370 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [306106336] [2023-11-29 01:23:00,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:00,371 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:00,371 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:00,371 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:23:00,371 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:23:00,372 INFO L87 Difference]: Start difference. First operand 18429 states and 29722 transitions. cyclomatic complexity: 11325 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:00,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:00,694 INFO L93 Difference]: Finished difference Result 33519 states and 53550 transitions. [2023-11-29 01:23:00,694 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33519 states and 53550 transitions. [2023-11-29 01:23:00,840 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31728 [2023-11-29 01:23:00,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33519 states to 33519 states and 53550 transitions. [2023-11-29 01:23:00,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33519 [2023-11-29 01:23:00,964 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33519 [2023-11-29 01:23:00,965 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33519 states and 53550 transitions. [2023-11-29 01:23:00,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:00,985 INFO L218 hiAutomatonCegarLoop]: Abstraction has 33519 states and 53550 transitions. [2023-11-29 01:23:01,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33519 states and 53550 transitions. [2023-11-29 01:23:01,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33519 to 33519. [2023-11-29 01:23:01,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33519 states, 33519 states have (on average 1.597601360422447) internal successors, (53550), 33518 states have internal predecessors, (53550), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:01,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33519 states to 33519 states and 53550 transitions. [2023-11-29 01:23:01,581 INFO L240 hiAutomatonCegarLoop]: Abstraction has 33519 states and 53550 transitions. [2023-11-29 01:23:01,581 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-29 01:23:01,582 INFO L428 stractBuchiCegarLoop]: Abstraction has 33519 states and 53550 transitions. [2023-11-29 01:23:01,582 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-29 01:23:01,582 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33519 states and 53550 transitions. [2023-11-29 01:23:01,700 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31728 [2023-11-29 01:23:01,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:01,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:01,701 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:01,701 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:01,702 INFO L748 eck$LassoCheckResult]: Stem: 150510#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 150511#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 150328#L256 assume !(1 == ~main_in1_req_up~0); 150281#L256-2 assume !(1 == ~main_in2_req_up~0); 150283#L267-1 assume !(1 == ~main_sum_req_up~0); 150730#L278-1 assume !(1 == ~main_diff_req_up~0); 150424#L289-1 assume !(1 == ~main_pres_req_up~0); 158294#L300-1 assume !(1 == ~main_dbl_req_up~0); 157317#L311-1 assume !(1 == ~main_zero_req_up~0); 157318#L322-1 assume !(1 == ~main_clk_req_up~0); 158702#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 158695#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 158687#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 158679#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 158672#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 158665#L371-1 assume !(0 == ~main_in1_ev~0); 158659#L376-1 assume !(0 == ~main_in2_ev~0); 158652#L381-1 assume !(0 == ~main_sum_ev~0); 158645#L386-1 assume !(0 == ~main_diff_ev~0); 158638#L391-1 assume !(0 == ~main_pres_ev~0); 158631#L396-1 assume !(0 == ~main_dbl_ev~0); 158623#L401-1 assume !(0 == ~main_zero_ev~0); 158619#L406-1 assume !(0 == ~main_clk_ev~0); 158616#L411-1 assume !(0 == ~main_clk_pos_edge~0); 158613#L416-1 assume !(0 == ~main_clk_neg_edge~0); 158491#L421-1 assume !(1 == ~main_clk_pos_edge~0); 158490#L426-1 assume !(1 == ~main_clk_pos_edge~0); 158489#L431-1 assume !(1 == ~main_clk_pos_edge~0); 158488#L436-1 assume !(1 == ~main_clk_pos_edge~0); 158487#L441-1 assume !(1 == ~main_clk_pos_edge~0); 158486#L446-1 assume !(1 == ~main_in1_ev~0); 158484#L451-1 assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2; 158485#L456-1 assume !(1 == ~main_sum_ev~0); 163786#L461-1 assume !(1 == ~main_diff_ev~0); 163785#L466-1 assume !(1 == ~main_pres_ev~0); 163784#L471-1 assume !(1 == ~main_dbl_ev~0); 163783#L476-1 assume !(1 == ~main_zero_ev~0); 163782#L481-1 assume !(1 == ~main_clk_ev~0); 163781#L486-1 assume !(1 == ~main_clk_pos_edge~0); 163744#L491-1 assume !(1 == ~main_clk_neg_edge~0); 163740#L742-1 [2023-11-29 01:23:01,702 INFO L750 eck$LassoCheckResult]: Loop: 163740#L742-1 assume !false; 163739#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 163735#L229 assume !false; 163733#L147 assume !(0 == ~N_generate_st~0); 163729#L151 assume !(0 == ~S1_addsub_st~0); 163730#L154 assume !(0 == ~S2_presdbl_st~0); 163731#L157 assume !(0 == ~S3_zero_st~0); 163732#L160 assume !(0 == ~D_print_st~0); 163734#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 165929#L509 assume !(1 == ~main_in1_req_up~0); 165927#L509-2 assume !(1 == ~main_in2_req_up~0); 165923#L520-1 assume !(1 == ~main_sum_req_up~0); 165919#L531-1 assume !(1 == ~main_diff_req_up~0); 165917#L542-1 assume !(1 == ~main_pres_req_up~0); 165914#L553-1 assume !(1 == ~main_dbl_req_up~0); 165911#L564-1 assume !(1 == ~main_zero_req_up~0); 165907#L575-1 assume !(1 == ~main_clk_req_up~0); 165905#L586-1 start_simulation_~kernel_st~0#1 := 3; 165903#L605 assume !(0 == ~main_in1_ev~0); 165899#L605-2 assume !(0 == ~main_in2_ev~0); 165889#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 165894#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 165892#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 165890#L625-1 assume !(0 == ~main_dbl_ev~0); 165887#L630-1 assume !(0 == ~main_zero_ev~0); 165885#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 165883#L640-1 assume !(0 == ~main_clk_pos_edge~0); 165881#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 165879#L650-1 assume !(1 == ~main_clk_pos_edge~0); 165877#L655-1 assume !(1 == ~main_clk_pos_edge~0); 165875#L660-1 assume !(1 == ~main_clk_pos_edge~0); 165873#L665-1 assume !(1 == ~main_clk_pos_edge~0); 165871#L670-1 assume !(1 == ~main_clk_pos_edge~0); 165869#L675-1 assume !(1 == ~main_in1_ev~0); 165859#L680-1 assume !(1 == ~main_in2_ev~0); 161666#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 165856#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 165854#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 165852#L700-1 assume !(1 == ~main_dbl_ev~0); 165850#L705-1 assume !(1 == ~main_zero_ev~0); 165848#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 165846#L715-1 assume !(1 == ~main_clk_pos_edge~0); 165845#L720-1 assume !(1 == ~main_clk_neg_edge~0); 163747#L725-1 assume 0 == ~N_generate_st~0; 163740#L742-1 [2023-11-29 01:23:01,702 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:01,702 INFO L85 PathProgramCache]: Analyzing trace with hash -457161483, now seen corresponding path program 1 times [2023-11-29 01:23:01,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:01,703 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572952502] [2023-11-29 01:23:01,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:01,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:01,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:01,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:01,852 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:01,855 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1572952502] [2023-11-29 01:23:01,855 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1572952502] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:01,855 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:01,856 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:23:01,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [178689834] [2023-11-29 01:23:01,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:01,856 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:23:01,857 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:01,857 INFO L85 PathProgramCache]: Analyzing trace with hash -1332141774, now seen corresponding path program 1 times [2023-11-29 01:23:01,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:01,859 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573838687] [2023-11-29 01:23:01,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:01,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:01,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:01,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:01,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:01,894 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573838687] [2023-11-29 01:23:01,894 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1573838687] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:01,894 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:01,894 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:23:01,895 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [591637720] [2023-11-29 01:23:01,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:01,895 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:01,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:01,896 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:23:01,896 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:23:01,896 INFO L87 Difference]: Start difference. First operand 33519 states and 53550 transitions. cyclomatic complexity: 20095 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:02,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:02,403 INFO L93 Difference]: Finished difference Result 34717 states and 54842 transitions. [2023-11-29 01:23:02,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34717 states and 54842 transitions. [2023-11-29 01:23:02,563 INFO L131 ngComponentsAnalysis]: Automaton has 66 accepting balls. 32815 [2023-11-29 01:23:02,658 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34717 states to 34717 states and 54842 transitions. [2023-11-29 01:23:02,658 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34717 [2023-11-29 01:23:02,676 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34717 [2023-11-29 01:23:02,676 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34717 states and 54842 transitions. [2023-11-29 01:23:02,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:02,711 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34717 states and 54842 transitions. [2023-11-29 01:23:02,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34717 states and 54842 transitions. [2023-11-29 01:23:03,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34717 to 33519. [2023-11-29 01:23:03,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33519 states, 33519 states have (on average 1.5798800680211222) internal successors, (52956), 33518 states have internal predecessors, (52956), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:03,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33519 states to 33519 states and 52956 transitions. [2023-11-29 01:23:03,325 INFO L240 hiAutomatonCegarLoop]: Abstraction has 33519 states and 52956 transitions. [2023-11-29 01:23:03,326 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:23:03,326 INFO L428 stractBuchiCegarLoop]: Abstraction has 33519 states and 52956 transitions. [2023-11-29 01:23:03,326 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-29 01:23:03,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33519 states and 52956 transitions. [2023-11-29 01:23:03,412 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31728 [2023-11-29 01:23:03,412 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:03,412 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:03,413 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:03,413 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:03,413 INFO L748 eck$LassoCheckResult]: Stem: 218752#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 218753#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 218574#L256 assume !(1 == ~main_in1_req_up~0); 218528#L256-2 assume !(1 == ~main_in2_req_up~0); 218530#L267-1 assume !(1 == ~main_sum_req_up~0); 218561#L278-1 assume !(1 == ~main_diff_req_up~0); 218509#L289-1 assume !(1 == ~main_pres_req_up~0); 218510#L300-1 assume !(1 == ~main_dbl_req_up~0); 218626#L311-1 assume !(1 == ~main_zero_req_up~0); 218997#L322-1 assume !(1 == ~main_clk_req_up~0); 218999#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 237321#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 237320#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 237319#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 237318#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 237317#L371-1 assume !(0 == ~main_in1_ev~0); 237316#L376-1 assume !(0 == ~main_in2_ev~0); 237315#L381-1 assume !(0 == ~main_sum_ev~0); 237314#L386-1 assume !(0 == ~main_diff_ev~0); 237313#L391-1 assume !(0 == ~main_pres_ev~0); 237312#L396-1 assume !(0 == ~main_dbl_ev~0); 237311#L401-1 assume !(0 == ~main_zero_ev~0); 237310#L406-1 assume !(0 == ~main_clk_ev~0); 237309#L411-1 assume !(0 == ~main_clk_pos_edge~0); 237308#L416-1 assume !(0 == ~main_clk_neg_edge~0); 237307#L421-1 assume !(1 == ~main_clk_pos_edge~0); 237306#L426-1 assume !(1 == ~main_clk_pos_edge~0); 237305#L431-1 assume !(1 == ~main_clk_pos_edge~0); 237304#L436-1 assume !(1 == ~main_clk_pos_edge~0); 237303#L441-1 assume !(1 == ~main_clk_pos_edge~0); 237302#L446-1 assume !(1 == ~main_in1_ev~0); 237301#L451-1 assume !(1 == ~main_in2_ev~0); 237300#L456-1 assume !(1 == ~main_sum_ev~0); 226375#L461-1 assume !(1 == ~main_diff_ev~0); 226374#L466-1 assume !(1 == ~main_pres_ev~0); 226373#L471-1 assume !(1 == ~main_dbl_ev~0); 226372#L476-1 assume !(1 == ~main_zero_ev~0); 226371#L481-1 assume !(1 == ~main_clk_ev~0); 226346#L486-1 assume !(1 == ~main_clk_pos_edge~0); 226347#L491-1 assume !(1 == ~main_clk_neg_edge~0); 225232#L742-1 [2023-11-29 01:23:03,414 INFO L750 eck$LassoCheckResult]: Loop: 225232#L742-1 assume !false; 225233#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 237252#L229 assume !false; 237251#L147 assume !(0 == ~N_generate_st~0); 237250#L151 assume !(0 == ~S1_addsub_st~0); 237249#L154 assume !(0 == ~S2_presdbl_st~0); 237248#L157 assume !(0 == ~S3_zero_st~0); 237247#L160 assume !(0 == ~D_print_st~0); 237246#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 237245#L509 assume !(1 == ~main_in1_req_up~0); 237244#L509-2 assume !(1 == ~main_in2_req_up~0); 237243#L520-1 assume !(1 == ~main_sum_req_up~0); 237242#L531-1 assume !(1 == ~main_diff_req_up~0); 237241#L542-1 assume !(1 == ~main_pres_req_up~0); 225190#L553-1 assume !(1 == ~main_dbl_req_up~0); 225192#L564-1 assume !(1 == ~main_zero_req_up~0); 225299#L575-1 assume !(1 == ~main_clk_req_up~0); 225300#L586-1 start_simulation_~kernel_st~0#1 := 3; 226464#L605 assume !(0 == ~main_in1_ev~0); 226460#L605-2 assume !(0 == ~main_in2_ev~0); 226456#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 226452#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 226450#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 226446#L625-1 assume !(0 == ~main_dbl_ev~0); 226403#L630-1 assume !(0 == ~main_zero_ev~0); 226402#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 226400#L640-1 assume !(0 == ~main_clk_pos_edge~0); 226399#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 226398#L650-1 assume !(1 == ~main_clk_pos_edge~0); 226397#L655-1 assume !(1 == ~main_clk_pos_edge~0); 226395#L660-1 assume !(1 == ~main_clk_pos_edge~0); 226393#L665-1 assume !(1 == ~main_clk_pos_edge~0); 226391#L670-1 assume !(1 == ~main_clk_pos_edge~0); 226389#L675-1 assume !(1 == ~main_in1_ev~0); 226387#L680-1 assume !(1 == ~main_in2_ev~0); 226385#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 226384#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 226382#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 226381#L700-1 assume !(1 == ~main_dbl_ev~0); 226380#L705-1 assume !(1 == ~main_zero_ev~0); 226379#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 225259#L715-1 assume !(1 == ~main_clk_pos_edge~0); 225255#L720-1 assume !(1 == ~main_clk_neg_edge~0); 225256#L725-1 assume 0 == ~N_generate_st~0; 225232#L742-1 [2023-11-29 01:23:03,414 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:03,414 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 2 times [2023-11-29 01:23:03,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:03,414 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006812129] [2023-11-29 01:23:03,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:03,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:03,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:03,426 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:03,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:03,446 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:03,446 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:03,446 INFO L85 PathProgramCache]: Analyzing trace with hash -1332141774, now seen corresponding path program 2 times [2023-11-29 01:23:03,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:03,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147309924] [2023-11-29 01:23:03,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:03,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:03,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:03,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:03,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:03,470 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1147309924] [2023-11-29 01:23:03,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1147309924] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:03,471 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:03,471 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:23:03,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1396956848] [2023-11-29 01:23:03,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:03,472 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:03,472 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:03,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:23:03,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:23:03,473 INFO L87 Difference]: Start difference. First operand 33519 states and 52956 transitions. cyclomatic complexity: 19501 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:03,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:03,781 INFO L93 Difference]: Finished difference Result 44288 states and 68290 transitions. [2023-11-29 01:23:03,782 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44288 states and 68290 transitions. [2023-11-29 01:23:03,924 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 41518 [2023-11-29 01:23:04,010 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44288 states to 44288 states and 68290 transitions. [2023-11-29 01:23:04,010 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44288 [2023-11-29 01:23:04,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44288 [2023-11-29 01:23:04,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44288 states and 68290 transitions. [2023-11-29 01:23:04,175 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:04,175 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44288 states and 68290 transitions. [2023-11-29 01:23:04,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44288 states and 68290 transitions. [2023-11-29 01:23:04,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44288 to 44288. [2023-11-29 01:23:04,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44288 states, 44288 states have (on average 1.5419526734104045) internal successors, (68290), 44287 states have internal predecessors, (68290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:04,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44288 states to 44288 states and 68290 transitions. [2023-11-29 01:23:04,745 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44288 states and 68290 transitions. [2023-11-29 01:23:04,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:23:04,746 INFO L428 stractBuchiCegarLoop]: Abstraction has 44288 states and 68290 transitions. [2023-11-29 01:23:04,746 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-29 01:23:04,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44288 states and 68290 transitions. [2023-11-29 01:23:05,002 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 41518 [2023-11-29 01:23:05,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:05,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:05,004 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:05,004 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:05,004 INFO L748 eck$LassoCheckResult]: Stem: 296572#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 296573#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 296388#L256 assume !(1 == ~main_in1_req_up~0); 296341#L256-2 assume !(1 == ~main_in2_req_up~0); 296343#L267-1 assume !(1 == ~main_sum_req_up~0); 296375#L278-1 assume !(1 == ~main_diff_req_up~0); 296322#L289-1 assume !(1 == ~main_pres_req_up~0); 296323#L300-1 assume !(1 == ~main_dbl_req_up~0); 299668#L311-1 assume !(1 == ~main_zero_req_up~0); 299669#L322-1 assume !(1 == ~main_clk_req_up~0); 299782#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 299926#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 299924#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 299922#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 299878#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 299877#L371-1 assume !(0 == ~main_in1_ev~0); 299876#L376-1 assume !(0 == ~main_in2_ev~0); 299874#L381-1 assume !(0 == ~main_sum_ev~0); 299872#L386-1 assume !(0 == ~main_diff_ev~0); 299871#L391-1 assume !(0 == ~main_pres_ev~0); 299870#L396-1 assume !(0 == ~main_dbl_ev~0); 299869#L401-1 assume !(0 == ~main_zero_ev~0); 299867#L406-1 assume !(0 == ~main_clk_ev~0); 299865#L411-1 assume !(0 == ~main_clk_pos_edge~0); 299862#L416-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 299860#L421-1 assume !(1 == ~main_clk_pos_edge~0); 299858#L426-1 assume !(1 == ~main_clk_pos_edge~0); 299853#L431-1 assume !(1 == ~main_clk_pos_edge~0); 299848#L436-1 assume !(1 == ~main_clk_pos_edge~0); 299843#L441-1 assume !(1 == ~main_clk_pos_edge~0); 299838#L446-1 assume !(1 == ~main_in1_ev~0); 299832#L451-1 assume !(1 == ~main_in2_ev~0); 299828#L456-1 assume !(1 == ~main_sum_ev~0); 299825#L461-1 assume !(1 == ~main_diff_ev~0); 299822#L466-1 assume !(1 == ~main_pres_ev~0); 299818#L471-1 assume !(1 == ~main_dbl_ev~0); 299814#L476-1 assume !(1 == ~main_zero_ev~0); 299790#L481-1 assume !(1 == ~main_clk_ev~0); 299741#L486-1 assume !(1 == ~main_clk_pos_edge~0); 299730#L491-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 299454#L742-1 [2023-11-29 01:23:05,004 INFO L750 eck$LassoCheckResult]: Loop: 299454#L742-1 assume !false; 299721#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 310987#L229 assume !false; 310985#L147 assume !(0 == ~N_generate_st~0); 310981#L151 assume !(0 == ~S1_addsub_st~0); 310982#L154 assume !(0 == ~S2_presdbl_st~0); 310983#L157 assume !(0 == ~S3_zero_st~0); 310984#L160 assume !(0 == ~D_print_st~0); 310986#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 311155#L509 assume !(1 == ~main_in1_req_up~0); 311153#L509-2 assume !(1 == ~main_in2_req_up~0); 311150#L520-1 assume !(1 == ~main_sum_req_up~0); 311148#L531-1 assume !(1 == ~main_diff_req_up~0); 311146#L542-1 assume !(1 == ~main_pres_req_up~0); 299509#L553-1 assume !(1 == ~main_dbl_req_up~0); 299507#L564-1 assume !(1 == ~main_zero_req_up~0); 299505#L575-1 assume !(1 == ~main_clk_req_up~0); 299506#L586-1 start_simulation_~kernel_st~0#1 := 3; 299868#L605 assume !(0 == ~main_in1_ev~0); 299866#L605-2 assume !(0 == ~main_in2_ev~0); 299864#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 299861#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 299859#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 299857#L625-1 assume !(0 == ~main_dbl_ev~0); 299852#L630-1 assume !(0 == ~main_zero_ev~0); 299847#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 299842#L640-1 assume !(0 == ~main_clk_pos_edge~0); 299836#L645-1 assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1; 299831#L650-1 assume !(1 == ~main_clk_pos_edge~0); 299827#L655-1 assume !(1 == ~main_clk_pos_edge~0); 299824#L660-1 assume !(1 == ~main_clk_pos_edge~0); 299821#L665-1 assume !(1 == ~main_clk_pos_edge~0); 299817#L670-1 assume !(1 == ~main_clk_pos_edge~0); 299813#L675-1 assume !(1 == ~main_in1_ev~0); 299784#L680-1 assume !(1 == ~main_in2_ev~0); 299735#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 299725#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 299717#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 299709#L700-1 assume !(1 == ~main_dbl_ev~0); 299704#L705-1 assume !(1 == ~main_zero_ev~0); 299678#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 299468#L715-1 assume !(1 == ~main_clk_pos_edge~0); 299463#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 299461#L725-1 assume 0 == ~N_generate_st~0; 299454#L742-1 [2023-11-29 01:23:05,005 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:05,005 INFO L85 PathProgramCache]: Analyzing trace with hash 1243965239, now seen corresponding path program 1 times [2023-11-29 01:23:05,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:05,005 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265309071] [2023-11-29 01:23:05,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:05,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:05,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:05,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:05,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:05,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [265309071] [2023-11-29 01:23:05,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [265309071] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:05,056 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:05,056 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:23:05,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613224520] [2023-11-29 01:23:05,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:05,056 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:23:05,057 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:05,057 INFO L85 PathProgramCache]: Analyzing trace with hash -1332141836, now seen corresponding path program 1 times [2023-11-29 01:23:05,057 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:05,057 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328239951] [2023-11-29 01:23:05,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:05,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:05,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:05,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:05,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:05,084 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328239951] [2023-11-29 01:23:05,084 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328239951] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:05,084 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:05,085 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:23:05,085 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [153913442] [2023-11-29 01:23:05,085 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:05,085 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:05,085 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:05,086 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:23:05,086 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:23:05,086 INFO L87 Difference]: Start difference. First operand 44288 states and 68290 transitions. cyclomatic complexity: 24066 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:05,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:05,415 INFO L93 Difference]: Finished difference Result 53275 states and 81140 transitions. [2023-11-29 01:23:05,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53275 states and 81140 transitions. [2023-11-29 01:23:05,621 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 50818 [2023-11-29 01:23:05,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53275 states to 53275 states and 81140 transitions. [2023-11-29 01:23:05,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53275 [2023-11-29 01:23:05,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53275 [2023-11-29 01:23:05,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53275 states and 81140 transitions. [2023-11-29 01:23:05,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:05,806 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53275 states and 81140 transitions. [2023-11-29 01:23:05,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53275 states and 81140 transitions. [2023-11-29 01:23:06,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53275 to 41741. [2023-11-29 01:23:06,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41741 states, 41741 states have (on average 1.5255504180541912) internal successors, (63678), 41740 states have internal predecessors, (63678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:06,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41741 states to 41741 states and 63678 transitions. [2023-11-29 01:23:06,403 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41741 states and 63678 transitions. [2023-11-29 01:23:06,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-29 01:23:06,404 INFO L428 stractBuchiCegarLoop]: Abstraction has 41741 states and 63678 transitions. [2023-11-29 01:23:06,404 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-29 01:23:06,405 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41741 states and 63678 transitions. [2023-11-29 01:23:06,515 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 39570 [2023-11-29 01:23:06,516 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:06,516 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:06,516 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:06,516 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:06,517 INFO L748 eck$LassoCheckResult]: Stem: 394150#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 394151#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 393960#L256 assume !(1 == ~main_in1_req_up~0); 393914#L256-2 assume !(1 == ~main_in2_req_up~0); 393916#L267-1 assume !(1 == ~main_sum_req_up~0); 393947#L278-1 assume !(1 == ~main_diff_req_up~0); 393895#L289-1 assume !(1 == ~main_pres_req_up~0); 393896#L300-1 assume !(1 == ~main_dbl_req_up~0); 394008#L311-1 assume !(1 == ~main_zero_req_up~0); 394443#L322-1 assume !(1 == ~main_clk_req_up~0); 394445#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 395260#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 393936#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 393937#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 394453#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 394454#L371-1 assume !(0 == ~main_in1_ev~0); 393986#L376-1 assume !(0 == ~main_in2_ev~0); 393987#L381-1 assume !(0 == ~main_sum_ev~0); 394159#L386-1 assume !(0 == ~main_diff_ev~0); 394160#L391-1 assume !(0 == ~main_pres_ev~0); 394315#L396-1 assume !(0 == ~main_dbl_ev~0); 394316#L401-1 assume !(0 == ~main_zero_ev~0); 401260#L406-1 assume !(0 == ~main_clk_ev~0); 401258#L411-1 assume !(0 == ~main_clk_pos_edge~0); 401259#L416-1 assume !(0 == ~main_clk_neg_edge~0); 401256#L421-1 assume !(1 == ~main_clk_pos_edge~0); 401257#L426-1 assume !(1 == ~main_clk_pos_edge~0); 401254#L431-1 assume !(1 == ~main_clk_pos_edge~0); 401255#L436-1 assume !(1 == ~main_clk_pos_edge~0); 401252#L441-1 assume !(1 == ~main_clk_pos_edge~0); 401253#L446-1 assume !(1 == ~main_in1_ev~0); 401249#L451-1 assume !(1 == ~main_in2_ev~0); 401250#L456-1 assume !(1 == ~main_sum_ev~0); 401245#L461-1 assume !(1 == ~main_diff_ev~0); 401246#L466-1 assume !(1 == ~main_pres_ev~0); 401241#L471-1 assume !(1 == ~main_dbl_ev~0); 401242#L476-1 assume !(1 == ~main_zero_ev~0); 401237#L481-1 assume !(1 == ~main_clk_ev~0); 401238#L486-1 assume !(1 == ~main_clk_pos_edge~0); 401185#L491-1 assume !(1 == ~main_clk_neg_edge~0); 401181#L742-1 [2023-11-29 01:23:06,517 INFO L750 eck$LassoCheckResult]: Loop: 401181#L742-1 assume !false; 401177#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 401068#L229 assume !false; 401064#L147 assume !(0 == ~N_generate_st~0); 401059#L151 assume !(0 == ~S1_addsub_st~0); 401057#L154 assume !(0 == ~S2_presdbl_st~0); 401055#L157 assume !(0 == ~S3_zero_st~0); 401052#L160 assume !(0 == ~D_print_st~0); 401050#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 401048#L509 assume !(1 == ~main_in1_req_up~0); 401044#L509-2 assume !(1 == ~main_in2_req_up~0); 401045#L520-1 assume !(1 == ~main_sum_req_up~0); 401357#L531-1 assume !(1 == ~main_diff_req_up~0); 401354#L542-1 assume !(1 == ~main_pres_req_up~0); 401349#L553-1 assume !(1 == ~main_dbl_req_up~0); 401340#L564-1 assume !(1 == ~main_zero_req_up~0); 401333#L575-1 assume !(1 == ~main_clk_req_up~0); 401334#L586-1 start_simulation_~kernel_st~0#1 := 3; 401405#L605 assume !(0 == ~main_in1_ev~0); 401398#L605-2 assume !(0 == ~main_in2_ev~0); 401396#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 401393#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 401390#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 401386#L625-1 assume !(0 == ~main_dbl_ev~0); 401382#L630-1 assume !(0 == ~main_zero_ev~0); 401381#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 401379#L640-1 assume !(0 == ~main_clk_pos_edge~0); 401377#L645-1 assume !(0 == ~main_clk_neg_edge~0); 401375#L650-1 assume !(1 == ~main_clk_pos_edge~0); 401373#L655-1 assume !(1 == ~main_clk_pos_edge~0); 401371#L660-1 assume !(1 == ~main_clk_pos_edge~0); 401369#L665-1 assume !(1 == ~main_clk_pos_edge~0); 401367#L670-1 assume !(1 == ~main_clk_pos_edge~0); 401365#L675-1 assume !(1 == ~main_in1_ev~0); 401364#L680-1 assume !(1 == ~main_in2_ev~0); 401363#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 401360#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 401356#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 401351#L700-1 assume !(1 == ~main_dbl_ev~0); 401346#L705-1 assume !(1 == ~main_zero_ev~0); 401338#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 401302#L715-1 assume !(1 == ~main_clk_pos_edge~0); 401266#L720-1 assume !(1 == ~main_clk_neg_edge~0); 401190#L725-1 assume 0 == ~N_generate_st~0; 401181#L742-1 [2023-11-29 01:23:06,517 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:06,517 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 3 times [2023-11-29 01:23:06,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:06,517 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706036887] [2023-11-29 01:23:06,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:06,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:06,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:06,531 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:06,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:06,555 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:06,555 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:06,556 INFO L85 PathProgramCache]: Analyzing trace with hash 1374477620, now seen corresponding path program 1 times [2023-11-29 01:23:06,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:06,556 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1244850797] [2023-11-29 01:23:06,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:06,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:06,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:06,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:06,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:06,584 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1244850797] [2023-11-29 01:23:06,584 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1244850797] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:06,584 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:06,585 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:23:06,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841296490] [2023-11-29 01:23:06,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:06,585 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:06,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:06,586 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:23:06,586 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:23:06,586 INFO L87 Difference]: Start difference. First operand 41741 states and 63678 transitions. cyclomatic complexity: 22001 Second operand has 3 states, 2 states have (on average 22.0) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:06,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:06,992 INFO L93 Difference]: Finished difference Result 57643 states and 86947 transitions. [2023-11-29 01:23:06,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57643 states and 86947 transitions. [2023-11-29 01:23:07,238 INFO L131 ngComponentsAnalysis]: Automaton has 72 accepting balls. 53732 [2023-11-29 01:23:07,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57643 states to 57643 states and 86947 transitions. [2023-11-29 01:23:07,378 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57643 [2023-11-29 01:23:07,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57643 [2023-11-29 01:23:07,409 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57643 states and 86947 transitions. [2023-11-29 01:23:07,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:07,433 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57643 states and 86947 transitions. [2023-11-29 01:23:07,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57643 states and 86947 transitions. [2023-11-29 01:23:08,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57643 to 57643. [2023-11-29 01:23:08,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57643 states, 57643 states have (on average 1.5083704873098207) internal successors, (86947), 57642 states have internal predecessors, (86947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:08,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57643 states to 57643 states and 86947 transitions. [2023-11-29 01:23:08,405 INFO L240 hiAutomatonCegarLoop]: Abstraction has 57643 states and 86947 transitions. [2023-11-29 01:23:08,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:23:08,406 INFO L428 stractBuchiCegarLoop]: Abstraction has 57643 states and 86947 transitions. [2023-11-29 01:23:08,406 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-29 01:23:08,406 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57643 states and 86947 transitions. [2023-11-29 01:23:08,595 INFO L131 ngComponentsAnalysis]: Automaton has 72 accepting balls. 53732 [2023-11-29 01:23:08,595 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:08,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:08,596 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:08,596 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:08,596 INFO L748 eck$LassoCheckResult]: Stem: 493538#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 493539#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 493352#L256 assume !(1 == ~main_in1_req_up~0); 493304#L256-2 assume !(1 == ~main_in2_req_up~0); 493306#L267-1 assume !(1 == ~main_sum_req_up~0); 493339#L278-1 assume !(1 == ~main_diff_req_up~0); 496626#L289-1 assume !(1 == ~main_pres_req_up~0); 493741#L300-1 assume !(1 == ~main_dbl_req_up~0); 493742#L311-1 assume !(1 == ~main_zero_req_up~0); 497327#L322-1 assume !(1 == ~main_clk_req_up~0); 497328#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 497401#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 497400#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 497399#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 497398#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 497397#L371-1 assume !(0 == ~main_in1_ev~0); 497396#L376-1 assume !(0 == ~main_in2_ev~0); 497395#L381-1 assume !(0 == ~main_sum_ev~0); 497394#L386-1 assume !(0 == ~main_diff_ev~0); 497393#L391-1 assume !(0 == ~main_pres_ev~0); 497392#L396-1 assume !(0 == ~main_dbl_ev~0); 497391#L401-1 assume !(0 == ~main_zero_ev~0); 497390#L406-1 assume !(0 == ~main_clk_ev~0); 497388#L411-1 assume !(0 == ~main_clk_pos_edge~0); 497389#L416-1 assume !(0 == ~main_clk_neg_edge~0); 502737#L421-1 assume !(1 == ~main_clk_pos_edge~0); 502736#L426-1 assume !(1 == ~main_clk_pos_edge~0); 502735#L431-1 assume !(1 == ~main_clk_pos_edge~0); 502734#L436-1 assume !(1 == ~main_clk_pos_edge~0); 502733#L441-1 assume !(1 == ~main_clk_pos_edge~0); 502732#L446-1 assume !(1 == ~main_in1_ev~0); 502731#L451-1 assume !(1 == ~main_in2_ev~0); 502730#L456-1 assume !(1 == ~main_sum_ev~0); 502729#L461-1 assume !(1 == ~main_diff_ev~0); 502728#L466-1 assume !(1 == ~main_pres_ev~0); 502727#L471-1 assume !(1 == ~main_dbl_ev~0); 502724#L476-1 assume !(1 == ~main_zero_ev~0); 502722#L481-1 assume !(1 == ~main_clk_ev~0); 502720#L486-1 assume !(1 == ~main_clk_pos_edge~0); 497233#L491-1 assume !(1 == ~main_clk_neg_edge~0); 497234#L742-1 [2023-11-29 01:23:08,597 INFO L750 eck$LassoCheckResult]: Loop: 497234#L742-1 assume !false; 497225#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 497222#L229 assume !false; 497216#L147 assume !(0 == ~N_generate_st~0); 496376#L151 assume !(0 == ~S1_addsub_st~0); 497210#L154 assume !(0 == ~S2_presdbl_st~0); 497211#L157 assume !(0 == ~S3_zero_st~0); 497202#L160 assume !(0 == ~D_print_st~0); 497203#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 497197#L509 assume !(1 == ~main_in1_req_up~0); 497198#L509-2 assume !(1 == ~main_in2_req_up~0); 497189#L520-1 assume !(1 == ~main_sum_req_up~0); 497188#L531-1 assume !(1 == ~main_diff_req_up~0); 497174#L542-1 assume !(1 == ~main_pres_req_up~0); 497173#L553-1 assume !(1 == ~main_dbl_req_up~0); 497164#L564-1 assume !(1 == ~main_zero_req_up~0); 497159#L575-1 assume !(1 == ~main_clk_req_up~0); 497160#L586-1 start_simulation_~kernel_st~0#1 := 3; 497351#L605 assume !(0 == ~main_in1_ev~0); 497349#L605-2 assume !(0 == ~main_in2_ev~0); 497347#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 497345#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 497343#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 497341#L625-1 assume !(0 == ~main_dbl_ev~0); 497339#L630-1 assume !(0 == ~main_zero_ev~0); 497337#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 497335#L640-1 assume !(0 == ~main_clk_pos_edge~0); 497333#L645-1 assume !(0 == ~main_clk_neg_edge~0); 497302#L650-1 assume !(1 == ~main_clk_pos_edge~0); 497300#L655-1 assume !(1 == ~main_clk_pos_edge~0); 497298#L660-1 assume !(1 == ~main_clk_pos_edge~0); 497296#L665-1 assume !(1 == ~main_clk_pos_edge~0); 497294#L670-1 assume !(1 == ~main_clk_pos_edge~0); 497291#L675-1 assume !(1 == ~main_in1_ev~0); 497292#L680-1 assume !(1 == ~main_in2_ev~0); 497285#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 497286#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 502746#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 502745#L700-1 assume !(1 == ~main_dbl_ev~0); 502744#L705-1 assume !(1 == ~main_zero_ev~0); 502743#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 502742#L715-1 assume !(1 == ~main_clk_pos_edge~0); 502741#L720-1 assume !(1 == ~main_clk_neg_edge~0); 502740#L725-1 assume !(0 == ~N_generate_st~0); 497238#L733 assume 0 == ~S1_addsub_st~0; 497234#L742-1 [2023-11-29 01:23:08,597 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:08,597 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 4 times [2023-11-29 01:23:08,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:08,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458782256] [2023-11-29 01:23:08,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:08,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:08,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:08,609 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:08,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:08,632 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:08,632 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:08,632 INFO L85 PathProgramCache]: Analyzing trace with hash -340865996, now seen corresponding path program 1 times [2023-11-29 01:23:08,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:08,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374632021] [2023-11-29 01:23:08,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:08,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:08,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:08,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:08,666 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:08,666 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [374632021] [2023-11-29 01:23:08,666 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [374632021] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:08,666 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:08,666 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:23:08,667 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242585387] [2023-11-29 01:23:08,667 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:08,667 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:08,667 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:08,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:23:08,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:23:08,668 INFO L87 Difference]: Start difference. First operand 57643 states and 86947 transitions. cyclomatic complexity: 29376 Second operand has 3 states, 2 states have (on average 22.5) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:09,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:09,288 INFO L93 Difference]: Finished difference Result 86850 states and 129727 transitions. [2023-11-29 01:23:09,289 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86850 states and 129727 transitions. [2023-11-29 01:23:09,610 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 79456 [2023-11-29 01:23:09,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86850 states to 86850 states and 129727 transitions. [2023-11-29 01:23:09,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86850 [2023-11-29 01:23:09,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86850 [2023-11-29 01:23:09,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86850 states and 129727 transitions. [2023-11-29 01:23:09,863 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:09,863 INFO L218 hiAutomatonCegarLoop]: Abstraction has 86850 states and 129727 transitions. [2023-11-29 01:23:09,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86850 states and 129727 transitions. [2023-11-29 01:23:10,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86850 to 86850. [2023-11-29 01:23:10,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86850 states, 86850 states have (on average 1.4936902705814623) internal successors, (129727), 86849 states have internal predecessors, (129727), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:11,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86850 states to 86850 states and 129727 transitions. [2023-11-29 01:23:11,035 INFO L240 hiAutomatonCegarLoop]: Abstraction has 86850 states and 129727 transitions. [2023-11-29 01:23:11,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:23:11,036 INFO L428 stractBuchiCegarLoop]: Abstraction has 86850 states and 129727 transitions. [2023-11-29 01:23:11,036 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-29 01:23:11,036 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 86850 states and 129727 transitions. [2023-11-29 01:23:11,309 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 79456 [2023-11-29 01:23:11,309 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:11,309 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:11,310 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:11,310 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:11,310 INFO L748 eck$LassoCheckResult]: Stem: 638035#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 638036#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 637852#L256 assume !(1 == ~main_in1_req_up~0); 637803#L256-2 assume !(1 == ~main_in2_req_up~0); 637805#L267-1 assume !(1 == ~main_sum_req_up~0); 638292#L278-1 assume !(1 == ~main_diff_req_up~0); 637951#L289-1 assume !(1 == ~main_pres_req_up~0); 638231#L300-1 assume !(1 == ~main_dbl_req_up~0); 638232#L311-1 assume !(1 == ~main_zero_req_up~0); 648287#L322-1 assume !(1 == ~main_clk_req_up~0); 648283#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 648284#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 648400#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 648398#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 648396#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 648394#L371-1 assume !(0 == ~main_in1_ev~0); 648392#L376-1 assume !(0 == ~main_in2_ev~0); 648390#L381-1 assume !(0 == ~main_sum_ev~0); 648388#L386-1 assume !(0 == ~main_diff_ev~0); 648386#L391-1 assume !(0 == ~main_pres_ev~0); 648384#L396-1 assume !(0 == ~main_dbl_ev~0); 648382#L401-1 assume !(0 == ~main_zero_ev~0); 648380#L406-1 assume !(0 == ~main_clk_ev~0); 648378#L411-1 assume !(0 == ~main_clk_pos_edge~0); 648376#L416-1 assume !(0 == ~main_clk_neg_edge~0); 648374#L421-1 assume !(1 == ~main_clk_pos_edge~0); 648372#L426-1 assume !(1 == ~main_clk_pos_edge~0); 648370#L431-1 assume !(1 == ~main_clk_pos_edge~0); 648368#L436-1 assume !(1 == ~main_clk_pos_edge~0); 648366#L441-1 assume !(1 == ~main_clk_pos_edge~0); 648364#L446-1 assume !(1 == ~main_in1_ev~0); 648362#L451-1 assume !(1 == ~main_in2_ev~0); 648360#L456-1 assume !(1 == ~main_sum_ev~0); 648358#L461-1 assume !(1 == ~main_diff_ev~0); 648354#L466-1 assume !(1 == ~main_pres_ev~0); 648352#L471-1 assume !(1 == ~main_dbl_ev~0); 648349#L476-1 assume !(1 == ~main_zero_ev~0); 648346#L481-1 assume !(1 == ~main_clk_ev~0); 648333#L486-1 assume !(1 == ~main_clk_pos_edge~0); 648334#L491-1 assume !(1 == ~main_clk_neg_edge~0); 645702#L742-1 [2023-11-29 01:23:11,311 INFO L750 eck$LassoCheckResult]: Loop: 645702#L742-1 assume !false; 648321#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 648299#L229 assume !false; 648300#L147 assume !(0 == ~N_generate_st~0); 646253#L151 assume !(0 == ~S1_addsub_st~0); 646252#L154 assume !(0 == ~S2_presdbl_st~0); 646251#L157 assume !(0 == ~S3_zero_st~0); 646249#L160 assume !(0 == ~D_print_st~0); 646248#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 646247#L509 assume !(1 == ~main_in1_req_up~0); 646245#L509-2 assume !(1 == ~main_in2_req_up~0); 646143#L520-1 assume !(1 == ~main_sum_req_up~0); 646131#L531-1 assume !(1 == ~main_diff_req_up~0); 645979#L542-1 assume !(1 == ~main_pres_req_up~0); 645975#L553-1 assume !(1 == ~main_dbl_req_up~0); 645972#L564-1 assume !(1 == ~main_zero_req_up~0); 645821#L575-1 assume !(1 == ~main_clk_req_up~0); 645818#L586-1 start_simulation_~kernel_st~0#1 := 3; 645816#L605 assume !(0 == ~main_in1_ev~0); 645814#L605-2 assume !(0 == ~main_in2_ev~0); 645812#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 645810#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 645808#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 645806#L625-1 assume !(0 == ~main_dbl_ev~0); 645804#L630-1 assume !(0 == ~main_zero_ev~0); 645802#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 645800#L640-1 assume !(0 == ~main_clk_pos_edge~0); 645798#L645-1 assume !(0 == ~main_clk_neg_edge~0); 645796#L650-1 assume !(1 == ~main_clk_pos_edge~0); 645794#L655-1 assume !(1 == ~main_clk_pos_edge~0); 645792#L660-1 assume !(1 == ~main_clk_pos_edge~0); 645790#L665-1 assume !(1 == ~main_clk_pos_edge~0); 645788#L670-1 assume !(1 == ~main_clk_pos_edge~0); 645786#L675-1 assume !(1 == ~main_in1_ev~0); 645784#L680-1 assume !(1 == ~main_in2_ev~0); 645782#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 645779#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 645777#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 645775#L700-1 assume !(1 == ~main_dbl_ev~0); 645773#L705-1 assume !(1 == ~main_zero_ev~0); 645771#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 645769#L715-1 assume !(1 == ~main_clk_pos_edge~0); 645767#L720-1 assume !(1 == ~main_clk_neg_edge~0); 645765#L725-1 assume !(0 == ~N_generate_st~0); 645763#L733 assume !(0 == ~S1_addsub_st~0); 645761#L736 assume 0 == ~S2_presdbl_st~0; 645702#L742-1 [2023-11-29 01:23:11,311 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:11,311 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 5 times [2023-11-29 01:23:11,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:11,312 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1962556398] [2023-11-29 01:23:11,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:11,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:11,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:11,327 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:11,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:11,346 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:11,346 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:11,346 INFO L85 PathProgramCache]: Analyzing trace with hash -1976910535, now seen corresponding path program 1 times [2023-11-29 01:23:11,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:11,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1352901976] [2023-11-29 01:23:11,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:11,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:11,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:11,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:11,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:11,639 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1352901976] [2023-11-29 01:23:11,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1352901976] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:11,640 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:11,640 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:23:11,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834192228] [2023-11-29 01:23:11,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:11,640 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:11,640 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:11,641 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:23:11,641 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:23:11,641 INFO L87 Difference]: Start difference. First operand 86850 states and 129727 transitions. cyclomatic complexity: 42973 Second operand has 3 states, 2 states have (on average 23.0) internal successors, (46), 3 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:12,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:12,035 INFO L93 Difference]: Finished difference Result 91777 states and 136566 transitions. [2023-11-29 01:23:12,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91777 states and 136566 transitions. [2023-11-29 01:23:12,400 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 84178 [2023-11-29 01:23:12,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91777 states to 91777 states and 136566 transitions. [2023-11-29 01:23:12,590 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91777 [2023-11-29 01:23:12,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91777 [2023-11-29 01:23:12,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91777 states and 136566 transitions. [2023-11-29 01:23:12,671 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:12,671 INFO L218 hiAutomatonCegarLoop]: Abstraction has 91777 states and 136566 transitions. [2023-11-29 01:23:12,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91777 states and 136566 transitions. [2023-11-29 01:23:13,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91777 to 91777. [2023-11-29 01:23:13,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91777 states, 91777 states have (on average 1.4880198742604356) internal successors, (136566), 91776 states have internal predecessors, (136566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:14,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91777 states to 91777 states and 136566 transitions. [2023-11-29 01:23:14,200 INFO L240 hiAutomatonCegarLoop]: Abstraction has 91777 states and 136566 transitions. [2023-11-29 01:23:14,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:23:14,201 INFO L428 stractBuchiCegarLoop]: Abstraction has 91777 states and 136566 transitions. [2023-11-29 01:23:14,201 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-29 01:23:14,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91777 states and 136566 transitions. [2023-11-29 01:23:14,816 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 84178 [2023-11-29 01:23:14,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:14,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:14,818 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:14,818 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:14,818 INFO L748 eck$LassoCheckResult]: Stem: 816675#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 816676#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 816484#L256 assume !(1 == ~main_in1_req_up~0); 816436#L256-2 assume !(1 == ~main_in2_req_up~0); 816438#L267-1 assume !(1 == ~main_sum_req_up~0); 816471#L278-1 assume !(1 == ~main_diff_req_up~0); 816417#L289-1 assume !(1 == ~main_pres_req_up~0); 816418#L300-1 assume !(1 == ~main_dbl_req_up~0); 819934#L311-1 assume !(1 == ~main_zero_req_up~0); 819929#L322-1 assume !(1 == ~main_clk_req_up~0); 819925#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 819926#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 826652#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 826677#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 826676#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 826675#L371-1 assume !(0 == ~main_in1_ev~0); 826674#L376-1 assume !(0 == ~main_in2_ev~0); 826673#L381-1 assume !(0 == ~main_sum_ev~0); 826672#L386-1 assume !(0 == ~main_diff_ev~0); 826671#L391-1 assume !(0 == ~main_pres_ev~0); 826670#L396-1 assume !(0 == ~main_dbl_ev~0); 826669#L401-1 assume !(0 == ~main_zero_ev~0); 826668#L406-1 assume !(0 == ~main_clk_ev~0); 826667#L411-1 assume !(0 == ~main_clk_pos_edge~0); 826666#L416-1 assume !(0 == ~main_clk_neg_edge~0); 826665#L421-1 assume !(1 == ~main_clk_pos_edge~0); 826664#L426-1 assume !(1 == ~main_clk_pos_edge~0); 826663#L431-1 assume !(1 == ~main_clk_pos_edge~0); 826662#L436-1 assume !(1 == ~main_clk_pos_edge~0); 826661#L441-1 assume !(1 == ~main_clk_pos_edge~0); 826660#L446-1 assume !(1 == ~main_in1_ev~0); 826659#L451-1 assume !(1 == ~main_in2_ev~0); 826658#L456-1 assume !(1 == ~main_sum_ev~0); 826657#L461-1 assume !(1 == ~main_diff_ev~0); 826656#L466-1 assume !(1 == ~main_pres_ev~0); 826653#L471-1 assume !(1 == ~main_dbl_ev~0); 826648#L476-1 assume !(1 == ~main_zero_ev~0); 826642#L481-1 assume !(1 == ~main_clk_ev~0); 826637#L486-1 assume !(1 == ~main_clk_pos_edge~0); 826565#L491-1 assume !(1 == ~main_clk_neg_edge~0); 826555#L742-1 [2023-11-29 01:23:14,819 INFO L750 eck$LassoCheckResult]: Loop: 826555#L742-1 assume !false; 826556#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 826269#L229 assume !false; 826270#L147 assume !(0 == ~N_generate_st~0); 819809#L151 assume !(0 == ~S1_addsub_st~0); 825299#L154 assume !(0 == ~S2_presdbl_st~0); 825298#L157 assume !(0 == ~S3_zero_st~0); 825296#L160 assume !(0 == ~D_print_st~0); 825295#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 825294#L509 assume !(1 == ~main_in1_req_up~0); 825292#L509-2 assume !(1 == ~main_in2_req_up~0); 825293#L520-1 assume !(1 == ~main_sum_req_up~0); 826649#L531-1 assume !(1 == ~main_diff_req_up~0); 826645#L542-1 assume !(1 == ~main_pres_req_up~0); 826639#L553-1 assume !(1 == ~main_dbl_req_up~0); 826633#L564-1 assume !(1 == ~main_zero_req_up~0); 826629#L575-1 assume !(1 == ~main_clk_req_up~0); 826626#L586-1 start_simulation_~kernel_st~0#1 := 3; 826624#L605 assume !(0 == ~main_in1_ev~0); 826622#L605-2 assume !(0 == ~main_in2_ev~0); 826620#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 826618#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 826616#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 826614#L625-1 assume !(0 == ~main_dbl_ev~0); 826612#L630-1 assume !(0 == ~main_zero_ev~0); 826610#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 826608#L640-1 assume !(0 == ~main_clk_pos_edge~0); 826606#L645-1 assume !(0 == ~main_clk_neg_edge~0); 826604#L650-1 assume !(1 == ~main_clk_pos_edge~0); 826602#L655-1 assume !(1 == ~main_clk_pos_edge~0); 826600#L660-1 assume !(1 == ~main_clk_pos_edge~0); 826598#L665-1 assume !(1 == ~main_clk_pos_edge~0); 826596#L670-1 assume !(1 == ~main_clk_pos_edge~0); 826594#L675-1 assume !(1 == ~main_in1_ev~0); 826592#L680-1 assume !(1 == ~main_in2_ev~0); 826590#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 826588#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 826586#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 826584#L700-1 assume !(1 == ~main_dbl_ev~0); 826582#L705-1 assume !(1 == ~main_zero_ev~0); 826580#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 826576#L715-1 assume !(1 == ~main_clk_pos_edge~0); 826573#L720-1 assume !(1 == ~main_clk_neg_edge~0); 826572#L725-1 assume !(0 == ~N_generate_st~0); 826571#L733 assume !(0 == ~S1_addsub_st~0); 826570#L736 assume !(0 == ~S2_presdbl_st~0); 826566#L739 assume 0 == ~S3_zero_st~0; 826555#L742-1 [2023-11-29 01:23:14,819 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:14,819 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 6 times [2023-11-29 01:23:14,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:14,820 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [865055846] [2023-11-29 01:23:14,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:14,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:14,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:14,831 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:14,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:14,849 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:14,850 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:14,850 INFO L85 PathProgramCache]: Analyzing trace with hash -1154683687, now seen corresponding path program 1 times [2023-11-29 01:23:14,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:14,851 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [211194734] [2023-11-29 01:23:14,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:14,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:14,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:14,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:14,884 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:14,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [211194734] [2023-11-29 01:23:14,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [211194734] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:14,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:14,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:23:14,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256232760] [2023-11-29 01:23:14,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:14,886 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:14,886 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:14,887 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:23:14,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:23:14,887 INFO L87 Difference]: Start difference. First operand 91777 states and 136566 transitions. cyclomatic complexity: 44885 Second operand has 3 states, 2 states have (on average 23.5) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:15,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:15,329 INFO L93 Difference]: Finished difference Result 147978 states and 218783 transitions. [2023-11-29 01:23:15,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 147978 states and 218783 transitions. [2023-11-29 01:23:15,957 INFO L131 ngComponentsAnalysis]: Automaton has 144 accepting balls. 133258 [2023-11-29 01:23:16,729 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 147978 states to 147978 states and 218783 transitions. [2023-11-29 01:23:16,729 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147978 [2023-11-29 01:23:16,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147978 [2023-11-29 01:23:16,779 INFO L73 IsDeterministic]: Start isDeterministic. Operand 147978 states and 218783 transitions. [2023-11-29 01:23:16,820 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:16,821 INFO L218 hiAutomatonCegarLoop]: Abstraction has 147978 states and 218783 transitions. [2023-11-29 01:23:16,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147978 states and 218783 transitions. [2023-11-29 01:23:17,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147978 to 147978. [2023-11-29 01:23:18,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147978 states, 147978 states have (on average 1.4784832880563328) internal successors, (218783), 147977 states have internal predecessors, (218783), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:18,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147978 states to 147978 states and 218783 transitions. [2023-11-29 01:23:18,463 INFO L240 hiAutomatonCegarLoop]: Abstraction has 147978 states and 218783 transitions. [2023-11-29 01:23:18,464 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:23:18,464 INFO L428 stractBuchiCegarLoop]: Abstraction has 147978 states and 218783 transitions. [2023-11-29 01:23:18,464 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-29 01:23:18,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147978 states and 218783 transitions. [2023-11-29 01:23:19,283 INFO L131 ngComponentsAnalysis]: Automaton has 144 accepting balls. 133258 [2023-11-29 01:23:19,283 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:19,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:19,284 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:19,284 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:19,285 INFO L748 eck$LassoCheckResult]: Stem: 1056434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1056435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1056243#L256 assume !(1 == ~main_in1_req_up~0); 1056196#L256-2 assume !(1 == ~main_in2_req_up~0); 1056198#L267-1 assume !(1 == ~main_sum_req_up~0); 1056230#L278-1 assume !(1 == ~main_diff_req_up~0); 1056178#L289-1 assume !(1 == ~main_pres_req_up~0); 1056179#L300-1 assume !(1 == ~main_dbl_req_up~0); 1069168#L311-1 assume !(1 == ~main_zero_req_up~0); 1069169#L322-1 assume !(1 == ~main_clk_req_up~0); 1070094#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1070348#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 1071478#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1071476#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 1071477#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 1071746#L371-1 assume !(0 == ~main_in1_ev~0); 1071745#L376-1 assume !(0 == ~main_in2_ev~0); 1071744#L381-1 assume !(0 == ~main_sum_ev~0); 1071743#L386-1 assume !(0 == ~main_diff_ev~0); 1071742#L391-1 assume !(0 == ~main_pres_ev~0); 1071741#L396-1 assume !(0 == ~main_dbl_ev~0); 1071740#L401-1 assume !(0 == ~main_zero_ev~0); 1071739#L406-1 assume !(0 == ~main_clk_ev~0); 1071738#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1071737#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1071736#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1071735#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1071733#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1071731#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1071729#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1071727#L446-1 assume !(1 == ~main_in1_ev~0); 1071725#L451-1 assume !(1 == ~main_in2_ev~0); 1071723#L456-1 assume !(1 == ~main_sum_ev~0); 1071721#L461-1 assume !(1 == ~main_diff_ev~0); 1071719#L466-1 assume !(1 == ~main_pres_ev~0); 1071717#L471-1 assume !(1 == ~main_dbl_ev~0); 1071715#L476-1 assume !(1 == ~main_zero_ev~0); 1071713#L481-1 assume !(1 == ~main_clk_ev~0); 1071695#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1071696#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1071708#L742-1 [2023-11-29 01:23:19,285 INFO L750 eck$LassoCheckResult]: Loop: 1071708#L742-1 assume !false; 1071707#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1070729#L229 assume !false; 1070730#L147 assume !(0 == ~N_generate_st~0); 1069172#L151 assume !(0 == ~S1_addsub_st~0); 1069173#L154 assume !(0 == ~S2_presdbl_st~0); 1069090#L157 assume !(0 == ~S3_zero_st~0); 1069091#L160 assume !(0 == ~D_print_st~0); 1069084#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 1069085#L509 assume !(1 == ~main_in1_req_up~0); 1069075#L509-2 assume !(1 == ~main_in2_req_up~0); 1069074#L520-1 assume !(1 == ~main_sum_req_up~0); 1073602#L531-1 assume !(1 == ~main_diff_req_up~0); 1069050#L542-1 assume !(1 == ~main_pres_req_up~0); 1069039#L553-1 assume !(1 == ~main_dbl_req_up~0); 1069038#L564-1 assume !(1 == ~main_zero_req_up~0); 1070024#L575-1 assume !(1 == ~main_clk_req_up~0); 1070025#L586-1 start_simulation_~kernel_st~0#1 := 3; 1071683#L605 assume !(0 == ~main_in1_ev~0); 1071684#L605-2 assume !(0 == ~main_in2_ev~0); 1071679#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 1071680#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 1071675#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 1071676#L625-1 assume !(0 == ~main_dbl_ev~0); 1071668#L630-1 assume !(0 == ~main_zero_ev~0); 1071669#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 1071660#L640-1 assume !(0 == ~main_clk_pos_edge~0); 1071661#L645-1 assume !(0 == ~main_clk_neg_edge~0); 1071654#L650-1 assume !(1 == ~main_clk_pos_edge~0); 1071655#L655-1 assume !(1 == ~main_clk_pos_edge~0); 1071647#L660-1 assume !(1 == ~main_clk_pos_edge~0); 1071648#L665-1 assume !(1 == ~main_clk_pos_edge~0); 1071639#L670-1 assume !(1 == ~main_clk_pos_edge~0); 1071640#L675-1 assume !(1 == ~main_in1_ev~0); 1071630#L680-1 assume !(1 == ~main_in2_ev~0); 1071631#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 1071622#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 1071623#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 1071614#L700-1 assume !(1 == ~main_dbl_ev~0); 1071615#L705-1 assume !(1 == ~main_zero_ev~0); 1071606#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 1071607#L715-1 assume !(1 == ~main_clk_pos_edge~0); 1071571#L720-1 assume !(1 == ~main_clk_neg_edge~0); 1071572#L725-1 assume !(0 == ~N_generate_st~0); 1071549#L733 assume !(0 == ~S1_addsub_st~0); 1071550#L736 assume !(0 == ~S2_presdbl_st~0); 1071538#L739 assume !(0 == ~S3_zero_st~0); 1071539#L742 assume 0 == ~D_print_st~0; 1071708#L742-1 [2023-11-29 01:23:19,285 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:19,285 INFO L85 PathProgramCache]: Analyzing trace with hash 222896887, now seen corresponding path program 7 times [2023-11-29 01:23:19,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:19,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234023953] [2023-11-29 01:23:19,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:19,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:19,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:19,300 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:19,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:19,320 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:19,321 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:19,321 INFO L85 PathProgramCache]: Analyzing trace with hash -1435455170, now seen corresponding path program 1 times [2023-11-29 01:23:19,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:19,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290145773] [2023-11-29 01:23:19,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:19,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:19,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:19,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:19,354 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:19,354 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290145773] [2023-11-29 01:23:19,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290145773] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:19,354 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:19,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:23:19,355 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887693980] [2023-11-29 01:23:19,355 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:19,355 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:19,355 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:19,356 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:23:19,356 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:23:19,356 INFO L87 Difference]: Start difference. First operand 147978 states and 218783 transitions. cyclomatic complexity: 70949 Second operand has 3 states, 2 states have (on average 24.0) internal successors, (48), 3 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:20,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:20,280 INFO L93 Difference]: Finished difference Result 253411 states and 370695 transitions. [2023-11-29 01:23:20,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 253411 states and 370695 transitions. [2023-11-29 01:23:22,102 INFO L131 ngComponentsAnalysis]: Automaton has 224 accepting balls. 219346 [2023-11-29 01:23:22,780 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 253411 states to 253411 states and 370695 transitions. [2023-11-29 01:23:22,780 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 253411 [2023-11-29 01:23:22,935 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 253411 [2023-11-29 01:23:22,935 INFO L73 IsDeterministic]: Start isDeterministic. Operand 253411 states and 370695 transitions. [2023-11-29 01:23:23,054 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:23,054 INFO L218 hiAutomatonCegarLoop]: Abstraction has 253411 states and 370695 transitions. [2023-11-29 01:23:23,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253411 states and 370695 transitions. [2023-11-29 01:23:25,550 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253411 to 253411. [2023-11-29 01:23:25,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 253411 states, 253411 states have (on average 1.4628212666379912) internal successors, (370695), 253410 states have internal predecessors, (370695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:26,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 253411 states to 253411 states and 370695 transitions. [2023-11-29 01:23:26,943 INFO L240 hiAutomatonCegarLoop]: Abstraction has 253411 states and 370695 transitions. [2023-11-29 01:23:26,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:23:26,951 INFO L428 stractBuchiCegarLoop]: Abstraction has 253411 states and 370695 transitions. [2023-11-29 01:23:26,951 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-29 01:23:26,952 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 253411 states and 370695 transitions. [2023-11-29 01:23:27,799 INFO L131 ngComponentsAnalysis]: Automaton has 224 accepting balls. 219346 [2023-11-29 01:23:27,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:27,800 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:27,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:27,800 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:27,801 INFO L748 eck$LassoCheckResult]: Stem: 1457826#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1457827#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1457639#L256 assume !(1 == ~main_in1_req_up~0); 1457591#L256-2 assume !(1 == ~main_in2_req_up~0); 1457593#L267-1 assume !(1 == ~main_sum_req_up~0); 1458130#L278-1 assume !(1 == ~main_diff_req_up~0); 1457573#L289-1 assume !(1 == ~main_pres_req_up~0); 1457574#L300-1 assume !(1 == ~main_dbl_req_up~0); 1474789#L311-1 assume !(1 == ~main_zero_req_up~0); 1474631#L322-1 assume !(1 == ~main_clk_req_up~0); 1474627#L333-1 assume 1 == ~N_generate_i~0;~N_generate_st~0 := 0; 1474624#L351-1 assume 1 == ~S1_addsub_i~0;~S1_addsub_st~0 := 0; 1474622#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1474621#L361-1 assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0; 1474617#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 1474615#L371-1 assume !(0 == ~main_in1_ev~0); 1474613#L376-1 assume !(0 == ~main_in2_ev~0); 1474611#L381-1 assume !(0 == ~main_sum_ev~0); 1474609#L386-1 assume !(0 == ~main_diff_ev~0); 1474607#L391-1 assume !(0 == ~main_pres_ev~0); 1474605#L396-1 assume !(0 == ~main_dbl_ev~0); 1474603#L401-1 assume !(0 == ~main_zero_ev~0); 1474601#L406-1 assume !(0 == ~main_clk_ev~0); 1474599#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1474597#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1474595#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1474593#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1474591#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1474589#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1474587#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1474585#L446-1 assume !(1 == ~main_in1_ev~0); 1474583#L451-1 assume !(1 == ~main_in2_ev~0); 1474581#L456-1 assume !(1 == ~main_sum_ev~0); 1474579#L461-1 assume !(1 == ~main_diff_ev~0); 1474577#L466-1 assume !(1 == ~main_pres_ev~0); 1474575#L471-1 assume !(1 == ~main_dbl_ev~0); 1474573#L476-1 assume !(1 == ~main_zero_ev~0); 1474571#L481-1 assume !(1 == ~main_clk_ev~0); 1474569#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1474567#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1474565#L742-1 assume !false; 1474563#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1474560#L229 [2023-11-29 01:23:27,801 INFO L750 eck$LassoCheckResult]: Loop: 1474560#L229 assume !false; 1474556#L147 assume 0 == ~N_generate_st~0; 1474552#L160-1 assume 0 == ~N_generate_st~0;havoc eval_#t~nondet4#1;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1; 1474548#L173 assume !(0 != eval_~tmp~0#1); 1474549#L169 assume 0 == ~S1_addsub_st~0;havoc eval_#t~nondet5#1;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1474636#L188 assume !(0 != eval_~tmp___0~0#1); 1474633#L184 assume !(0 == ~S2_presdbl_st~0); 1474629#L199 assume 0 == ~S3_zero_st~0;havoc eval_#t~nondet7#1;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1474626#L218 assume !(0 != eval_~tmp___2~0#1); 1474623#L214 assume 0 == ~D_print_st~0;havoc eval_#t~nondet8#1;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1474561#L233 assume !(0 != eval_~tmp___3~0#1); 1474560#L229 [2023-11-29 01:23:27,801 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:27,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1897430713, now seen corresponding path program 1 times [2023-11-29 01:23:27,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:27,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1976799440] [2023-11-29 01:23:27,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:27,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:27,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:27,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:27,865 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:27,865 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1976799440] [2023-11-29 01:23:27,865 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1976799440] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:27,866 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:27,866 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:23:27,866 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [169071416] [2023-11-29 01:23:27,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:27,866 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:23:27,867 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:27,867 INFO L85 PathProgramCache]: Analyzing trace with hash 263530038, now seen corresponding path program 1 times [2023-11-29 01:23:27,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:27,867 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1802967759] [2023-11-29 01:23:27,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:27,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:27,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:27,872 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:27,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:27,877 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:27,964 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:27,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:23:27,965 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:23:27,965 INFO L87 Difference]: Start difference. First operand 253411 states and 370695 transitions. cyclomatic complexity: 117508 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:28,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:28,663 INFO L93 Difference]: Finished difference Result 152871 states and 223090 transitions. [2023-11-29 01:23:28,663 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 152871 states and 223090 transitions. [2023-11-29 01:23:29,893 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 131250 [2023-11-29 01:23:30,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 152871 states to 152871 states and 223090 transitions. [2023-11-29 01:23:30,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 152871 [2023-11-29 01:23:30,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 152871 [2023-11-29 01:23:30,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 152871 states and 223090 transitions. [2023-11-29 01:23:30,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:30,460 INFO L218 hiAutomatonCegarLoop]: Abstraction has 152871 states and 223090 transitions. [2023-11-29 01:23:30,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152871 states and 223090 transitions. [2023-11-29 01:23:31,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152871 to 152871. [2023-11-29 01:23:32,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 152871 states, 152871 states have (on average 1.4593349948649514) internal successors, (223090), 152870 states have internal predecessors, (223090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:32,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152871 states to 152871 states and 223090 transitions. [2023-11-29 01:23:32,443 INFO L240 hiAutomatonCegarLoop]: Abstraction has 152871 states and 223090 transitions. [2023-11-29 01:23:32,444 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:23:32,444 INFO L428 stractBuchiCegarLoop]: Abstraction has 152871 states and 223090 transitions. [2023-11-29 01:23:32,444 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-29 01:23:32,444 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 152871 states and 223090 transitions. [2023-11-29 01:23:33,320 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 131250 [2023-11-29 01:23:33,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:33,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:33,321 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:33,321 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:33,321 INFO L748 eck$LassoCheckResult]: Stem: 1864129#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 1864130#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 1863930#L256 assume !(1 == ~main_in1_req_up~0); 1863883#L256-2 assume !(1 == ~main_in2_req_up~0); 1863885#L267-1 assume !(1 == ~main_sum_req_up~0); 1863917#L278-1 assume !(1 == ~main_diff_req_up~0); 1863865#L289-1 assume !(1 == ~main_pres_req_up~0); 1863866#L300-1 assume !(1 == ~main_dbl_req_up~0); 1893381#L311-1 assume !(1 == ~main_zero_req_up~0); 1893375#L322-1 assume !(1 == ~main_clk_req_up~0); 1893371#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 1893367#L351-1 assume 1 == ~S1_addsub_i~0;~S1_addsub_st~0 := 0; 1893368#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 1893421#L361-1 assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0; 1893418#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 1893416#L371-1 assume !(0 == ~main_in1_ev~0); 1893414#L376-1 assume !(0 == ~main_in2_ev~0); 1893412#L381-1 assume !(0 == ~main_sum_ev~0); 1893410#L386-1 assume !(0 == ~main_diff_ev~0); 1893408#L391-1 assume !(0 == ~main_pres_ev~0); 1893406#L396-1 assume !(0 == ~main_dbl_ev~0); 1893404#L401-1 assume !(0 == ~main_zero_ev~0); 1893402#L406-1 assume !(0 == ~main_clk_ev~0); 1893400#L411-1 assume !(0 == ~main_clk_pos_edge~0); 1893398#L416-1 assume !(0 == ~main_clk_neg_edge~0); 1893396#L421-1 assume !(1 == ~main_clk_pos_edge~0); 1893393#L426-1 assume !(1 == ~main_clk_pos_edge~0); 1893391#L431-1 assume !(1 == ~main_clk_pos_edge~0); 1893388#L436-1 assume !(1 == ~main_clk_pos_edge~0); 1893383#L441-1 assume !(1 == ~main_clk_pos_edge~0); 1893377#L446-1 assume !(1 == ~main_in1_ev~0); 1893372#L451-1 assume !(1 == ~main_in2_ev~0); 1893369#L456-1 assume !(1 == ~main_sum_ev~0); 1893365#L461-1 assume !(1 == ~main_diff_ev~0); 1893362#L466-1 assume !(1 == ~main_pres_ev~0); 1893361#L471-1 assume !(1 == ~main_dbl_ev~0); 1893360#L476-1 assume !(1 == ~main_zero_ev~0); 1893359#L481-1 assume !(1 == ~main_clk_ev~0); 1893358#L486-1 assume !(1 == ~main_clk_pos_edge~0); 1893357#L491-1 assume !(1 == ~main_clk_neg_edge~0); 1893356#L742-1 assume !false; 1893286#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 1893278#L229 [2023-11-29 01:23:33,321 INFO L750 eck$LassoCheckResult]: Loop: 1893278#L229 assume !false; 1893272#L147 assume !(0 == ~N_generate_st~0); 1893269#L151 assume 0 == ~S1_addsub_st~0; 1893265#L160-1 assume !(0 == ~N_generate_st~0); 1893261#L169 assume 0 == ~S1_addsub_st~0;havoc eval_#t~nondet5#1;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1893256#L188 assume !(0 != eval_~tmp___0~0#1); 1893257#L184 assume !(0 == ~S2_presdbl_st~0); 1893288#L199 assume 0 == ~S3_zero_st~0;havoc eval_#t~nondet7#1;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1893289#L218 assume !(0 != eval_~tmp___2~0#1); 1893354#L214 assume 0 == ~D_print_st~0;havoc eval_#t~nondet8#1;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1893284#L233 assume !(0 != eval_~tmp___3~0#1); 1893278#L229 [2023-11-29 01:23:33,322 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:33,322 INFO L85 PathProgramCache]: Analyzing trace with hash -2122776969, now seen corresponding path program 1 times [2023-11-29 01:23:33,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:33,322 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530655526] [2023-11-29 01:23:33,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:33,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:33,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:33,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:33,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:33,374 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1530655526] [2023-11-29 01:23:33,374 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1530655526] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:33,374 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:33,374 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:23:33,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1153710057] [2023-11-29 01:23:33,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:33,375 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:23:33,375 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:33,375 INFO L85 PathProgramCache]: Analyzing trace with hash 105804796, now seen corresponding path program 1 times [2023-11-29 01:23:33,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:33,375 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2104224718] [2023-11-29 01:23:33,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:33,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:33,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:33,379 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:33,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:33,383 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:33,440 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:33,441 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:23:33,441 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:23:33,441 INFO L87 Difference]: Start difference. First operand 152871 states and 223090 transitions. cyclomatic complexity: 70315 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:33,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:33,890 INFO L93 Difference]: Finished difference Result 109199 states and 158994 transitions. [2023-11-29 01:23:33,890 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109199 states and 158994 transitions. [2023-11-29 01:23:34,356 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 94626 [2023-11-29 01:23:34,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109199 states to 109199 states and 158994 transitions. [2023-11-29 01:23:34,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 109199 [2023-11-29 01:23:34,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 109199 [2023-11-29 01:23:34,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 109199 states and 158994 transitions. [2023-11-29 01:23:34,746 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:34,746 INFO L218 hiAutomatonCegarLoop]: Abstraction has 109199 states and 158994 transitions. [2023-11-29 01:23:34,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109199 states and 158994 transitions. [2023-11-29 01:23:36,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109199 to 109199. [2023-11-29 01:23:36,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 109199 states, 109199 states have (on average 1.4560023443438126) internal successors, (158994), 109198 states have internal predecessors, (158994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:36,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109199 states to 109199 states and 158994 transitions. [2023-11-29 01:23:36,847 INFO L240 hiAutomatonCegarLoop]: Abstraction has 109199 states and 158994 transitions. [2023-11-29 01:23:36,848 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:23:36,848 INFO L428 stractBuchiCegarLoop]: Abstraction has 109199 states and 158994 transitions. [2023-11-29 01:23:36,849 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-29 01:23:36,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 109199 states and 158994 transitions. [2023-11-29 01:23:37,655 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 94626 [2023-11-29 01:23:37,656 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:37,656 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:37,656 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:37,656 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:37,657 INFO L748 eck$LassoCheckResult]: Stem: 2126198#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2126199#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2126010#L256 assume !(1 == ~main_in1_req_up~0); 2125963#L256-2 assume !(1 == ~main_in2_req_up~0); 2125965#L267-1 assume !(1 == ~main_sum_req_up~0); 2125997#L278-1 assume !(1 == ~main_diff_req_up~0); 2125945#L289-1 assume !(1 == ~main_pres_req_up~0); 2125946#L300-1 assume !(1 == ~main_dbl_req_up~0); 2128335#L311-1 assume !(1 == ~main_zero_req_up~0); 2128326#L322-1 assume !(1 == ~main_clk_req_up~0); 2128327#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2129961#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2129960#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2129958#L361-1 assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0; 2129959#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 2129970#L371-1 assume !(0 == ~main_in1_ev~0); 2129969#L376-1 assume !(0 == ~main_in2_ev~0); 2129968#L381-1 assume !(0 == ~main_sum_ev~0); 2129967#L386-1 assume !(0 == ~main_diff_ev~0); 2129966#L391-1 assume !(0 == ~main_pres_ev~0); 2129965#L396-1 assume !(0 == ~main_dbl_ev~0); 2129964#L401-1 assume !(0 == ~main_zero_ev~0); 2129963#L406-1 assume !(0 == ~main_clk_ev~0); 2129962#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2129868#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2129866#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2129863#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2129861#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2129858#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2129855#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2129852#L446-1 assume !(1 == ~main_in1_ev~0); 2129849#L451-1 assume !(1 == ~main_in2_ev~0); 2129846#L456-1 assume !(1 == ~main_sum_ev~0); 2129843#L461-1 assume !(1 == ~main_diff_ev~0); 2129840#L466-1 assume !(1 == ~main_pres_ev~0); 2129837#L471-1 assume !(1 == ~main_dbl_ev~0); 2129834#L476-1 assume !(1 == ~main_zero_ev~0); 2129831#L481-1 assume !(1 == ~main_clk_ev~0); 2129828#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2129825#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2129565#L742-1 assume !false; 2129562#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2129556#L229 [2023-11-29 01:23:37,657 INFO L750 eck$LassoCheckResult]: Loop: 2129556#L229 assume !false; 2129553#L147 assume !(0 == ~N_generate_st~0); 2129548#L151 assume !(0 == ~S1_addsub_st~0); 2129549#L154 assume !(0 == ~S2_presdbl_st~0); 2129801#L157 assume 0 == ~S3_zero_st~0; 2129799#L160-1 assume !(0 == ~N_generate_st~0); 2129796#L169 assume !(0 == ~S1_addsub_st~0); 2129761#L184 assume !(0 == ~S2_presdbl_st~0); 2129755#L199 assume 0 == ~S3_zero_st~0;havoc eval_#t~nondet7#1;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2129753#L218 assume !(0 != eval_~tmp___2~0#1); 2129748#L214 assume 0 == ~D_print_st~0;havoc eval_#t~nondet8#1;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2129559#L233 assume !(0 != eval_~tmp___3~0#1); 2129556#L229 [2023-11-29 01:23:37,657 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:37,657 INFO L85 PathProgramCache]: Analyzing trace with hash -1421177095, now seen corresponding path program 1 times [2023-11-29 01:23:37,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:37,657 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1476765934] [2023-11-29 01:23:37,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:37,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:37,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:37,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:37,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:37,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1476765934] [2023-11-29 01:23:37,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1476765934] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:37,717 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:37,717 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:23:37,717 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077785298] [2023-11-29 01:23:37,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:37,717 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:23:37,718 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:37,718 INFO L85 PathProgramCache]: Analyzing trace with hash 1118247229, now seen corresponding path program 1 times [2023-11-29 01:23:37,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:37,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675335684] [2023-11-29 01:23:37,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:37,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:37,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:37,722 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:37,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:37,726 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:37,776 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:37,777 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:23:37,777 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:23:37,777 INFO L87 Difference]: Start difference. First operand 109199 states and 158994 transitions. cyclomatic complexity: 49859 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:38,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:38,102 INFO L93 Difference]: Finished difference Result 81667 states and 118838 transitions. [2023-11-29 01:23:38,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81667 states and 118838 transitions. [2023-11-29 01:23:38,509 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 71796 [2023-11-29 01:23:38,727 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81667 states to 81667 states and 118838 transitions. [2023-11-29 01:23:38,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81667 [2023-11-29 01:23:38,777 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81667 [2023-11-29 01:23:38,777 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81667 states and 118838 transitions. [2023-11-29 01:23:38,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:38,819 INFO L218 hiAutomatonCegarLoop]: Abstraction has 81667 states and 118838 transitions. [2023-11-29 01:23:38,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81667 states and 118838 transitions. [2023-11-29 01:23:39,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81667 to 81667. [2023-11-29 01:23:39,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81667 states, 81667 states have (on average 1.4551532442724724) internal successors, (118838), 81666 states have internal predecessors, (118838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:40,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81667 states to 81667 states and 118838 transitions. [2023-11-29 01:23:40,034 INFO L240 hiAutomatonCegarLoop]: Abstraction has 81667 states and 118838 transitions. [2023-11-29 01:23:40,035 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:23:40,035 INFO L428 stractBuchiCegarLoop]: Abstraction has 81667 states and 118838 transitions. [2023-11-29 01:23:40,035 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-29 01:23:40,035 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81667 states and 118838 transitions. [2023-11-29 01:23:40,270 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 71796 [2023-11-29 01:23:40,270 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:40,270 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:40,271 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:40,271 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:40,271 INFO L748 eck$LassoCheckResult]: Stem: 2317075#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2317076#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2316888#L256 assume !(1 == ~main_in1_req_up~0); 2316839#L256-2 assume !(1 == ~main_in2_req_up~0); 2316841#L267-1 assume !(1 == ~main_sum_req_up~0); 2316874#L278-1 assume !(1 == ~main_diff_req_up~0); 2316821#L289-1 assume !(1 == ~main_pres_req_up~0); 2316822#L300-1 assume !(1 == ~main_dbl_req_up~0); 2317119#L311-1 assume !(1 == ~main_zero_req_up~0); 2317116#L322-1 assume !(1 == ~main_clk_req_up~0); 2317408#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2331395#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2331385#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2331379#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2331372#L366-1 assume 1 == ~D_print_i~0;~D_print_st~0 := 0; 2331371#L371-1 assume !(0 == ~main_in1_ev~0); 2331370#L376-1 assume !(0 == ~main_in2_ev~0); 2331368#L381-1 assume !(0 == ~main_sum_ev~0); 2331366#L386-1 assume !(0 == ~main_diff_ev~0); 2331364#L391-1 assume !(0 == ~main_pres_ev~0); 2331362#L396-1 assume !(0 == ~main_dbl_ev~0); 2331360#L401-1 assume !(0 == ~main_zero_ev~0); 2331358#L406-1 assume !(0 == ~main_clk_ev~0); 2331356#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2331354#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2331352#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2331351#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2331350#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2331347#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2331345#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2331343#L446-1 assume !(1 == ~main_in1_ev~0); 2331341#L451-1 assume !(1 == ~main_in2_ev~0); 2331338#L456-1 assume !(1 == ~main_sum_ev~0); 2331336#L461-1 assume !(1 == ~main_diff_ev~0); 2331334#L466-1 assume !(1 == ~main_pres_ev~0); 2331332#L471-1 assume !(1 == ~main_dbl_ev~0); 2331330#L476-1 assume !(1 == ~main_zero_ev~0); 2331328#L481-1 assume !(1 == ~main_clk_ev~0); 2331326#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2331324#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2331322#L742-1 assume !false; 2331320#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2331192#L229 [2023-11-29 01:23:40,271 INFO L750 eck$LassoCheckResult]: Loop: 2331192#L229 assume !false; 2331318#L147 assume !(0 == ~N_generate_st~0); 2331122#L151 assume !(0 == ~S1_addsub_st~0); 2331117#L154 assume !(0 == ~S2_presdbl_st~0); 2321044#L157 assume !(0 == ~S3_zero_st~0); 2321045#L160 assume 0 == ~D_print_st~0; 2331235#L160-1 assume !(0 == ~N_generate_st~0); 2331229#L169 assume !(0 == ~S1_addsub_st~0); 2331223#L184 assume !(0 == ~S2_presdbl_st~0); 2331217#L199 assume !(0 == ~S3_zero_st~0); 2331193#L214 assume 0 == ~D_print_st~0;havoc eval_#t~nondet8#1;eval_~tmp___3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2331191#L233 assume !(0 != eval_~tmp___3~0#1); 2331192#L229 [2023-11-29 01:23:40,272 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:40,272 INFO L85 PathProgramCache]: Analyzing trace with hash -34973701, now seen corresponding path program 1 times [2023-11-29 01:23:40,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:40,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081837160] [2023-11-29 01:23:40,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:40,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:40,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:40,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:40,312 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:40,312 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2081837160] [2023-11-29 01:23:40,313 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2081837160] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:40,313 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:40,313 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:23:40,313 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315261392] [2023-11-29 01:23:40,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:40,313 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:23:40,313 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:40,314 INFO L85 PathProgramCache]: Analyzing trace with hash -1420110094, now seen corresponding path program 1 times [2023-11-29 01:23:40,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:40,314 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579660752] [2023-11-29 01:23:40,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:40,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:40,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:40,316 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:40,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:40,319 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:40,361 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:40,362 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:23:40,362 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:23:40,362 INFO L87 Difference]: Start difference. First operand 81667 states and 118838 transitions. cyclomatic complexity: 37219 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:40,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:40,607 INFO L93 Difference]: Finished difference Result 66199 states and 96067 transitions. [2023-11-29 01:23:40,608 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66199 states and 96067 transitions. [2023-11-29 01:23:40,872 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 59042 [2023-11-29 01:23:41,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66199 states to 66199 states and 96067 transitions. [2023-11-29 01:23:41,058 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66199 [2023-11-29 01:23:41,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66199 [2023-11-29 01:23:41,099 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66199 states and 96067 transitions. [2023-11-29 01:23:41,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:41,132 INFO L218 hiAutomatonCegarLoop]: Abstraction has 66199 states and 96067 transitions. [2023-11-29 01:23:41,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66199 states and 96067 transitions. [2023-11-29 01:23:42,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66199 to 66199. [2023-11-29 01:23:42,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66199 states, 66199 states have (on average 1.4511850632184775) internal successors, (96067), 66198 states have internal predecessors, (96067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:42,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66199 states to 66199 states and 96067 transitions. [2023-11-29 01:23:42,369 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66199 states and 96067 transitions. [2023-11-29 01:23:42,369 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:23:42,370 INFO L428 stractBuchiCegarLoop]: Abstraction has 66199 states and 96067 transitions. [2023-11-29 01:23:42,370 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-29 01:23:42,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66199 states and 96067 transitions. [2023-11-29 01:23:42,587 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 59042 [2023-11-29 01:23:42,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:42,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:42,588 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:42,589 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:42,589 INFO L748 eck$LassoCheckResult]: Stem: 2464950#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2464951#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2464763#L256 assume !(1 == ~main_in1_req_up~0); 2464715#L256-2 assume !(1 == ~main_in2_req_up~0); 2464717#L267-1 assume !(1 == ~main_sum_req_up~0); 2464749#L278-1 assume !(1 == ~main_diff_req_up~0); 2464697#L289-1 assume !(1 == ~main_pres_req_up~0); 2464698#L300-1 assume !(1 == ~main_dbl_req_up~0); 2464811#L311-1 assume !(1 == ~main_zero_req_up~0); 2467438#L322-1 assume 1 == ~main_clk_req_up~0; 2467436#L334 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 2467433#L337 assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2; 2467430#L334-1 ~main_clk_req_up~0 := 0; 2467401#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2467327#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2467256#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2467253#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2467250#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2467248#L371-1 assume !(0 == ~main_in1_ev~0); 2467246#L376-1 assume !(0 == ~main_in2_ev~0); 2467244#L381-1 assume !(0 == ~main_sum_ev~0); 2467242#L386-1 assume !(0 == ~main_diff_ev~0); 2467240#L391-1 assume !(0 == ~main_pres_ev~0); 2467238#L396-1 assume !(0 == ~main_dbl_ev~0); 2467236#L401-1 assume !(0 == ~main_zero_ev~0); 2467234#L406-1 assume !(0 == ~main_clk_ev~0); 2467231#L411-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 2467229#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2467225#L421-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 2467222#L426-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 2467218#L431-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 2467214#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2467215#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2467843#L446-1 assume !(1 == ~main_in1_ev~0); 2467840#L451-1 assume !(1 == ~main_in2_ev~0); 2467838#L456-1 assume !(1 == ~main_sum_ev~0); 2467836#L461-1 assume !(1 == ~main_diff_ev~0); 2467834#L466-1 assume !(1 == ~main_pres_ev~0); 2467832#L471-1 assume !(1 == ~main_dbl_ev~0); 2467817#L476-1 assume !(1 == ~main_zero_ev~0); 2467812#L481-1 assume !(1 == ~main_clk_ev~0); 2467808#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2467802#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2467592#L742-1 [2023-11-29 01:23:42,589 INFO L750 eck$LassoCheckResult]: Loop: 2467592#L742-1 assume !false; 2467589#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2467273#L229 assume !false; 2467582#L147 assume !(0 == ~N_generate_st~0); 2467583#L151 assume !(0 == ~S1_addsub_st~0); 2468453#L154 assume !(0 == ~S2_presdbl_st~0); 2468454#L157 assume !(0 == ~S3_zero_st~0); 2468586#L160 assume !(0 == ~D_print_st~0); 2468589#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2479460#L509 assume !(1 == ~main_in1_req_up~0); 2479459#L509-2 assume !(1 == ~main_in2_req_up~0); 2467465#L520-1 assume !(1 == ~main_sum_req_up~0); 2467464#L531-1 assume !(1 == ~main_diff_req_up~0); 2500195#L542-1 assume !(1 == ~main_pres_req_up~0); 2500193#L553-1 assume !(1 == ~main_dbl_req_up~0); 2467449#L564-1 assume !(1 == ~main_zero_req_up~0); 2467367#L575-1 assume 1 == ~main_clk_req_up~0; 2467254#L587 assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0; 2467251#L590 assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2; 2467249#L587-1 ~main_clk_req_up~0 := 0; 2467247#L586-1 start_simulation_~kernel_st~0#1 := 3; 2467245#L605 assume !(0 == ~main_in1_ev~0); 2467243#L605-2 assume !(0 == ~main_in2_ev~0); 2467241#L610-1 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2467239#L615-1 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2467237#L620-1 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2467235#L625-1 assume !(0 == ~main_dbl_ev~0); 2467233#L630-1 assume !(0 == ~main_zero_ev~0); 2467230#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2467227#L640-1 assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1; 2467224#L645-1 assume !(0 == ~main_clk_neg_edge~0); 2467220#L650-1 assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0; 2467216#L655-1 assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0; 2467212#L660-1 assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0; 2467208#L665-1 assume !(1 == ~main_clk_pos_edge~0); 2467209#L670-1 assume !(1 == ~main_clk_pos_edge~0); 2467830#L675-1 assume !(1 == ~main_in1_ev~0); 2467829#L680-1 assume !(1 == ~main_in2_ev~0); 2467827#L685-1 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2467825#L690-1 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2467823#L695-1 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2467821#L700-1 assume !(1 == ~main_dbl_ev~0); 2467819#L705-1 assume !(1 == ~main_zero_ev~0); 2467818#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2467814#L715-1 assume !(1 == ~main_clk_pos_edge~0); 2467809#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2467803#L725-1 assume 0 == ~N_generate_st~0; 2467592#L742-1 [2023-11-29 01:23:42,590 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:42,590 INFO L85 PathProgramCache]: Analyzing trace with hash 1830128562, now seen corresponding path program 1 times [2023-11-29 01:23:42,590 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:42,590 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1604001577] [2023-11-29 01:23:42,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:42,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:42,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:42,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:42,630 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:42,631 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1604001577] [2023-11-29 01:23:42,631 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1604001577] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:42,631 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:42,631 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:23:42,631 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [116001122] [2023-11-29 01:23:42,631 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:42,632 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:23:42,632 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:42,632 INFO L85 PathProgramCache]: Analyzing trace with hash 744593900, now seen corresponding path program 1 times [2023-11-29 01:23:42,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:42,632 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309287358] [2023-11-29 01:23:42,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:42,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:42,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:42,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:42,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:42,650 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1309287358] [2023-11-29 01:23:42,650 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1309287358] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:42,650 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:42,650 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:23:42,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1772961351] [2023-11-29 01:23:42,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:42,651 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:42,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:42,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:23:42,651 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:23:42,651 INFO L87 Difference]: Start difference. First operand 66199 states and 96067 transitions. cyclomatic complexity: 29908 Second operand has 4 states, 4 states have (on average 10.75) internal successors, (43), 4 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:42,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:42,818 INFO L93 Difference]: Finished difference Result 38411 states and 55018 transitions. [2023-11-29 01:23:42,818 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38411 states and 55018 transitions. [2023-11-29 01:23:42,988 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36848 [2023-11-29 01:23:43,098 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38411 states to 38411 states and 55018 transitions. [2023-11-29 01:23:43,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38411 [2023-11-29 01:23:43,122 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38411 [2023-11-29 01:23:43,122 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38411 states and 55018 transitions. [2023-11-29 01:23:43,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:43,141 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38411 states and 55018 transitions. [2023-11-29 01:23:43,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38411 states and 55018 transitions. [2023-11-29 01:23:43,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38411 to 38395. [2023-11-29 01:23:43,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38395 states, 38395 states have (on average 1.4325302773798672) internal successors, (55002), 38394 states have internal predecessors, (55002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:44,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38395 states to 38395 states and 55002 transitions. [2023-11-29 01:23:44,050 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38395 states and 55002 transitions. [2023-11-29 01:23:44,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:23:44,051 INFO L428 stractBuchiCegarLoop]: Abstraction has 38395 states and 55002 transitions. [2023-11-29 01:23:44,051 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-29 01:23:44,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38395 states and 55002 transitions. [2023-11-29 01:23:44,189 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36848 [2023-11-29 01:23:44,189 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:44,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:44,191 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:44,191 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:44,191 INFO L748 eck$LassoCheckResult]: Stem: 2569551#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2569552#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2569373#L256 assume !(1 == ~main_in1_req_up~0); 2569334#L256-2 assume !(1 == ~main_in2_req_up~0); 2569336#L267-1 assume !(1 == ~main_sum_req_up~0); 2569362#L278-1 assume !(1 == ~main_diff_req_up~0); 2569318#L289-1 assume !(1 == ~main_pres_req_up~0); 2569319#L300-1 assume !(1 == ~main_dbl_req_up~0); 2569416#L311-1 assume !(1 == ~main_zero_req_up~0); 2569839#L322-1 assume !(1 == ~main_clk_req_up~0); 2569840#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2570281#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2570282#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2570366#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2570275#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2570276#L371-1 assume !(0 == ~main_in1_ev~0); 2569399#L376-1 assume !(0 == ~main_in2_ev~0); 2569400#L381-1 assume !(0 == ~main_sum_ev~0); 2569814#L386-1 assume !(0 == ~main_diff_ev~0); 2569832#L391-1 assume !(0 == ~main_pres_ev~0); 2569833#L396-1 assume !(0 == ~main_dbl_ev~0); 2575229#L401-1 assume !(0 == ~main_zero_ev~0); 2575227#L406-1 assume !(0 == ~main_clk_ev~0); 2575225#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2575223#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2575221#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2575219#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2575217#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2575215#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2575213#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2575211#L446-1 assume !(1 == ~main_in1_ev~0); 2575209#L451-1 assume !(1 == ~main_in2_ev~0); 2575207#L456-1 assume !(1 == ~main_sum_ev~0); 2575205#L461-1 assume !(1 == ~main_diff_ev~0); 2575203#L466-1 assume !(1 == ~main_pres_ev~0); 2575201#L471-1 assume !(1 == ~main_dbl_ev~0); 2575199#L476-1 assume !(1 == ~main_zero_ev~0); 2575197#L481-1 assume !(1 == ~main_clk_ev~0); 2575195#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2575193#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2575191#L742-1 assume !false; 2575189#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2575187#L229 assume !false; 2575185#L147 assume !(0 == ~N_generate_st~0); 2575183#L151 assume !(0 == ~S1_addsub_st~0); 2575181#L154 assume !(0 == ~S2_presdbl_st~0); 2575179#L157 assume !(0 == ~S3_zero_st~0); 2575177#L160 assume !(0 == ~D_print_st~0); 2575175#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2575173#L509 assume !(1 == ~main_in1_req_up~0); 2575169#L509-2 assume !(1 == ~main_in2_req_up~0); 2575165#L520-1 assume !(1 == ~main_sum_req_up~0); 2575160#L531-1 assume !(1 == ~main_diff_req_up~0); 2575157#L542-1 assume !(1 == ~main_pres_req_up~0); 2575152#L553-1 assume !(1 == ~main_dbl_req_up~0); 2575126#L564-1 assume !(1 == ~main_zero_req_up~0); 2575123#L575-1 assume !(1 == ~main_clk_req_up~0); 2575121#L586-1 start_simulation_~kernel_st~0#1 := 3; 2575119#L605 assume !(0 == ~main_in1_ev~0); 2575117#L605-2 assume !(0 == ~main_in2_ev~0); 2575115#L610-1 assume !(0 == ~main_sum_ev~0); 2575113#L615-1 assume !(0 == ~main_diff_ev~0); 2575111#L620-1 assume !(0 == ~main_pres_ev~0); 2575109#L625-1 assume !(0 == ~main_dbl_ev~0); 2575107#L630-1 assume !(0 == ~main_zero_ev~0); 2575105#L635-1 assume !(0 == ~main_clk_ev~0); 2575103#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2575101#L645-1 assume !(0 == ~main_clk_neg_edge~0); 2575099#L650-1 assume !(1 == ~main_clk_pos_edge~0); 2575097#L655-1 assume !(1 == ~main_clk_pos_edge~0); 2575095#L660-1 assume !(1 == ~main_clk_pos_edge~0); 2575093#L665-1 assume !(1 == ~main_clk_pos_edge~0); 2575091#L670-1 assume !(1 == ~main_clk_pos_edge~0); 2575089#L675-1 assume !(1 == ~main_in1_ev~0); 2575087#L680-1 assume !(1 == ~main_in2_ev~0); 2575085#L685-1 assume !(1 == ~main_sum_ev~0); 2575083#L690-1 assume !(1 == ~main_diff_ev~0); 2575081#L695-1 assume !(1 == ~main_pres_ev~0); 2575079#L700-1 assume !(1 == ~main_dbl_ev~0); 2575077#L705-1 assume !(1 == ~main_zero_ev~0); 2575075#L710-1 assume !(1 == ~main_clk_ev~0); 2575073#L715-1 assume !(1 == ~main_clk_pos_edge~0); 2575071#L720-1 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 2575069#L725-1 assume !(0 == ~N_generate_st~0); 2575067#L733 assume !(0 == ~S1_addsub_st~0); 2575065#L736 assume !(0 == ~S2_presdbl_st~0); 2575063#L739 assume !(0 == ~S3_zero_st~0); 2575061#L742 assume !(0 == ~D_print_st~0); 2575059#start_simulation_returnLabel#1 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 2575057#L795-2 [2023-11-29 01:23:44,193 INFO L750 eck$LassoCheckResult]: Loop: 2575057#L795-2 assume !false; 2575044#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2575040#L256-3 assume !(1 == ~main_in1_req_up~0); 2575033#L256-5 assume !(1 == ~main_in2_req_up~0); 2575023#L267-3 assume !(1 == ~main_sum_req_up~0); 2575014#L278-3 assume !(1 == ~main_diff_req_up~0); 2575009#L289-3 assume !(1 == ~main_pres_req_up~0); 2575003#L300-3 assume !(1 == ~main_dbl_req_up~0); 2574998#L311-3 assume !(1 == ~main_zero_req_up~0); 2574992#L322-3 assume !(1 == ~main_clk_req_up~0); 2574988#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2574985#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2574982#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2574979#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2574976#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2574973#L371-3 assume !(0 == ~main_in1_ev~0); 2574970#L376-3 assume !(0 == ~main_in2_ev~0); 2574967#L381-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2574964#L386-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2574961#L391-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2574958#L396-3 assume !(0 == ~main_dbl_ev~0); 2574955#L401-3 assume !(0 == ~main_zero_ev~0); 2574952#L406-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2574949#L411-3 assume !(0 == ~main_clk_pos_edge~0); 2574946#L416-3 assume !(0 == ~main_clk_neg_edge~0); 2574943#L421-3 assume !(1 == ~main_clk_pos_edge~0); 2574940#L426-3 assume !(1 == ~main_clk_pos_edge~0); 2574937#L431-3 assume !(1 == ~main_clk_pos_edge~0); 2574934#L436-3 assume !(1 == ~main_clk_pos_edge~0); 2574931#L441-3 assume !(1 == ~main_clk_pos_edge~0); 2574928#L446-3 assume !(1 == ~main_in1_ev~0); 2574925#L451-3 assume !(1 == ~main_in2_ev~0); 2574923#L456-3 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2574921#L461-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2574919#L466-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2574917#L471-3 assume !(1 == ~main_dbl_ev~0); 2574915#L476-3 assume !(1 == ~main_zero_ev~0); 2574913#L481-3 assume !(1 == ~main_clk_ev~0); 2574911#L486-3 assume !(1 == ~main_clk_pos_edge~0); 2574909#L491-3 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 2574907#L742-3 assume !false; 2574905#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2574903#L229-1 assume !false; 2574901#L147-1 assume !(0 == ~N_generate_st~0); 2574899#L151-2 assume !(0 == ~S1_addsub_st~0); 2574896#L154-2 assume !(0 == ~S2_presdbl_st~0); 2574892#L157-2 assume !(0 == ~S3_zero_st~0); 2574888#L160-2 assume !(0 == ~D_print_st~0); 2574884#eval_returnLabel#2 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2574879#L509-3 assume !(1 == ~main_in1_req_up~0); 2574872#L509-5 assume !(1 == ~main_in2_req_up~0); 2574862#L520-3 assume !(1 == ~main_sum_req_up~0); 2574856#L531-3 assume !(1 == ~main_diff_req_up~0); 2574850#L542-3 assume !(1 == ~main_pres_req_up~0); 2574842#L553-3 assume !(1 == ~main_dbl_req_up~0); 2574835#L564-3 assume !(1 == ~main_zero_req_up~0); 2574831#L575-3 assume !(1 == ~main_clk_req_up~0); 2574827#L586-3 start_simulation_~kernel_st~0#1 := 3; 2574822#L605-3 assume !(0 == ~main_in1_ev~0); 2574816#L605-5 assume !(0 == ~main_in2_ev~0); 2574813#L610-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2574809#L615-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2574805#L620-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2574804#L625-3 assume !(0 == ~main_dbl_ev~0); 2574798#L630-3 assume !(0 == ~main_zero_ev~0); 2574797#L635-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2574788#L640-3 assume !(0 == ~main_clk_pos_edge~0); 2574776#L645-3 assume !(0 == ~main_clk_neg_edge~0); 2574774#L650-3 assume !(1 == ~main_clk_pos_edge~0); 2574772#L655-3 assume !(1 == ~main_clk_pos_edge~0); 2574770#L660-3 assume !(1 == ~main_clk_pos_edge~0); 2574709#L665-3 assume !(1 == ~main_clk_pos_edge~0); 2574703#L670-3 assume !(1 == ~main_clk_pos_edge~0); 2574697#L675-3 assume !(1 == ~main_in1_ev~0); 2574691#L680-3 assume !(1 == ~main_in2_ev~0); 2574685#L685-3 assume !(1 == ~main_sum_ev~0); 2574680#L690-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2574676#L695-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2574672#L700-3 assume !(1 == ~main_dbl_ev~0); 2574668#L705-3 assume !(1 == ~main_zero_ev~0); 2574664#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2574660#L715-3 assume !(1 == ~main_clk_pos_edge~0); 2574656#L720-3 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 2574652#L725-3 assume !(0 == ~N_generate_st~0); 2574648#L733-2 assume !(0 == ~S1_addsub_st~0); 2574642#L736-2 assume !(0 == ~S2_presdbl_st~0); 2574636#L739-2 assume !(0 == ~S3_zero_st~0); 2574629#L742-2 assume !(0 == ~D_print_st~0); 2574628#start_simulation_returnLabel#2 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 2574617#L803 assume !(5 == main_~count~0#1); 2574612#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2574611#L256-6 assume !(1 == ~main_in1_req_up~0); 2574609#L256-8 assume !(1 == ~main_in2_req_up~0); 2574594#L267-5 assume !(1 == ~main_sum_req_up~0); 2574591#L278-5 assume !(1 == ~main_diff_req_up~0); 2574588#L289-5 assume !(1 == ~main_pres_req_up~0); 2574576#L300-5 assume !(1 == ~main_dbl_req_up~0); 2574577#L311-5 assume !(1 == ~main_zero_req_up~0); 2575236#L322-5 assume !(1 == ~main_clk_req_up~0); 2575234#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2575233#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2575232#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2575231#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2575230#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2575228#L371-5 assume !(0 == ~main_in1_ev~0); 2575226#L376-5 assume !(0 == ~main_in2_ev~0); 2575224#L381-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2575222#L386-5 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2575220#L391-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2575218#L396-5 assume !(0 == ~main_dbl_ev~0); 2575216#L401-5 assume !(0 == ~main_zero_ev~0); 2575214#L406-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2575212#L411-5 assume !(0 == ~main_clk_pos_edge~0); 2575210#L416-5 assume !(0 == ~main_clk_neg_edge~0); 2575208#L421-5 assume !(1 == ~main_clk_pos_edge~0); 2575206#L426-5 assume !(1 == ~main_clk_pos_edge~0); 2575204#L431-5 assume !(1 == ~main_clk_pos_edge~0); 2575202#L436-5 assume !(1 == ~main_clk_pos_edge~0); 2575200#L441-5 assume !(1 == ~main_clk_pos_edge~0); 2575198#L446-5 assume !(1 == ~main_in1_ev~0); 2575196#L451-5 assume !(1 == ~main_in2_ev~0); 2575194#L456-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2575192#L461-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2575190#L466-5 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2575188#L471-5 assume !(1 == ~main_dbl_ev~0); 2575186#L476-5 assume !(1 == ~main_zero_ev~0); 2575184#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2575182#L486-5 assume !(1 == ~main_clk_pos_edge~0); 2575180#L491-5 assume !(1 == ~main_clk_neg_edge~0); 2575178#L742-5 assume !false; 2575176#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2575174#L229-2 assume !false; 2575171#L147-2 assume !(0 == ~N_generate_st~0); 2575167#L151-4 assume !(0 == ~S1_addsub_st~0); 2575163#L154-4 assume !(0 == ~S2_presdbl_st~0); 2575159#L157-4 assume !(0 == ~S3_zero_st~0); 2575154#L160-4 assume !(0 == ~D_print_st~0); 2575150#eval_returnLabel#3 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2575149#L509-6 assume !(1 == ~main_in1_req_up~0); 2575146#L509-8 assume !(1 == ~main_in2_req_up~0); 2575142#L520-5 assume !(1 == ~main_sum_req_up~0); 2575140#L531-5 assume !(1 == ~main_diff_req_up~0); 2575137#L542-5 assume !(1 == ~main_pres_req_up~0); 2575133#L553-5 assume !(1 == ~main_dbl_req_up~0); 2575129#L564-5 assume !(1 == ~main_zero_req_up~0); 2575124#L575-5 assume !(1 == ~main_clk_req_up~0); 2575122#L586-5 start_simulation_~kernel_st~0#1 := 3; 2575120#L605-6 assume !(0 == ~main_in1_ev~0); 2575118#L605-8 assume !(0 == ~main_in2_ev~0); 2575116#L610-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2575114#L615-5 assume !(0 == ~main_diff_ev~0); 2575112#L620-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2575110#L625-5 assume !(0 == ~main_dbl_ev~0); 2575108#L630-5 assume !(0 == ~main_zero_ev~0); 2575106#L635-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2575104#L640-5 assume !(0 == ~main_clk_pos_edge~0); 2575102#L645-5 assume !(0 == ~main_clk_neg_edge~0); 2575100#L650-5 assume !(1 == ~main_clk_pos_edge~0); 2575098#L655-5 assume !(1 == ~main_clk_pos_edge~0); 2575096#L660-5 assume !(1 == ~main_clk_pos_edge~0); 2575094#L665-5 assume !(1 == ~main_clk_pos_edge~0); 2575092#L670-5 assume !(1 == ~main_clk_pos_edge~0); 2575090#L675-5 assume !(1 == ~main_in1_ev~0); 2575088#L680-5 assume !(1 == ~main_in2_ev~0); 2575086#L685-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2575084#L690-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2575082#L695-5 assume !(1 == ~main_pres_ev~0); 2575080#L700-5 assume !(1 == ~main_dbl_ev~0); 2575078#L705-5 assume !(1 == ~main_zero_ev~0); 2575076#L710-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2575074#L715-5 assume !(1 == ~main_clk_pos_edge~0); 2575072#L720-5 assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2; 2575070#L725-5 assume !(0 == ~N_generate_st~0); 2575068#L733-4 assume !(0 == ~S1_addsub_st~0); 2575066#L736-4 assume !(0 == ~S2_presdbl_st~0); 2575064#L739-4 assume !(0 == ~S3_zero_st~0); 2575062#L742-4 assume !(0 == ~D_print_st~0); 2575060#start_simulation_returnLabel#3 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 2575057#L795-2 [2023-11-29 01:23:44,193 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:44,193 INFO L85 PathProgramCache]: Analyzing trace with hash 1683661513, now seen corresponding path program 1 times [2023-11-29 01:23:44,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:44,194 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078923342] [2023-11-29 01:23:44,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:44,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:44,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:44,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:44,278 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:44,278 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1078923342] [2023-11-29 01:23:44,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1078923342] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:44,279 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:44,279 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:23:44,279 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1687693104] [2023-11-29 01:23:44,279 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:44,280 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:23:44,280 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:44,280 INFO L85 PathProgramCache]: Analyzing trace with hash -160574958, now seen corresponding path program 1 times [2023-11-29 01:23:44,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:44,281 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083707333] [2023-11-29 01:23:44,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:44,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:44,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:44,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:44,337 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:44,337 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2083707333] [2023-11-29 01:23:44,337 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2083707333] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:44,337 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:44,337 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:23:44,338 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [66512570] [2023-11-29 01:23:44,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:44,338 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:44,339 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:44,339 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:23:44,339 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:23:44,339 INFO L87 Difference]: Start difference. First operand 38395 states and 55002 transitions. cyclomatic complexity: 16631 Second operand has 4 states, 4 states have (on average 22.25) internal successors, (89), 4 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:44,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:44,703 INFO L93 Difference]: Finished difference Result 38449 states and 54838 transitions. [2023-11-29 01:23:44,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38449 states and 54838 transitions. [2023-11-29 01:23:44,895 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36848 [2023-11-29 01:23:45,021 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38449 states to 38449 states and 54838 transitions. [2023-11-29 01:23:45,021 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38449 [2023-11-29 01:23:45,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38449 [2023-11-29 01:23:45,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38449 states and 54838 transitions. [2023-11-29 01:23:45,067 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:45,067 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38449 states and 54838 transitions. [2023-11-29 01:23:45,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38449 states and 54838 transitions. [2023-11-29 01:23:45,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38449 to 38395. [2023-11-29 01:23:45,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38395 states, 38395 states have (on average 1.425446021617398) internal successors, (54730), 38394 states have internal predecessors, (54730), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:45,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38395 states to 38395 states and 54730 transitions. [2023-11-29 01:23:45,542 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38395 states and 54730 transitions. [2023-11-29 01:23:45,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:23:45,543 INFO L428 stractBuchiCegarLoop]: Abstraction has 38395 states and 54730 transitions. [2023-11-29 01:23:45,543 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-29 01:23:45,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38395 states and 54730 transitions. [2023-11-29 01:23:45,831 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36848 [2023-11-29 01:23:45,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:45,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:45,833 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:45,833 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:45,834 INFO L748 eck$LassoCheckResult]: Stem: 2646412#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2646413#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2646228#L256 assume !(1 == ~main_in1_req_up~0); 2646189#L256-2 assume !(1 == ~main_in2_req_up~0); 2646191#L267-1 assume !(1 == ~main_sum_req_up~0); 2646218#L278-1 assume !(1 == ~main_diff_req_up~0); 2646173#L289-1 assume !(1 == ~main_pres_req_up~0); 2646174#L300-1 assume !(1 == ~main_dbl_req_up~0); 2646270#L311-1 assume !(1 == ~main_zero_req_up~0); 2646700#L322-1 assume !(1 == ~main_clk_req_up~0); 2646701#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2647127#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2647128#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2647210#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2647121#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2647122#L371-1 assume !(0 == ~main_in1_ev~0); 2646253#L376-1 assume !(0 == ~main_in2_ev~0); 2646254#L381-1 assume !(0 == ~main_sum_ev~0); 2646671#L386-1 assume !(0 == ~main_diff_ev~0); 2646695#L391-1 assume !(0 == ~main_pres_ev~0); 2646696#L396-1 assume !(0 == ~main_dbl_ev~0); 2652211#L401-1 assume !(0 == ~main_zero_ev~0); 2652208#L406-1 assume !(0 == ~main_clk_ev~0); 2652205#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2652202#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2652199#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2652196#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2652193#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2652190#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2652187#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2652185#L446-1 assume !(1 == ~main_in1_ev~0); 2652183#L451-1 assume !(1 == ~main_in2_ev~0); 2652181#L456-1 assume !(1 == ~main_sum_ev~0); 2652179#L461-1 assume !(1 == ~main_diff_ev~0); 2652177#L466-1 assume !(1 == ~main_pres_ev~0); 2652175#L471-1 assume !(1 == ~main_dbl_ev~0); 2652173#L476-1 assume !(1 == ~main_zero_ev~0); 2652171#L481-1 assume !(1 == ~main_clk_ev~0); 2652169#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2652167#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2652165#L742-1 assume !false; 2652163#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2652160#L229 assume !false; 2652156#L147 assume !(0 == ~N_generate_st~0); 2652152#L151 assume !(0 == ~S1_addsub_st~0); 2652148#L154 assume !(0 == ~S2_presdbl_st~0); 2652144#L157 assume !(0 == ~S3_zero_st~0); 2652143#L160 assume !(0 == ~D_print_st~0); 2652142#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2652141#L509 assume !(1 == ~main_in1_req_up~0); 2652138#L509-2 assume !(1 == ~main_in2_req_up~0); 2652135#L520-1 assume !(1 == ~main_sum_req_up~0); 2652125#L531-1 assume !(1 == ~main_diff_req_up~0); 2652109#L542-1 assume !(1 == ~main_pres_req_up~0); 2652089#L553-1 assume !(1 == ~main_dbl_req_up~0); 2652078#L564-1 assume !(1 == ~main_zero_req_up~0); 2652071#L575-1 assume !(1 == ~main_clk_req_up~0); 2652065#L586-1 start_simulation_~kernel_st~0#1 := 3; 2652059#L605 assume !(0 == ~main_in1_ev~0); 2652053#L605-2 assume !(0 == ~main_in2_ev~0); 2652047#L610-1 assume !(0 == ~main_sum_ev~0); 2652041#L615-1 assume !(0 == ~main_diff_ev~0); 2652035#L620-1 assume !(0 == ~main_pres_ev~0); 2652029#L625-1 assume !(0 == ~main_dbl_ev~0); 2652023#L630-1 assume !(0 == ~main_zero_ev~0); 2652017#L635-1 assume !(0 == ~main_clk_ev~0); 2652011#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2652005#L645-1 assume !(0 == ~main_clk_neg_edge~0); 2651999#L650-1 assume !(1 == ~main_clk_pos_edge~0); 2651993#L655-1 assume !(1 == ~main_clk_pos_edge~0); 2651987#L660-1 assume !(1 == ~main_clk_pos_edge~0); 2651981#L665-1 assume !(1 == ~main_clk_pos_edge~0); 2651975#L670-1 assume !(1 == ~main_clk_pos_edge~0); 2651969#L675-1 assume !(1 == ~main_in1_ev~0); 2651963#L680-1 assume !(1 == ~main_in2_ev~0); 2651957#L685-1 assume !(1 == ~main_sum_ev~0); 2651951#L690-1 assume !(1 == ~main_diff_ev~0); 2651945#L695-1 assume !(1 == ~main_pres_ev~0); 2651941#L700-1 assume !(1 == ~main_dbl_ev~0); 2651937#L705-1 assume !(1 == ~main_zero_ev~0); 2651932#L710-1 assume !(1 == ~main_clk_ev~0); 2651926#L715-1 assume !(1 == ~main_clk_pos_edge~0); 2651921#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2651916#L725-1 assume !(0 == ~N_generate_st~0); 2651911#L733 assume !(0 == ~S1_addsub_st~0); 2651906#L736 assume !(0 == ~S2_presdbl_st~0); 2651901#L739 assume !(0 == ~S3_zero_st~0); 2651897#L742 assume !(0 == ~D_print_st~0); 2651893#start_simulation_returnLabel#1 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 2651889#L795-2 [2023-11-29 01:23:45,834 INFO L750 eck$LassoCheckResult]: Loop: 2651889#L795-2 assume !false; 2651884#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2651879#L256-3 assume !(1 == ~main_in1_req_up~0); 2651872#L256-5 assume !(1 == ~main_in2_req_up~0); 2651864#L267-3 assume !(1 == ~main_sum_req_up~0); 2651858#L278-3 assume !(1 == ~main_diff_req_up~0); 2651852#L289-3 assume !(1 == ~main_pres_req_up~0); 2651832#L300-3 assume !(1 == ~main_dbl_req_up~0); 2651828#L311-3 assume !(1 == ~main_zero_req_up~0); 2651807#L322-3 assume !(1 == ~main_clk_req_up~0); 2651804#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2651802#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2651800#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2651798#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2651796#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2651794#L371-3 assume !(0 == ~main_in1_ev~0); 2651792#L376-3 assume !(0 == ~main_in2_ev~0); 2651790#L381-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2651788#L386-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2651786#L391-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2651784#L396-3 assume !(0 == ~main_dbl_ev~0); 2651781#L401-3 assume !(0 == ~main_zero_ev~0); 2651779#L406-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2651777#L411-3 assume !(0 == ~main_clk_pos_edge~0); 2651775#L416-3 assume !(0 == ~main_clk_neg_edge~0); 2651773#L421-3 assume !(1 == ~main_clk_pos_edge~0); 2651771#L426-3 assume !(1 == ~main_clk_pos_edge~0); 2651769#L431-3 assume !(1 == ~main_clk_pos_edge~0); 2651767#L436-3 assume !(1 == ~main_clk_pos_edge~0); 2651765#L441-3 assume !(1 == ~main_clk_pos_edge~0); 2651763#L446-3 assume !(1 == ~main_in1_ev~0); 2651756#L451-3 assume !(1 == ~main_in2_ev~0); 2651749#L456-3 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2651744#L461-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2651739#L466-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2651734#L471-3 assume !(1 == ~main_dbl_ev~0); 2651729#L476-3 assume !(1 == ~main_zero_ev~0); 2651725#L481-3 assume !(1 == ~main_clk_ev~0); 2651721#L486-3 assume !(1 == ~main_clk_pos_edge~0); 2651716#L491-3 assume !(1 == ~main_clk_neg_edge~0); 2651711#L742-3 assume !false; 2651707#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2651702#L229-1 assume !false; 2651697#L147-1 assume !(0 == ~N_generate_st~0); 2651692#L151-2 assume !(0 == ~S1_addsub_st~0); 2651687#L154-2 assume !(0 == ~S2_presdbl_st~0); 2651682#L157-2 assume !(0 == ~S3_zero_st~0); 2651677#L160-2 assume !(0 == ~D_print_st~0); 2651671#eval_returnLabel#2 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2651664#L509-3 assume !(1 == ~main_in1_req_up~0); 2651651#L509-5 assume !(1 == ~main_in2_req_up~0); 2651637#L520-3 assume !(1 == ~main_sum_req_up~0); 2651624#L531-3 assume !(1 == ~main_diff_req_up~0); 2651620#L542-3 assume !(1 == ~main_pres_req_up~0); 2651617#L553-3 assume !(1 == ~main_dbl_req_up~0); 2651613#L564-3 assume !(1 == ~main_zero_req_up~0); 2651614#L575-3 assume !(1 == ~main_clk_req_up~0); 2651720#L586-3 start_simulation_~kernel_st~0#1 := 3; 2651715#L605-3 assume !(0 == ~main_in1_ev~0); 2651710#L605-5 assume !(0 == ~main_in2_ev~0); 2651706#L610-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2651701#L615-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2651696#L620-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2651691#L625-3 assume !(0 == ~main_dbl_ev~0); 2651686#L630-3 assume !(0 == ~main_zero_ev~0); 2651681#L635-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2651676#L640-3 assume !(0 == ~main_clk_pos_edge~0); 2651670#L645-3 assume !(0 == ~main_clk_neg_edge~0); 2651663#L650-3 assume !(1 == ~main_clk_pos_edge~0); 2651662#L655-3 assume !(1 == ~main_clk_pos_edge~0); 2651650#L660-3 assume !(1 == ~main_clk_pos_edge~0); 2651648#L665-3 assume !(1 == ~main_clk_pos_edge~0); 2651646#L670-3 assume !(1 == ~main_clk_pos_edge~0); 2651644#L675-3 assume !(1 == ~main_in1_ev~0); 2651633#L680-3 assume !(1 == ~main_in2_ev~0); 2651609#L685-3 assume !(1 == ~main_sum_ev~0); 2651607#L690-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2651605#L695-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2651531#L700-3 assume !(1 == ~main_dbl_ev~0); 2651525#L705-3 assume !(1 == ~main_zero_ev~0); 2651520#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2651516#L715-3 assume !(1 == ~main_clk_pos_edge~0); 2651512#L720-3 assume !(1 == ~main_clk_neg_edge~0); 2651508#L725-3 assume !(0 == ~N_generate_st~0); 2651504#L733-2 assume !(0 == ~S1_addsub_st~0); 2651500#L736-2 assume !(0 == ~S2_presdbl_st~0); 2651496#L739-2 assume !(0 == ~S3_zero_st~0); 2651492#L742-2 assume !(0 == ~D_print_st~0); 2651483#start_simulation_returnLabel#2 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 2651466#L803 assume !(5 == main_~count~0#1); 2651459#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2651458#L256-6 assume !(1 == ~main_in1_req_up~0); 2651445#L256-8 assume !(1 == ~main_in2_req_up~0); 2651428#L267-5 assume !(1 == ~main_sum_req_up~0); 2651425#L278-5 assume !(1 == ~main_diff_req_up~0); 2649970#L289-5 assume !(1 == ~main_pres_req_up~0); 2649969#L300-5 assume !(1 == ~main_dbl_req_up~0); 2649953#L311-5 assume !(1 == ~main_zero_req_up~0); 2649954#L322-5 assume !(1 == ~main_clk_req_up~0); 2652342#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2652341#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2652340#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2652339#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2652338#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2652337#L371-5 assume !(0 == ~main_in1_ev~0); 2652336#L376-5 assume !(0 == ~main_in2_ev~0); 2652335#L381-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2652334#L386-5 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2652332#L391-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2652329#L396-5 assume !(0 == ~main_dbl_ev~0); 2652326#L401-5 assume !(0 == ~main_zero_ev~0); 2652323#L406-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2652320#L411-5 assume !(0 == ~main_clk_pos_edge~0); 2652317#L416-5 assume !(0 == ~main_clk_neg_edge~0); 2652314#L421-5 assume !(1 == ~main_clk_pos_edge~0); 2652311#L426-5 assume !(1 == ~main_clk_pos_edge~0); 2652308#L431-5 assume !(1 == ~main_clk_pos_edge~0); 2652305#L436-5 assume !(1 == ~main_clk_pos_edge~0); 2652302#L441-5 assume !(1 == ~main_clk_pos_edge~0); 2652299#L446-5 assume !(1 == ~main_in1_ev~0); 2652296#L451-5 assume !(1 == ~main_in2_ev~0); 2652293#L456-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2652290#L461-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2652287#L466-5 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2652285#L471-5 assume !(1 == ~main_dbl_ev~0); 2652283#L476-5 assume !(1 == ~main_zero_ev~0); 2652281#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2652279#L486-5 assume !(1 == ~main_clk_pos_edge~0); 2652277#L491-5 assume !(1 == ~main_clk_neg_edge~0); 2652275#L742-5 assume !false; 2652273#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2652271#L229-2 assume !false; 2652269#L147-2 assume !(0 == ~N_generate_st~0); 2652267#L151-4 assume !(0 == ~S1_addsub_st~0); 2652265#L154-4 assume !(0 == ~S2_presdbl_st~0); 2652263#L157-4 assume !(0 == ~S3_zero_st~0); 2652260#L160-4 assume !(0 == ~D_print_st~0); 2652256#eval_returnLabel#3 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2652255#L509-6 assume !(1 == ~main_in1_req_up~0); 2652252#L509-8 assume !(1 == ~main_in2_req_up~0); 2652248#L520-5 assume !(1 == ~main_sum_req_up~0); 2652129#L531-5 assume !(1 == ~main_diff_req_up~0); 2652112#L542-5 assume !(1 == ~main_pres_req_up~0); 2652093#L553-5 assume !(1 == ~main_dbl_req_up~0); 2652081#L564-5 assume !(1 == ~main_zero_req_up~0); 2652072#L575-5 assume !(1 == ~main_clk_req_up~0); 2652066#L586-5 start_simulation_~kernel_st~0#1 := 3; 2652060#L605-6 assume !(0 == ~main_in1_ev~0); 2652054#L605-8 assume !(0 == ~main_in2_ev~0); 2652048#L610-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2652042#L615-5 assume !(0 == ~main_diff_ev~0); 2652036#L620-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2652030#L625-5 assume !(0 == ~main_dbl_ev~0); 2652024#L630-5 assume !(0 == ~main_zero_ev~0); 2652018#L635-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2652012#L640-5 assume !(0 == ~main_clk_pos_edge~0); 2652006#L645-5 assume !(0 == ~main_clk_neg_edge~0); 2652000#L650-5 assume !(1 == ~main_clk_pos_edge~0); 2651994#L655-5 assume !(1 == ~main_clk_pos_edge~0); 2651988#L660-5 assume !(1 == ~main_clk_pos_edge~0); 2651982#L665-5 assume !(1 == ~main_clk_pos_edge~0); 2651976#L670-5 assume !(1 == ~main_clk_pos_edge~0); 2651970#L675-5 assume !(1 == ~main_in1_ev~0); 2651964#L680-5 assume !(1 == ~main_in2_ev~0); 2651958#L685-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2651952#L690-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2651946#L695-5 assume !(1 == ~main_pres_ev~0); 2651942#L700-5 assume !(1 == ~main_dbl_ev~0); 2651938#L705-5 assume !(1 == ~main_zero_ev~0); 2651933#L710-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2651927#L715-5 assume !(1 == ~main_clk_pos_edge~0); 2651922#L720-5 assume !(1 == ~main_clk_neg_edge~0); 2651917#L725-5 assume !(0 == ~N_generate_st~0); 2651912#L733-4 assume !(0 == ~S1_addsub_st~0); 2651907#L736-4 assume !(0 == ~S2_presdbl_st~0); 2651902#L739-4 assume !(0 == ~S3_zero_st~0); 2651898#L742-4 assume !(0 == ~D_print_st~0); 2651894#start_simulation_returnLabel#3 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 2651889#L795-2 [2023-11-29 01:23:45,835 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:45,835 INFO L85 PathProgramCache]: Analyzing trace with hash -836298421, now seen corresponding path program 1 times [2023-11-29 01:23:45,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:45,836 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002700358] [2023-11-29 01:23:45,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:45,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:45,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:45,846 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:45,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:45,872 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:45,872 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:45,873 INFO L85 PathProgramCache]: Analyzing trace with hash -1230168620, now seen corresponding path program 1 times [2023-11-29 01:23:45,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:45,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771611360] [2023-11-29 01:23:45,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:45,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:45,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:45,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:45,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:45,907 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771611360] [2023-11-29 01:23:45,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1771611360] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:45,907 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:45,907 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:23:45,908 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2070564320] [2023-11-29 01:23:45,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:45,908 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:45,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:45,909 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:23:45,909 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:23:45,909 INFO L87 Difference]: Start difference. First operand 38395 states and 54730 transitions. cyclomatic complexity: 16359 Second operand has 3 states, 3 states have (on average 59.333333333333336) internal successors, (178), 3 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:46,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:46,016 INFO L93 Difference]: Finished difference Result 38395 states and 54568 transitions. [2023-11-29 01:23:46,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38395 states and 54568 transitions. [2023-11-29 01:23:46,160 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36848 [2023-11-29 01:23:46,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38395 states to 38395 states and 54568 transitions. [2023-11-29 01:23:46,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38395 [2023-11-29 01:23:46,283 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38395 [2023-11-29 01:23:46,283 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38395 states and 54568 transitions. [2023-11-29 01:23:46,303 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:46,303 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38395 states and 54568 transitions. [2023-11-29 01:23:46,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38395 states and 54568 transitions. [2023-11-29 01:23:46,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38395 to 38395. [2023-11-29 01:23:46,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38395 states, 38395 states have (on average 1.421226722229457) internal successors, (54568), 38394 states have internal predecessors, (54568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:46,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38395 states to 38395 states and 54568 transitions. [2023-11-29 01:23:46,746 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38395 states and 54568 transitions. [2023-11-29 01:23:46,747 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:23:46,747 INFO L428 stractBuchiCegarLoop]: Abstraction has 38395 states and 54568 transitions. [2023-11-29 01:23:46,747 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-29 01:23:46,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38395 states and 54568 transitions. [2023-11-29 01:23:46,846 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36848 [2023-11-29 01:23:46,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:46,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:46,848 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:46,848 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:46,848 INFO L748 eck$LassoCheckResult]: Stem: 2723205#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2723206#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2723023#L256 assume !(1 == ~main_in1_req_up~0); 2722985#L256-2 assume !(1 == ~main_in2_req_up~0); 2722987#L267-1 assume !(1 == ~main_sum_req_up~0); 2723013#L278-1 assume !(1 == ~main_diff_req_up~0); 2722969#L289-1 assume !(1 == ~main_pres_req_up~0); 2722970#L300-1 assume !(1 == ~main_dbl_req_up~0); 2723069#L311-1 assume !(1 == ~main_zero_req_up~0); 2723484#L322-1 assume !(1 == ~main_clk_req_up~0); 2723485#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2723883#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2723884#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2723970#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2723877#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2723878#L371-1 assume !(0 == ~main_in1_ev~0); 2723049#L376-1 assume !(0 == ~main_in2_ev~0); 2723050#L381-1 assume !(0 == ~main_sum_ev~0); 2723211#L386-1 assume !(0 == ~main_diff_ev~0); 2723212#L391-1 assume !(0 == ~main_pres_ev~0); 2723359#L396-1 assume !(0 == ~main_dbl_ev~0); 2723360#L401-1 assume !(0 == ~main_zero_ev~0); 2727099#L406-1 assume !(0 == ~main_clk_ev~0); 2727098#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2727097#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2727096#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2727093#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2727088#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2727082#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2727076#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2727070#L446-1 assume !(1 == ~main_in1_ev~0); 2727063#L451-1 assume !(1 == ~main_in2_ev~0); 2727057#L456-1 assume !(1 == ~main_sum_ev~0); 2727052#L461-1 assume !(1 == ~main_diff_ev~0); 2727025#L466-1 assume !(1 == ~main_pres_ev~0); 2727017#L471-1 assume !(1 == ~main_dbl_ev~0); 2727010#L476-1 assume !(1 == ~main_zero_ev~0); 2727003#L481-1 assume !(1 == ~main_clk_ev~0); 2726997#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2726991#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2726985#L742-1 assume !false; 2726980#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2726975#L229 assume !false; 2726970#L147 assume !(0 == ~N_generate_st~0); 2726965#L151 assume !(0 == ~S1_addsub_st~0); 2726961#L154 assume !(0 == ~S2_presdbl_st~0); 2726957#L157 assume !(0 == ~S3_zero_st~0); 2726953#L160 assume !(0 == ~D_print_st~0); 2726949#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2726945#L509 assume !(1 == ~main_in1_req_up~0); 2726940#L509-2 assume !(1 == ~main_in2_req_up~0); 2726941#L520-1 assume !(1 == ~main_sum_req_up~0); 2727192#L531-1 assume !(1 == ~main_diff_req_up~0); 2727188#L542-1 assume !(1 == ~main_pres_req_up~0); 2727181#L553-1 assume !(1 == ~main_dbl_req_up~0); 2727174#L564-1 assume !(1 == ~main_zero_req_up~0); 2727175#L575-1 assume !(1 == ~main_clk_req_up~0); 2727234#L586-1 start_simulation_~kernel_st~0#1 := 3; 2727233#L605 assume !(0 == ~main_in1_ev~0); 2727232#L605-2 assume !(0 == ~main_in2_ev~0); 2727231#L610-1 assume !(0 == ~main_sum_ev~0); 2727230#L615-1 assume !(0 == ~main_diff_ev~0); 2727229#L620-1 assume !(0 == ~main_pres_ev~0); 2727228#L625-1 assume !(0 == ~main_dbl_ev~0); 2727227#L630-1 assume !(0 == ~main_zero_ev~0); 2727226#L635-1 assume !(0 == ~main_clk_ev~0); 2727225#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2727224#L645-1 assume !(0 == ~main_clk_neg_edge~0); 2727223#L650-1 assume !(1 == ~main_clk_pos_edge~0); 2727222#L655-1 assume !(1 == ~main_clk_pos_edge~0); 2727221#L660-1 assume !(1 == ~main_clk_pos_edge~0); 2727220#L665-1 assume !(1 == ~main_clk_pos_edge~0); 2727219#L670-1 assume !(1 == ~main_clk_pos_edge~0); 2727218#L675-1 assume !(1 == ~main_in1_ev~0); 2727217#L680-1 assume !(1 == ~main_in2_ev~0); 2727216#L685-1 assume !(1 == ~main_sum_ev~0); 2727215#L690-1 assume !(1 == ~main_diff_ev~0); 2727214#L695-1 assume !(1 == ~main_pres_ev~0); 2727213#L700-1 assume !(1 == ~main_dbl_ev~0); 2727212#L705-1 assume !(1 == ~main_zero_ev~0); 2727211#L710-1 assume !(1 == ~main_clk_ev~0); 2727210#L715-1 assume !(1 == ~main_clk_pos_edge~0); 2727209#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2727208#L725-1 assume !(0 == ~N_generate_st~0); 2727207#L733 assume !(0 == ~S1_addsub_st~0); 2727206#L736 assume !(0 == ~S2_presdbl_st~0); 2727205#L739 assume !(0 == ~S3_zero_st~0); 2727204#L742 assume !(0 == ~D_print_st~0); 2727202#start_simulation_returnLabel#1 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 2727200#L795-2 [2023-11-29 01:23:46,848 INFO L750 eck$LassoCheckResult]: Loop: 2727200#L795-2 assume !false; 2727198#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2727104#L256-3 assume !(1 == ~main_in1_req_up~0); 2727105#L256-5 assume !(1 == ~main_in2_req_up~0); 2727931#L267-3 assume !(1 == ~main_sum_req_up~0); 2727925#L278-3 assume !(1 == ~main_diff_req_up~0); 2727918#L289-3 assume !(1 == ~main_pres_req_up~0); 2727911#L300-3 assume !(1 == ~main_dbl_req_up~0); 2727904#L311-3 assume !(1 == ~main_zero_req_up~0); 2727900#L322-3 assume 1 == ~main_clk_req_up~0; 2727894#L334-2 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 2727891#L334-3 ~main_clk_req_up~0 := 0; 2727888#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2727885#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2727882#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2727879#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2727876#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2727873#L371-3 assume !(0 == ~main_in1_ev~0); 2727868#L376-3 assume !(0 == ~main_in2_ev~0); 2727864#L381-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2727860#L386-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2727856#L391-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2727852#L396-3 assume !(0 == ~main_dbl_ev~0); 2727848#L401-3 assume !(0 == ~main_zero_ev~0); 2727844#L406-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2727840#L411-3 assume !(0 == ~main_clk_pos_edge~0); 2727836#L416-3 assume !(0 == ~main_clk_neg_edge~0); 2727832#L421-3 assume !(1 == ~main_clk_pos_edge~0); 2727828#L426-3 assume !(1 == ~main_clk_pos_edge~0); 2727822#L431-3 assume !(1 == ~main_clk_pos_edge~0); 2727816#L436-3 assume !(1 == ~main_clk_pos_edge~0); 2727810#L441-3 assume !(1 == ~main_clk_pos_edge~0); 2727804#L446-3 assume !(1 == ~main_in1_ev~0); 2727798#L451-3 assume !(1 == ~main_in2_ev~0); 2727792#L456-3 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2727786#L461-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2727780#L466-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2727774#L471-3 assume !(1 == ~main_dbl_ev~0); 2727768#L476-3 assume !(1 == ~main_zero_ev~0); 2727763#L481-3 assume !(1 == ~main_clk_ev~0); 2727758#L486-3 assume !(1 == ~main_clk_pos_edge~0); 2727753#L491-3 assume !(1 == ~main_clk_neg_edge~0); 2727748#L742-3 assume !false; 2727743#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2727738#L229-1 assume !false; 2727733#L147-1 assume !(0 == ~N_generate_st~0); 2727728#L151-2 assume !(0 == ~S1_addsub_st~0); 2727724#L154-2 assume !(0 == ~S2_presdbl_st~0); 2727720#L157-2 assume !(0 == ~S3_zero_st~0); 2727716#L160-2 assume !(0 == ~D_print_st~0); 2727712#eval_returnLabel#2 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2727706#L509-3 assume !(1 == ~main_in1_req_up~0); 2727698#L509-5 assume !(1 == ~main_in2_req_up~0); 2727691#L520-3 assume !(1 == ~main_sum_req_up~0); 2727677#L531-3 assume !(1 == ~main_diff_req_up~0); 2727674#L542-3 assume !(1 == ~main_pres_req_up~0); 2727671#L553-3 assume !(1 == ~main_dbl_req_up~0); 2727620#L564-3 assume !(1 == ~main_zero_req_up~0); 2727614#L575-3 assume !(1 == ~main_clk_req_up~0); 2727609#L586-3 start_simulation_~kernel_st~0#1 := 3; 2727606#L605-3 assume !(0 == ~main_in1_ev~0); 2727603#L605-5 assume !(0 == ~main_in2_ev~0); 2727600#L610-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2727597#L615-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2727594#L620-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2727591#L625-3 assume !(0 == ~main_dbl_ev~0); 2727588#L630-3 assume !(0 == ~main_zero_ev~0); 2727585#L635-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2727582#L640-3 assume !(0 == ~main_clk_pos_edge~0); 2727579#L645-3 assume !(0 == ~main_clk_neg_edge~0); 2727576#L650-3 assume !(1 == ~main_clk_pos_edge~0); 2727573#L655-3 assume !(1 == ~main_clk_pos_edge~0); 2727570#L660-3 assume !(1 == ~main_clk_pos_edge~0); 2727567#L665-3 assume !(1 == ~main_clk_pos_edge~0); 2727564#L670-3 assume !(1 == ~main_clk_pos_edge~0); 2727561#L675-3 assume !(1 == ~main_in1_ev~0); 2727558#L680-3 assume !(1 == ~main_in2_ev~0); 2727555#L685-3 assume !(1 == ~main_sum_ev~0); 2727552#L690-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2727549#L695-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2727546#L700-3 assume !(1 == ~main_dbl_ev~0); 2727543#L705-3 assume !(1 == ~main_zero_ev~0); 2727540#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2727537#L715-3 assume !(1 == ~main_clk_pos_edge~0); 2727535#L720-3 assume !(1 == ~main_clk_neg_edge~0); 2727533#L725-3 assume !(0 == ~N_generate_st~0); 2727531#L733-2 assume !(0 == ~S1_addsub_st~0); 2727529#L736-2 assume !(0 == ~S2_presdbl_st~0); 2727527#L739-2 assume !(0 == ~S3_zero_st~0); 2727525#L742-2 assume !(0 == ~D_print_st~0); 2727523#start_simulation_returnLabel#2 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 2727520#L803 assume !(5 == main_~count~0#1); 2727517#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2727513#L256-6 assume !(1 == ~main_in1_req_up~0); 2727509#L256-8 assume !(1 == ~main_in2_req_up~0); 2727504#L267-5 assume !(1 == ~main_sum_req_up~0); 2727498#L278-5 assume !(1 == ~main_diff_req_up~0); 2727492#L289-5 assume !(1 == ~main_pres_req_up~0); 2727485#L300-5 assume !(1 == ~main_dbl_req_up~0); 2727478#L311-5 assume !(1 == ~main_zero_req_up~0); 2727479#L322-5 assume 1 == ~main_clk_req_up~0; 2727869#L334-4 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 2727865#L334-5 ~main_clk_req_up~0 := 0; 2727861#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2727857#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2727853#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2727849#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2727845#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2727841#L371-5 assume !(0 == ~main_in1_ev~0); 2727837#L376-5 assume !(0 == ~main_in2_ev~0); 2727833#L381-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2727829#L386-5 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2727823#L391-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2727817#L396-5 assume !(0 == ~main_dbl_ev~0); 2727811#L401-5 assume !(0 == ~main_zero_ev~0); 2727805#L406-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2727799#L411-5 assume !(0 == ~main_clk_pos_edge~0); 2727793#L416-5 assume !(0 == ~main_clk_neg_edge~0); 2727787#L421-5 assume !(1 == ~main_clk_pos_edge~0); 2727781#L426-5 assume !(1 == ~main_clk_pos_edge~0); 2727775#L431-5 assume !(1 == ~main_clk_pos_edge~0); 2727769#L436-5 assume !(1 == ~main_clk_pos_edge~0); 2727764#L441-5 assume !(1 == ~main_clk_pos_edge~0); 2727759#L446-5 assume !(1 == ~main_in1_ev~0); 2727754#L451-5 assume !(1 == ~main_in2_ev~0); 2727749#L456-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2727744#L461-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2727739#L466-5 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2727734#L471-5 assume !(1 == ~main_dbl_ev~0); 2727729#L476-5 assume !(1 == ~main_zero_ev~0); 2727725#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2727721#L486-5 assume !(1 == ~main_clk_pos_edge~0); 2727717#L491-5 assume !(1 == ~main_clk_neg_edge~0); 2727713#L742-5 assume !false; 2727708#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2727701#L229-2 assume !false; 2727693#L147-2 assume !(0 == ~N_generate_st~0); 2727688#L151-4 assume !(0 == ~S1_addsub_st~0); 2727669#L154-4 assume !(0 == ~S2_presdbl_st~0); 2727666#L157-4 assume !(0 == ~S3_zero_st~0); 2727664#L160-4 assume !(0 == ~D_print_st~0); 2727662#eval_returnLabel#3 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2727660#L509-6 assume !(1 == ~main_in1_req_up~0); 2727656#L509-8 assume !(1 == ~main_in2_req_up~0); 2727657#L520-5 assume !(1 == ~main_sum_req_up~0); 2727645#L531-5 assume !(1 == ~main_diff_req_up~0); 2727386#L542-5 assume !(1 == ~main_pres_req_up~0); 2727385#L553-5 assume !(1 == ~main_dbl_req_up~0); 2727366#L564-5 assume !(1 == ~main_zero_req_up~0); 2727367#L575-5 assume !(1 == ~main_clk_req_up~0); 2727359#L586-5 start_simulation_~kernel_st~0#1 := 3; 2727350#L605-6 assume !(0 == ~main_in1_ev~0); 2727343#L605-8 assume !(0 == ~main_in2_ev~0); 2727338#L610-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2727333#L615-5 assume !(0 == ~main_diff_ev~0); 2727328#L620-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2727323#L625-5 assume !(0 == ~main_dbl_ev~0); 2727318#L630-5 assume !(0 == ~main_zero_ev~0); 2727313#L635-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2727308#L640-5 assume !(0 == ~main_clk_pos_edge~0); 2727304#L645-5 assume !(0 == ~main_clk_neg_edge~0); 2727300#L650-5 assume !(1 == ~main_clk_pos_edge~0); 2727297#L655-5 assume !(1 == ~main_clk_pos_edge~0); 2727294#L660-5 assume !(1 == ~main_clk_pos_edge~0); 2727290#L665-5 assume !(1 == ~main_clk_pos_edge~0); 2727287#L670-5 assume !(1 == ~main_clk_pos_edge~0); 2727283#L675-5 assume !(1 == ~main_in1_ev~0); 2727279#L680-5 assume !(1 == ~main_in2_ev~0); 2727275#L685-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2727271#L690-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2727267#L695-5 assume !(1 == ~main_pres_ev~0); 2727263#L700-5 assume !(1 == ~main_dbl_ev~0); 2727259#L705-5 assume !(1 == ~main_zero_ev~0); 2727255#L710-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2727251#L715-5 assume !(1 == ~main_clk_pos_edge~0); 2727247#L720-5 assume !(1 == ~main_clk_neg_edge~0); 2727244#L725-5 assume !(0 == ~N_generate_st~0); 2727242#L733-4 assume !(0 == ~S1_addsub_st~0); 2727240#L736-4 assume !(0 == ~S2_presdbl_st~0); 2727238#L739-4 assume !(0 == ~S3_zero_st~0); 2727236#L742-4 assume !(0 == ~D_print_st~0); 2727203#start_simulation_returnLabel#3 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 2727200#L795-2 [2023-11-29 01:23:46,849 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:46,849 INFO L85 PathProgramCache]: Analyzing trace with hash -836298421, now seen corresponding path program 2 times [2023-11-29 01:23:46,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:46,849 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070088202] [2023-11-29 01:23:46,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:46,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:46,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:46,859 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:46,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:46,891 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:46,891 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:46,892 INFO L85 PathProgramCache]: Analyzing trace with hash 690367316, now seen corresponding path program 1 times [2023-11-29 01:23:46,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:46,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [423592177] [2023-11-29 01:23:46,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:46,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:46,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:46,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:46,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:46,934 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [423592177] [2023-11-29 01:23:46,934 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [423592177] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:46,934 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:46,934 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:23:46,935 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [33424924] [2023-11-29 01:23:46,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:46,935 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:46,935 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:46,936 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:23:46,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:23:46,936 INFO L87 Difference]: Start difference. First operand 38395 states and 54568 transitions. cyclomatic complexity: 16197 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:47,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:47,121 INFO L93 Difference]: Finished difference Result 50093 states and 69934 transitions. [2023-11-29 01:23:47,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50093 states and 69934 transitions. [2023-11-29 01:23:47,330 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 47876 [2023-11-29 01:23:47,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50093 states to 50093 states and 69934 transitions. [2023-11-29 01:23:47,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50093 [2023-11-29 01:23:47,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50093 [2023-11-29 01:23:47,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50093 states and 69934 transitions. [2023-11-29 01:23:47,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:47,600 INFO L218 hiAutomatonCegarLoop]: Abstraction has 50093 states and 69934 transitions. [2023-11-29 01:23:47,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50093 states and 69934 transitions. [2023-11-29 01:23:47,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50093 to 50093. [2023-11-29 01:23:47,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50093 states, 50093 states have (on average 1.3960832850897331) internal successors, (69934), 50092 states have internal predecessors, (69934), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:48,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50093 states to 50093 states and 69934 transitions. [2023-11-29 01:23:48,008 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50093 states and 69934 transitions. [2023-11-29 01:23:48,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:23:48,009 INFO L428 stractBuchiCegarLoop]: Abstraction has 50093 states and 69934 transitions. [2023-11-29 01:23:48,009 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-29 01:23:48,009 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50093 states and 69934 transitions. [2023-11-29 01:23:48,131 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 47876 [2023-11-29 01:23:48,131 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:48,132 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:48,133 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:48,133 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:48,133 INFO L748 eck$LassoCheckResult]: Stem: 2811698#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2811699#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2811517#L256 assume !(1 == ~main_in1_req_up~0); 2811479#L256-2 assume !(1 == ~main_in2_req_up~0); 2811481#L267-1 assume !(1 == ~main_sum_req_up~0); 2811507#L278-1 assume !(1 == ~main_diff_req_up~0); 2811463#L289-1 assume !(1 == ~main_pres_req_up~0); 2811464#L300-1 assume !(1 == ~main_dbl_req_up~0); 2811560#L311-1 assume !(1 == ~main_zero_req_up~0); 2811989#L322-1 assume !(1 == ~main_clk_req_up~0); 2811990#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2812454#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2812455#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2812506#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2812448#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2812449#L371-1 assume !(0 == ~main_in1_ev~0); 2811543#L376-1 assume !(0 == ~main_in2_ev~0); 2811544#L381-1 assume !(0 == ~main_sum_ev~0); 2811962#L386-1 assume !(0 == ~main_diff_ev~0); 2811982#L391-1 assume !(0 == ~main_pres_ev~0); 2811983#L396-1 assume !(0 == ~main_dbl_ev~0); 2819445#L401-1 assume !(0 == ~main_zero_ev~0); 2819439#L406-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2819435#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2819430#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2819424#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2819418#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2819412#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2819405#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2819398#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2819393#L446-1 assume !(1 == ~main_in1_ev~0); 2819391#L451-1 assume !(1 == ~main_in2_ev~0); 2819388#L456-1 assume !(1 == ~main_sum_ev~0); 2819386#L461-1 assume !(1 == ~main_diff_ev~0); 2819384#L466-1 assume !(1 == ~main_pres_ev~0); 2819382#L471-1 assume !(1 == ~main_dbl_ev~0); 2819380#L476-1 assume !(1 == ~main_zero_ev~0); 2819378#L481-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2819012#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2819013#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2819008#L742-1 assume !false; 2819009#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2819004#L229 assume !false; 2819005#L147 assume !(0 == ~N_generate_st~0); 2819000#L151 assume !(0 == ~S1_addsub_st~0); 2819001#L154 assume !(0 == ~S2_presdbl_st~0); 2818996#L157 assume !(0 == ~S3_zero_st~0); 2818997#L160 assume !(0 == ~D_print_st~0); 2818992#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2818993#L509 assume !(1 == ~main_in1_req_up~0); 2818988#L509-2 assume !(1 == ~main_in2_req_up~0); 2818989#L520-1 assume !(1 == ~main_sum_req_up~0); 2819354#L531-1 assume !(1 == ~main_diff_req_up~0); 2819335#L542-1 assume !(1 == ~main_pres_req_up~0); 2819312#L553-1 assume !(1 == ~main_dbl_req_up~0); 2819282#L564-1 assume !(1 == ~main_zero_req_up~0); 2819280#L575-1 assume !(1 == ~main_clk_req_up~0); 2819278#L586-1 start_simulation_~kernel_st~0#1 := 3; 2819277#L605 assume !(0 == ~main_in1_ev~0); 2819252#L605-2 assume !(0 == ~main_in2_ev~0); 2819250#L610-1 assume !(0 == ~main_sum_ev~0); 2819248#L615-1 assume !(0 == ~main_diff_ev~0); 2819216#L620-1 assume !(0 == ~main_pres_ev~0); 2819214#L625-1 assume !(0 == ~main_dbl_ev~0); 2819177#L630-1 assume !(0 == ~main_zero_ev~0); 2819174#L635-1 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2819172#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2819170#L645-1 assume !(0 == ~main_clk_neg_edge~0); 2819168#L650-1 assume !(1 == ~main_clk_pos_edge~0); 2819131#L655-1 assume !(1 == ~main_clk_pos_edge~0); 2819129#L660-1 assume !(1 == ~main_clk_pos_edge~0); 2819127#L665-1 assume !(1 == ~main_clk_pos_edge~0); 2819125#L670-1 assume !(1 == ~main_clk_pos_edge~0); 2819123#L675-1 assume !(1 == ~main_in1_ev~0); 2819121#L680-1 assume !(1 == ~main_in2_ev~0); 2819119#L685-1 assume !(1 == ~main_sum_ev~0); 2819117#L690-1 assume !(1 == ~main_diff_ev~0); 2819115#L695-1 assume !(1 == ~main_pres_ev~0); 2819113#L700-1 assume !(1 == ~main_dbl_ev~0); 2819037#L705-1 assume !(1 == ~main_zero_ev~0); 2818884#L710-1 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2818881#L715-1 assume !(1 == ~main_clk_pos_edge~0); 2818879#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2818877#L725-1 assume !(0 == ~N_generate_st~0); 2818875#L733 assume !(0 == ~S1_addsub_st~0); 2818873#L736 assume !(0 == ~S2_presdbl_st~0); 2818871#L739 assume !(0 == ~S3_zero_st~0); 2818869#L742 assume !(0 == ~D_print_st~0); 2818758#start_simulation_returnLabel#1 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 2818752#L795-2 [2023-11-29 01:23:48,134 INFO L750 eck$LassoCheckResult]: Loop: 2818752#L795-2 assume !false; 2818747#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2818743#L256-3 assume !(1 == ~main_in1_req_up~0); 2818741#L256-5 assume !(1 == ~main_in2_req_up~0); 2818742#L267-3 assume !(1 == ~main_sum_req_up~0); 2819751#L278-3 assume !(1 == ~main_diff_req_up~0); 2819746#L289-3 assume !(1 == ~main_pres_req_up~0); 2819741#L300-3 assume !(1 == ~main_dbl_req_up~0); 2819735#L311-3 assume !(1 == ~main_zero_req_up~0); 2819731#L322-3 assume 1 == ~main_clk_req_up~0; 2819727#L334-2 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 2819724#L334-3 ~main_clk_req_up~0 := 0; 2819721#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2819718#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2819713#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2819708#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2819703#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2819698#L371-3 assume !(0 == ~main_in1_ev~0); 2819693#L376-3 assume !(0 == ~main_in2_ev~0); 2819688#L381-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2819683#L386-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2819678#L391-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2819673#L396-3 assume !(0 == ~main_dbl_ev~0); 2819670#L401-3 assume !(0 == ~main_zero_ev~0); 2819667#L406-3 assume !(0 == ~main_clk_ev~0); 2819663#L411-3 assume !(0 == ~main_clk_pos_edge~0); 2819659#L416-3 assume !(0 == ~main_clk_neg_edge~0); 2819655#L421-3 assume !(1 == ~main_clk_pos_edge~0); 2819651#L426-3 assume !(1 == ~main_clk_pos_edge~0); 2819648#L431-3 assume !(1 == ~main_clk_pos_edge~0); 2819645#L436-3 assume !(1 == ~main_clk_pos_edge~0); 2819642#L441-3 assume !(1 == ~main_clk_pos_edge~0); 2819639#L446-3 assume !(1 == ~main_in1_ev~0); 2819636#L451-3 assume !(1 == ~main_in2_ev~0); 2819633#L456-3 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2819630#L461-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2819627#L466-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2819622#L471-3 assume !(1 == ~main_dbl_ev~0); 2819619#L476-3 assume !(1 == ~main_zero_ev~0); 2819616#L481-3 assume !(1 == ~main_clk_ev~0); 2819612#L486-3 assume !(1 == ~main_clk_pos_edge~0); 2819605#L491-3 assume !(1 == ~main_clk_neg_edge~0); 2819598#L742-3 assume !false; 2819590#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2819583#L229-1 assume !false; 2819576#L147-1 assume !(0 == ~N_generate_st~0); 2819573#L151-2 assume !(0 == ~S1_addsub_st~0); 2819568#L154-2 assume !(0 == ~S2_presdbl_st~0); 2819565#L157-2 assume !(0 == ~S3_zero_st~0); 2819562#L160-2 assume !(0 == ~D_print_st~0); 2819559#eval_returnLabel#2 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2819555#L509-3 assume !(1 == ~main_in1_req_up~0); 2819550#L509-5 assume !(1 == ~main_in2_req_up~0); 2819546#L520-3 assume !(1 == ~main_sum_req_up~0); 2819541#L531-3 assume !(1 == ~main_diff_req_up~0); 2819535#L542-3 assume !(1 == ~main_pres_req_up~0); 2819530#L553-3 assume !(1 == ~main_dbl_req_up~0); 2819525#L564-3 assume !(1 == ~main_zero_req_up~0); 2819523#L575-3 assume !(1 == ~main_clk_req_up~0); 2819521#L586-3 start_simulation_~kernel_st~0#1 := 3; 2819519#L605-3 assume !(0 == ~main_in1_ev~0); 2819516#L605-5 assume !(0 == ~main_in2_ev~0); 2819514#L610-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2819512#L615-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2819510#L620-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2819508#L625-3 assume !(0 == ~main_dbl_ev~0); 2819506#L630-3 assume !(0 == ~main_zero_ev~0); 2819505#L635-3 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2819503#L640-3 assume !(0 == ~main_clk_pos_edge~0); 2819501#L645-3 assume !(0 == ~main_clk_neg_edge~0); 2819499#L650-3 assume !(1 == ~main_clk_pos_edge~0); 2819497#L655-3 assume !(1 == ~main_clk_pos_edge~0); 2819495#L660-3 assume !(1 == ~main_clk_pos_edge~0); 2819491#L665-3 assume !(1 == ~main_clk_pos_edge~0); 2819487#L670-3 assume !(1 == ~main_clk_pos_edge~0); 2819483#L675-3 assume !(1 == ~main_in1_ev~0); 2819479#L680-3 assume !(1 == ~main_in2_ev~0); 2819475#L685-3 assume !(1 == ~main_sum_ev~0); 2819471#L690-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2819467#L695-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2819463#L700-3 assume !(1 == ~main_dbl_ev~0); 2819460#L705-3 assume !(1 == ~main_zero_ev~0); 2819457#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2819455#L715-3 assume !(1 == ~main_clk_pos_edge~0); 2819453#L720-3 assume !(1 == ~main_clk_neg_edge~0); 2819451#L725-3 assume !(0 == ~N_generate_st~0); 2819450#L733-2 assume !(0 == ~S1_addsub_st~0); 2819449#L736-2 assume !(0 == ~S2_presdbl_st~0); 2819448#L739-2 assume !(0 == ~S3_zero_st~0); 2819447#L742-2 assume !(0 == ~D_print_st~0); 2819446#start_simulation_returnLabel#2 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 2819443#L803 assume !(5 == main_~count~0#1); 2819438#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2819434#L256-6 assume !(1 == ~main_in1_req_up~0); 2819428#L256-8 assume !(1 == ~main_in2_req_up~0); 2819422#L267-5 assume !(1 == ~main_sum_req_up~0); 2819416#L278-5 assume !(1 == ~main_diff_req_up~0); 2819410#L289-5 assume !(1 == ~main_pres_req_up~0); 2819403#L300-5 assume !(1 == ~main_dbl_req_up~0); 2819396#L311-5 assume !(1 == ~main_zero_req_up~0); 2819392#L322-5 assume 1 == ~main_clk_req_up~0; 2819389#L334-4 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 2819387#L334-5 ~main_clk_req_up~0 := 0; 2819385#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2819383#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2819381#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2819379#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2819377#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2819376#L371-5 assume !(0 == ~main_in1_ev~0); 2819375#L376-5 assume !(0 == ~main_in2_ev~0); 2819374#L381-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2819373#L386-5 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2819372#L391-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2819371#L396-5 assume !(0 == ~main_dbl_ev~0); 2819370#L401-5 assume !(0 == ~main_zero_ev~0); 2819368#L406-5 assume !(0 == ~main_clk_ev~0); 2819369#L411-5 assume !(0 == ~main_clk_pos_edge~0); 2819810#L416-5 assume !(0 == ~main_clk_neg_edge~0); 2819807#L421-5 assume !(1 == ~main_clk_pos_edge~0); 2819358#L426-5 assume !(1 == ~main_clk_pos_edge~0); 2819357#L431-5 assume !(1 == ~main_clk_pos_edge~0); 2819343#L436-5 assume !(1 == ~main_clk_pos_edge~0); 2819328#L441-5 assume !(1 == ~main_clk_pos_edge~0); 2819305#L446-5 assume !(1 == ~main_in1_ev~0); 2819303#L451-5 assume !(1 == ~main_in2_ev~0); 2819301#L456-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2819273#L461-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2819272#L466-5 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2819243#L471-5 assume !(1 == ~main_dbl_ev~0); 2819241#L476-5 assume !(1 == ~main_zero_ev~0); 2819211#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2819209#L486-5 assume !(1 == ~main_clk_pos_edge~0); 2819207#L491-5 assume !(1 == ~main_clk_neg_edge~0); 2819205#L742-5 assume !false; 2819166#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2819164#L229-2 assume !false; 2819162#L147-2 assume !(0 == ~N_generate_st~0); 2819111#L151-4 assume !(0 == ~S1_addsub_st~0); 2819109#L154-4 assume !(0 == ~S2_presdbl_st~0); 2819107#L157-4 assume !(0 == ~S3_zero_st~0); 2819105#L160-4 assume !(0 == ~D_print_st~0); 2819103#eval_returnLabel#3 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2819101#L509-6 assume !(1 == ~main_in1_req_up~0); 2819033#L509-8 assume !(1 == ~main_in2_req_up~0); 2819034#L520-5 assume !(1 == ~main_sum_req_up~0); 2819147#L531-5 assume !(1 == ~main_diff_req_up~0); 2819095#L542-5 assume !(1 == ~main_pres_req_up~0); 2819091#L553-5 assume !(1 == ~main_dbl_req_up~0); 2819087#L564-5 assume !(1 == ~main_zero_req_up~0); 2819084#L575-5 assume !(1 == ~main_clk_req_up~0); 2819082#L586-5 start_simulation_~kernel_st~0#1 := 3; 2819080#L605-6 assume !(0 == ~main_in1_ev~0); 2819079#L605-8 assume !(0 == ~main_in2_ev~0); 2819078#L610-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2819076#L615-5 assume !(0 == ~main_diff_ev~0); 2819074#L620-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2819072#L625-5 assume !(0 == ~main_dbl_ev~0); 2819070#L630-5 assume !(0 == ~main_zero_ev~0); 2819067#L635-5 assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1; 2819065#L640-5 assume !(0 == ~main_clk_pos_edge~0); 2819063#L645-5 assume !(0 == ~main_clk_neg_edge~0); 2819061#L650-5 assume !(1 == ~main_clk_pos_edge~0); 2819059#L655-5 assume !(1 == ~main_clk_pos_edge~0); 2819057#L660-5 assume !(1 == ~main_clk_pos_edge~0); 2819055#L665-5 assume !(1 == ~main_clk_pos_edge~0); 2819053#L670-5 assume !(1 == ~main_clk_pos_edge~0); 2819051#L675-5 assume !(1 == ~main_in1_ev~0); 2819048#L680-5 assume !(1 == ~main_in2_ev~0); 2819046#L685-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2819044#L690-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2819042#L695-5 assume !(1 == ~main_pres_ev~0); 2819040#L700-5 assume !(1 == ~main_dbl_ev~0); 2819038#L705-5 assume !(1 == ~main_zero_ev~0); 2818885#L710-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2818882#L715-5 assume !(1 == ~main_clk_pos_edge~0); 2818880#L720-5 assume !(1 == ~main_clk_neg_edge~0); 2818878#L725-5 assume !(0 == ~N_generate_st~0); 2818876#L733-4 assume !(0 == ~S1_addsub_st~0); 2818874#L736-4 assume !(0 == ~S2_presdbl_st~0); 2818872#L739-4 assume !(0 == ~S3_zero_st~0); 2818870#L742-4 assume !(0 == ~D_print_st~0); 2818759#start_simulation_returnLabel#3 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 2818752#L795-2 [2023-11-29 01:23:48,134 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:48,134 INFO L85 PathProgramCache]: Analyzing trace with hash -1704529589, now seen corresponding path program 1 times [2023-11-29 01:23:48,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:48,134 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636057908] [2023-11-29 01:23:48,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:48,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:48,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:48,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:48,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:48,171 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636057908] [2023-11-29 01:23:48,171 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1636057908] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:48,171 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:48,171 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-29 01:23:48,171 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732421320] [2023-11-29 01:23:48,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:48,172 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:23:48,172 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:48,172 INFO L85 PathProgramCache]: Analyzing trace with hash 1573952020, now seen corresponding path program 1 times [2023-11-29 01:23:48,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:48,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027683219] [2023-11-29 01:23:48,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:48,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:48,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:48,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:48,218 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:48,218 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027683219] [2023-11-29 01:23:48,218 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2027683219] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:48,218 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:48,218 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:23:48,218 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [17307422] [2023-11-29 01:23:48,218 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:48,218 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:48,219 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:48,219 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:23:48,219 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:23:48,219 INFO L87 Difference]: Start difference. First operand 50093 states and 69934 transitions. cyclomatic complexity: 19865 Second operand has 4 states, 4 states have (on average 22.25) internal successors, (89), 4 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:48,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:48,439 INFO L93 Difference]: Finished difference Result 51445 states and 71874 transitions. [2023-11-29 01:23:48,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51445 states and 71874 transitions. [2023-11-29 01:23:48,608 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48892 [2023-11-29 01:23:48,713 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51445 states to 51445 states and 71874 transitions. [2023-11-29 01:23:48,714 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51445 [2023-11-29 01:23:48,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51445 [2023-11-29 01:23:48,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51445 states and 71874 transitions. [2023-11-29 01:23:48,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:48,755 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51445 states and 71874 transitions. [2023-11-29 01:23:48,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51445 states and 71874 transitions. [2023-11-29 01:23:49,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51445 to 46347. [2023-11-29 01:23:49,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46347 states, 46347 states have (on average 1.4040606727512028) internal successors, (65074), 46346 states have internal predecessors, (65074), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:49,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46347 states to 46347 states and 65074 transitions. [2023-11-29 01:23:49,426 INFO L240 hiAutomatonCegarLoop]: Abstraction has 46347 states and 65074 transitions. [2023-11-29 01:23:49,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-29 01:23:49,427 INFO L428 stractBuchiCegarLoop]: Abstraction has 46347 states and 65074 transitions. [2023-11-29 01:23:49,427 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-29 01:23:49,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46347 states and 65074 transitions. [2023-11-29 01:23:49,530 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 44800 [2023-11-29 01:23:49,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:49,530 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:49,531 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:49,532 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:49,532 INFO L748 eck$LassoCheckResult]: Stem: 2913245#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 2913246#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2913066#L256 assume !(1 == ~main_in1_req_up~0); 2913027#L256-2 assume !(1 == ~main_in2_req_up~0); 2913029#L267-1 assume !(1 == ~main_sum_req_up~0); 2913056#L278-1 assume !(1 == ~main_diff_req_up~0); 2913011#L289-1 assume !(1 == ~main_pres_req_up~0); 2913012#L300-1 assume !(1 == ~main_dbl_req_up~0); 2913109#L311-1 assume !(1 == ~main_zero_req_up~0); 2913510#L322-1 assume !(1 == ~main_clk_req_up~0); 2913511#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2913801#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2913802#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2913878#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2913795#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2913796#L371-1 assume !(0 == ~main_in1_ev~0); 2913092#L376-1 assume !(0 == ~main_in2_ev~0); 2913093#L381-1 assume !(0 == ~main_sum_ev~0); 2913488#L386-1 assume !(0 == ~main_diff_ev~0); 2913504#L391-1 assume !(0 == ~main_pres_ev~0); 2913505#L396-1 assume !(0 == ~main_dbl_ev~0); 2918081#L401-1 assume !(0 == ~main_zero_ev~0); 2918080#L406-1 assume !(0 == ~main_clk_ev~0); 2918079#L411-1 assume !(0 == ~main_clk_pos_edge~0); 2918078#L416-1 assume !(0 == ~main_clk_neg_edge~0); 2918077#L421-1 assume !(1 == ~main_clk_pos_edge~0); 2918076#L426-1 assume !(1 == ~main_clk_pos_edge~0); 2918075#L431-1 assume !(1 == ~main_clk_pos_edge~0); 2918074#L436-1 assume !(1 == ~main_clk_pos_edge~0); 2918073#L441-1 assume !(1 == ~main_clk_pos_edge~0); 2918072#L446-1 assume !(1 == ~main_in1_ev~0); 2918071#L451-1 assume !(1 == ~main_in2_ev~0); 2918070#L456-1 assume !(1 == ~main_sum_ev~0); 2918069#L461-1 assume !(1 == ~main_diff_ev~0); 2918068#L466-1 assume !(1 == ~main_pres_ev~0); 2918067#L471-1 assume !(1 == ~main_dbl_ev~0); 2918066#L476-1 assume !(1 == ~main_zero_ev~0); 2918065#L481-1 assume !(1 == ~main_clk_ev~0); 2918063#L486-1 assume !(1 == ~main_clk_pos_edge~0); 2918061#L491-1 assume !(1 == ~main_clk_neg_edge~0); 2918059#L742-1 assume !false; 2918057#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2918055#L229 assume !false; 2918053#L147 assume !(0 == ~N_generate_st~0); 2918051#L151 assume !(0 == ~S1_addsub_st~0); 2918049#L154 assume !(0 == ~S2_presdbl_st~0); 2918047#L157 assume !(0 == ~S3_zero_st~0); 2918045#L160 assume !(0 == ~D_print_st~0); 2918043#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2918041#L509 assume !(1 == ~main_in1_req_up~0); 2918037#L509-2 assume !(1 == ~main_in2_req_up~0); 2918033#L520-1 assume !(1 == ~main_sum_req_up~0); 2918028#L531-1 assume !(1 == ~main_diff_req_up~0); 2917987#L542-1 assume !(1 == ~main_pres_req_up~0); 2917958#L553-1 assume !(1 == ~main_dbl_req_up~0); 2917952#L564-1 assume !(1 == ~main_zero_req_up~0); 2917949#L575-1 assume !(1 == ~main_clk_req_up~0); 2917935#L586-1 start_simulation_~kernel_st~0#1 := 3; 2917929#L605 assume !(0 == ~main_in1_ev~0); 2917923#L605-2 assume !(0 == ~main_in2_ev~0); 2917917#L610-1 assume !(0 == ~main_sum_ev~0); 2917911#L615-1 assume !(0 == ~main_diff_ev~0); 2917905#L620-1 assume !(0 == ~main_pres_ev~0); 2917899#L625-1 assume !(0 == ~main_dbl_ev~0); 2917893#L630-1 assume !(0 == ~main_zero_ev~0); 2917887#L635-1 assume !(0 == ~main_clk_ev~0); 2917881#L640-1 assume !(0 == ~main_clk_pos_edge~0); 2917875#L645-1 assume !(0 == ~main_clk_neg_edge~0); 2917869#L650-1 assume !(1 == ~main_clk_pos_edge~0); 2917863#L655-1 assume !(1 == ~main_clk_pos_edge~0); 2917857#L660-1 assume !(1 == ~main_clk_pos_edge~0); 2917851#L665-1 assume !(1 == ~main_clk_pos_edge~0); 2917845#L670-1 assume !(1 == ~main_clk_pos_edge~0); 2917839#L675-1 assume !(1 == ~main_in1_ev~0); 2917833#L680-1 assume !(1 == ~main_in2_ev~0); 2917827#L685-1 assume !(1 == ~main_sum_ev~0); 2917821#L690-1 assume !(1 == ~main_diff_ev~0); 2917817#L695-1 assume !(1 == ~main_pres_ev~0); 2917813#L700-1 assume !(1 == ~main_dbl_ev~0); 2917809#L705-1 assume !(1 == ~main_zero_ev~0); 2917805#L710-1 assume !(1 == ~main_clk_ev~0); 2917801#L715-1 assume !(1 == ~main_clk_pos_edge~0); 2917797#L720-1 assume !(1 == ~main_clk_neg_edge~0); 2917793#L725-1 assume !(0 == ~N_generate_st~0); 2917789#L733 assume !(0 == ~S1_addsub_st~0); 2917785#L736 assume !(0 == ~S2_presdbl_st~0); 2917781#L739 assume !(0 == ~S3_zero_st~0); 2917777#L742 assume !(0 == ~D_print_st~0); 2917773#start_simulation_returnLabel#1 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 2917770#L795-2 [2023-11-29 01:23:49,532 INFO L750 eck$LassoCheckResult]: Loop: 2917770#L795-2 assume !false; 2917767#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2917765#L256-3 assume !(1 == ~main_in1_req_up~0); 2917763#L256-5 assume !(1 == ~main_in2_req_up~0); 2917761#L267-3 assume !(1 == ~main_sum_req_up~0); 2917755#L278-3 assume !(1 == ~main_diff_req_up~0); 2917748#L289-3 assume !(1 == ~main_pres_req_up~0); 2917738#L300-3 assume !(1 == ~main_dbl_req_up~0); 2917728#L311-3 assume !(1 == ~main_zero_req_up~0); 2917718#L322-3 assume 1 == ~main_clk_req_up~0; 2917710#L334-2 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 2917703#L334-3 ~main_clk_req_up~0 := 0; 2917700#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2917695#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2917692#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2917689#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2917686#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2917683#L371-3 assume !(0 == ~main_in1_ev~0); 2917680#L376-3 assume !(0 == ~main_in2_ev~0); 2917677#L381-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2917674#L386-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2917671#L391-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2917668#L396-3 assume !(0 == ~main_dbl_ev~0); 2917665#L401-3 assume !(0 == ~main_zero_ev~0); 2917662#L406-3 assume !(0 == ~main_clk_ev~0); 2917659#L411-3 assume !(0 == ~main_clk_pos_edge~0); 2917656#L416-3 assume !(0 == ~main_clk_neg_edge~0); 2917653#L421-3 assume !(1 == ~main_clk_pos_edge~0); 2917650#L426-3 assume !(1 == ~main_clk_pos_edge~0); 2917647#L431-3 assume !(1 == ~main_clk_pos_edge~0); 2917644#L436-3 assume !(1 == ~main_clk_pos_edge~0); 2917641#L441-3 assume !(1 == ~main_clk_pos_edge~0); 2917638#L446-3 assume !(1 == ~main_in1_ev~0); 2917635#L451-3 assume !(1 == ~main_in2_ev~0); 2917632#L456-3 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2917629#L461-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2917626#L466-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2917624#L471-3 assume !(1 == ~main_dbl_ev~0); 2917622#L476-3 assume !(1 == ~main_zero_ev~0); 2917620#L481-3 assume !(1 == ~main_clk_ev~0); 2917618#L486-3 assume !(1 == ~main_clk_pos_edge~0); 2917616#L491-3 assume !(1 == ~main_clk_neg_edge~0); 2917614#L742-3 assume !false; 2917612#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2917610#L229-1 assume !false; 2917608#L147-1 assume !(0 == ~N_generate_st~0); 2917606#L151-2 assume !(0 == ~S1_addsub_st~0); 2917604#L154-2 assume !(0 == ~S2_presdbl_st~0); 2917602#L157-2 assume !(0 == ~S3_zero_st~0); 2917600#L160-2 assume !(0 == ~D_print_st~0); 2917598#eval_returnLabel#2 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2917596#L509-3 assume !(1 == ~main_in1_req_up~0); 2917593#L509-5 assume !(1 == ~main_in2_req_up~0); 2917594#L520-3 assume !(1 == ~main_sum_req_up~0); 2918302#L531-3 assume !(1 == ~main_diff_req_up~0); 2918297#L542-3 assume !(1 == ~main_pres_req_up~0); 2918290#L553-3 assume !(1 == ~main_dbl_req_up~0); 2918284#L564-3 assume !(1 == ~main_zero_req_up~0); 2918281#L575-3 assume !(1 == ~main_clk_req_up~0); 2918278#L586-3 start_simulation_~kernel_st~0#1 := 3; 2918275#L605-3 assume !(0 == ~main_in1_ev~0); 2918272#L605-5 assume !(0 == ~main_in2_ev~0); 2918269#L610-3 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2918266#L615-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2918263#L620-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2918260#L625-3 assume !(0 == ~main_dbl_ev~0); 2918258#L630-3 assume !(0 == ~main_zero_ev~0); 2918256#L635-3 assume !(0 == ~main_clk_ev~0); 2918254#L640-3 assume !(0 == ~main_clk_pos_edge~0); 2918252#L645-3 assume !(0 == ~main_clk_neg_edge~0); 2918250#L650-3 assume !(1 == ~main_clk_pos_edge~0); 2917530#L655-3 assume !(1 == ~main_clk_pos_edge~0); 2917527#L660-3 assume !(1 == ~main_clk_pos_edge~0); 2917524#L665-3 assume !(1 == ~main_clk_pos_edge~0); 2917521#L670-3 assume !(1 == ~main_clk_pos_edge~0); 2917518#L675-3 assume !(1 == ~main_in1_ev~0); 2917515#L680-3 assume !(1 == ~main_in2_ev~0); 2917512#L685-3 assume !(1 == ~main_sum_ev~0); 2917509#L690-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2917506#L695-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2917504#L700-3 assume !(1 == ~main_dbl_ev~0); 2917502#L705-3 assume !(1 == ~main_zero_ev~0); 2917500#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2917498#L715-3 assume !(1 == ~main_clk_pos_edge~0); 2917496#L720-3 assume !(1 == ~main_clk_neg_edge~0); 2917494#L725-3 assume !(0 == ~N_generate_st~0); 2917492#L733-2 assume !(0 == ~S1_addsub_st~0); 2917490#L736-2 assume !(0 == ~S2_presdbl_st~0); 2917488#L739-2 assume !(0 == ~S3_zero_st~0); 2917486#L742-2 assume !(0 == ~D_print_st~0); 2917484#start_simulation_returnLabel#2 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 2917481#L803 assume !(5 == main_~count~0#1); 2917478#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 2917475#L256-6 assume !(1 == ~main_in1_req_up~0); 2917476#L256-8 assume !(1 == ~main_in2_req_up~0); 2918185#L267-5 assume !(1 == ~main_sum_req_up~0); 2918181#L278-5 assume !(1 == ~main_diff_req_up~0); 2918177#L289-5 assume !(1 == ~main_pres_req_up~0); 2918172#L300-5 assume !(1 == ~main_dbl_req_up~0); 2918168#L311-5 assume !(1 == ~main_zero_req_up~0); 2918152#L322-5 assume 1 == ~main_clk_req_up~0; 2918124#L334-4 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 2918122#L334-5 ~main_clk_req_up~0 := 0; 2918120#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 2918118#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 2918116#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 2918114#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 2918112#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 2918110#L371-5 assume !(0 == ~main_in1_ev~0); 2918108#L376-5 assume !(0 == ~main_in2_ev~0); 2918106#L381-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2918104#L386-5 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 2918102#L391-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2918100#L396-5 assume !(0 == ~main_dbl_ev~0); 2918097#L401-5 assume !(0 == ~main_zero_ev~0); 2918094#L406-5 assume !(0 == ~main_clk_ev~0); 2918093#L411-5 assume !(0 == ~main_clk_pos_edge~0); 2918089#L416-5 assume !(0 == ~main_clk_neg_edge~0); 2918085#L421-5 assume !(1 == ~main_clk_pos_edge~0); 2918084#L426-5 assume !(1 == ~main_clk_pos_edge~0); 2918083#L431-5 assume !(1 == ~main_clk_pos_edge~0); 2918082#L436-5 assume !(1 == ~main_clk_pos_edge~0); 2918064#L441-5 assume !(1 == ~main_clk_pos_edge~0); 2918062#L446-5 assume !(1 == ~main_in1_ev~0); 2918060#L451-5 assume !(1 == ~main_in2_ev~0); 2918058#L456-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2918056#L461-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2918054#L466-5 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 2918052#L471-5 assume !(1 == ~main_dbl_ev~0); 2918050#L476-5 assume !(1 == ~main_zero_ev~0); 2918048#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2918046#L486-5 assume !(1 == ~main_clk_pos_edge~0); 2918044#L491-5 assume !(1 == ~main_clk_neg_edge~0); 2918042#L742-5 assume !false; 2918039#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 2918035#L229-2 assume !false; 2918031#L147-2 assume !(0 == ~N_generate_st~0); 2918027#L151-4 assume !(0 == ~S1_addsub_st~0); 2918026#L154-4 assume !(0 == ~S2_presdbl_st~0); 2918025#L157-4 assume !(0 == ~S3_zero_st~0); 2918024#L160-4 assume !(0 == ~D_print_st~0); 2918023#eval_returnLabel#3 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 2918022#L509-6 assume !(1 == ~main_in1_req_up~0); 2918019#L509-8 assume !(1 == ~main_in2_req_up~0); 2918015#L520-5 assume !(1 == ~main_sum_req_up~0); 2918013#L531-5 assume !(1 == ~main_diff_req_up~0); 2917982#L542-5 assume !(1 == ~main_pres_req_up~0); 2917979#L553-5 assume !(1 == ~main_dbl_req_up~0); 2917955#L564-5 assume !(1 == ~main_zero_req_up~0); 2917950#L575-5 assume !(1 == ~main_clk_req_up~0); 2917936#L586-5 start_simulation_~kernel_st~0#1 := 3; 2917930#L605-6 assume !(0 == ~main_in1_ev~0); 2917924#L605-8 assume !(0 == ~main_in2_ev~0); 2917918#L610-5 assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1; 2917912#L615-5 assume !(0 == ~main_diff_ev~0); 2917906#L620-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 2917900#L625-5 assume !(0 == ~main_dbl_ev~0); 2917894#L630-5 assume !(0 == ~main_zero_ev~0); 2917888#L635-5 assume !(0 == ~main_clk_ev~0); 2917882#L640-5 assume !(0 == ~main_clk_pos_edge~0); 2917876#L645-5 assume !(0 == ~main_clk_neg_edge~0); 2917870#L650-5 assume !(1 == ~main_clk_pos_edge~0); 2917864#L655-5 assume !(1 == ~main_clk_pos_edge~0); 2917858#L660-5 assume !(1 == ~main_clk_pos_edge~0); 2917852#L665-5 assume !(1 == ~main_clk_pos_edge~0); 2917846#L670-5 assume !(1 == ~main_clk_pos_edge~0); 2917840#L675-5 assume !(1 == ~main_in1_ev~0); 2917834#L680-5 assume !(1 == ~main_in2_ev~0); 2917828#L685-5 assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2; 2917822#L690-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 2917818#L695-5 assume !(1 == ~main_pres_ev~0); 2917814#L700-5 assume !(1 == ~main_dbl_ev~0); 2917810#L705-5 assume !(1 == ~main_zero_ev~0); 2917806#L710-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 2917802#L715-5 assume !(1 == ~main_clk_pos_edge~0); 2917798#L720-5 assume !(1 == ~main_clk_neg_edge~0); 2917794#L725-5 assume !(0 == ~N_generate_st~0); 2917790#L733-4 assume !(0 == ~S1_addsub_st~0); 2917786#L736-4 assume !(0 == ~S2_presdbl_st~0); 2917782#L739-4 assume !(0 == ~S3_zero_st~0); 2917778#L742-4 assume !(0 == ~D_print_st~0); 2917774#start_simulation_returnLabel#3 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 2917770#L795-2 [2023-11-29 01:23:49,532 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:49,532 INFO L85 PathProgramCache]: Analyzing trace with hash -836298421, now seen corresponding path program 3 times [2023-11-29 01:23:49,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:49,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780006548] [2023-11-29 01:23:49,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:49,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:49,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:49,543 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:49,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:49,568 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:49,569 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:49,569 INFO L85 PathProgramCache]: Analyzing trace with hash -926096556, now seen corresponding path program 1 times [2023-11-29 01:23:49,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:49,569 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1836974083] [2023-11-29 01:23:49,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:49,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:49,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:49,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:49,616 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:49,616 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1836974083] [2023-11-29 01:23:49,616 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1836974083] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:49,616 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:49,617 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:23:49,617 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1209427716] [2023-11-29 01:23:49,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:49,617 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:49,617 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:49,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:23:49,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:23:49,618 INFO L87 Difference]: Start difference. First operand 46347 states and 65074 transitions. cyclomatic complexity: 18751 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:49,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:49,898 INFO L93 Difference]: Finished difference Result 92683 states and 128236 transitions. [2023-11-29 01:23:49,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 92683 states and 128236 transitions. [2023-11-29 01:23:50,198 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 89600 [2023-11-29 01:23:50,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 92683 states to 92683 states and 128236 transitions. [2023-11-29 01:23:50,408 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 92683 [2023-11-29 01:23:50,770 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 92683 [2023-11-29 01:23:50,770 INFO L73 IsDeterministic]: Start isDeterministic. Operand 92683 states and 128236 transitions. [2023-11-29 01:23:50,788 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:50,788 INFO L218 hiAutomatonCegarLoop]: Abstraction has 92683 states and 128236 transitions. [2023-11-29 01:23:50,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92683 states and 128236 transitions. [2023-11-29 01:23:51,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92683 to 92683. [2023-11-29 01:23:51,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92683 states, 92683 states have (on average 1.3835978550543249) internal successors, (128236), 92682 states have internal predecessors, (128236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:51,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92683 states to 92683 states and 128236 transitions. [2023-11-29 01:23:51,489 INFO L240 hiAutomatonCegarLoop]: Abstraction has 92683 states and 128236 transitions. [2023-11-29 01:23:51,489 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:23:51,490 INFO L428 stractBuchiCegarLoop]: Abstraction has 92683 states and 128236 transitions. [2023-11-29 01:23:51,490 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-29 01:23:51,490 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92683 states and 128236 transitions. [2023-11-29 01:23:51,710 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 89600 [2023-11-29 01:23:51,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:51,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:51,712 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:51,712 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:51,712 INFO L748 eck$LassoCheckResult]: Stem: 3052289#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 3052290#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3052103#L256 assume !(1 == ~main_in1_req_up~0); 3052063#L256-2 assume !(1 == ~main_in2_req_up~0); 3052065#L267-1 assume !(1 == ~main_sum_req_up~0); 3052455#L278-1 assume !(1 == ~main_diff_req_up~0); 3052047#L289-1 assume !(1 == ~main_pres_req_up~0); 3052048#L300-1 assume !(1 == ~main_dbl_req_up~0); 3052148#L311-1 assume !(1 == ~main_zero_req_up~0); 3052578#L322-1 assume !(1 == ~main_clk_req_up~0); 3052579#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3053357#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3053358#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3053417#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3053351#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3053352#L371-1 assume !(0 == ~main_in1_ev~0); 3052131#L376-1 assume !(0 == ~main_in2_ev~0); 3052132#L381-1 assume !(0 == ~main_sum_ev~0); 3053411#L386-1 assume !(0 == ~main_diff_ev~0); 3053412#L391-1 assume !(0 == ~main_pres_ev~0); 3052446#L396-1 assume !(0 == ~main_dbl_ev~0); 3052203#L401-1 assume !(0 == ~main_zero_ev~0); 3052204#L406-1 assume !(0 == ~main_clk_ev~0); 3066991#L411-1 assume !(0 == ~main_clk_pos_edge~0); 3066987#L416-1 assume !(0 == ~main_clk_neg_edge~0); 3066983#L421-1 assume !(1 == ~main_clk_pos_edge~0); 3066979#L426-1 assume !(1 == ~main_clk_pos_edge~0); 3066975#L431-1 assume !(1 == ~main_clk_pos_edge~0); 3066972#L436-1 assume !(1 == ~main_clk_pos_edge~0); 3066969#L441-1 assume !(1 == ~main_clk_pos_edge~0); 3066966#L446-1 assume !(1 == ~main_in1_ev~0); 3066233#L451-1 assume !(1 == ~main_in2_ev~0); 3065585#L456-1 assume !(1 == ~main_sum_ev~0); 3065328#L461-1 assume !(1 == ~main_diff_ev~0); 3065326#L466-1 assume !(1 == ~main_pres_ev~0); 3065324#L471-1 assume !(1 == ~main_dbl_ev~0); 3065321#L476-1 assume !(1 == ~main_zero_ev~0); 3065319#L481-1 assume !(1 == ~main_clk_ev~0); 3065317#L486-1 assume !(1 == ~main_clk_pos_edge~0); 3065315#L491-1 assume !(1 == ~main_clk_neg_edge~0); 3065313#L742-1 assume !false; 3065311#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3065309#L229 assume !false; 3065307#L147 assume !(0 == ~N_generate_st~0); 3065049#L151 assume !(0 == ~S1_addsub_st~0); 3065047#L154 assume !(0 == ~S2_presdbl_st~0); 3065045#L157 assume !(0 == ~S3_zero_st~0); 3065044#L160 assume !(0 == ~D_print_st~0); 3065042#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3065041#L509 assume !(1 == ~main_in1_req_up~0); 3065040#L509-2 assume !(1 == ~main_in2_req_up~0); 3065038#L520-1 assume !(1 == ~main_sum_req_up~0); 3065034#L531-1 assume !(1 == ~main_diff_req_up~0); 3064693#L542-1 assume !(1 == ~main_pres_req_up~0); 3064690#L553-1 assume !(1 == ~main_dbl_req_up~0); 3064523#L564-1 assume !(1 == ~main_zero_req_up~0); 3064520#L575-1 assume !(1 == ~main_clk_req_up~0); 3064340#L586-1 start_simulation_~kernel_st~0#1 := 3; 3064338#L605 assume !(0 == ~main_in1_ev~0); 3064336#L605-2 assume !(0 == ~main_in2_ev~0); 3064334#L610-1 assume !(0 == ~main_sum_ev~0); 3064332#L615-1 assume !(0 == ~main_diff_ev~0); 3064143#L620-1 assume !(0 == ~main_pres_ev~0); 3064141#L625-1 assume !(0 == ~main_dbl_ev~0); 3063993#L630-1 assume !(0 == ~main_zero_ev~0); 3063991#L635-1 assume !(0 == ~main_clk_ev~0); 3063989#L640-1 assume !(0 == ~main_clk_pos_edge~0); 3063987#L645-1 assume !(0 == ~main_clk_neg_edge~0); 3063985#L650-1 assume !(1 == ~main_clk_pos_edge~0); 3063983#L655-1 assume !(1 == ~main_clk_pos_edge~0); 3063981#L660-1 assume !(1 == ~main_clk_pos_edge~0); 3063979#L665-1 assume !(1 == ~main_clk_pos_edge~0); 3063978#L670-1 assume !(1 == ~main_clk_pos_edge~0); 3063977#L675-1 assume !(1 == ~main_in1_ev~0); 3063973#L680-1 assume !(1 == ~main_in2_ev~0); 3063971#L685-1 assume !(1 == ~main_sum_ev~0); 3063967#L690-1 assume !(1 == ~main_diff_ev~0); 3063965#L695-1 assume !(1 == ~main_pres_ev~0); 3063963#L700-1 assume !(1 == ~main_dbl_ev~0); 3063962#L705-1 assume !(1 == ~main_zero_ev~0); 3063961#L710-1 assume !(1 == ~main_clk_ev~0); 3063545#L715-1 assume !(1 == ~main_clk_pos_edge~0); 3063543#L720-1 assume !(1 == ~main_clk_neg_edge~0); 3063541#L725-1 assume !(0 == ~N_generate_st~0); 3063539#L733 assume !(0 == ~S1_addsub_st~0); 3063537#L736 assume !(0 == ~S2_presdbl_st~0); 3063535#L739 assume !(0 == ~S3_zero_st~0); 3063533#L742 assume !(0 == ~D_print_st~0); 3063455#start_simulation_returnLabel#1 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 3063454#L795-2 [2023-11-29 01:23:51,713 INFO L750 eck$LassoCheckResult]: Loop: 3063454#L795-2 assume !false; 3063453#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3063452#L256-3 assume !(1 == ~main_in1_req_up~0); 3063449#L256-5 assume !(1 == ~main_in2_req_up~0); 3063450#L267-3 assume !(1 == ~main_sum_req_up~0); 3063563#L278-3 assume !(1 == ~main_diff_req_up~0); 3063559#L289-3 assume !(1 == ~main_pres_req_up~0); 3063555#L300-3 assume !(1 == ~main_dbl_req_up~0); 3063556#L311-3 assume !(1 == ~main_zero_req_up~0); 3064188#L322-3 assume 1 == ~main_clk_req_up~0; 3064186#L334-2 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 3064184#L334-3 ~main_clk_req_up~0 := 0; 3064183#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3064182#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3064179#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3064177#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3064174#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3064172#L371-3 assume !(0 == ~main_in1_ev~0); 3064170#L376-3 assume !(0 == ~main_in2_ev~0); 3064168#L381-3 assume !(0 == ~main_sum_ev~0); 3064166#L386-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 3064164#L391-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3064162#L396-3 assume !(0 == ~main_dbl_ev~0); 3064160#L401-3 assume !(0 == ~main_zero_ev~0); 3064158#L406-3 assume !(0 == ~main_clk_ev~0); 3064156#L411-3 assume !(0 == ~main_clk_pos_edge~0); 3064154#L416-3 assume !(0 == ~main_clk_neg_edge~0); 3064152#L421-3 assume !(1 == ~main_clk_pos_edge~0); 3064150#L426-3 assume !(1 == ~main_clk_pos_edge~0); 3064148#L431-3 assume !(1 == ~main_clk_pos_edge~0); 3064146#L436-3 assume !(1 == ~main_clk_pos_edge~0); 3064144#L441-3 assume !(1 == ~main_clk_pos_edge~0); 3064142#L446-3 assume !(1 == ~main_in1_ev~0); 3064140#L451-3 assume !(1 == ~main_in2_ev~0); 3063976#L456-3 assume !(1 == ~main_sum_ev~0); 3063972#L461-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 3063968#L466-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 3063966#L471-3 assume !(1 == ~main_dbl_ev~0); 3063964#L476-3 assume !(1 == ~main_zero_ev~0); 3063546#L481-3 assume !(1 == ~main_clk_ev~0); 3063544#L486-3 assume !(1 == ~main_clk_pos_edge~0); 3063542#L491-3 assume !(1 == ~main_clk_neg_edge~0); 3063540#L742-3 assume !false; 3063538#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3063536#L229-1 assume !false; 3063534#L147-1 assume !(0 == ~N_generate_st~0); 3063304#L151-2 assume !(0 == ~S1_addsub_st~0); 3062990#L154-2 assume !(0 == ~S2_presdbl_st~0); 3062986#L157-2 assume !(0 == ~S3_zero_st~0); 3059807#L160-2 assume !(0 == ~D_print_st~0); 3059808#eval_returnLabel#2 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3062978#L509-3 assume !(1 == ~main_in1_req_up~0); 3062976#L509-5 assume !(1 == ~main_in2_req_up~0); 3059792#L520-3 assume !(1 == ~main_sum_req_up~0); 3059794#L531-3 assume !(1 == ~main_diff_req_up~0); 3065706#L542-3 assume !(1 == ~main_pres_req_up~0); 3065703#L553-3 assume !(1 == ~main_dbl_req_up~0); 3065698#L564-3 assume !(1 == ~main_zero_req_up~0); 3065697#L575-3 assume !(1 == ~main_clk_req_up~0); 3065696#L586-3 start_simulation_~kernel_st~0#1 := 3; 3065695#L605-3 assume !(0 == ~main_in1_ev~0); 3065694#L605-5 assume !(0 == ~main_in2_ev~0); 3065693#L610-3 assume !(0 == ~main_sum_ev~0); 3065692#L615-3 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 3065691#L620-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3065690#L625-3 assume !(0 == ~main_dbl_ev~0); 3065689#L630-3 assume !(0 == ~main_zero_ev~0); 3065688#L635-3 assume !(0 == ~main_clk_ev~0); 3065687#L640-3 assume !(0 == ~main_clk_pos_edge~0); 3065686#L645-3 assume !(0 == ~main_clk_neg_edge~0); 3065685#L650-3 assume !(1 == ~main_clk_pos_edge~0); 3065684#L655-3 assume !(1 == ~main_clk_pos_edge~0); 3065683#L660-3 assume !(1 == ~main_clk_pos_edge~0); 3065682#L665-3 assume !(1 == ~main_clk_pos_edge~0); 3065681#L670-3 assume !(1 == ~main_clk_pos_edge~0); 3065680#L675-3 assume !(1 == ~main_in1_ev~0); 3065679#L680-3 assume !(1 == ~main_in2_ev~0); 3065678#L685-3 assume !(1 == ~main_sum_ev~0); 3065399#L690-3 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 3065677#L695-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 3065676#L700-3 assume !(1 == ~main_dbl_ev~0); 3065675#L705-3 assume !(1 == ~main_zero_ev~0); 3065674#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3065673#L715-3 assume !(1 == ~main_clk_pos_edge~0); 3065672#L720-3 assume !(1 == ~main_clk_neg_edge~0); 3065671#L725-3 assume !(0 == ~N_generate_st~0); 3065670#L733-2 assume !(0 == ~S1_addsub_st~0); 3065669#L736-2 assume !(0 == ~S2_presdbl_st~0); 3065668#L739-2 assume !(0 == ~S3_zero_st~0); 3065667#L742-2 assume !(0 == ~D_print_st~0); 3065666#start_simulation_returnLabel#2 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 3065664#L803 assume !(5 == main_~count~0#1); 3065662#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3065661#L256-6 assume !(1 == ~main_in1_req_up~0); 3059058#L256-8 assume !(1 == ~main_in2_req_up~0); 3059053#L267-5 assume !(1 == ~main_sum_req_up~0); 3059054#L278-5 assume !(1 == ~main_diff_req_up~0); 3059266#L289-5 assume !(1 == ~main_pres_req_up~0); 3059265#L300-5 assume !(1 == ~main_dbl_req_up~0); 3065142#L311-5 assume !(1 == ~main_zero_req_up~0); 3065139#L322-5 assume 1 == ~main_clk_req_up~0; 3065135#L334-4 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 3065133#L334-5 ~main_clk_req_up~0 := 0; 3065131#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3065127#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3065124#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3065121#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3065120#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3065116#L371-5 assume !(0 == ~main_in1_ev~0); 3065114#L376-5 assume !(0 == ~main_in2_ev~0); 3065112#L381-5 assume !(0 == ~main_sum_ev~0); 3065110#L386-5 assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1; 3065108#L391-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3065106#L396-5 assume !(0 == ~main_dbl_ev~0); 3065104#L401-5 assume !(0 == ~main_zero_ev~0); 3065102#L406-5 assume !(0 == ~main_clk_ev~0); 3065100#L411-5 assume !(0 == ~main_clk_pos_edge~0); 3065098#L416-5 assume !(0 == ~main_clk_neg_edge~0); 3065096#L421-5 assume !(1 == ~main_clk_pos_edge~0); 3065094#L426-5 assume !(1 == ~main_clk_pos_edge~0); 3065092#L431-5 assume !(1 == ~main_clk_pos_edge~0); 3065090#L436-5 assume !(1 == ~main_clk_pos_edge~0); 3065088#L441-5 assume !(1 == ~main_clk_pos_edge~0); 3065086#L446-5 assume !(1 == ~main_in1_ev~0); 3065084#L451-5 assume !(1 == ~main_in2_ev~0); 3064809#L456-5 assume !(1 == ~main_sum_ev~0); 3064573#L461-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 3064571#L466-5 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 3064569#L471-5 assume !(1 == ~main_dbl_ev~0); 3064566#L476-5 assume !(1 == ~main_zero_ev~0); 3064562#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3064560#L486-5 assume !(1 == ~main_clk_pos_edge~0); 3064558#L491-5 assume !(1 == ~main_clk_neg_edge~0); 3064556#L742-5 assume !false; 3064554#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3064552#L229-2 assume !false; 3064550#L147-2 assume !(0 == ~N_generate_st~0); 3064548#L151-4 assume !(0 == ~S1_addsub_st~0); 3064546#L154-4 assume !(0 == ~S2_presdbl_st~0); 3064544#L157-4 assume !(0 == ~S3_zero_st~0); 3064362#L160-4 assume !(0 == ~D_print_st~0); 3064360#eval_returnLabel#3 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3064358#L509-6 assume !(1 == ~main_in1_req_up~0); 3064356#L509-8 assume !(1 == ~main_in2_req_up~0); 3064353#L520-5 assume !(1 == ~main_sum_req_up~0); 3064354#L531-5 assume !(1 == ~main_diff_req_up~0); 3064263#L542-5 assume !(1 == ~main_pres_req_up~0); 3064259#L553-5 assume !(1 == ~main_dbl_req_up~0); 3064036#L564-5 assume !(1 == ~main_zero_req_up~0); 3064033#L575-5 assume !(1 == ~main_clk_req_up~0); 3064031#L586-5 start_simulation_~kernel_st~0#1 := 3; 3064029#L605-6 assume !(0 == ~main_in1_ev~0); 3064027#L605-8 assume !(0 == ~main_in2_ev~0); 3064025#L610-5 assume !(0 == ~main_sum_ev~0); 3064023#L615-5 assume !(0 == ~main_diff_ev~0); 3064021#L620-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3063884#L625-5 assume !(0 == ~main_dbl_ev~0); 3063881#L630-5 assume !(0 == ~main_zero_ev~0); 3063877#L635-5 assume !(0 == ~main_clk_ev~0); 3063875#L640-5 assume !(0 == ~main_clk_pos_edge~0); 3063873#L645-5 assume !(0 == ~main_clk_neg_edge~0); 3063872#L650-5 assume !(1 == ~main_clk_pos_edge~0); 3063870#L655-5 assume !(1 == ~main_clk_pos_edge~0); 3063869#L660-5 assume !(1 == ~main_clk_pos_edge~0); 3063867#L665-5 assume !(1 == ~main_clk_pos_edge~0); 3063866#L670-5 assume !(1 == ~main_clk_pos_edge~0); 3063865#L675-5 assume !(1 == ~main_in1_ev~0); 3063864#L680-5 assume !(1 == ~main_in2_ev~0); 3063862#L685-5 assume !(1 == ~main_sum_ev~0); 3063704#L690-5 assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2; 3063860#L695-5 assume !(1 == ~main_pres_ev~0); 3063859#L700-5 assume !(1 == ~main_dbl_ev~0); 3063858#L705-5 assume !(1 == ~main_zero_ev~0); 3063854#L710-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3063852#L715-5 assume !(1 == ~main_clk_pos_edge~0); 3063849#L720-5 assume !(1 == ~main_clk_neg_edge~0); 3063847#L725-5 assume !(0 == ~N_generate_st~0); 3063845#L733-4 assume !(0 == ~S1_addsub_st~0); 3063843#L736-4 assume !(0 == ~S2_presdbl_st~0); 3063841#L739-4 assume !(0 == ~S3_zero_st~0); 3063458#L742-4 assume !(0 == ~D_print_st~0); 3063456#start_simulation_returnLabel#3 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 3063454#L795-2 [2023-11-29 01:23:51,713 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:51,713 INFO L85 PathProgramCache]: Analyzing trace with hash -836298421, now seen corresponding path program 4 times [2023-11-29 01:23:51,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:51,713 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934075034] [2023-11-29 01:23:51,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:51,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:51,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:51,721 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:51,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:51,752 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:51,753 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:51,753 INFO L85 PathProgramCache]: Analyzing trace with hash -71918254, now seen corresponding path program 1 times [2023-11-29 01:23:51,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:51,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308335440] [2023-11-29 01:23:51,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:51,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:51,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:51,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:51,801 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:51,802 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [308335440] [2023-11-29 01:23:51,802 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [308335440] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:51,802 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:51,802 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:23:51,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [17131843] [2023-11-29 01:23:51,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:51,802 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:51,803 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:51,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:23:51,803 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:23:51,803 INFO L87 Difference]: Start difference. First operand 92683 states and 128236 transitions. cyclomatic complexity: 35577 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:52,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:52,640 INFO L93 Difference]: Finished difference Result 185343 states and 252645 transitions. [2023-11-29 01:23:52,640 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 185343 states and 252645 transitions. [2023-11-29 01:23:53,191 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 179200 [2023-11-29 01:23:53,551 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 185343 states to 185343 states and 252645 transitions. [2023-11-29 01:23:53,551 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 185343 [2023-11-29 01:23:53,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 185343 [2023-11-29 01:23:53,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 185343 states and 252645 transitions. [2023-11-29 01:23:54,087 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:23:54,087 INFO L218 hiAutomatonCegarLoop]: Abstraction has 185343 states and 252645 transitions. [2023-11-29 01:23:54,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 185343 states and 252645 transitions. [2023-11-29 01:23:55,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 185343 to 185343. [2023-11-29 01:23:55,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 185343 states, 185343 states have (on average 1.3631213479872453) internal successors, (252645), 185342 states have internal predecessors, (252645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:55,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185343 states to 185343 states and 252645 transitions. [2023-11-29 01:23:55,769 INFO L240 hiAutomatonCegarLoop]: Abstraction has 185343 states and 252645 transitions. [2023-11-29 01:23:55,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:23:55,770 INFO L428 stractBuchiCegarLoop]: Abstraction has 185343 states and 252645 transitions. [2023-11-29 01:23:55,770 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2023-11-29 01:23:55,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 185343 states and 252645 transitions. [2023-11-29 01:23:56,234 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 179200 [2023-11-29 01:23:56,235 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:23:56,235 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:23:56,237 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:56,237 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:23:56,237 INFO L748 eck$LassoCheckResult]: Stem: 3330327#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 3330328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3330136#L256 assume !(1 == ~main_in1_req_up~0); 3330095#L256-2 assume !(1 == ~main_in2_req_up~0); 3330097#L267-1 assume !(1 == ~main_sum_req_up~0); 3330509#L278-1 assume !(1 == ~main_diff_req_up~0); 3330079#L289-1 assume !(1 == ~main_pres_req_up~0); 3330080#L300-1 assume !(1 == ~main_dbl_req_up~0); 3330183#L311-1 assume !(1 == ~main_zero_req_up~0); 3330641#L322-1 assume !(1 == ~main_clk_req_up~0); 3330642#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3330321#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3330322#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3332158#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3330659#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3330660#L371-1 assume !(0 == ~main_in1_ev~0); 3330163#L376-1 assume !(0 == ~main_in2_ev~0); 3330164#L381-1 assume !(0 == ~main_sum_ev~0); 3332157#L386-1 assume !(0 == ~main_diff_ev~0); 3332153#L391-1 assume !(0 == ~main_pres_ev~0); 3332154#L396-1 assume !(0 == ~main_dbl_ev~0); 3339777#L401-1 assume !(0 == ~main_zero_ev~0); 3339776#L406-1 assume !(0 == ~main_clk_ev~0); 3339774#L411-1 assume !(0 == ~main_clk_pos_edge~0); 3339772#L416-1 assume !(0 == ~main_clk_neg_edge~0); 3339770#L421-1 assume !(1 == ~main_clk_pos_edge~0); 3339768#L426-1 assume !(1 == ~main_clk_pos_edge~0); 3339766#L431-1 assume !(1 == ~main_clk_pos_edge~0); 3339764#L436-1 assume !(1 == ~main_clk_pos_edge~0); 3339762#L441-1 assume !(1 == ~main_clk_pos_edge~0); 3339758#L446-1 assume !(1 == ~main_in1_ev~0); 3339754#L451-1 assume !(1 == ~main_in2_ev~0); 3339750#L456-1 assume !(1 == ~main_sum_ev~0); 3339744#L461-1 assume !(1 == ~main_diff_ev~0); 3339737#L466-1 assume !(1 == ~main_pres_ev~0); 3339739#L471-1 assume !(1 == ~main_dbl_ev~0); 3339736#L476-1 assume !(1 == ~main_zero_ev~0); 3339731#L481-1 assume !(1 == ~main_clk_ev~0); 3339726#L486-1 assume !(1 == ~main_clk_pos_edge~0); 3339722#L491-1 assume !(1 == ~main_clk_neg_edge~0); 3339718#L742-1 assume !false; 3339714#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3339710#L229 assume !false; 3339706#L147 assume !(0 == ~N_generate_st~0); 3339702#L151 assume !(0 == ~S1_addsub_st~0); 3339698#L154 assume !(0 == ~S2_presdbl_st~0); 3339694#L157 assume !(0 == ~S3_zero_st~0); 3339690#L160 assume !(0 == ~D_print_st~0); 3339686#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3339682#L509 assume !(1 == ~main_in1_req_up~0); 3339676#L509-2 assume !(1 == ~main_in2_req_up~0); 3339669#L520-1 assume !(1 == ~main_sum_req_up~0); 3339670#L531-1 assume !(1 == ~main_diff_req_up~0); 3339850#L542-1 assume !(1 == ~main_pres_req_up~0); 3339939#L553-1 assume !(1 == ~main_dbl_req_up~0); 3339931#L564-1 assume !(1 == ~main_zero_req_up~0); 3339926#L575-1 assume !(1 == ~main_clk_req_up~0); 3339924#L586-1 start_simulation_~kernel_st~0#1 := 3; 3339922#L605 assume !(0 == ~main_in1_ev~0); 3339920#L605-2 assume !(0 == ~main_in2_ev~0); 3339918#L610-1 assume !(0 == ~main_sum_ev~0); 3339916#L615-1 assume !(0 == ~main_diff_ev~0); 3339914#L620-1 assume !(0 == ~main_pres_ev~0); 3339912#L625-1 assume !(0 == ~main_dbl_ev~0); 3339910#L630-1 assume !(0 == ~main_zero_ev~0); 3339908#L635-1 assume !(0 == ~main_clk_ev~0); 3339906#L640-1 assume !(0 == ~main_clk_pos_edge~0); 3339904#L645-1 assume !(0 == ~main_clk_neg_edge~0); 3339902#L650-1 assume !(1 == ~main_clk_pos_edge~0); 3339900#L655-1 assume !(1 == ~main_clk_pos_edge~0); 3339898#L660-1 assume !(1 == ~main_clk_pos_edge~0); 3339896#L665-1 assume !(1 == ~main_clk_pos_edge~0); 3339894#L670-1 assume !(1 == ~main_clk_pos_edge~0); 3339892#L675-1 assume !(1 == ~main_in1_ev~0); 3339890#L680-1 assume !(1 == ~main_in2_ev~0); 3339888#L685-1 assume !(1 == ~main_sum_ev~0); 3339885#L690-1 assume !(1 == ~main_diff_ev~0); 3339815#L695-1 assume !(1 == ~main_pres_ev~0); 3339884#L700-1 assume !(1 == ~main_dbl_ev~0); 3339883#L705-1 assume !(1 == ~main_zero_ev~0); 3339882#L710-1 assume !(1 == ~main_clk_ev~0); 3339881#L715-1 assume !(1 == ~main_clk_pos_edge~0); 3339880#L720-1 assume !(1 == ~main_clk_neg_edge~0); 3339879#L725-1 assume !(0 == ~N_generate_st~0); 3339878#L733 assume !(0 == ~S1_addsub_st~0); 3339877#L736 assume !(0 == ~S2_presdbl_st~0); 3339876#L739 assume !(0 == ~S3_zero_st~0); 3339875#L742 assume !(0 == ~D_print_st~0); 3339873#start_simulation_returnLabel#1 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 3339868#L795-2 [2023-11-29 01:23:56,237 INFO L750 eck$LassoCheckResult]: Loop: 3339868#L795-2 assume !false; 3339863#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3339858#L256-3 assume !(1 == ~main_in1_req_up~0); 3339859#L256-5 assume !(1 == ~main_in2_req_up~0); 3339584#L267-3 assume !(1 == ~main_sum_req_up~0); 3350837#L278-3 assume !(1 == ~main_diff_req_up~0); 3350833#L289-3 assume !(1 == ~main_pres_req_up~0); 3350596#L300-3 assume !(1 == ~main_dbl_req_up~0); 3350592#L311-3 assume !(1 == ~main_zero_req_up~0); 3350589#L322-3 assume 1 == ~main_clk_req_up~0; 3350586#L334-2 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 3350584#L334-3 ~main_clk_req_up~0 := 0; 3350582#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3350580#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3350578#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3350576#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3350574#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3350572#L371-3 assume !(0 == ~main_in1_ev~0); 3350570#L376-3 assume !(0 == ~main_in2_ev~0); 3350568#L381-3 assume !(0 == ~main_sum_ev~0); 3350566#L386-3 assume !(0 == ~main_diff_ev~0); 3350564#L391-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3350562#L396-3 assume !(0 == ~main_dbl_ev~0); 3350560#L401-3 assume !(0 == ~main_zero_ev~0); 3350558#L406-3 assume !(0 == ~main_clk_ev~0); 3350556#L411-3 assume !(0 == ~main_clk_pos_edge~0); 3350554#L416-3 assume !(0 == ~main_clk_neg_edge~0); 3350552#L421-3 assume !(1 == ~main_clk_pos_edge~0); 3350550#L426-3 assume !(1 == ~main_clk_pos_edge~0); 3350548#L431-3 assume !(1 == ~main_clk_pos_edge~0); 3350547#L436-3 assume !(1 == ~main_clk_pos_edge~0); 3350545#L441-3 assume !(1 == ~main_clk_pos_edge~0); 3350543#L446-3 assume !(1 == ~main_in1_ev~0); 3350541#L451-3 assume !(1 == ~main_in2_ev~0); 3350539#L456-3 assume !(1 == ~main_sum_ev~0); 3350274#L461-3 assume !(1 == ~main_diff_ev~0); 3350485#L466-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 3350535#L471-3 assume !(1 == ~main_dbl_ev~0); 3350533#L476-3 assume !(1 == ~main_zero_ev~0); 3350531#L481-3 assume !(1 == ~main_clk_ev~0); 3350529#L486-3 assume !(1 == ~main_clk_pos_edge~0); 3350527#L491-3 assume !(1 == ~main_clk_neg_edge~0); 3350525#L742-3 assume !false; 3350523#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3350521#L229-1 assume !false; 3350519#L147-1 assume !(0 == ~N_generate_st~0); 3350438#L151-2 assume !(0 == ~S1_addsub_st~0); 3350340#L154-2 assume !(0 == ~S2_presdbl_st~0); 3350338#L157-2 assume !(0 == ~S3_zero_st~0); 3336572#L160-2 assume !(0 == ~D_print_st~0); 3336568#eval_returnLabel#2 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3336569#L509-3 assume !(1 == ~main_in1_req_up~0); 3350328#L509-5 assume !(1 == ~main_in2_req_up~0); 3350329#L520-3 assume !(1 == ~main_sum_req_up~0); 3351678#L531-3 assume !(1 == ~main_diff_req_up~0); 3336520#L542-3 assume !(1 == ~main_pres_req_up~0); 3336514#L553-3 assume !(1 == ~main_dbl_req_up~0); 3336490#L564-3 assume !(1 == ~main_zero_req_up~0); 3336466#L575-3 assume !(1 == ~main_clk_req_up~0); 3336454#L586-3 start_simulation_~kernel_st~0#1 := 3; 3336446#L605-3 assume !(0 == ~main_in1_ev~0); 3336442#L605-5 assume !(0 == ~main_in2_ev~0); 3336438#L610-3 assume !(0 == ~main_sum_ev~0); 3336434#L615-3 assume !(0 == ~main_diff_ev~0); 3336430#L620-3 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3336426#L625-3 assume !(0 == ~main_dbl_ev~0); 3336422#L630-3 assume !(0 == ~main_zero_ev~0); 3336418#L635-3 assume !(0 == ~main_clk_ev~0); 3336414#L640-3 assume !(0 == ~main_clk_pos_edge~0); 3336410#L645-3 assume !(0 == ~main_clk_neg_edge~0); 3336406#L650-3 assume !(1 == ~main_clk_pos_edge~0); 3336402#L655-3 assume !(1 == ~main_clk_pos_edge~0); 3336398#L660-3 assume !(1 == ~main_clk_pos_edge~0); 3336394#L665-3 assume !(1 == ~main_clk_pos_edge~0); 3336390#L670-3 assume !(1 == ~main_clk_pos_edge~0); 3336386#L675-3 assume !(1 == ~main_in1_ev~0); 3336382#L680-3 assume !(1 == ~main_in2_ev~0); 3336378#L685-3 assume !(1 == ~main_sum_ev~0); 3336367#L690-3 assume !(1 == ~main_diff_ev~0); 3336368#L695-3 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 3336361#L700-3 assume !(1 == ~main_dbl_ev~0); 3336356#L705-3 assume !(1 == ~main_zero_ev~0); 3336352#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3336348#L715-3 assume !(1 == ~main_clk_pos_edge~0); 3336344#L720-3 assume !(1 == ~main_clk_neg_edge~0); 3336340#L725-3 assume !(0 == ~N_generate_st~0); 3336336#L733-2 assume !(0 == ~S1_addsub_st~0); 3336331#L736-2 assume !(0 == ~S2_presdbl_st~0); 3336326#L739-2 assume !(0 == ~S3_zero_st~0); 3336321#L742-2 assume !(0 == ~D_print_st~0); 3336315#start_simulation_returnLabel#2 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 3336316#L803 assume !(5 == main_~count~0#1); 3351431#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3351429#L256-6 assume !(1 == ~main_in1_req_up~0); 3351427#L256-8 assume !(1 == ~main_in2_req_up~0); 3351424#L267-5 assume !(1 == ~main_sum_req_up~0); 3351420#L278-5 assume !(1 == ~main_diff_req_up~0); 3351416#L289-5 assume !(1 == ~main_pres_req_up~0); 3351412#L300-5 assume !(1 == ~main_dbl_req_up~0); 3351408#L311-5 assume !(1 == ~main_zero_req_up~0); 3351405#L322-5 assume 1 == ~main_clk_req_up~0; 3351402#L334-4 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 3351400#L334-5 ~main_clk_req_up~0 := 0; 3351398#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3351396#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3351393#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3351390#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3351386#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3351384#L371-5 assume !(0 == ~main_in1_ev~0); 3351382#L376-5 assume !(0 == ~main_in2_ev~0); 3351380#L381-5 assume !(0 == ~main_sum_ev~0); 3351378#L386-5 assume !(0 == ~main_diff_ev~0); 3351376#L391-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3351374#L396-5 assume !(0 == ~main_dbl_ev~0); 3351372#L401-5 assume !(0 == ~main_zero_ev~0); 3351370#L406-5 assume !(0 == ~main_clk_ev~0); 3351368#L411-5 assume !(0 == ~main_clk_pos_edge~0); 3351366#L416-5 assume !(0 == ~main_clk_neg_edge~0); 3351270#L421-5 assume !(1 == ~main_clk_pos_edge~0); 3351269#L426-5 assume !(1 == ~main_clk_pos_edge~0); 3351267#L431-5 assume !(1 == ~main_clk_pos_edge~0); 3351265#L436-5 assume !(1 == ~main_clk_pos_edge~0); 3351263#L441-5 assume !(1 == ~main_clk_pos_edge~0); 3351261#L446-5 assume !(1 == ~main_in1_ev~0); 3351260#L451-5 assume !(1 == ~main_in2_ev~0); 3351259#L456-5 assume !(1 == ~main_sum_ev~0); 3351256#L461-5 assume !(1 == ~main_diff_ev~0); 3351005#L466-5 assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2; 3351254#L471-5 assume !(1 == ~main_dbl_ev~0); 3351253#L476-5 assume !(1 == ~main_zero_ev~0); 3351251#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3351250#L486-5 assume !(1 == ~main_clk_pos_edge~0); 3351249#L491-5 assume !(1 == ~main_clk_neg_edge~0); 3351248#L742-5 assume !false; 3351244#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3351240#L229-2 assume !false; 3351239#L147-2 assume !(0 == ~N_generate_st~0); 3351237#L151-4 assume !(0 == ~S1_addsub_st~0); 3351236#L154-4 assume !(0 == ~S2_presdbl_st~0); 3351235#L157-4 assume !(0 == ~S3_zero_st~0); 3340210#L160-4 assume !(0 == ~D_print_st~0); 3340206#eval_returnLabel#3 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3340202#L509-6 assume !(1 == ~main_in1_req_up~0); 3340203#L509-8 assume !(1 == ~main_in2_req_up~0); 3340192#L520-5 assume !(1 == ~main_sum_req_up~0); 3340193#L531-5 assume !(1 == ~main_diff_req_up~0); 3340226#L542-5 assume !(1 == ~main_pres_req_up~0); 3340152#L553-5 assume !(1 == ~main_dbl_req_up~0); 3340149#L564-5 assume !(1 == ~main_zero_req_up~0); 3340146#L575-5 assume !(1 == ~main_clk_req_up~0); 3340141#L586-5 start_simulation_~kernel_st~0#1 := 3; 3340136#L605-6 assume !(0 == ~main_in1_ev~0); 3340112#L605-8 assume !(0 == ~main_in2_ev~0); 3340099#L610-5 assume !(0 == ~main_sum_ev~0); 3340090#L615-5 assume !(0 == ~main_diff_ev~0); 3340081#L620-5 assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1; 3340072#L625-5 assume !(0 == ~main_dbl_ev~0); 3340066#L630-5 assume !(0 == ~main_zero_ev~0); 3340062#L635-5 assume !(0 == ~main_clk_ev~0); 3340058#L640-5 assume !(0 == ~main_clk_pos_edge~0); 3340054#L645-5 assume !(0 == ~main_clk_neg_edge~0); 3340050#L650-5 assume !(1 == ~main_clk_pos_edge~0); 3340046#L655-5 assume !(1 == ~main_clk_pos_edge~0); 3340042#L660-5 assume !(1 == ~main_clk_pos_edge~0); 3340038#L665-5 assume !(1 == ~main_clk_pos_edge~0); 3340033#L670-5 assume !(1 == ~main_clk_pos_edge~0); 3340028#L675-5 assume !(1 == ~main_in1_ev~0); 3340023#L680-5 assume !(1 == ~main_in2_ev~0); 3340018#L685-5 assume !(1 == ~main_sum_ev~0); 3340012#L690-5 assume !(1 == ~main_diff_ev~0); 3339995#L695-5 assume !(1 == ~main_pres_ev~0); 3340005#L700-5 assume !(1 == ~main_dbl_ev~0); 3340000#L705-5 assume !(1 == ~main_zero_ev~0); 3339996#L710-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3339992#L715-5 assume !(1 == ~main_clk_pos_edge~0); 3339988#L720-5 assume !(1 == ~main_clk_neg_edge~0); 3339984#L725-5 assume !(0 == ~N_generate_st~0); 3339978#L733-4 assume !(0 == ~S1_addsub_st~0); 3339973#L736-4 assume !(0 == ~S2_presdbl_st~0); 3339968#L739-4 assume !(0 == ~S3_zero_st~0); 3339963#L742-4 assume !(0 == ~D_print_st~0); 3339874#start_simulation_returnLabel#3 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 3339868#L795-2 [2023-11-29 01:23:56,238 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:56,238 INFO L85 PathProgramCache]: Analyzing trace with hash -836298421, now seen corresponding path program 5 times [2023-11-29 01:23:56,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:56,238 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472999473] [2023-11-29 01:23:56,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:56,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:56,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:56,249 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:23:56,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:23:56,274 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:23:56,274 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:23:56,275 INFO L85 PathProgramCache]: Analyzing trace with hash 1023118996, now seen corresponding path program 1 times [2023-11-29 01:23:56,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:23:56,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475377682] [2023-11-29 01:23:56,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:23:56,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:23:56,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:23:56,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:23:56,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:23:56,320 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475377682] [2023-11-29 01:23:56,320 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [475377682] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:23:56,320 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:23:56,320 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:23:56,320 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3954755] [2023-11-29 01:23:56,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:23:56,321 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:23:56,321 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:23:56,321 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:23:56,321 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:23:56,322 INFO L87 Difference]: Start difference. First operand 185343 states and 252645 transitions. cyclomatic complexity: 67326 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:23:57,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:23:57,516 INFO L93 Difference]: Finished difference Result 370639 states and 497633 transitions. [2023-11-29 01:23:57,516 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 370639 states and 497633 transitions. [2023-11-29 01:23:59,404 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 358400 [2023-11-29 01:24:00,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 370639 states to 370639 states and 497633 transitions. [2023-11-29 01:24:00,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 370639 [2023-11-29 01:24:00,219 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 370639 [2023-11-29 01:24:00,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 370639 states and 497633 transitions. [2023-11-29 01:24:00,338 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:24:00,339 INFO L218 hiAutomatonCegarLoop]: Abstraction has 370639 states and 497633 transitions. [2023-11-29 01:24:00,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 370639 states and 497633 transitions. [2023-11-29 01:24:03,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 370639 to 370639. [2023-11-29 01:24:03,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 370639 states, 370639 states have (on average 1.3426352866266098) internal successors, (497633), 370638 states have internal predecessors, (497633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:24:04,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 370639 states to 370639 states and 497633 transitions. [2023-11-29 01:24:04,195 INFO L240 hiAutomatonCegarLoop]: Abstraction has 370639 states and 497633 transitions. [2023-11-29 01:24:04,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:24:04,196 INFO L428 stractBuchiCegarLoop]: Abstraction has 370639 states and 497633 transitions. [2023-11-29 01:24:04,196 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2023-11-29 01:24:04,196 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 370639 states and 497633 transitions. [2023-11-29 01:24:05,662 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 358400 [2023-11-29 01:24:05,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:24:05,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:24:05,666 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:24:05,666 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:24:05,666 INFO L748 eck$LassoCheckResult]: Stem: 3886306#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 3886307#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3886122#L256 assume !(1 == ~main_in1_req_up~0); 3886083#L256-2 assume !(1 == ~main_in2_req_up~0); 3886085#L267-1 assume !(1 == ~main_sum_req_up~0); 3886480#L278-1 assume !(1 == ~main_diff_req_up~0); 3886214#L289-1 assume !(1 == ~main_pres_req_up~0); 3886499#L300-1 assume !(1 == ~main_dbl_req_up~0); 3886166#L311-1 assume !(1 == ~main_zero_req_up~0); 3886335#L322-1 assume !(1 == ~main_clk_req_up~0); 3889404#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3889403#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3889402#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3889401#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3889400#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3889399#L371-1 assume !(0 == ~main_in1_ev~0); 3889397#L376-1 assume !(0 == ~main_in2_ev~0); 3889398#L381-1 assume !(0 == ~main_sum_ev~0); 3911617#L386-1 assume !(0 == ~main_diff_ev~0); 3911616#L391-1 assume !(0 == ~main_pres_ev~0); 3911615#L396-1 assume !(0 == ~main_dbl_ev~0); 3911614#L401-1 assume !(0 == ~main_zero_ev~0); 3911613#L406-1 assume !(0 == ~main_clk_ev~0); 3911612#L411-1 assume !(0 == ~main_clk_pos_edge~0); 3911560#L416-1 assume !(0 == ~main_clk_neg_edge~0); 3911505#L421-1 assume !(1 == ~main_clk_pos_edge~0); 3911452#L426-1 assume !(1 == ~main_clk_pos_edge~0); 3911450#L431-1 assume !(1 == ~main_clk_pos_edge~0); 3911448#L436-1 assume !(1 == ~main_clk_pos_edge~0); 3911400#L441-1 assume !(1 == ~main_clk_pos_edge~0); 3911363#L446-1 assume !(1 == ~main_in1_ev~0); 3911361#L451-1 assume !(1 == ~main_in2_ev~0); 3911330#L456-1 assume !(1 == ~main_sum_ev~0); 3911327#L461-1 assume !(1 == ~main_diff_ev~0); 3911323#L466-1 assume !(1 == ~main_pres_ev~0); 3911288#L471-1 assume !(1 == ~main_dbl_ev~0); 3911260#L476-1 assume !(1 == ~main_zero_ev~0); 3911230#L481-1 assume !(1 == ~main_clk_ev~0); 3911228#L486-1 assume !(1 == ~main_clk_pos_edge~0); 3911226#L491-1 assume !(1 == ~main_clk_neg_edge~0); 3911201#L742-1 assume !false; 3911199#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3911197#L229 assume !false; 3911168#L147 assume !(0 == ~N_generate_st~0); 3911166#L151 assume !(0 == ~S1_addsub_st~0); 3911164#L154 assume !(0 == ~S2_presdbl_st~0); 3911132#L157 assume !(0 == ~S3_zero_st~0); 3911110#L160 assume !(0 == ~D_print_st~0); 3911108#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3911106#L509 assume !(1 == ~main_in1_req_up~0); 3911103#L509-2 assume !(1 == ~main_in2_req_up~0); 3911104#L520-1 assume !(1 == ~main_sum_req_up~0); 3912330#L531-1 assume !(1 == ~main_diff_req_up~0); 3912331#L542-1 assume !(1 == ~main_pres_req_up~0); 3913547#L553-1 assume !(1 == ~main_dbl_req_up~0); 3913529#L564-1 assume !(1 == ~main_zero_req_up~0); 3913518#L575-1 assume !(1 == ~main_clk_req_up~0); 3913514#L586-1 start_simulation_~kernel_st~0#1 := 3; 3913510#L605 assume !(0 == ~main_in1_ev~0); 3913506#L605-2 assume !(0 == ~main_in2_ev~0); 3913502#L610-1 assume !(0 == ~main_sum_ev~0); 3913498#L615-1 assume !(0 == ~main_diff_ev~0); 3913494#L620-1 assume !(0 == ~main_pres_ev~0); 3913490#L625-1 assume !(0 == ~main_dbl_ev~0); 3913486#L630-1 assume !(0 == ~main_zero_ev~0); 3913482#L635-1 assume !(0 == ~main_clk_ev~0); 3913478#L640-1 assume !(0 == ~main_clk_pos_edge~0); 3913474#L645-1 assume !(0 == ~main_clk_neg_edge~0); 3913470#L650-1 assume !(1 == ~main_clk_pos_edge~0); 3913466#L655-1 assume !(1 == ~main_clk_pos_edge~0); 3913462#L660-1 assume !(1 == ~main_clk_pos_edge~0); 3913458#L665-1 assume !(1 == ~main_clk_pos_edge~0); 3913454#L670-1 assume !(1 == ~main_clk_pos_edge~0); 3913450#L675-1 assume !(1 == ~main_in1_ev~0); 3913446#L680-1 assume !(1 == ~main_in2_ev~0); 3913442#L685-1 assume !(1 == ~main_sum_ev~0); 3913436#L690-1 assume !(1 == ~main_diff_ev~0); 3912178#L695-1 assume !(1 == ~main_pres_ev~0); 3913433#L700-1 assume !(1 == ~main_dbl_ev~0); 3913432#L705-1 assume !(1 == ~main_zero_ev~0); 3913431#L710-1 assume !(1 == ~main_clk_ev~0); 3913430#L715-1 assume !(1 == ~main_clk_pos_edge~0); 3913429#L720-1 assume !(1 == ~main_clk_neg_edge~0); 3913428#L725-1 assume !(0 == ~N_generate_st~0); 3913427#L733 assume !(0 == ~S1_addsub_st~0); 3913426#L736 assume !(0 == ~S2_presdbl_st~0); 3913425#L739 assume !(0 == ~S3_zero_st~0); 3913424#L742 assume !(0 == ~D_print_st~0); 3913422#start_simulation_returnLabel#1 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 3913420#L795-2 [2023-11-29 01:24:05,667 INFO L750 eck$LassoCheckResult]: Loop: 3913420#L795-2 assume !false; 3913418#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3913415#L256-3 assume !(1 == ~main_in1_req_up~0); 3913416#L256-5 assume !(1 == ~main_in2_req_up~0); 3940846#L267-3 assume !(1 == ~main_sum_req_up~0); 3949533#L278-3 assume !(1 == ~main_diff_req_up~0); 3949529#L289-3 assume !(1 == ~main_pres_req_up~0); 3949526#L300-3 assume !(1 == ~main_dbl_req_up~0); 3949522#L311-3 assume !(1 == ~main_zero_req_up~0); 3949519#L322-3 assume 1 == ~main_clk_req_up~0; 3949516#L334-2 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 3949514#L334-3 ~main_clk_req_up~0 := 0; 3949512#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3949510#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3949508#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3949506#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3949504#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3949502#L371-3 assume !(0 == ~main_in1_ev~0); 3949500#L376-3 assume !(0 == ~main_in2_ev~0); 3949496#L381-3 assume !(0 == ~main_sum_ev~0); 3949493#L386-3 assume !(0 == ~main_diff_ev~0); 3949491#L391-3 assume !(0 == ~main_pres_ev~0); 3949490#L396-3 assume !(0 == ~main_dbl_ev~0); 3949488#L401-3 assume !(0 == ~main_zero_ev~0); 3949486#L406-3 assume !(0 == ~main_clk_ev~0); 3949484#L411-3 assume !(0 == ~main_clk_pos_edge~0); 3949482#L416-3 assume !(0 == ~main_clk_neg_edge~0); 3949480#L421-3 assume !(1 == ~main_clk_pos_edge~0); 3949478#L426-3 assume !(1 == ~main_clk_pos_edge~0); 3949476#L431-3 assume !(1 == ~main_clk_pos_edge~0); 3949474#L436-3 assume !(1 == ~main_clk_pos_edge~0); 3949472#L441-3 assume !(1 == ~main_clk_pos_edge~0); 3949470#L446-3 assume !(1 == ~main_in1_ev~0); 3949468#L451-3 assume !(1 == ~main_in2_ev~0); 3949466#L456-3 assume !(1 == ~main_sum_ev~0); 3939243#L461-3 assume !(1 == ~main_diff_ev~0); 3939240#L466-3 assume !(1 == ~main_pres_ev~0); 3939236#L471-3 assume !(1 == ~main_dbl_ev~0); 3939234#L476-3 assume !(1 == ~main_zero_ev~0); 3939232#L481-3 assume !(1 == ~main_clk_ev~0); 3939231#L486-3 assume !(1 == ~main_clk_pos_edge~0); 3939230#L491-3 assume !(1 == ~main_clk_neg_edge~0); 3939228#L742-3 assume !false; 3939227#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3939226#L229-1 assume !false; 3939225#L147-1 assume !(0 == ~N_generate_st~0); 3939224#L151-2 assume !(0 == ~S1_addsub_st~0); 3939223#L154-2 assume !(0 == ~S2_presdbl_st~0); 3939222#L157-2 assume !(0 == ~S3_zero_st~0); 3939221#L160-2 assume !(0 == ~D_print_st~0); 3939220#eval_returnLabel#2 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3939219#L509-3 assume !(1 == ~main_in1_req_up~0); 3939217#L509-5 assume !(1 == ~main_in2_req_up~0); 3939218#L520-3 assume !(1 == ~main_sum_req_up~0); 3941986#L531-3 assume !(1 == ~main_diff_req_up~0); 3942094#L542-3 assume !(1 == ~main_pres_req_up~0); 3897029#L553-3 assume !(1 == ~main_dbl_req_up~0); 3897030#L564-3 assume !(1 == ~main_zero_req_up~0); 3897109#L575-3 assume !(1 == ~main_clk_req_up~0); 3897107#L586-3 start_simulation_~kernel_st~0#1 := 3; 3897105#L605-3 assume !(0 == ~main_in1_ev~0); 3897103#L605-5 assume !(0 == ~main_in2_ev~0); 3897101#L610-3 assume !(0 == ~main_sum_ev~0); 3897099#L615-3 assume !(0 == ~main_diff_ev~0); 3897097#L620-3 assume !(0 == ~main_pres_ev~0); 3897095#L625-3 assume !(0 == ~main_dbl_ev~0); 3897093#L630-3 assume !(0 == ~main_zero_ev~0); 3897091#L635-3 assume !(0 == ~main_clk_ev~0); 3897089#L640-3 assume !(0 == ~main_clk_pos_edge~0); 3897087#L645-3 assume !(0 == ~main_clk_neg_edge~0); 3897085#L650-3 assume !(1 == ~main_clk_pos_edge~0); 3897082#L655-3 assume !(1 == ~main_clk_pos_edge~0); 3897083#L660-3 assume !(1 == ~main_clk_pos_edge~0); 3897076#L665-3 assume !(1 == ~main_clk_pos_edge~0); 3897077#L670-3 assume !(1 == ~main_clk_pos_edge~0); 3897070#L675-3 assume !(1 == ~main_in1_ev~0); 3897071#L680-3 assume !(1 == ~main_in2_ev~0); 3897062#L685-3 assume !(1 == ~main_sum_ev~0); 3897063#L690-3 assume !(1 == ~main_diff_ev~0); 3897034#L695-3 assume !(1 == ~main_pres_ev~0); 3897035#L700-3 assume !(1 == ~main_dbl_ev~0); 3896897#L705-3 assume !(1 == ~main_zero_ev~0); 3896898#L710-3 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3896889#L715-3 assume !(1 == ~main_clk_pos_edge~0); 3896890#L720-3 assume !(1 == ~main_clk_neg_edge~0); 3896881#L725-3 assume !(0 == ~N_generate_st~0); 3896882#L733-2 assume !(0 == ~S1_addsub_st~0); 3896873#L736-2 assume !(0 == ~S2_presdbl_st~0); 3896874#L739-2 assume !(0 == ~S3_zero_st~0); 3896865#L742-2 assume !(0 == ~D_print_st~0); 3896866#start_simulation_returnLabel#2 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 3896853#L803 assume !(5 == main_~count~0#1); 3896852#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 3896839#L256-6 assume !(1 == ~main_in1_req_up~0); 3896840#L256-8 assume !(1 == ~main_in2_req_up~0); 3908855#L267-5 assume !(1 == ~main_sum_req_up~0); 3944401#L278-5 assume !(1 == ~main_diff_req_up~0); 3945132#L289-5 assume !(1 == ~main_pres_req_up~0); 3945166#L300-5 assume !(1 == ~main_dbl_req_up~0); 3945113#L311-5 assume !(1 == ~main_zero_req_up~0); 3945108#L322-5 assume 1 == ~main_clk_req_up~0; 3945105#L334-4 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 3945102#L334-5 ~main_clk_req_up~0 := 0; 3945100#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 3945098#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 3945096#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 3945094#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 3945092#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 3945090#L371-5 assume !(0 == ~main_in1_ev~0); 3945044#L376-5 assume !(0 == ~main_in2_ev~0); 3945032#L381-5 assume !(0 == ~main_sum_ev~0); 3945023#L386-5 assume !(0 == ~main_diff_ev~0); 3945013#L391-5 assume !(0 == ~main_pres_ev~0); 3945005#L396-5 assume !(0 == ~main_dbl_ev~0); 3944997#L401-5 assume !(0 == ~main_zero_ev~0); 3944990#L406-5 assume !(0 == ~main_clk_ev~0); 3944964#L411-5 assume !(0 == ~main_clk_pos_edge~0); 3944948#L416-5 assume !(0 == ~main_clk_neg_edge~0); 3944937#L421-5 assume !(1 == ~main_clk_pos_edge~0); 3944919#L426-5 assume !(1 == ~main_clk_pos_edge~0); 3944909#L431-5 assume !(1 == ~main_clk_pos_edge~0); 3944901#L436-5 assume !(1 == ~main_clk_pos_edge~0); 3944896#L441-5 assume !(1 == ~main_clk_pos_edge~0); 3944890#L446-5 assume !(1 == ~main_in1_ev~0); 3944882#L451-5 assume !(1 == ~main_in2_ev~0); 3942908#L456-5 assume !(1 == ~main_sum_ev~0); 3941260#L461-5 assume !(1 == ~main_diff_ev~0); 3941256#L466-5 assume !(1 == ~main_pres_ev~0); 3941252#L471-5 assume !(1 == ~main_dbl_ev~0); 3941250#L476-5 assume !(1 == ~main_zero_ev~0); 3941248#L481-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3941245#L486-5 assume !(1 == ~main_clk_pos_edge~0); 3941243#L491-5 assume !(1 == ~main_clk_neg_edge~0); 3941241#L742-5 assume !false; 3941239#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 3941237#L229-2 assume !false; 3941235#L147-2 assume !(0 == ~N_generate_st~0); 3941234#L151-4 assume !(0 == ~S1_addsub_st~0); 3941233#L154-4 assume !(0 == ~S2_presdbl_st~0); 3941232#L157-4 assume !(0 == ~S3_zero_st~0); 3941231#L160-4 assume !(0 == ~D_print_st~0); 3941230#eval_returnLabel#3 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 3941229#L509-6 assume !(1 == ~main_in1_req_up~0); 3941228#L509-8 assume !(1 == ~main_in2_req_up~0); 3912905#L520-5 assume !(1 == ~main_sum_req_up~0); 3912902#L531-5 assume !(1 == ~main_diff_req_up~0); 3912903#L542-5 assume !(1 == ~main_pres_req_up~0); 3913661#L553-5 assume !(1 == ~main_dbl_req_up~0); 3913652#L564-5 assume !(1 == ~main_zero_req_up~0); 3913647#L575-5 assume !(1 == ~main_clk_req_up~0); 3913645#L586-5 start_simulation_~kernel_st~0#1 := 3; 3913643#L605-6 assume !(0 == ~main_in1_ev~0); 3913641#L605-8 assume !(0 == ~main_in2_ev~0); 3913639#L610-5 assume !(0 == ~main_sum_ev~0); 3913637#L615-5 assume !(0 == ~main_diff_ev~0); 3913635#L620-5 assume !(0 == ~main_pres_ev~0); 3913633#L625-5 assume !(0 == ~main_dbl_ev~0); 3913631#L630-5 assume !(0 == ~main_zero_ev~0); 3913629#L635-5 assume !(0 == ~main_clk_ev~0); 3913627#L640-5 assume !(0 == ~main_clk_pos_edge~0); 3913625#L645-5 assume !(0 == ~main_clk_neg_edge~0); 3913622#L650-5 assume !(1 == ~main_clk_pos_edge~0); 3913623#L655-5 assume !(1 == ~main_clk_pos_edge~0); 3943372#L660-5 assume !(1 == ~main_clk_pos_edge~0); 3943370#L665-5 assume !(1 == ~main_clk_pos_edge~0); 3913613#L670-5 assume !(1 == ~main_clk_pos_edge~0); 3913611#L675-5 assume !(1 == ~main_in1_ev~0); 3913608#L680-5 assume !(1 == ~main_in2_ev~0); 3913609#L685-5 assume !(1 == ~main_sum_ev~0); 3940657#L690-5 assume !(1 == ~main_diff_ev~0); 3913597#L695-5 assume !(1 == ~main_pres_ev~0); 3913596#L700-5 assume !(1 == ~main_dbl_ev~0); 3913594#L705-5 assume !(1 == ~main_zero_ev~0); 3913593#L710-5 assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2; 3913591#L715-5 assume !(1 == ~main_clk_pos_edge~0); 3913589#L720-5 assume !(1 == ~main_clk_neg_edge~0); 3913587#L725-5 assume !(0 == ~N_generate_st~0); 3913583#L733-4 assume !(0 == ~S1_addsub_st~0); 3913579#L736-4 assume !(0 == ~S2_presdbl_st~0); 3913577#L739-4 assume !(0 == ~S3_zero_st~0); 3913559#L742-4 assume !(0 == ~D_print_st~0); 3913423#start_simulation_returnLabel#3 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 3913420#L795-2 [2023-11-29 01:24:05,667 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:24:05,668 INFO L85 PathProgramCache]: Analyzing trace with hash -836298421, now seen corresponding path program 6 times [2023-11-29 01:24:05,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:24:05,668 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262588074] [2023-11-29 01:24:05,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:24:05,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:24:05,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:24:05,683 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:24:05,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:24:05,718 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:24:05,718 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:24:05,719 INFO L85 PathProgramCache]: Analyzing trace with hash -1848556586, now seen corresponding path program 1 times [2023-11-29 01:24:05,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:24:05,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841848572] [2023-11-29 01:24:05,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:24:05,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:24:05,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:24:05,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:24:05,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:24:05,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841848572] [2023-11-29 01:24:05,780 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1841848572] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:24:05,781 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:24:05,781 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:24:05,781 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114672695] [2023-11-29 01:24:05,781 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:24:05,782 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:24:05,782 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:24:05,782 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:24:05,783 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:24:05,783 INFO L87 Difference]: Start difference. First operand 370639 states and 497633 transitions. cyclomatic complexity: 127018 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:24:06,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:24:06,683 INFO L93 Difference]: Finished difference Result 370639 states and 495201 transitions. [2023-11-29 01:24:06,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 370639 states and 495201 transitions. [2023-11-29 01:24:08,529 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 358400 [2023-11-29 01:24:09,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 370639 states to 370639 states and 495201 transitions. [2023-11-29 01:24:09,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 370639 [2023-11-29 01:24:09,971 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 370639 [2023-11-29 01:24:09,971 INFO L73 IsDeterministic]: Start isDeterministic. Operand 370639 states and 495201 transitions. [2023-11-29 01:24:10,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:24:10,081 INFO L218 hiAutomatonCegarLoop]: Abstraction has 370639 states and 495201 transitions. [2023-11-29 01:24:10,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 370639 states and 495201 transitions. [2023-11-29 01:24:12,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 370639 to 370639. [2023-11-29 01:24:13,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 370639 states, 370639 states have (on average 1.3360736457847124) internal successors, (495201), 370638 states have internal predecessors, (495201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:24:14,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 370639 states to 370639 states and 495201 transitions. [2023-11-29 01:24:14,353 INFO L240 hiAutomatonCegarLoop]: Abstraction has 370639 states and 495201 transitions. [2023-11-29 01:24:14,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:24:14,355 INFO L428 stractBuchiCegarLoop]: Abstraction has 370639 states and 495201 transitions. [2023-11-29 01:24:14,355 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2023-11-29 01:24:14,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 370639 states and 495201 transitions. [2023-11-29 01:24:15,127 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 358400 [2023-11-29 01:24:15,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:24:15,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:24:15,129 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:24:15,129 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:24:15,129 INFO L748 eck$LassoCheckResult]: Stem: 4627597#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0; 4627598#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 4627409#L256 assume !(1 == ~main_in1_req_up~0); 4627367#L256-2 assume !(1 == ~main_in2_req_up~0); 4627369#L267-1 assume !(1 == ~main_sum_req_up~0); 4627783#L278-1 assume !(1 == ~main_diff_req_up~0); 4627502#L289-1 assume !(1 == ~main_pres_req_up~0); 4627386#L300-1 assume !(1 == ~main_dbl_req_up~0); 4627454#L311-1 assume !(1 == ~main_zero_req_up~0); 4627890#L322-1 assume !(1 == ~main_clk_req_up~0); 4627891#L333-1 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 4627593#L351-1 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 4627594#L356-1 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 4627579#L361-1 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 4627580#L366-1 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 4627569#L371-1 assume !(0 == ~main_in1_ev~0); 4627570#L376-1 assume !(0 == ~main_in2_ev~0); 4631010#L381-1 assume !(0 == ~main_sum_ev~0); 4656695#L386-1 assume !(0 == ~main_diff_ev~0); 4656693#L391-1 assume !(0 == ~main_pres_ev~0); 4656691#L396-1 assume !(0 == ~main_dbl_ev~0); 4656689#L401-1 assume !(0 == ~main_zero_ev~0); 4656687#L406-1 assume !(0 == ~main_clk_ev~0); 4656543#L411-1 assume !(0 == ~main_clk_pos_edge~0); 4656396#L416-1 assume !(0 == ~main_clk_neg_edge~0); 4656335#L421-1 assume !(1 == ~main_clk_pos_edge~0); 4656333#L426-1 assume !(1 == ~main_clk_pos_edge~0); 4656331#L431-1 assume !(1 == ~main_clk_pos_edge~0); 4656329#L436-1 assume !(1 == ~main_clk_pos_edge~0); 4656262#L441-1 assume !(1 == ~main_clk_pos_edge~0); 4656260#L446-1 assume !(1 == ~main_in1_ev~0); 4656210#L451-1 assume !(1 == ~main_in2_ev~0); 4656171#L456-1 assume !(1 == ~main_sum_ev~0); 4656167#L461-1 assume !(1 == ~main_diff_ev~0); 4656104#L466-1 assume !(1 == ~main_pres_ev~0); 4656100#L471-1 assume !(1 == ~main_dbl_ev~0); 4656097#L476-1 assume !(1 == ~main_zero_ev~0); 4656045#L481-1 assume !(1 == ~main_clk_ev~0); 4656043#L486-1 assume !(1 == ~main_clk_pos_edge~0); 4655999#L491-1 assume !(1 == ~main_clk_neg_edge~0); 4655963#L742-1 assume !false; 4655933#L503 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 4655931#L229 assume !false; 4655929#L147 assume !(0 == ~N_generate_st~0); 4655927#L151 assume !(0 == ~S1_addsub_st~0); 4655925#L154 assume !(0 == ~S2_presdbl_st~0); 4655923#L157 assume !(0 == ~S3_zero_st~0); 4655884#L160 assume !(0 == ~D_print_st~0); 4655882#eval_returnLabel#1 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 4655880#L509 assume !(1 == ~main_in1_req_up~0); 4655840#L509-2 assume !(1 == ~main_in2_req_up~0); 4655836#L520-1 assume !(1 == ~main_sum_req_up~0); 4655837#L531-1 assume !(1 == ~main_diff_req_up~0); 4659263#L542-1 assume !(1 == ~main_pres_req_up~0); 4659264#L553-1 assume !(1 == ~main_dbl_req_up~0); 4659272#L564-1 assume !(1 == ~main_zero_req_up~0); 4659273#L575-1 assume !(1 == ~main_clk_req_up~0); 4662378#L586-1 start_simulation_~kernel_st~0#1 := 3; 4662370#L605 assume !(0 == ~main_in1_ev~0); 4662362#L605-2 assume !(0 == ~main_in2_ev~0); 4662354#L610-1 assume !(0 == ~main_sum_ev~0); 4662346#L615-1 assume !(0 == ~main_diff_ev~0); 4662338#L620-1 assume !(0 == ~main_pres_ev~0); 4662330#L625-1 assume !(0 == ~main_dbl_ev~0); 4662322#L630-1 assume !(0 == ~main_zero_ev~0); 4662314#L635-1 assume !(0 == ~main_clk_ev~0); 4662306#L640-1 assume !(0 == ~main_clk_pos_edge~0); 4662298#L645-1 assume !(0 == ~main_clk_neg_edge~0); 4662290#L650-1 assume !(1 == ~main_clk_pos_edge~0); 4662282#L655-1 assume !(1 == ~main_clk_pos_edge~0); 4662274#L660-1 assume !(1 == ~main_clk_pos_edge~0); 4662266#L665-1 assume !(1 == ~main_clk_pos_edge~0); 4662258#L670-1 assume !(1 == ~main_clk_pos_edge~0); 4662250#L675-1 assume !(1 == ~main_in1_ev~0); 4662242#L680-1 assume !(1 == ~main_in2_ev~0); 4662234#L685-1 assume !(1 == ~main_sum_ev~0); 4662222#L690-1 assume !(1 == ~main_diff_ev~0); 4662216#L695-1 assume !(1 == ~main_pres_ev~0); 4662213#L700-1 assume !(1 == ~main_dbl_ev~0); 4662212#L705-1 assume !(1 == ~main_zero_ev~0); 4662211#L710-1 assume !(1 == ~main_clk_ev~0); 4662210#L715-1 assume !(1 == ~main_clk_pos_edge~0); 4662209#L720-1 assume !(1 == ~main_clk_neg_edge~0); 4662208#L725-1 assume !(0 == ~N_generate_st~0); 4662207#L733 assume !(0 == ~S1_addsub_st~0); 4662206#L736 assume !(0 == ~S2_presdbl_st~0); 4662205#L739 assume !(0 == ~S3_zero_st~0); 4662204#L742 assume !(0 == ~D_print_st~0); 4662202#start_simulation_returnLabel#1 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 4662194#L795-2 [2023-11-29 01:24:15,130 INFO L750 eck$LassoCheckResult]: Loop: 4662194#L795-2 assume !false; 4662155#L796 ~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 4662124#L256-3 assume !(1 == ~main_in1_req_up~0); 4662022#L256-5 assume !(1 == ~main_in2_req_up~0); 4662023#L267-3 assume !(1 == ~main_sum_req_up~0); 4679848#L278-3 assume !(1 == ~main_diff_req_up~0); 4691805#L289-3 assume !(1 == ~main_pres_req_up~0); 4709649#L300-3 assume !(1 == ~main_dbl_req_up~0); 4709646#L311-3 assume !(1 == ~main_zero_req_up~0); 4709647#L322-3 assume 1 == ~main_clk_req_up~0; 4714411#L334-2 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 4714410#L334-3 ~main_clk_req_up~0 := 0; 4714409#L333-3 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 4714408#L351-3 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 4714407#L356-3 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 4714406#L361-3 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 4714405#L366-3 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 4714403#L371-3 assume !(0 == ~main_in1_ev~0); 4714402#L376-3 assume !(0 == ~main_in2_ev~0); 4714401#L381-3 assume !(0 == ~main_sum_ev~0); 4714400#L386-3 assume !(0 == ~main_diff_ev~0); 4714399#L391-3 assume !(0 == ~main_pres_ev~0); 4714396#L396-3 assume !(0 == ~main_dbl_ev~0); 4714394#L401-3 assume !(0 == ~main_zero_ev~0); 4714393#L406-3 assume !(0 == ~main_clk_ev~0); 4714392#L411-3 assume !(0 == ~main_clk_pos_edge~0); 4714390#L416-3 assume !(0 == ~main_clk_neg_edge~0); 4714389#L421-3 assume !(1 == ~main_clk_pos_edge~0); 4714388#L426-3 assume !(1 == ~main_clk_pos_edge~0); 4714387#L431-3 assume !(1 == ~main_clk_pos_edge~0); 4714386#L436-3 assume !(1 == ~main_clk_pos_edge~0); 4714385#L441-3 assume !(1 == ~main_clk_pos_edge~0); 4714384#L446-3 assume !(1 == ~main_in1_ev~0); 4709674#L451-3 assume !(1 == ~main_in2_ev~0); 4709101#L456-3 assume !(1 == ~main_sum_ev~0); 4680916#L461-3 assume !(1 == ~main_diff_ev~0); 4709098#L466-3 assume !(1 == ~main_pres_ev~0); 4708834#L471-3 assume !(1 == ~main_dbl_ev~0); 4709097#L476-3 assume !(1 == ~main_zero_ev~0); 4709095#L481-3 assume !(1 == ~main_clk_ev~0); 4709093#L486-3 assume !(1 == ~main_clk_pos_edge~0); 4709091#L491-3 assume !(1 == ~main_clk_neg_edge~0); 4709089#L742-3 assume !false; 4709087#L503-1 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 4709083#L229-1 assume !false; 4709080#L147-1 assume !(0 == ~N_generate_st~0); 4709076#L151-2 assume !(0 == ~S1_addsub_st~0); 4709075#L154-2 assume !(0 == ~S2_presdbl_st~0); 4709074#L157-2 assume !(0 == ~S3_zero_st~0); 4709073#L160-2 assume !(0 == ~D_print_st~0); 4709072#eval_returnLabel#2 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 4709071#L509-3 assume !(1 == ~main_in1_req_up~0); 4709068#L509-5 assume !(1 == ~main_in2_req_up~0); 4709066#L520-3 assume !(1 == ~main_sum_req_up~0); 4709067#L531-3 assume !(1 == ~main_diff_req_up~0); 4709944#L542-3 assume !(1 == ~main_pres_req_up~0); 4709941#L553-3 assume !(1 == ~main_dbl_req_up~0); 4709939#L564-3 assume !(1 == ~main_zero_req_up~0); 4672336#L575-3 assume !(1 == ~main_clk_req_up~0); 4672332#L586-3 start_simulation_~kernel_st~0#1 := 3; 4672329#L605-3 assume !(0 == ~main_in1_ev~0); 4672324#L605-5 assume !(0 == ~main_in2_ev~0); 4672319#L610-3 assume !(0 == ~main_sum_ev~0); 4672320#L615-3 assume !(0 == ~main_diff_ev~0); 4672308#L620-3 assume !(0 == ~main_pres_ev~0); 4672309#L625-3 assume !(0 == ~main_dbl_ev~0); 4672302#L630-3 assume !(0 == ~main_zero_ev~0); 4672303#L635-3 assume !(0 == ~main_clk_ev~0); 4672265#L640-3 assume !(0 == ~main_clk_pos_edge~0); 4672266#L645-3 assume !(0 == ~main_clk_neg_edge~0); 4672250#L650-3 assume !(1 == ~main_clk_pos_edge~0); 4672251#L655-3 assume !(1 == ~main_clk_pos_edge~0); 4672226#L660-3 assume !(1 == ~main_clk_pos_edge~0); 4672227#L665-3 assume !(1 == ~main_clk_pos_edge~0); 4672222#L670-3 assume !(1 == ~main_clk_pos_edge~0); 4672223#L675-3 assume !(1 == ~main_in1_ev~0); 4672217#L680-3 assume !(1 == ~main_in2_ev~0); 4672218#L685-3 assume !(1 == ~main_sum_ev~0); 4671975#L690-3 assume !(1 == ~main_diff_ev~0); 4671930#L695-3 assume !(1 == ~main_pres_ev~0); 4671926#L700-3 assume !(1 == ~main_dbl_ev~0); 4671922#L705-3 assume !(1 == ~main_zero_ev~0); 4671920#L710-3 assume !(1 == ~main_clk_ev~0); 4671825#L715-3 assume !(1 == ~main_clk_pos_edge~0); 4671824#L720-3 assume !(1 == ~main_clk_neg_edge~0); 4671823#L725-3 assume !(0 == ~N_generate_st~0); 4671822#L733-2 assume !(0 == ~S1_addsub_st~0); 4671821#L736-2 assume !(0 == ~S2_presdbl_st~0); 4671817#L739-2 assume !(0 == ~S3_zero_st~0); 4671815#L742-2 assume !(0 == ~D_print_st~0); 4671812#start_simulation_returnLabel#2 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1; 4671813#L803 assume !(5 == main_~count~0#1); 4706157#L803-2 ~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0; 4706156#L256-6 assume !(1 == ~main_in1_req_up~0); 4706155#L256-8 assume !(1 == ~main_in2_req_up~0); 4671797#L267-5 assume !(1 == ~main_sum_req_up~0); 4671798#L278-5 assume !(1 == ~main_diff_req_up~0); 4672479#L289-5 assume !(1 == ~main_pres_req_up~0); 4707461#L300-5 assume !(1 == ~main_dbl_req_up~0); 4707452#L311-5 assume !(1 == ~main_zero_req_up~0); 4707445#L322-5 assume 1 == ~main_clk_req_up~0; 4707438#L334-4 assume !(~main_clk_val~0 != ~main_clk_val_t~0); 4707432#L334-5 ~main_clk_req_up~0 := 0; 4707426#L333-5 assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2; 4707417#L351-5 assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2; 4707409#L356-5 assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2; 4707404#L361-5 assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2; 4707400#L366-5 assume !(1 == ~D_print_i~0);~D_print_st~0 := 2; 4707396#L371-5 assume !(0 == ~main_in1_ev~0); 4707392#L376-5 assume !(0 == ~main_in2_ev~0); 4707388#L381-5 assume !(0 == ~main_sum_ev~0); 4707384#L386-5 assume !(0 == ~main_diff_ev~0); 4707213#L391-5 assume !(0 == ~main_pres_ev~0); 4707212#L396-5 assume !(0 == ~main_dbl_ev~0); 4707209#L401-5 assume !(0 == ~main_zero_ev~0); 4707206#L406-5 assume !(0 == ~main_clk_ev~0); 4707204#L411-5 assume !(0 == ~main_clk_pos_edge~0); 4707202#L416-5 assume !(0 == ~main_clk_neg_edge~0); 4707200#L421-5 assume !(1 == ~main_clk_pos_edge~0); 4707198#L426-5 assume !(1 == ~main_clk_pos_edge~0); 4707196#L431-5 assume !(1 == ~main_clk_pos_edge~0); 4707194#L436-5 assume !(1 == ~main_clk_pos_edge~0); 4707192#L441-5 assume !(1 == ~main_clk_pos_edge~0); 4707190#L446-5 assume !(1 == ~main_in1_ev~0); 4707188#L451-5 assume !(1 == ~main_in2_ev~0); 4707186#L456-5 assume !(1 == ~main_sum_ev~0); 4707182#L461-5 assume !(1 == ~main_diff_ev~0); 4707178#L466-5 assume !(1 == ~main_pres_ev~0); 4707176#L471-5 assume !(1 == ~main_dbl_ev~0); 4707174#L476-5 assume !(1 == ~main_zero_ev~0); 4707172#L481-5 assume !(1 == ~main_clk_ev~0); 4707170#L486-5 assume !(1 == ~main_clk_pos_edge~0); 4707168#L491-5 assume !(1 == ~main_clk_neg_edge~0); 4707167#L742-5 assume !false; 4707166#L503-2 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1; 4707165#L229-2 assume !false; 4707164#L147-2 assume !(0 == ~N_generate_st~0); 4707163#L151-4 assume !(0 == ~S1_addsub_st~0); 4707162#L154-4 assume !(0 == ~S2_presdbl_st~0); 4707160#L157-4 assume !(0 == ~S3_zero_st~0); 4660617#L160-4 assume !(0 == ~D_print_st~0); 4660492#eval_returnLabel#3 havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2; 4660482#L509-6 assume !(1 == ~main_in1_req_up~0); 4660478#L509-8 assume !(1 == ~main_in2_req_up~0); 4660469#L520-5 assume !(1 == ~main_sum_req_up~0); 4660470#L531-5 assume !(1 == ~main_diff_req_up~0); 4660664#L542-5 assume !(1 == ~main_pres_req_up~0); 4660660#L553-5 assume !(1 == ~main_dbl_req_up~0); 4660655#L564-5 assume !(1 == ~main_zero_req_up~0); 4660656#L575-5 assume !(1 == ~main_clk_req_up~0); 4662762#L586-5 start_simulation_~kernel_st~0#1 := 3; 4662759#L605-6 assume !(0 == ~main_in1_ev~0); 4662755#L605-8 assume !(0 == ~main_in2_ev~0); 4662750#L610-5 assume !(0 == ~main_sum_ev~0); 4662744#L615-5 assume !(0 == ~main_diff_ev~0); 4662734#L620-5 assume !(0 == ~main_pres_ev~0); 4662725#L625-5 assume !(0 == ~main_dbl_ev~0); 4662721#L630-5 assume !(0 == ~main_zero_ev~0); 4662717#L635-5 assume !(0 == ~main_clk_ev~0); 4662709#L640-5 assume !(0 == ~main_clk_pos_edge~0); 4662701#L645-5 assume !(0 == ~main_clk_neg_edge~0); 4662691#L650-5 assume !(1 == ~main_clk_pos_edge~0); 4662668#L655-5 assume !(1 == ~main_clk_pos_edge~0); 4662612#L660-5 assume !(1 == ~main_clk_pos_edge~0); 4662603#L665-5 assume !(1 == ~main_clk_pos_edge~0); 4662573#L670-5 assume !(1 == ~main_clk_pos_edge~0); 4662564#L675-5 assume !(1 == ~main_in1_ev~0); 4662555#L680-5 assume !(1 == ~main_in2_ev~0); 4662506#L685-5 assume !(1 == ~main_sum_ev~0); 4662492#L690-5 assume !(1 == ~main_diff_ev~0); 4662473#L695-5 assume !(1 == ~main_pres_ev~0); 4662466#L700-5 assume !(1 == ~main_dbl_ev~0); 4662460#L705-5 assume !(1 == ~main_zero_ev~0); 4662454#L710-5 assume !(1 == ~main_clk_ev~0); 4662448#L715-5 assume !(1 == ~main_clk_pos_edge~0); 4662442#L720-5 assume !(1 == ~main_clk_neg_edge~0); 4662435#L725-5 assume !(0 == ~N_generate_st~0); 4662427#L733-4 assume !(0 == ~S1_addsub_st~0); 4662413#L736-4 assume !(0 == ~S2_presdbl_st~0); 4662403#L739-4 assume !(0 == ~S3_zero_st~0); 4662386#L742-4 assume !(0 == ~D_print_st~0); 4662203#start_simulation_returnLabel#3 havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true; 4662194#L795-2 [2023-11-29 01:24:15,130 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:24:15,130 INFO L85 PathProgramCache]: Analyzing trace with hash -836298421, now seen corresponding path program 7 times [2023-11-29 01:24:15,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:24:15,130 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390910307] [2023-11-29 01:24:15,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:24:15,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:24:15,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:24:15,141 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:24:15,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:24:15,168 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:24:15,168 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:24:15,168 INFO L85 PathProgramCache]: Analyzing trace with hash -2027628716, now seen corresponding path program 1 times [2023-11-29 01:24:15,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:24:15,168 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2026487333] [2023-11-29 01:24:15,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:24:15,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:24:15,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:24:15,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:24:15,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:24:15,253 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2026487333] [2023-11-29 01:24:15,253 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2026487333] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:24:15,253 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:24:15,253 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:24:15,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [454134907] [2023-11-29 01:24:15,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:24:15,254 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:24:15,254 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:24:15,254 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 01:24:15,255 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 01:24:15,255 INFO L87 Difference]: Start difference. First operand 370639 states and 495201 transitions. cyclomatic complexity: 124586 Second operand has 5 states, 5 states have (on average 36.4) internal successors, (182), 5 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:24:16,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:24:16,635 INFO L93 Difference]: Finished difference Result 383287 states and 511929 transitions. [2023-11-29 01:24:16,635 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 383287 states and 511929 transitions. [2023-11-29 01:24:18,448 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 352064 [2023-11-29 01:24:19,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 383287 states to 383287 states and 511929 transitions. [2023-11-29 01:24:19,175 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 383287 [2023-11-29 01:24:19,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 383287 [2023-11-29 01:24:19,339 INFO L73 IsDeterministic]: Start isDeterministic. Operand 383287 states and 511929 transitions. [2023-11-29 01:24:19,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:24:19,459 INFO L218 hiAutomatonCegarLoop]: Abstraction has 383287 states and 511929 transitions. [2023-11-29 01:24:19,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 383287 states and 511929 transitions. [2023-11-29 01:24:22,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 383287 to 340767. [2023-11-29 01:24:22,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 340767 states, 340767 states have (on average 1.3432433304868137) internal successors, (457733), 340766 states have internal predecessors, (457733), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)