./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-28 23:51:55,401 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-28 23:51:55,482 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-28 23:51:55,487 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-28 23:51:55,488 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-28 23:51:55,521 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-28 23:51:55,521 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-28 23:51:55,522 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-28 23:51:55,522 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-28 23:51:55,523 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-28 23:51:55,524 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-28 23:51:55,524 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-28 23:51:55,525 INFO L153 SettingsManager]: * Use SBE=true [2023-11-28 23:51:55,525 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-28 23:51:55,526 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-28 23:51:55,526 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-28 23:51:55,527 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-28 23:51:55,527 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-28 23:51:55,528 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-28 23:51:55,528 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-28 23:51:55,529 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-28 23:51:55,530 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-28 23:51:55,530 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-28 23:51:55,531 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-28 23:51:55,531 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-28 23:51:55,531 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-28 23:51:55,532 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-28 23:51:55,532 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-28 23:51:55,533 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-28 23:51:55,533 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-28 23:51:55,534 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-28 23:51:55,534 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-28 23:51:55,534 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-28 23:51:55,535 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-28 23:51:55,535 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-28 23:51:55,535 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-28 23:51:55,536 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-28 23:51:55,536 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-28 23:51:55,536 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba [2023-11-28 23:51:55,757 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-28 23:51:55,778 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-28 23:51:55,781 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-28 23:51:55,782 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-28 23:51:55,783 INFO L274 PluginConnector]: CDTParser initialized [2023-11-28 23:51:55,784 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2023-11-28 23:51:58,434 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-28 23:51:58,638 INFO L384 CDTParser]: Found 1 translation units. [2023-11-28 23:51:58,638 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2023-11-28 23:51:58,651 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/data/675bd07b1/91d824f6cb3149898e5d50705f2d202e/FLAG28bf7a8b8 [2023-11-28 23:51:58,663 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/data/675bd07b1/91d824f6cb3149898e5d50705f2d202e [2023-11-28 23:51:58,664 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-28 23:51:58,666 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-28 23:51:58,666 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-28 23:51:58,667 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-28 23:51:58,670 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-28 23:51:58,671 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 11:51:58" (1/1) ... [2023-11-28 23:51:58,672 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@36b4297c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58, skipping insertion in model container [2023-11-28 23:51:58,672 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 11:51:58" (1/1) ... [2023-11-28 23:51:58,714 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-28 23:51:58,906 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-28 23:51:58,917 INFO L202 MainTranslator]: Completed pre-run [2023-11-28 23:51:58,952 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-28 23:51:58,971 INFO L206 MainTranslator]: Completed translation [2023-11-28 23:51:58,972 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58 WrapperNode [2023-11-28 23:51:58,972 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-28 23:51:58,973 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-28 23:51:58,973 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-28 23:51:58,973 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-28 23:51:58,981 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58" (1/1) ... [2023-11-28 23:51:58,991 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58" (1/1) ... [2023-11-28 23:51:59,044 INFO L138 Inliner]: procedures = 36, calls = 44, calls flagged for inlining = 39, calls inlined = 78, statements flattened = 1073 [2023-11-28 23:51:59,044 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-28 23:51:59,045 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-28 23:51:59,045 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-28 23:51:59,045 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-28 23:51:59,058 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58" (1/1) ... [2023-11-28 23:51:59,058 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58" (1/1) ... [2023-11-28 23:51:59,064 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58" (1/1) ... [2023-11-28 23:51:59,088 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-28 23:51:59,089 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58" (1/1) ... [2023-11-28 23:51:59,089 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58" (1/1) ... [2023-11-28 23:51:59,105 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58" (1/1) ... [2023-11-28 23:51:59,121 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58" (1/1) ... [2023-11-28 23:51:59,124 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58" (1/1) ... [2023-11-28 23:51:59,128 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58" (1/1) ... [2023-11-28 23:51:59,135 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-28 23:51:59,136 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-28 23:51:59,136 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-28 23:51:59,136 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-28 23:51:59,137 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58" (1/1) ... [2023-11-28 23:51:59,143 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 23:51:59,157 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 23:51:59,169 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 23:51:59,182 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-28 23:51:59,229 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-28 23:51:59,230 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-28 23:51:59,230 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-28 23:51:59,230 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-28 23:51:59,347 INFO L241 CfgBuilder]: Building ICFG [2023-11-28 23:51:59,350 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-28 23:52:00,070 INFO L282 CfgBuilder]: Performing block encoding [2023-11-28 23:52:00,091 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-28 23:52:00,092 INFO L309 CfgBuilder]: Removed 7 assume(true) statements. [2023-11-28 23:52:00,094 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:52:00 BoogieIcfgContainer [2023-11-28 23:52:00,094 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-28 23:52:00,095 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-28 23:52:00,095 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-28 23:52:00,098 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-28 23:52:00,099 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-28 23:52:00,099 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.11 11:51:58" (1/3) ... [2023-11-28 23:52:00,100 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@a207695 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 11:52:00, skipping insertion in model container [2023-11-28 23:52:00,100 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-28 23:52:00,100 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 11:51:58" (2/3) ... [2023-11-28 23:52:00,101 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@a207695 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 11:52:00, skipping insertion in model container [2023-11-28 23:52:00,101 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-28 23:52:00,101 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:52:00" (3/3) ... [2023-11-28 23:52:00,102 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-1.c [2023-11-28 23:52:00,163 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-28 23:52:00,163 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-28 23:52:00,164 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-28 23:52:00,164 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-28 23:52:00,164 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-28 23:52:00,164 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-28 23:52:00,164 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-28 23:52:00,164 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-28 23:52:00,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 437 states, 436 states have (on average 1.525229357798165) internal successors, (665), 436 states have internal predecessors, (665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:00,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 366 [2023-11-28 23:52:00,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:00,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:00,224 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:00,225 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:00,225 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-28 23:52:00,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 437 states, 436 states have (on average 1.525229357798165) internal successors, (665), 436 states have internal predecessors, (665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:00,241 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 366 [2023-11-28 23:52:00,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:00,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:00,245 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:00,245 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:00,254 INFO L748 eck$LassoCheckResult]: Stem: 128#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 363#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 208#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 359#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 73#L353true assume !(1 == ~m_i~0);~m_st~0 := 2; 293#L353-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 370#L358-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 43#L363-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 415#L368-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 122#L373-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57#L514true assume !(0 == ~M_E~0); 384#L514-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 322#L519-1true assume !(0 == ~T2_E~0); 36#L524-1true assume !(0 == ~T3_E~0); 105#L529-1true assume !(0 == ~T4_E~0); 325#L534-1true assume !(0 == ~E_M~0); 259#L539-1true assume !(0 == ~E_1~0); 291#L544-1true assume !(0 == ~E_2~0); 292#L549-1true assume !(0 == ~E_3~0); 330#L554-1true assume 0 == ~E_4~0;~E_4~0 := 1; 34#L559-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 174#L250true assume 1 == ~m_pc~0; 396#L251true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 323#L261true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114#is_master_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 295#L637true assume !(0 != activate_threads_~tmp~1#1); 37#L637-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49#L269true assume !(1 == ~t1_pc~0); 102#L269-2true is_transmit1_triggered_~__retres1~1#1 := 0; 180#L280true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 324#L645true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 147#L645-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 232#L288true assume 1 == ~t2_pc~0; 355#L289true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 244#L299true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 212#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 254#L653true assume !(0 != activate_threads_~tmp___1~0#1); 306#L653-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 165#L307true assume !(1 == ~t3_pc~0); 223#L307-2true is_transmit3_triggered_~__retres1~3#1 := 0; 205#L318true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 301#L661true assume !(0 != activate_threads_~tmp___2~0#1); 127#L661-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 348#L326true assume 1 == ~t4_pc~0; 342#L327true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 163#L337true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 302#L669true assume !(0 != activate_threads_~tmp___3~0#1); 257#L669-2true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 297#L572true assume !(1 == ~M_E~0); 343#L572-2true assume !(1 == ~T1_E~0); 41#L577-1true assume !(1 == ~T2_E~0); 239#L582-1true assume !(1 == ~T3_E~0); 247#L587-1true assume !(1 == ~T4_E~0); 375#L592-1true assume !(1 == ~E_M~0); 11#L597-1true assume 1 == ~E_1~0;~E_1~0 := 2; 417#L602-1true assume !(1 == ~E_2~0); 140#L607-1true assume !(1 == ~E_3~0); 421#L612-1true assume !(1 == ~E_4~0); 104#L617-1true assume { :end_inline_reset_delta_events } true; 436#L803-2true [2023-11-28 23:52:00,256 INFO L750 eck$LassoCheckResult]: Loop: 436#L803-2true assume !false; 218#L804true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 188#L489-1true assume !true; 63#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 307#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 194#L514-3true assume !(0 == ~M_E~0); 154#L514-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 313#L519-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 237#L524-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 86#L529-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 172#L534-3true assume 0 == ~E_M~0;~E_M~0 := 1; 6#L539-3true assume 0 == ~E_1~0;~E_1~0 := 1; 328#L544-3true assume 0 == ~E_2~0;~E_2~0 := 1; 401#L549-3true assume !(0 == ~E_3~0); 118#L554-3true assume 0 == ~E_4~0;~E_4~0 := 1; 191#L559-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 269#L250-18true assume !(1 == ~m_pc~0); 378#L250-20true is_master_triggered_~__retres1~0#1 := 0; 203#L261-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 137#is_master_triggered_returnLabel#7true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 267#L637-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91#L637-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26#L269-18true assume 1 == ~t1_pc~0; 195#L270-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 67#L280-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 366#is_transmit1_triggered_returnLabel#7true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 182#L645-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 285#L645-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110#L288-18true assume !(1 == ~t2_pc~0); 397#L288-20true is_transmit2_triggered_~__retres1~2#1 := 0; 10#L299-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 202#is_transmit2_triggered_returnLabel#7true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 170#L653-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95#L653-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 310#L307-18true assume 1 == ~t3_pc~0; 141#L308-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 121#L318-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222#is_transmit3_triggered_returnLabel#7true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 84#L661-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 346#L661-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 270#L326-18true assume 1 == ~t4_pc~0; 367#L327-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 280#L337-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155#is_transmit4_triggered_returnLabel#7true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4#L669-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 371#L669-20true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 425#L572-3true assume 1 == ~M_E~0;~M_E~0 := 2; 93#L572-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 109#L577-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 33#L582-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 374#L587-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 190#L592-3true assume !(1 == ~E_M~0); 245#L597-3true assume 1 == ~E_1~0;~E_1~0 := 2; 132#L602-3true assume 1 == ~E_2~0;~E_2~0 := 2; 318#L607-3true assume 1 == ~E_3~0;~E_3~0 := 2; 100#L612-3true assume 1 == ~E_4~0;~E_4~0 := 2; 192#L617-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 136#L386-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 125#L413-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 185#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 164#L822true assume !(0 == start_simulation_~tmp~3#1); 265#L822-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 395#L386-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 407#L413-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 19#L777true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 198#L784true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 319#stop_simulation_returnLabel#1true start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 311#L835true assume !(0 != start_simulation_~tmp___0~1#1); 436#L803-2true [2023-11-28 23:52:00,262 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:00,263 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2023-11-28 23:52:00,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:00,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1577015970] [2023-11-28 23:52:00,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:00,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:00,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:00,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:00,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:00,539 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1577015970] [2023-11-28 23:52:00,540 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1577015970] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:00,540 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:00,540 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:00,542 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832683482] [2023-11-28 23:52:00,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:00,547 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:00,548 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:00,549 INFO L85 PathProgramCache]: Analyzing trace with hash 868114677, now seen corresponding path program 1 times [2023-11-28 23:52:00,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:00,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [532757857] [2023-11-28 23:52:00,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:00,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:00,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:00,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:00,595 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:00,595 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [532757857] [2023-11-28 23:52:00,595 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [532757857] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:00,596 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:00,596 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 23:52:00,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1144888247] [2023-11-28 23:52:00,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:00,598 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:00,599 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:00,633 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:00,633 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:00,636 INFO L87 Difference]: Start difference. First operand has 437 states, 436 states have (on average 1.525229357798165) internal successors, (665), 436 states have internal predecessors, (665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:00,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:00,688 INFO L93 Difference]: Finished difference Result 435 states and 647 transitions. [2023-11-28 23:52:00,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 647 transitions. [2023-11-28 23:52:00,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-28 23:52:00,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 430 states and 642 transitions. [2023-11-28 23:52:00,706 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2023-11-28 23:52:00,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2023-11-28 23:52:00,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 642 transitions. [2023-11-28 23:52:00,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:00,712 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 642 transitions. [2023-11-28 23:52:00,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 642 transitions. [2023-11-28 23:52:00,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2023-11-28 23:52:00,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4930232558139536) internal successors, (642), 429 states have internal predecessors, (642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:00,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 642 transitions. [2023-11-28 23:52:00,767 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 642 transitions. [2023-11-28 23:52:00,768 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:00,772 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 642 transitions. [2023-11-28 23:52:00,772 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-28 23:52:00,772 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 642 transitions. [2023-11-28 23:52:00,776 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-28 23:52:00,777 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:00,777 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:00,780 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:00,780 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:00,781 INFO L748 eck$LassoCheckResult]: Stem: 1110#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1111#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1210#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1211#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1022#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1023#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1277#L358-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 966#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 967#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1103#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 994#L514 assume !(0 == ~M_E~0); 995#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1291#L519-1 assume !(0 == ~T2_E~0); 954#L524-1 assume !(0 == ~T3_E~0); 955#L529-1 assume !(0 == ~T4_E~0); 1079#L534-1 assume !(0 == ~E_M~0); 1255#L539-1 assume !(0 == ~E_1~0); 1256#L544-1 assume !(0 == ~E_2~0); 1275#L549-1 assume !(0 == ~E_3~0); 1276#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 949#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 950#L250 assume 1 == ~m_pc~0; 1168#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1279#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1092#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1093#L637 assume !(0 != activate_threads_~tmp~1#1); 956#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 957#L269 assume !(1 == ~t1_pc~0); 894#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 893#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 944#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 945#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1137#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1138#L288 assume 1 == ~t2_pc~0; 1231#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1134#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1215#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1216#L653 assume !(0 != activate_threads_~tmp___1~0#1); 1251#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1158#L307 assume !(1 == ~t3_pc~0); 1095#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1096#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 897#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 898#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1108#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1109#L326 assume 1 == ~t4_pc~0; 1300#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 910#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 998#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 999#L669 assume !(0 != activate_threads_~tmp___3~0#1); 1252#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1253#L572 assume !(1 == ~M_E~0); 1280#L572-2 assume !(1 == ~T1_E~0); 962#L577-1 assume !(1 == ~T2_E~0); 963#L582-1 assume !(1 == ~T3_E~0); 1235#L587-1 assume !(1 == ~T4_E~0); 1244#L592-1 assume !(1 == ~E_M~0); 901#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 902#L602-1 assume !(1 == ~E_2~0); 1130#L607-1 assume !(1 == ~E_3~0); 1131#L612-1 assume !(1 == ~E_4~0); 1077#L617-1 assume { :end_inline_reset_delta_events } true; 1078#L803-2 [2023-11-28 23:52:00,782 INFO L750 eck$LassoCheckResult]: Loop: 1078#L803-2 assume !false; 1222#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1188#L489-1 assume !false; 1189#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1159#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1008#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1074#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1224#L428 assume !(0 != eval_~tmp~0#1); 1003#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1004#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1193#L514-3 assume !(0 == ~M_E~0); 1143#L514-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1144#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1234#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1048#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1049#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 890#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 891#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1293#L549-3 assume !(0 == ~E_3~0); 1099#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1100#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1192#L250-18 assume 1 == ~m_pc~0; 1229#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1202#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1126#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1127#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1058#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 933#L269-18 assume 1 == ~t1_pc~0; 934#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1010#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1011#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1181#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1182#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1085#L288-18 assume 1 == ~t2_pc~0; 1069#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 899#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 900#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1167#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1064#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1065#L307-18 assume !(1 == ~t3_pc~0); 1031#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1032#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1102#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1045#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1046#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1262#L326-18 assume 1 == ~t4_pc~0; 1264#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1270#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1145#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 886#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 887#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1305#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1061#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1062#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 947#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 948#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1190#L592-3 assume !(1 == ~E_M~0); 1191#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1117#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1118#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1072#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1073#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1124#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1089#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1106#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1156#L822 assume !(0 == start_simulation_~tmp~3#1); 1157#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1259#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1197#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 943#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 918#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 919#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1195#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1287#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1078#L803-2 [2023-11-28 23:52:00,783 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:00,783 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2023-11-28 23:52:00,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:00,783 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406944365] [2023-11-28 23:52:00,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:00,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:00,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:00,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:00,852 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:00,852 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [406944365] [2023-11-28 23:52:00,852 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [406944365] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:00,853 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:00,853 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:00,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533608831] [2023-11-28 23:52:00,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:00,854 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:00,854 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:00,854 INFO L85 PathProgramCache]: Analyzing trace with hash -691501310, now seen corresponding path program 1 times [2023-11-28 23:52:00,855 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:00,855 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2043018962] [2023-11-28 23:52:00,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:00,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:00,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:00,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:00,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:00,935 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2043018962] [2023-11-28 23:52:00,935 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2043018962] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:00,935 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:00,935 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:00,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2056833887] [2023-11-28 23:52:00,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:00,936 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:00,936 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:00,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:00,937 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:00,937 INFO L87 Difference]: Start difference. First operand 430 states and 642 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:00,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:00,956 INFO L93 Difference]: Finished difference Result 430 states and 641 transitions. [2023-11-28 23:52:00,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 641 transitions. [2023-11-28 23:52:00,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-28 23:52:00,964 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 641 transitions. [2023-11-28 23:52:00,965 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2023-11-28 23:52:00,965 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2023-11-28 23:52:00,966 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 641 transitions. [2023-11-28 23:52:00,967 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:00,968 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 641 transitions. [2023-11-28 23:52:00,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 641 transitions. [2023-11-28 23:52:00,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2023-11-28 23:52:00,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4906976744186047) internal successors, (641), 429 states have internal predecessors, (641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:00,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 641 transitions. [2023-11-28 23:52:00,984 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 641 transitions. [2023-11-28 23:52:00,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:00,985 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 641 transitions. [2023-11-28 23:52:00,985 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-28 23:52:00,986 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 641 transitions. [2023-11-28 23:52:00,989 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-28 23:52:00,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:00,989 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:00,991 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:00,991 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:00,992 INFO L748 eck$LassoCheckResult]: Stem: 1977#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1978#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2077#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2078#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1889#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1890#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2144#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1833#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1834#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1970#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1861#L514 assume !(0 == ~M_E~0); 1862#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2158#L519-1 assume !(0 == ~T2_E~0); 1821#L524-1 assume !(0 == ~T3_E~0); 1822#L529-1 assume !(0 == ~T4_E~0); 1946#L534-1 assume !(0 == ~E_M~0); 2122#L539-1 assume !(0 == ~E_1~0); 2123#L544-1 assume !(0 == ~E_2~0); 2142#L549-1 assume !(0 == ~E_3~0); 2143#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1816#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1817#L250 assume 1 == ~m_pc~0; 2035#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2146#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1959#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1960#L637 assume !(0 != activate_threads_~tmp~1#1); 1823#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1824#L269 assume !(1 == ~t1_pc~0); 1761#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1760#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1811#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1812#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2004#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2005#L288 assume 1 == ~t2_pc~0; 2098#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2001#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2082#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2083#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2118#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2025#L307 assume !(1 == ~t3_pc~0); 1962#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1963#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1764#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1765#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1975#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1976#L326 assume 1 == ~t4_pc~0; 2167#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1777#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1865#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1866#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2119#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2120#L572 assume !(1 == ~M_E~0); 2147#L572-2 assume !(1 == ~T1_E~0); 1829#L577-1 assume !(1 == ~T2_E~0); 1830#L582-1 assume !(1 == ~T3_E~0); 2102#L587-1 assume !(1 == ~T4_E~0); 2111#L592-1 assume !(1 == ~E_M~0); 1768#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1769#L602-1 assume !(1 == ~E_2~0); 1997#L607-1 assume !(1 == ~E_3~0); 1998#L612-1 assume !(1 == ~E_4~0); 1944#L617-1 assume { :end_inline_reset_delta_events } true; 1945#L803-2 [2023-11-28 23:52:00,992 INFO L750 eck$LassoCheckResult]: Loop: 1945#L803-2 assume !false; 2089#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2055#L489-1 assume !false; 2056#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2026#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1875#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1941#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2091#L428 assume !(0 != eval_~tmp~0#1); 1870#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1871#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2060#L514-3 assume !(0 == ~M_E~0); 2010#L514-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2011#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2101#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1915#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1916#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1757#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1758#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2160#L549-3 assume !(0 == ~E_3~0); 1966#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1967#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2059#L250-18 assume 1 == ~m_pc~0; 2096#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2069#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1993#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1994#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1925#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1800#L269-18 assume 1 == ~t1_pc~0; 1801#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1877#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1878#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2048#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2049#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1952#L288-18 assume 1 == ~t2_pc~0; 1936#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1766#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1767#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2034#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1931#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1932#L307-18 assume !(1 == ~t3_pc~0); 1898#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1899#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1969#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1912#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1913#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2129#L326-18 assume !(1 == ~t4_pc~0); 2130#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 2137#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2012#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1753#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1754#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2172#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1928#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1929#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1814#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1815#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2057#L592-3 assume !(1 == ~E_M~0); 2058#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1984#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1985#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1939#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1940#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1991#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1956#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1973#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2023#L822 assume !(0 == start_simulation_~tmp~3#1); 2024#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2126#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2064#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1810#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 1785#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1786#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2062#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2154#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1945#L803-2 [2023-11-28 23:52:00,993 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:00,993 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2023-11-28 23:52:00,993 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:00,993 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125329290] [2023-11-28 23:52:00,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:00,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:01,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:01,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:01,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:01,043 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [125329290] [2023-11-28 23:52:01,043 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [125329290] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:01,043 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:01,043 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:01,044 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1037912454] [2023-11-28 23:52:01,044 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:01,044 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:01,045 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:01,045 INFO L85 PathProgramCache]: Analyzing trace with hash -1663175997, now seen corresponding path program 1 times [2023-11-28 23:52:01,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:01,045 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783651536] [2023-11-28 23:52:01,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:01,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:01,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:01,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:01,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:01,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783651536] [2023-11-28 23:52:01,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [783651536] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:01,102 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:01,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:01,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1969328196] [2023-11-28 23:52:01,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:01,103 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:01,103 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:01,104 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:01,104 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:01,104 INFO L87 Difference]: Start difference. First operand 430 states and 641 transitions. cyclomatic complexity: 212 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:01,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:01,120 INFO L93 Difference]: Finished difference Result 430 states and 640 transitions. [2023-11-28 23:52:01,120 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 640 transitions. [2023-11-28 23:52:01,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-28 23:52:01,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 640 transitions. [2023-11-28 23:52:01,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2023-11-28 23:52:01,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2023-11-28 23:52:01,129 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 640 transitions. [2023-11-28 23:52:01,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:01,130 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 640 transitions. [2023-11-28 23:52:01,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 640 transitions. [2023-11-28 23:52:01,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2023-11-28 23:52:01,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4883720930232558) internal successors, (640), 429 states have internal predecessors, (640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:01,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 640 transitions. [2023-11-28 23:52:01,141 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 640 transitions. [2023-11-28 23:52:01,141 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:01,142 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 640 transitions. [2023-11-28 23:52:01,142 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-28 23:52:01,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 640 transitions. [2023-11-28 23:52:01,146 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-28 23:52:01,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:01,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:01,148 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:01,148 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:01,149 INFO L748 eck$LassoCheckResult]: Stem: 2844#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2944#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2945#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2756#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 2757#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3011#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2700#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2701#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2837#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2728#L514 assume !(0 == ~M_E~0); 2729#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3025#L519-1 assume !(0 == ~T2_E~0); 2688#L524-1 assume !(0 == ~T3_E~0); 2689#L529-1 assume !(0 == ~T4_E~0); 2813#L534-1 assume !(0 == ~E_M~0); 2989#L539-1 assume !(0 == ~E_1~0); 2990#L544-1 assume !(0 == ~E_2~0); 3009#L549-1 assume !(0 == ~E_3~0); 3010#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2683#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2684#L250 assume 1 == ~m_pc~0; 2902#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3013#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2826#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2827#L637 assume !(0 != activate_threads_~tmp~1#1); 2690#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2691#L269 assume !(1 == ~t1_pc~0); 2628#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2627#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2678#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2679#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2871#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2872#L288 assume 1 == ~t2_pc~0; 2965#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2868#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2949#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2950#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2985#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2892#L307 assume !(1 == ~t3_pc~0); 2829#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2830#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2631#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2632#L661 assume !(0 != activate_threads_~tmp___2~0#1); 2842#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2843#L326 assume 1 == ~t4_pc~0; 3034#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2644#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2732#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2733#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2986#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2987#L572 assume !(1 == ~M_E~0); 3014#L572-2 assume !(1 == ~T1_E~0); 2696#L577-1 assume !(1 == ~T2_E~0); 2697#L582-1 assume !(1 == ~T3_E~0); 2969#L587-1 assume !(1 == ~T4_E~0); 2978#L592-1 assume !(1 == ~E_M~0); 2635#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2636#L602-1 assume !(1 == ~E_2~0); 2864#L607-1 assume !(1 == ~E_3~0); 2865#L612-1 assume !(1 == ~E_4~0); 2811#L617-1 assume { :end_inline_reset_delta_events } true; 2812#L803-2 [2023-11-28 23:52:01,149 INFO L750 eck$LassoCheckResult]: Loop: 2812#L803-2 assume !false; 2956#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2922#L489-1 assume !false; 2923#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2893#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2742#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2808#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2958#L428 assume !(0 != eval_~tmp~0#1); 2737#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2738#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2927#L514-3 assume !(0 == ~M_E~0); 2877#L514-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2878#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2968#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2782#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2783#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2624#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2625#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3027#L549-3 assume !(0 == ~E_3~0); 2833#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2834#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2926#L250-18 assume 1 == ~m_pc~0; 2963#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2936#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2860#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2861#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2792#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2667#L269-18 assume 1 == ~t1_pc~0; 2668#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2744#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2745#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2915#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2916#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2819#L288-18 assume 1 == ~t2_pc~0; 2803#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2633#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2634#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2901#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2798#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2799#L307-18 assume 1 == ~t3_pc~0; 2866#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2766#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2836#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2779#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2780#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2996#L326-18 assume !(1 == ~t4_pc~0); 2997#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 3004#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2879#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2620#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2621#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3039#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2795#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2796#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2681#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2682#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2924#L592-3 assume !(1 == ~E_M~0); 2925#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2851#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2852#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2806#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2807#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2858#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2823#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2840#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2890#L822 assume !(0 == start_simulation_~tmp~3#1); 2891#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2993#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2931#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2677#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 2652#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2653#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2929#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3021#L835 assume !(0 != start_simulation_~tmp___0~1#1); 2812#L803-2 [2023-11-28 23:52:01,150 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:01,150 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2023-11-28 23:52:01,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:01,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534723047] [2023-11-28 23:52:01,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:01,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:01,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:01,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:01,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:01,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534723047] [2023-11-28 23:52:01,190 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1534723047] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:01,190 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:01,190 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:01,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1815445302] [2023-11-28 23:52:01,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:01,191 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:01,191 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:01,192 INFO L85 PathProgramCache]: Analyzing trace with hash 1580342210, now seen corresponding path program 1 times [2023-11-28 23:52:01,192 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:01,192 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411784019] [2023-11-28 23:52:01,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:01,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:01,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:01,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:01,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:01,238 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1411784019] [2023-11-28 23:52:01,238 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1411784019] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:01,238 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:01,239 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:01,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1068316085] [2023-11-28 23:52:01,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:01,239 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:01,239 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:01,240 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:01,240 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:01,240 INFO L87 Difference]: Start difference. First operand 430 states and 640 transitions. cyclomatic complexity: 211 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:01,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:01,255 INFO L93 Difference]: Finished difference Result 430 states and 639 transitions. [2023-11-28 23:52:01,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 639 transitions. [2023-11-28 23:52:01,259 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-28 23:52:01,263 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 639 transitions. [2023-11-28 23:52:01,263 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2023-11-28 23:52:01,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2023-11-28 23:52:01,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 639 transitions. [2023-11-28 23:52:01,264 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:01,265 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 639 transitions. [2023-11-28 23:52:01,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 639 transitions. [2023-11-28 23:52:01,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2023-11-28 23:52:01,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.486046511627907) internal successors, (639), 429 states have internal predecessors, (639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:01,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 639 transitions. [2023-11-28 23:52:01,275 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 639 transitions. [2023-11-28 23:52:01,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:01,277 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 639 transitions. [2023-11-28 23:52:01,277 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-28 23:52:01,277 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 639 transitions. [2023-11-28 23:52:01,280 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-28 23:52:01,280 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:01,280 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:01,281 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:01,282 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:01,282 INFO L748 eck$LassoCheckResult]: Stem: 3711#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3712#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3811#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3812#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3623#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 3624#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3879#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3567#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3568#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3704#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3597#L514 assume !(0 == ~M_E~0); 3598#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3892#L519-1 assume !(0 == ~T2_E~0); 3555#L524-1 assume !(0 == ~T3_E~0); 3556#L529-1 assume !(0 == ~T4_E~0); 3680#L534-1 assume !(0 == ~E_M~0); 3856#L539-1 assume !(0 == ~E_1~0); 3857#L544-1 assume !(0 == ~E_2~0); 3876#L549-1 assume !(0 == ~E_3~0); 3877#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3550#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3551#L250 assume 1 == ~m_pc~0; 3769#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3880#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3693#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3694#L637 assume !(0 != activate_threads_~tmp~1#1); 3557#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3558#L269 assume !(1 == ~t1_pc~0); 3495#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3494#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3545#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3546#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3738#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3739#L288 assume 1 == ~t2_pc~0; 3832#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3735#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3816#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3817#L653 assume !(0 != activate_threads_~tmp___1~0#1); 3852#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3759#L307 assume !(1 == ~t3_pc~0); 3696#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3697#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3498#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3499#L661 assume !(0 != activate_threads_~tmp___2~0#1); 3709#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3710#L326 assume 1 == ~t4_pc~0; 3901#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3511#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3599#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3600#L669 assume !(0 != activate_threads_~tmp___3~0#1); 3853#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3854#L572 assume !(1 == ~M_E~0); 3881#L572-2 assume !(1 == ~T1_E~0); 3563#L577-1 assume !(1 == ~T2_E~0); 3564#L582-1 assume !(1 == ~T3_E~0); 3836#L587-1 assume !(1 == ~T4_E~0); 3845#L592-1 assume !(1 == ~E_M~0); 3502#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3503#L602-1 assume !(1 == ~E_2~0); 3731#L607-1 assume !(1 == ~E_3~0); 3732#L612-1 assume !(1 == ~E_4~0); 3678#L617-1 assume { :end_inline_reset_delta_events } true; 3679#L803-2 [2023-11-28 23:52:01,282 INFO L750 eck$LassoCheckResult]: Loop: 3679#L803-2 assume !false; 3823#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3789#L489-1 assume !false; 3790#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3760#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3609#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3675#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3825#L428 assume !(0 != eval_~tmp~0#1); 3604#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3605#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3794#L514-3 assume !(0 == ~M_E~0); 3744#L514-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3745#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3835#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3649#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3650#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3491#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3492#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3894#L549-3 assume !(0 == ~E_3~0); 3700#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3701#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3793#L250-18 assume 1 == ~m_pc~0; 3830#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3803#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3727#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3728#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3659#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3534#L269-18 assume !(1 == ~t1_pc~0); 3536#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3611#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3612#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3782#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3783#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3686#L288-18 assume 1 == ~t2_pc~0; 3670#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3500#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3501#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3768#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3665#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3666#L307-18 assume !(1 == ~t3_pc~0); 3632#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 3633#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3703#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3646#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3647#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3863#L326-18 assume !(1 == ~t4_pc~0); 3864#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 3871#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3746#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3487#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3488#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3906#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3662#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3663#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3548#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3549#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3791#L592-3 assume !(1 == ~E_M~0); 3792#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3718#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3719#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3673#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3674#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3725#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3690#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3707#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3757#L822 assume !(0 == start_simulation_~tmp~3#1); 3758#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3860#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3798#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3544#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 3519#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3520#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3796#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3888#L835 assume !(0 != start_simulation_~tmp___0~1#1); 3679#L803-2 [2023-11-28 23:52:01,283 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:01,283 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2023-11-28 23:52:01,283 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:01,283 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061042665] [2023-11-28 23:52:01,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:01,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:01,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:01,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:01,340 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:01,340 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2061042665] [2023-11-28 23:52:01,340 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2061042665] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:01,340 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:01,340 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 23:52:01,340 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [731355636] [2023-11-28 23:52:01,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:01,341 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:01,341 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:01,341 INFO L85 PathProgramCache]: Analyzing trace with hash 738349124, now seen corresponding path program 1 times [2023-11-28 23:52:01,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:01,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625925325] [2023-11-28 23:52:01,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:01,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:01,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:01,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:01,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:01,382 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625925325] [2023-11-28 23:52:01,382 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [625925325] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:01,382 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:01,382 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:01,383 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [789332890] [2023-11-28 23:52:01,383 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:01,383 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:01,383 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:01,384 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:01,384 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:01,384 INFO L87 Difference]: Start difference. First operand 430 states and 639 transitions. cyclomatic complexity: 210 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:01,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:01,406 INFO L93 Difference]: Finished difference Result 430 states and 634 transitions. [2023-11-28 23:52:01,406 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 634 transitions. [2023-11-28 23:52:01,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-28 23:52:01,414 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 634 transitions. [2023-11-28 23:52:01,414 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2023-11-28 23:52:01,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2023-11-28 23:52:01,415 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 634 transitions. [2023-11-28 23:52:01,415 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:01,415 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 634 transitions. [2023-11-28 23:52:01,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 634 transitions. [2023-11-28 23:52:01,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2023-11-28 23:52:01,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4744186046511627) internal successors, (634), 429 states have internal predecessors, (634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:01,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 634 transitions. [2023-11-28 23:52:01,426 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 634 transitions. [2023-11-28 23:52:01,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:01,427 INFO L428 stractBuchiCegarLoop]: Abstraction has 430 states and 634 transitions. [2023-11-28 23:52:01,427 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-28 23:52:01,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 634 transitions. [2023-11-28 23:52:01,430 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2023-11-28 23:52:01,430 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:01,430 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:01,431 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:01,432 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:01,432 INFO L748 eck$LassoCheckResult]: Stem: 4578#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4579#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4678#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4679#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4490#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 4491#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4745#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4434#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4435#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4571#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4462#L514 assume !(0 == ~M_E~0); 4463#L514-2 assume !(0 == ~T1_E~0); 4759#L519-1 assume !(0 == ~T2_E~0); 4422#L524-1 assume !(0 == ~T3_E~0); 4423#L529-1 assume !(0 == ~T4_E~0); 4547#L534-1 assume !(0 == ~E_M~0); 4723#L539-1 assume !(0 == ~E_1~0); 4724#L544-1 assume !(0 == ~E_2~0); 4743#L549-1 assume !(0 == ~E_3~0); 4744#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4417#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4418#L250 assume 1 == ~m_pc~0; 4639#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4747#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4560#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4561#L637 assume !(0 != activate_threads_~tmp~1#1); 4424#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4425#L269 assume !(1 == ~t1_pc~0); 4362#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4361#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4412#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4413#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4605#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4606#L288 assume 1 == ~t2_pc~0; 4699#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4602#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4683#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4684#L653 assume !(0 != activate_threads_~tmp___1~0#1); 4719#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4626#L307 assume !(1 == ~t3_pc~0); 4563#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4564#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4365#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4366#L661 assume !(0 != activate_threads_~tmp___2~0#1); 4576#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4577#L326 assume 1 == ~t4_pc~0; 4768#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4378#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4466#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4467#L669 assume !(0 != activate_threads_~tmp___3~0#1); 4720#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4721#L572 assume !(1 == ~M_E~0); 4748#L572-2 assume !(1 == ~T1_E~0); 4430#L577-1 assume !(1 == ~T2_E~0); 4431#L582-1 assume !(1 == ~T3_E~0); 4704#L587-1 assume !(1 == ~T4_E~0); 4713#L592-1 assume !(1 == ~E_M~0); 4369#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4370#L602-1 assume !(1 == ~E_2~0); 4598#L607-1 assume !(1 == ~E_3~0); 4599#L612-1 assume !(1 == ~E_4~0); 4545#L617-1 assume { :end_inline_reset_delta_events } true; 4546#L803-2 [2023-11-28 23:52:01,432 INFO L750 eck$LassoCheckResult]: Loop: 4546#L803-2 assume !false; 4691#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4656#L489-1 assume !false; 4657#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4627#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4476#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4542#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4692#L428 assume !(0 != eval_~tmp~0#1); 4471#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4472#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4661#L514-3 assume !(0 == ~M_E~0); 4612#L514-5 assume !(0 == ~T1_E~0); 4613#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4702#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4518#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4519#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4358#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4359#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4761#L549-3 assume !(0 == ~E_3~0); 4567#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4568#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4660#L250-18 assume 1 == ~m_pc~0; 4697#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4670#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4594#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4595#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4526#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4401#L269-18 assume 1 == ~t1_pc~0; 4402#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4478#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4479#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4649#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4650#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4553#L288-18 assume 1 == ~t2_pc~0; 4534#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4367#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4368#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4635#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4532#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4533#L307-18 assume !(1 == ~t3_pc~0); 4497#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 4498#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4570#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4510#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4511#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4730#L326-18 assume !(1 == ~t4_pc~0); 4731#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 4738#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4611#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4354#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4355#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4773#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4529#L572-5 assume !(1 == ~T1_E~0); 4530#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4415#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4416#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4658#L592-3 assume !(1 == ~E_M~0); 4659#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4585#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4586#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4540#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4541#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4592#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4557#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4573#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4624#L822 assume !(0 == start_simulation_~tmp~3#1); 4625#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4726#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4665#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4411#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 4386#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4387#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4663#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4755#L835 assume !(0 != start_simulation_~tmp___0~1#1); 4546#L803-2 [2023-11-28 23:52:01,433 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:01,433 INFO L85 PathProgramCache]: Analyzing trace with hash 1082208576, now seen corresponding path program 1 times [2023-11-28 23:52:01,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:01,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040582629] [2023-11-28 23:52:01,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:01,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:01,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:01,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:01,493 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:01,493 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040582629] [2023-11-28 23:52:01,494 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1040582629] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:01,494 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:01,494 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:01,494 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919756134] [2023-11-28 23:52:01,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:01,495 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:01,495 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:01,495 INFO L85 PathProgramCache]: Analyzing trace with hash -1861717885, now seen corresponding path program 1 times [2023-11-28 23:52:01,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:01,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284867776] [2023-11-28 23:52:01,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:01,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:01,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:01,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:01,539 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:01,540 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284867776] [2023-11-28 23:52:01,540 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [284867776] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:01,540 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:01,540 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:01,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1582481706] [2023-11-28 23:52:01,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:01,541 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:01,541 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:01,541 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-28 23:52:01,542 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-28 23:52:01,542 INFO L87 Difference]: Start difference. First operand 430 states and 634 transitions. cyclomatic complexity: 205 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:01,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:01,674 INFO L93 Difference]: Finished difference Result 720 states and 1058 transitions. [2023-11-28 23:52:01,674 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 720 states and 1058 transitions. [2023-11-28 23:52:01,681 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2023-11-28 23:52:01,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 720 states to 720 states and 1058 transitions. [2023-11-28 23:52:01,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 720 [2023-11-28 23:52:01,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 720 [2023-11-28 23:52:01,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 720 states and 1058 transitions. [2023-11-28 23:52:01,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:01,690 INFO L218 hiAutomatonCegarLoop]: Abstraction has 720 states and 1058 transitions. [2023-11-28 23:52:01,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 720 states and 1058 transitions. [2023-11-28 23:52:01,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 720 to 719. [2023-11-28 23:52:01,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 719 states, 719 states have (on average 1.4700973574408902) internal successors, (1057), 718 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:01,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 719 states to 719 states and 1057 transitions. [2023-11-28 23:52:01,709 INFO L240 hiAutomatonCegarLoop]: Abstraction has 719 states and 1057 transitions. [2023-11-28 23:52:01,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-28 23:52:01,711 INFO L428 stractBuchiCegarLoop]: Abstraction has 719 states and 1057 transitions. [2023-11-28 23:52:01,711 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-28 23:52:01,711 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 719 states and 1057 transitions. [2023-11-28 23:52:01,716 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2023-11-28 23:52:01,716 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:01,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:01,718 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:01,718 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:01,719 INFO L748 eck$LassoCheckResult]: Stem: 5741#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5742#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5848#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5849#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5650#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 5651#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5926#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5594#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5595#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5734#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5622#L514 assume !(0 == ~M_E~0); 5623#L514-2 assume !(0 == ~T1_E~0); 5946#L519-1 assume !(0 == ~T2_E~0); 5582#L524-1 assume !(0 == ~T3_E~0); 5583#L529-1 assume !(0 == ~T4_E~0); 5709#L534-1 assume !(0 == ~E_M~0); 5901#L539-1 assume !(0 == ~E_1~0); 5902#L544-1 assume !(0 == ~E_2~0); 5924#L549-1 assume !(0 == ~E_3~0); 5925#L554-1 assume !(0 == ~E_4~0); 5577#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5578#L250 assume 1 == ~m_pc~0; 5805#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5928#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5723#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5724#L637 assume !(0 != activate_threads_~tmp~1#1); 5584#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5585#L269 assume !(1 == ~t1_pc~0); 5522#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5521#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5572#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5573#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5768#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5769#L288 assume 1 == ~t2_pc~0; 5874#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5765#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5853#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5854#L653 assume !(0 != activate_threads_~tmp___1~0#1); 5897#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5791#L307 assume !(1 == ~t3_pc~0); 5726#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5727#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5525#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5526#L661 assume !(0 != activate_threads_~tmp___2~0#1); 5739#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5740#L326 assume 1 == ~t4_pc~0; 5955#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5538#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5626#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5627#L669 assume !(0 != activate_threads_~tmp___3~0#1); 5898#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5899#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 5929#L572-2 assume !(1 == ~T1_E~0); 5590#L577-1 assume !(1 == ~T2_E~0); 5591#L582-1 assume !(1 == ~T3_E~0); 5880#L587-1 assume !(1 == ~T4_E~0); 5890#L592-1 assume !(1 == ~E_M~0); 5962#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6079#L602-1 assume !(1 == ~E_2~0); 5998#L607-1 assume !(1 == ~E_3~0); 5997#L612-1 assume !(1 == ~E_4~0); 5707#L617-1 assume { :end_inline_reset_delta_events } true; 5708#L803-2 [2023-11-28 23:52:01,719 INFO L750 eck$LassoCheckResult]: Loop: 5708#L803-2 assume !false; 5861#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5862#L489-1 assume !false; 5985#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5984#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5703#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5704#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5978#L428 assume !(0 != eval_~tmp~0#1); 5977#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5938#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5939#L514-3 assume !(0 == ~M_E~0); 5777#L514-5 assume !(0 == ~T1_E~0); 5778#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5878#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5676#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5677#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5518#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5519#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5948#L549-3 assume !(0 == ~E_3~0); 5730#L554-3 assume !(0 == ~E_4~0); 5731#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5826#L250-18 assume !(1 == ~m_pc~0); 5872#L250-20 is_master_triggered_~__retres1~0#1 := 0; 5840#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5757#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5758#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5686#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5561#L269-18 assume 1 == ~t1_pc~0; 5562#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5638#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5639#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5815#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5816#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5716#L288-18 assume 1 == ~t2_pc~0; 5694#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5527#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5528#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5800#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5692#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5693#L307-18 assume 1 == ~t3_pc~0; 5763#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5658#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5733#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5670#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5671#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5909#L326-18 assume !(1 == ~t4_pc~0); 5910#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 5917#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5776#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5514#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5515#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5961#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5689#L572-5 assume !(1 == ~T1_E~0); 5690#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5715#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6135#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6134#L592-3 assume !(1 == ~E_M~0); 6133#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6132#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6131#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6130#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5701#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5755#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5720#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5736#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5789#L822 assume !(0 == start_simulation_~tmp~3#1); 5790#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5968#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5833#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5571#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 5546#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5547#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5831#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5941#L835 assume !(0 != start_simulation_~tmp___0~1#1); 5708#L803-2 [2023-11-28 23:52:01,720 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:01,720 INFO L85 PathProgramCache]: Analyzing trace with hash -516249280, now seen corresponding path program 1 times [2023-11-28 23:52:01,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:01,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822580676] [2023-11-28 23:52:01,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:01,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:01,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:01,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:01,761 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:01,761 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1822580676] [2023-11-28 23:52:01,762 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1822580676] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:01,762 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:01,762 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 23:52:01,762 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1731705259] [2023-11-28 23:52:01,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:01,763 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:01,763 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:01,763 INFO L85 PathProgramCache]: Analyzing trace with hash -1800160059, now seen corresponding path program 1 times [2023-11-28 23:52:01,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:01,764 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [852638569] [2023-11-28 23:52:01,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:01,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:01,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:01,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:01,801 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:01,801 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [852638569] [2023-11-28 23:52:01,802 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [852638569] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:01,802 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:01,802 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:01,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1401811752] [2023-11-28 23:52:01,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:01,803 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:01,803 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:01,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:01,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:01,804 INFO L87 Difference]: Start difference. First operand 719 states and 1057 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:01,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:01,864 INFO L93 Difference]: Finished difference Result 1344 states and 1952 transitions. [2023-11-28 23:52:01,865 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1344 states and 1952 transitions. [2023-11-28 23:52:01,876 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1264 [2023-11-28 23:52:01,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1344 states to 1344 states and 1952 transitions. [2023-11-28 23:52:01,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1344 [2023-11-28 23:52:01,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1344 [2023-11-28 23:52:01,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1344 states and 1952 transitions. [2023-11-28 23:52:01,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:01,893 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1344 states and 1952 transitions. [2023-11-28 23:52:01,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1344 states and 1952 transitions. [2023-11-28 23:52:01,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1344 to 1276. [2023-11-28 23:52:01,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1276 states, 1276 states have (on average 1.4561128526645768) internal successors, (1858), 1275 states have internal predecessors, (1858), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:01,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1276 states to 1276 states and 1858 transitions. [2023-11-28 23:52:01,929 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1276 states and 1858 transitions. [2023-11-28 23:52:01,930 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:01,930 INFO L428 stractBuchiCegarLoop]: Abstraction has 1276 states and 1858 transitions. [2023-11-28 23:52:01,930 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-28 23:52:01,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1276 states and 1858 transitions. [2023-11-28 23:52:01,939 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1196 [2023-11-28 23:52:01,939 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:01,939 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:01,940 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:01,940 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:01,941 INFO L748 eck$LassoCheckResult]: Stem: 7820#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7821#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7945#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7946#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7720#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 7721#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8043#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7664#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7665#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7812#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7692#L514 assume !(0 == ~M_E~0); 7693#L514-2 assume !(0 == ~T1_E~0); 8073#L519-1 assume !(0 == ~T2_E~0); 7652#L524-1 assume !(0 == ~T3_E~0); 7653#L529-1 assume !(0 == ~T4_E~0); 7783#L534-1 assume !(0 == ~E_M~0); 8005#L539-1 assume !(0 == ~E_1~0); 8006#L544-1 assume !(0 == ~E_2~0); 8041#L549-1 assume !(0 == ~E_3~0); 8042#L554-1 assume !(0 == ~E_4~0); 7647#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7648#L250 assume !(1 == ~m_pc~0); 7894#L250-2 is_master_triggered_~__retres1~0#1 := 0; 8045#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7797#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7798#L637 assume !(0 != activate_threads_~tmp~1#1); 7654#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7655#L269 assume !(1 == ~t1_pc~0); 7592#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7591#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7642#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7643#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7857#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7858#L288 assume 1 == ~t2_pc~0; 7975#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7847#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7952#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7953#L653 assume !(0 != activate_threads_~tmp___1~0#1); 8000#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7882#L307 assume !(1 == ~t3_pc~0); 7800#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7801#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7595#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7596#L661 assume !(0 != activate_threads_~tmp___2~0#1); 7818#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7819#L326 assume 1 == ~t4_pc~0; 8084#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7608#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7696#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7697#L669 assume !(0 != activate_threads_~tmp___3~0#1); 8002#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8003#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 8046#L572-2 assume !(1 == ~T1_E~0); 7660#L577-1 assume !(1 == ~T2_E~0); 7661#L582-1 assume !(1 == ~T3_E~0); 7983#L587-1 assume !(1 == ~T4_E~0); 7993#L592-1 assume !(1 == ~E_M~0); 7599#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7600#L602-1 assume !(1 == ~E_2~0); 7843#L607-1 assume !(1 == ~E_3~0); 7844#L612-1 assume !(1 == ~E_4~0); 8127#L617-1 assume { :end_inline_reset_delta_events } true; 8466#L803-2 [2023-11-28 23:52:01,941 INFO L750 eck$LassoCheckResult]: Loop: 8466#L803-2 assume !false; 8187#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8188#L489-1 assume !false; 8444#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7883#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7706#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7962#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7963#L428 assume !(0 != eval_~tmp~0#1); 8434#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8819#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8817#L514-3 assume !(0 == ~M_E~0); 8815#L514-5 assume !(0 == ~T1_E~0); 8813#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8811#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8809#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8807#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8804#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8802#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8800#L549-3 assume !(0 == ~E_3~0); 8798#L554-3 assume !(0 == ~E_4~0); 8748#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8016#L250-18 assume !(1 == ~m_pc~0); 8017#L250-20 is_master_triggered_~__retres1~0#1 := 0; 8766#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8763#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8762#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8761#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8760#L269-18 assume 1 == ~t1_pc~0; 8758#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8757#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8756#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8755#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8754#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8753#L288-18 assume 1 == ~t2_pc~0; 8752#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8750#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8749#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7891#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7764#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7765#L307-18 assume !(1 == ~t3_pc~0); 7729#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 7730#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7811#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7744#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7745#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8018#L326-18 assume !(1 == ~t4_pc~0); 8019#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 8425#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8424#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8423#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8422#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8421#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8420#L572-5 assume !(1 == ~T1_E~0); 8416#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7645#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7646#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7918#L592-3 assume !(1 == ~E_M~0); 7919#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8410#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8409#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8407#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8408#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8204#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8192#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8186#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7880#L822 assume !(0 == start_simulation_~tmp~3#1); 7881#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8337#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8331#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8328#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 8326#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8325#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8322#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 8323#L835 assume !(0 != start_simulation_~tmp___0~1#1); 8466#L803-2 [2023-11-28 23:52:01,941 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:01,941 INFO L85 PathProgramCache]: Analyzing trace with hash -1001423999, now seen corresponding path program 1 times [2023-11-28 23:52:01,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:01,942 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794453204] [2023-11-28 23:52:01,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:01,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:01,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:02,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:02,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:02,031 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1794453204] [2023-11-28 23:52:02,032 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1794453204] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:02,032 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:02,032 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 23:52:02,032 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181873905] [2023-11-28 23:52:02,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:02,033 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:02,033 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:02,033 INFO L85 PathProgramCache]: Analyzing trace with hash -748710970, now seen corresponding path program 1 times [2023-11-28 23:52:02,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:02,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [79997804] [2023-11-28 23:52:02,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:02,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:02,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:02,070 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:02,070 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:02,070 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [79997804] [2023-11-28 23:52:02,071 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [79997804] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:02,071 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:02,071 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:02,071 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1749302229] [2023-11-28 23:52:02,071 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:02,072 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:02,072 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:02,072 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-28 23:52:02,072 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-28 23:52:02,073 INFO L87 Difference]: Start difference. First operand 1276 states and 1858 transitions. cyclomatic complexity: 586 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:02,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:02,302 INFO L93 Difference]: Finished difference Result 2962 states and 4255 transitions. [2023-11-28 23:52:02,302 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2962 states and 4255 transitions. [2023-11-28 23:52:02,325 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2810 [2023-11-28 23:52:02,348 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2962 states to 2962 states and 4255 transitions. [2023-11-28 23:52:02,349 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2962 [2023-11-28 23:52:02,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2962 [2023-11-28 23:52:02,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2962 states and 4255 transitions. [2023-11-28 23:52:02,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:02,357 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2962 states and 4255 transitions. [2023-11-28 23:52:02,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2962 states and 4255 transitions. [2023-11-28 23:52:02,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2962 to 1345. [2023-11-28 23:52:02,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1345 states, 1345 states have (on average 1.4327137546468403) internal successors, (1927), 1344 states have internal predecessors, (1927), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:02,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1345 states to 1345 states and 1927 transitions. [2023-11-28 23:52:02,401 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1345 states and 1927 transitions. [2023-11-28 23:52:02,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-28 23:52:02,402 INFO L428 stractBuchiCegarLoop]: Abstraction has 1345 states and 1927 transitions. [2023-11-28 23:52:02,402 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-28 23:52:02,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1345 states and 1927 transitions. [2023-11-28 23:52:02,411 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1262 [2023-11-28 23:52:02,411 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:02,411 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:02,412 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:02,412 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:02,412 INFO L748 eck$LassoCheckResult]: Stem: 12077#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 12078#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 12201#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12202#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11979#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 11980#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12292#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11918#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11919#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12068#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11949#L514 assume !(0 == ~M_E~0); 11950#L514-2 assume !(0 == ~T1_E~0); 12319#L519-1 assume !(0 == ~T2_E~0); 11906#L524-1 assume !(0 == ~T3_E~0); 11907#L529-1 assume !(0 == ~T4_E~0); 12040#L534-1 assume !(0 == ~E_M~0); 12258#L539-1 assume !(0 == ~E_1~0); 12259#L544-1 assume !(0 == ~E_2~0); 12290#L549-1 assume !(0 == ~E_3~0); 12291#L554-1 assume !(0 == ~E_4~0); 11901#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11902#L250 assume !(1 == ~m_pc~0); 12148#L250-2 is_master_triggered_~__retres1~0#1 := 0; 12294#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12056#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12057#L637 assume !(0 != activate_threads_~tmp~1#1); 11908#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11909#L269 assume !(1 == ~t1_pc~0); 11843#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12035#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12159#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12320#L645 assume !(0 != activate_threads_~tmp___0~0#1); 12111#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12112#L288 assume 1 == ~t2_pc~0; 12229#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12104#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12207#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12208#L653 assume !(0 != activate_threads_~tmp___1~0#1); 12254#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12136#L307 assume !(1 == ~t3_pc~0); 12059#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12060#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11846#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11847#L661 assume !(0 != activate_threads_~tmp___2~0#1); 12075#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12076#L326 assume 1 == ~t4_pc~0; 12334#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11861#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11953#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11954#L669 assume !(0 != activate_threads_~tmp___3~0#1); 12255#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12256#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 12295#L572-2 assume !(1 == ~T1_E~0); 11914#L577-1 assume !(1 == ~T2_E~0); 11915#L582-1 assume !(1 == ~T3_E~0); 12235#L587-1 assume !(1 == ~T4_E~0); 12246#L592-1 assume !(1 == ~E_M~0); 11850#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11851#L602-1 assume !(1 == ~E_2~0); 12100#L607-1 assume !(1 == ~E_3~0); 12101#L612-1 assume !(1 == ~E_4~0); 12375#L617-1 assume { :end_inline_reset_delta_events } true; 12390#L803-2 [2023-11-28 23:52:02,413 INFO L750 eck$LassoCheckResult]: Loop: 12390#L803-2 assume !false; 12391#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12171#L489-1 assume !false; 12172#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12137#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11964#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12218#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12219#L428 assume !(0 != eval_~tmp~0#1); 12632#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12631#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12630#L514-3 assume !(0 == ~M_E~0); 12624#L514-5 assume !(0 == ~T1_E~0); 12625#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12613#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12614#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12145#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12146#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12322#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12323#L549-3 assume !(0 == ~E_3~0); 12063#L554-3 assume !(0 == ~E_4~0); 12064#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12176#L250-18 assume !(1 == ~m_pc~0); 12266#L250-20 is_master_triggered_~__retres1~0#1 := 0; 12922#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12921#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12920#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12919#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12918#L269-18 assume 1 == ~t1_pc~0; 12916#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12914#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12912#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12910#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12908#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12906#L288-18 assume !(1 == ~t2_pc~0); 12903#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 12889#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12887#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12885#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12882#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12880#L307-18 assume 1 == ~t3_pc~0; 12877#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12875#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12873#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12871#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12868#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12866#L326-18 assume 1 == ~t4_pc~0; 12864#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12784#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12626#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12627#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12552#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12553#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12472#L572-5 assume !(1 == ~T1_E~0); 12473#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12464#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12465#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12453#L592-3 assume !(1 == ~E_M~0); 12454#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12439#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12440#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12426#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12427#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12415#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12407#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12406#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 12134#L822 assume !(0 == start_simulation_~tmp~3#1); 12135#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12263#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12643#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12642#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 12641#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12640#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12639#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 12638#L835 assume !(0 != start_simulation_~tmp___0~1#1); 12390#L803-2 [2023-11-28 23:52:02,413 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:02,413 INFO L85 PathProgramCache]: Analyzing trace with hash -299824125, now seen corresponding path program 1 times [2023-11-28 23:52:02,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:02,414 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2124197423] [2023-11-28 23:52:02,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:02,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:02,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:02,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:02,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:02,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2124197423] [2023-11-28 23:52:02,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2124197423] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:02,455 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:02,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 23:52:02,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [594018865] [2023-11-28 23:52:02,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:02,456 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:02,457 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:02,457 INFO L85 PathProgramCache]: Analyzing trace with hash -1313660091, now seen corresponding path program 1 times [2023-11-28 23:52:02,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:02,457 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1538207824] [2023-11-28 23:52:02,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:02,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:02,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:02,492 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:02,492 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:02,492 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1538207824] [2023-11-28 23:52:02,492 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1538207824] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:02,493 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:02,493 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:02,493 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [210057918] [2023-11-28 23:52:02,493 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:02,493 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:02,493 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:02,494 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:02,494 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:02,494 INFO L87 Difference]: Start difference. First operand 1345 states and 1927 transitions. cyclomatic complexity: 586 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:02,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:02,555 INFO L93 Difference]: Finished difference Result 2430 states and 3458 transitions. [2023-11-28 23:52:02,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2430 states and 3458 transitions. [2023-11-28 23:52:02,574 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2336 [2023-11-28 23:52:02,593 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2430 states to 2430 states and 3458 transitions. [2023-11-28 23:52:02,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2430 [2023-11-28 23:52:02,596 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2430 [2023-11-28 23:52:02,596 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2430 states and 3458 transitions. [2023-11-28 23:52:02,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:02,600 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2430 states and 3458 transitions. [2023-11-28 23:52:02,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2430 states and 3458 transitions. [2023-11-28 23:52:02,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2430 to 2422. [2023-11-28 23:52:02,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2422 states, 2422 states have (on average 1.4244426094137077) internal successors, (3450), 2421 states have internal predecessors, (3450), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:02,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2422 states to 2422 states and 3450 transitions. [2023-11-28 23:52:02,673 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2422 states and 3450 transitions. [2023-11-28 23:52:02,673 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:02,674 INFO L428 stractBuchiCegarLoop]: Abstraction has 2422 states and 3450 transitions. [2023-11-28 23:52:02,674 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-28 23:52:02,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2422 states and 3450 transitions. [2023-11-28 23:52:02,689 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2328 [2023-11-28 23:52:02,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:02,689 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:02,690 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:02,690 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:02,691 INFO L748 eck$LassoCheckResult]: Stem: 15847#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 15848#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 15957#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15958#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15753#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 15754#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16051#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15698#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15699#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15839#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15724#L514 assume !(0 == ~M_E~0); 15725#L514-2 assume !(0 == ~T1_E~0); 16070#L519-1 assume !(0 == ~T2_E~0); 15686#L524-1 assume !(0 == ~T3_E~0); 15687#L529-1 assume !(0 == ~T4_E~0); 15813#L534-1 assume !(0 == ~E_M~0); 16019#L539-1 assume !(0 == ~E_1~0); 16020#L544-1 assume !(0 == ~E_2~0); 16049#L549-1 assume !(0 == ~E_3~0); 16050#L554-1 assume !(0 == ~E_4~0); 15681#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15682#L250 assume !(1 == ~m_pc~0); 15912#L250-2 is_master_triggered_~__retres1~0#1 := 0; 16053#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15828#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15829#L637 assume !(0 != activate_threads_~tmp~1#1); 15688#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15689#L269 assume !(1 == ~t1_pc~0); 15625#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15808#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16139#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16071#L645 assume !(0 != activate_threads_~tmp___0~0#1); 15878#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15879#L288 assume !(1 == ~t2_pc~0); 15870#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15871#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15966#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15967#L653 assume !(0 != activate_threads_~tmp___1~0#1); 16014#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15903#L307 assume !(1 == ~t3_pc~0); 15831#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15832#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15628#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15629#L661 assume !(0 != activate_threads_~tmp___2~0#1); 15845#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15846#L326 assume 1 == ~t4_pc~0; 16087#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15641#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15728#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15729#L669 assume !(0 != activate_threads_~tmp___3~0#1); 16016#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16017#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 16054#L572-2 assume !(1 == ~T1_E~0); 17591#L577-1 assume !(1 == ~T2_E~0); 17589#L582-1 assume !(1 == ~T3_E~0); 17587#L587-1 assume !(1 == ~T4_E~0); 16098#L592-1 assume !(1 == ~E_M~0); 16099#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16122#L602-1 assume !(1 == ~E_2~0); 15867#L607-1 assume !(1 == ~E_3~0); 15868#L612-1 assume !(1 == ~E_4~0); 16125#L617-1 assume { :end_inline_reset_delta_events } true; 17488#L803-2 [2023-11-28 23:52:02,691 INFO L750 eck$LassoCheckResult]: Loop: 17488#L803-2 assume !false; 17480#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17478#L489-1 assume !false; 17476#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 15904#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 15739#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 15807#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15980#L428 assume !(0 != eval_~tmp~0#1); 16126#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17802#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17799#L514-3 assume !(0 == ~M_E~0); 17797#L514-5 assume !(0 == ~T1_E~0); 17795#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17792#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17790#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17788#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17786#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17784#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17782#L549-3 assume !(0 == ~E_3~0); 17779#L554-3 assume !(0 == ~E_4~0); 17777#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17758#L250-18 assume !(1 == ~m_pc~0); 17756#L250-20 is_master_triggered_~__retres1~0#1 := 0; 17753#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17752#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17749#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17748#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17747#L269-18 assume !(1 == ~t1_pc~0); 17745#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 17743#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17741#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17740#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 17738#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17737#L288-18 assume !(1 == ~t2_pc~0); 17734#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 17729#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17727#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17725#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17724#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17723#L307-18 assume 1 == ~t3_pc~0; 17721#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17720#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17719#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17718#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17717#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17716#L326-18 assume !(1 == ~t4_pc~0); 17714#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 17713#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17711#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17709#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17707#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17705#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17630#L572-5 assume !(1 == ~T1_E~0); 17702#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17700#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17698#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17696#L592-3 assume !(1 == ~E_M~0); 17694#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17692#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17690#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17688#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17615#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 17685#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 17659#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 17612#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 17595#L822 assume !(0 == start_simulation_~tmp~3#1); 16015#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 17530#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 17508#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 17504#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 17502#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17500#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17499#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 17491#L835 assume !(0 != start_simulation_~tmp___0~1#1); 17488#L803-2 [2023-11-28 23:52:02,691 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:02,691 INFO L85 PathProgramCache]: Analyzing trace with hash -1271498812, now seen corresponding path program 1 times [2023-11-28 23:52:02,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:02,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1474140408] [2023-11-28 23:52:02,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:02,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:02,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:02,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:02,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:02,735 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1474140408] [2023-11-28 23:52:02,735 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1474140408] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:02,735 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:02,735 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 23:52:02,736 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1204115052] [2023-11-28 23:52:02,736 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:02,736 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:02,736 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:02,737 INFO L85 PathProgramCache]: Analyzing trace with hash -781202935, now seen corresponding path program 1 times [2023-11-28 23:52:02,737 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:02,737 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847204603] [2023-11-28 23:52:02,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:02,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:02,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:02,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:02,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:02,772 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1847204603] [2023-11-28 23:52:02,772 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1847204603] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:02,772 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:02,772 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:02,772 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1751431531] [2023-11-28 23:52:02,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:02,773 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:02,773 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:02,773 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:02,774 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:02,774 INFO L87 Difference]: Start difference. First operand 2422 states and 3450 transitions. cyclomatic complexity: 1036 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:02,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:02,844 INFO L93 Difference]: Finished difference Result 4413 states and 6255 transitions. [2023-11-28 23:52:02,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4413 states and 6255 transitions. [2023-11-28 23:52:02,871 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4288 [2023-11-28 23:52:02,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4413 states to 4413 states and 6255 transitions. [2023-11-28 23:52:02,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4413 [2023-11-28 23:52:02,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4413 [2023-11-28 23:52:02,910 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4413 states and 6255 transitions. [2023-11-28 23:52:02,916 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:02,917 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4413 states and 6255 transitions. [2023-11-28 23:52:02,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4413 states and 6255 transitions. [2023-11-28 23:52:02,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4413 to 4397. [2023-11-28 23:52:03,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4397 states, 4397 states have (on average 1.4189219922674552) internal successors, (6239), 4396 states have internal predecessors, (6239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:03,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4397 states to 4397 states and 6239 transitions. [2023-11-28 23:52:03,020 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4397 states and 6239 transitions. [2023-11-28 23:52:03,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:03,021 INFO L428 stractBuchiCegarLoop]: Abstraction has 4397 states and 6239 transitions. [2023-11-28 23:52:03,021 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-28 23:52:03,021 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4397 states and 6239 transitions. [2023-11-28 23:52:03,040 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4272 [2023-11-28 23:52:03,040 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:03,040 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:03,041 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:03,041 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:03,042 INFO L748 eck$LassoCheckResult]: Stem: 22688#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 22689#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 22795#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22796#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22598#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 22599#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22880#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22542#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22543#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22681#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22569#L514 assume !(0 == ~M_E~0); 22570#L514-2 assume !(0 == ~T1_E~0); 22900#L519-1 assume !(0 == ~T2_E~0); 22528#L524-1 assume !(0 == ~T3_E~0); 22529#L529-1 assume !(0 == ~T4_E~0); 22656#L534-1 assume !(0 == ~E_M~0); 22852#L539-1 assume !(0 == ~E_1~0); 22853#L544-1 assume !(0 == ~E_2~0); 22878#L549-1 assume !(0 == ~E_3~0); 22879#L554-1 assume !(0 == ~E_4~0); 22523#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22524#L250 assume !(1 == ~m_pc~0); 22751#L250-2 is_master_triggered_~__retres1~0#1 := 0; 22882#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22669#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22670#L637 assume !(0 != activate_threads_~tmp~1#1); 22530#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22531#L269 assume !(1 == ~t1_pc~0); 22467#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22651#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22969#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22901#L645 assume !(0 != activate_threads_~tmp___0~0#1); 22717#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22718#L288 assume !(1 == ~t2_pc~0); 22711#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22712#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22803#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22804#L653 assume !(0 != activate_threads_~tmp___1~0#1); 22847#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22741#L307 assume !(1 == ~t3_pc~0); 22672#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22673#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22470#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22471#L661 assume !(0 != activate_threads_~tmp___2~0#1); 22686#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22687#L326 assume !(1 == ~t4_pc~0); 22482#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22483#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22573#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22574#L669 assume !(0 != activate_threads_~tmp___3~0#1); 22849#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22850#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 22883#L572-2 assume !(1 == ~T1_E~0); 26079#L577-1 assume !(1 == ~T2_E~0); 26078#L582-1 assume !(1 == ~T3_E~0); 26077#L587-1 assume !(1 == ~T4_E~0); 26076#L592-1 assume !(1 == ~E_M~0); 26075#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 26074#L602-1 assume !(1 == ~E_2~0); 26073#L607-1 assume !(1 == ~E_3~0); 26072#L612-1 assume !(1 == ~E_4~0); 22960#L617-1 assume { :end_inline_reset_delta_events } true; 26051#L803-2 [2023-11-28 23:52:03,042 INFO L750 eck$LassoCheckResult]: Loop: 26051#L803-2 assume !false; 26025#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26023#L489-1 assume !false; 26021#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 26014#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 26000#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 25999#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25985#L428 assume !(0 != eval_~tmp~0#1); 25986#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26650#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26649#L514-3 assume !(0 == ~M_E~0); 26648#L514-5 assume !(0 == ~T1_E~0); 26221#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26220#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26219#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26218#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26217#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26216#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26215#L549-3 assume !(0 == ~E_3~0); 26213#L554-3 assume !(0 == ~E_4~0); 26212#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26211#L250-18 assume !(1 == ~m_pc~0); 26210#L250-20 is_master_triggered_~__retres1~0#1 := 0; 26209#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26207#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26206#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26205#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26204#L269-18 assume !(1 == ~t1_pc~0); 26200#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 26198#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26196#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26194#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 26191#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26189#L288-18 assume !(1 == ~t2_pc~0); 26187#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 26185#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26183#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26181#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26179#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26177#L307-18 assume 1 == ~t3_pc~0; 26174#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26172#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26170#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26168#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26166#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26164#L326-18 assume !(1 == ~t4_pc~0); 26160#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 26158#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26156#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26154#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26151#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26149#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26123#L572-5 assume !(1 == ~T1_E~0); 26146#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26144#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26142#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26140#L592-3 assume !(1 == ~E_M~0); 26103#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26101#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26098#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26096#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26093#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 26091#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 26085#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 26083#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 26081#L822 assume !(0 == start_simulation_~tmp~3#1); 22848#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 26069#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 26063#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 26061#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 26059#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26057#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26055#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 26053#L835 assume !(0 != start_simulation_~tmp___0~1#1); 26051#L803-2 [2023-11-28 23:52:03,042 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:03,042 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2023-11-28 23:52:03,043 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:03,043 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745360236] [2023-11-28 23:52:03,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:03,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:03,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:03,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:03,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:03,089 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745360236] [2023-11-28 23:52:03,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1745360236] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:03,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:03,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 23:52:03,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [557320557] [2023-11-28 23:52:03,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:03,090 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:03,090 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:03,090 INFO L85 PathProgramCache]: Analyzing trace with hash -781202935, now seen corresponding path program 2 times [2023-11-28 23:52:03,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:03,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494733440] [2023-11-28 23:52:03,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:03,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:03,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:03,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:03,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:03,166 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494733440] [2023-11-28 23:52:03,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1494733440] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:03,166 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:03,166 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:03,166 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414678041] [2023-11-28 23:52:03,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:03,166 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:03,167 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:03,167 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:03,167 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:03,167 INFO L87 Difference]: Start difference. First operand 4397 states and 6239 transitions. cyclomatic complexity: 1858 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:03,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:03,228 INFO L93 Difference]: Finished difference Result 6588 states and 9333 transitions. [2023-11-28 23:52:03,228 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6588 states and 9333 transitions. [2023-11-28 23:52:03,264 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6448 [2023-11-28 23:52:03,309 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6588 states to 6588 states and 9333 transitions. [2023-11-28 23:52:03,309 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6588 [2023-11-28 23:52:03,317 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6588 [2023-11-28 23:52:03,317 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6588 states and 9333 transitions. [2023-11-28 23:52:03,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:03,327 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6588 states and 9333 transitions. [2023-11-28 23:52:03,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6588 states and 9333 transitions. [2023-11-28 23:52:03,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6588 to 4775. [2023-11-28 23:52:03,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4775 states, 4775 states have (on average 1.4157068062827225) internal successors, (6760), 4774 states have internal predecessors, (6760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:03,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4775 states to 4775 states and 6760 transitions. [2023-11-28 23:52:03,440 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4775 states and 6760 transitions. [2023-11-28 23:52:03,440 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:03,440 INFO L428 stractBuchiCegarLoop]: Abstraction has 4775 states and 6760 transitions. [2023-11-28 23:52:03,441 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-28 23:52:03,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4775 states and 6760 transitions. [2023-11-28 23:52:03,460 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4660 [2023-11-28 23:52:03,460 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:03,460 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:03,462 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:03,462 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:03,462 INFO L748 eck$LassoCheckResult]: Stem: 33679#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 33680#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 33785#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33786#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33590#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 33591#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33863#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33532#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33533#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33671#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33563#L514 assume !(0 == ~M_E~0); 33564#L514-2 assume !(0 == ~T1_E~0); 33884#L519-1 assume !(0 == ~T2_E~0); 33520#L524-1 assume !(0 == ~T3_E~0); 33521#L529-1 assume !(0 == ~T4_E~0); 33647#L534-1 assume !(0 == ~E_M~0); 33837#L539-1 assume !(0 == ~E_1~0); 33838#L544-1 assume !(0 == ~E_2~0); 33860#L549-1 assume !(0 == ~E_3~0); 33861#L554-1 assume !(0 == ~E_4~0); 33515#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33516#L250 assume !(1 == ~m_pc~0); 33741#L250-2 is_master_triggered_~__retres1~0#1 := 0; 33864#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33660#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33661#L637 assume !(0 != activate_threads_~tmp~1#1); 33522#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33523#L269 assume !(1 == ~t1_pc~0); 33459#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33642#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33927#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33885#L645 assume !(0 != activate_threads_~tmp___0~0#1); 33708#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33709#L288 assume !(1 == ~t2_pc~0); 33704#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33705#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33792#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33793#L653 assume !(0 != activate_threads_~tmp___1~0#1); 33832#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33731#L307 assume !(1 == ~t3_pc~0); 33663#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33664#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33462#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33463#L661 assume !(0 != activate_threads_~tmp___2~0#1); 33677#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33678#L326 assume !(1 == ~t4_pc~0); 33474#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33475#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33565#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33566#L669 assume !(0 != activate_threads_~tmp___3~0#1); 33834#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33835#L572 assume !(1 == ~M_E~0); 33865#L572-2 assume !(1 == ~T1_E~0); 33528#L577-1 assume !(1 == ~T2_E~0); 33529#L582-1 assume !(1 == ~T3_E~0); 33816#L587-1 assume !(1 == ~T4_E~0); 33825#L592-1 assume !(1 == ~E_M~0); 33468#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 33469#L602-1 assume !(1 == ~E_2~0); 33701#L607-1 assume !(1 == ~E_3~0); 33702#L612-1 assume !(1 == ~E_4~0); 33645#L617-1 assume { :end_inline_reset_delta_events } true; 33646#L803-2 [2023-11-28 23:52:03,462 INFO L750 eck$LassoCheckResult]: Loop: 33646#L803-2 assume !false; 36824#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36818#L489-1 assume !false; 36815#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 36813#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 36805#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 36802#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 36797#L428 assume !(0 != eval_~tmp~0#1); 36790#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36789#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36788#L514-3 assume !(0 == ~M_E~0); 36787#L514-5 assume !(0 == ~T1_E~0); 36785#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36783#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36781#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36715#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36712#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36710#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36708#L549-3 assume !(0 == ~E_3~0); 36706#L554-3 assume !(0 == ~E_4~0); 36704#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36693#L250-18 assume !(1 == ~m_pc~0); 36643#L250-20 is_master_triggered_~__retres1~0#1 := 0; 36634#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36627#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 36619#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36612#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36607#L269-18 assume 1 == ~t1_pc~0; 36604#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36601#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36594#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 36591#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36589#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36586#L288-18 assume !(1 == ~t2_pc~0); 36584#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 36582#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36580#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 36578#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36576#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36574#L307-18 assume 1 == ~t3_pc~0; 36571#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36569#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36567#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 36565#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36563#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36561#L326-18 assume !(1 == ~t4_pc~0); 36559#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 36557#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36554#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 36552#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36550#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36548#L572-3 assume !(1 == ~M_E~0); 35021#L572-5 assume !(1 == ~T1_E~0); 36545#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36542#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36539#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36536#L592-3 assume !(1 == ~E_M~0); 36533#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36531#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36529#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36527#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36525#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 36523#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 36517#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 36516#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 36399#L822 assume !(0 == start_simulation_~tmp~3#1); 36400#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 36908#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 36901#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 36889#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 36852#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 36849#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36847#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 36839#L835 assume !(0 != start_simulation_~tmp___0~1#1); 33646#L803-2 [2023-11-28 23:52:03,463 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:03,463 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2023-11-28 23:52:03,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:03,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15301814] [2023-11-28 23:52:03,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:03,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:03,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:03,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:03,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:03,519 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [15301814] [2023-11-28 23:52:03,519 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [15301814] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:03,519 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:03,519 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:03,519 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [29036576] [2023-11-28 23:52:03,520 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:03,520 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:03,520 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:03,520 INFO L85 PathProgramCache]: Analyzing trace with hash 204194184, now seen corresponding path program 1 times [2023-11-28 23:52:03,521 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:03,521 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747076837] [2023-11-28 23:52:03,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:03,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:03,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:03,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:03,577 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:03,577 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [747076837] [2023-11-28 23:52:03,577 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [747076837] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:03,577 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:03,577 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:03,577 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [208218334] [2023-11-28 23:52:03,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:03,578 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:03,578 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:03,578 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-28 23:52:03,578 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-28 23:52:03,579 INFO L87 Difference]: Start difference. First operand 4775 states and 6760 transitions. cyclomatic complexity: 1993 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:03,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:03,715 INFO L93 Difference]: Finished difference Result 6527 states and 9077 transitions. [2023-11-28 23:52:03,715 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6527 states and 9077 transitions. [2023-11-28 23:52:03,753 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 6310 [2023-11-28 23:52:03,794 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6527 states to 6527 states and 9077 transitions. [2023-11-28 23:52:03,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6527 [2023-11-28 23:52:03,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6527 [2023-11-28 23:52:03,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6527 states and 9077 transitions. [2023-11-28 23:52:03,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:03,814 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6527 states and 9077 transitions. [2023-11-28 23:52:03,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6527 states and 9077 transitions. [2023-11-28 23:52:03,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6527 to 5362. [2023-11-28 23:52:03,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5362 states, 5362 states have (on average 1.3979858261842597) internal successors, (7496), 5361 states have internal predecessors, (7496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:03,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5362 states to 5362 states and 7496 transitions. [2023-11-28 23:52:03,948 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5362 states and 7496 transitions. [2023-11-28 23:52:03,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-28 23:52:03,949 INFO L428 stractBuchiCegarLoop]: Abstraction has 5362 states and 7496 transitions. [2023-11-28 23:52:03,949 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-28 23:52:03,949 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5362 states and 7496 transitions. [2023-11-28 23:52:03,968 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5204 [2023-11-28 23:52:03,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:03,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:03,970 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:03,970 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:03,970 INFO L748 eck$LassoCheckResult]: Stem: 44990#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 44991#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 45098#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45099#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44901#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 44902#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45176#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44842#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44843#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44982#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44872#L514 assume !(0 == ~M_E~0); 44873#L514-2 assume !(0 == ~T1_E~0); 45196#L519-1 assume !(0 == ~T2_E~0); 44830#L524-1 assume !(0 == ~T3_E~0); 44831#L529-1 assume !(0 == ~T4_E~0); 44957#L534-1 assume !(0 == ~E_M~0); 45150#L539-1 assume 0 == ~E_1~0;~E_1~0 := 1; 45151#L544-1 assume !(0 == ~E_2~0); 45174#L549-1 assume !(0 == ~E_3~0); 45175#L554-1 assume !(0 == ~E_4~0); 44825#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44826#L250 assume !(1 == ~m_pc~0); 45178#L250-2 is_master_triggered_~__retres1~0#1 := 0; 45179#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45279#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 45278#L637 assume !(0 != activate_threads_~tmp~1#1); 45277#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44854#L269 assume !(1 == ~t1_pc~0); 44855#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45281#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45280#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45273#L645 assume !(0 != activate_threads_~tmp___0~0#1); 45272#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45271#L288 assume !(1 == ~t2_pc~0); 45270#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45269#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45268#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45267#L653 assume !(0 != activate_threads_~tmp___1~0#1); 45266#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45265#L307 assume !(1 == ~t3_pc~0); 45263#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45262#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45261#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45260#L661 assume !(0 != activate_threads_~tmp___2~0#1); 45259#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45258#L326 assume !(1 == ~t4_pc~0); 45257#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 45256#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45255#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45254#L669 assume !(0 != activate_threads_~tmp___3~0#1); 45253#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45252#L572 assume !(1 == ~M_E~0); 45251#L572-2 assume !(1 == ~T1_E~0); 45250#L577-1 assume !(1 == ~T2_E~0); 45249#L582-1 assume !(1 == ~T3_E~0); 45248#L587-1 assume !(1 == ~T4_E~0); 45247#L592-1 assume !(1 == ~E_M~0); 45246#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 44779#L602-1 assume !(1 == ~E_2~0); 45010#L607-1 assume !(1 == ~E_3~0); 45011#L612-1 assume !(1 == ~E_4~0); 44955#L617-1 assume { :end_inline_reset_delta_events } true; 44956#L803-2 [2023-11-28 23:52:03,970 INFO L750 eck$LassoCheckResult]: Loop: 44956#L803-2 assume !false; 47749#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47122#L489-1 assume !false; 47115#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 47009#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 47003#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 47001#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 46998#L428 assume !(0 != eval_~tmp~0#1); 46996#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46994#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46992#L514-3 assume !(0 == ~M_E~0); 46990#L514-5 assume !(0 == ~T1_E~0); 46989#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46987#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46976#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46966#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46956#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46955#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46954#L549-3 assume !(0 == ~E_3~0); 46953#L554-3 assume !(0 == ~E_4~0); 46952#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46951#L250-18 assume !(1 == ~m_pc~0); 46950#L250-20 is_master_triggered_~__retres1~0#1 := 0; 46949#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46948#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 46947#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46946#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46945#L269-18 assume !(1 == ~t1_pc~0); 46944#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 46941#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46939#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 46937#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 46935#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46934#L288-18 assume !(1 == ~t2_pc~0); 46933#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 46932#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46931#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46930#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46929#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46928#L307-18 assume 1 == ~t3_pc~0; 46926#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46925#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46924#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46923#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46922#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46921#L326-18 assume !(1 == ~t4_pc~0); 46920#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 46919#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46918#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46917#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46916#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46915#L572-3 assume !(1 == ~M_E~0); 46778#L572-5 assume !(1 == ~T1_E~0); 46914#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46913#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46912#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46911#L592-3 assume !(1 == ~E_M~0); 46909#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46904#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46901#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46894#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46891#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 46888#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 46878#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 46872#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 46738#L822 assume !(0 == start_simulation_~tmp~3#1); 46739#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 47781#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 47776#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 47774#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 47772#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47770#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47768#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 47766#L835 assume !(0 != start_simulation_~tmp___0~1#1); 44956#L803-2 [2023-11-28 23:52:03,971 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:03,971 INFO L85 PathProgramCache]: Analyzing trace with hash -383711415, now seen corresponding path program 1 times [2023-11-28 23:52:03,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:03,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1176944012] [2023-11-28 23:52:03,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:03,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:03,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:04,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:04,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:04,017 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1176944012] [2023-11-28 23:52:04,017 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1176944012] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:04,017 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:04,017 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:04,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1452452759] [2023-11-28 23:52:04,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:04,018 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:04,018 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:04,018 INFO L85 PathProgramCache]: Analyzing trace with hash 1708326027, now seen corresponding path program 1 times [2023-11-28 23:52:04,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:04,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635688145] [2023-11-28 23:52:04,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:04,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:04,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:04,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:04,054 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:04,054 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635688145] [2023-11-28 23:52:04,054 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1635688145] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:04,054 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:04,054 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:04,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [731074939] [2023-11-28 23:52:04,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:04,055 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:04,055 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:04,055 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-28 23:52:04,056 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-28 23:52:04,056 INFO L87 Difference]: Start difference. First operand 5362 states and 7496 transitions. cyclomatic complexity: 2142 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:04,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:04,135 INFO L93 Difference]: Finished difference Result 5478 states and 7611 transitions. [2023-11-28 23:52:04,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5478 states and 7611 transitions. [2023-11-28 23:52:04,180 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5342 [2023-11-28 23:52:04,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5478 states to 5478 states and 7611 transitions. [2023-11-28 23:52:04,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5478 [2023-11-28 23:52:04,202 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5478 [2023-11-28 23:52:04,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5478 states and 7611 transitions. [2023-11-28 23:52:04,207 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:04,207 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5478 states and 7611 transitions. [2023-11-28 23:52:04,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5478 states and 7611 transitions. [2023-11-28 23:52:04,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5478 to 4556. [2023-11-28 23:52:04,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4556 states, 4556 states have (on average 1.3926690079016681) internal successors, (6345), 4555 states have internal predecessors, (6345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:04,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4556 states to 4556 states and 6345 transitions. [2023-11-28 23:52:04,293 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4556 states and 6345 transitions. [2023-11-28 23:52:04,293 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-28 23:52:04,294 INFO L428 stractBuchiCegarLoop]: Abstraction has 4556 states and 6345 transitions. [2023-11-28 23:52:04,294 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-28 23:52:04,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4556 states and 6345 transitions. [2023-11-28 23:52:04,309 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4444 [2023-11-28 23:52:04,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:04,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:04,311 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:04,311 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:04,311 INFO L748 eck$LassoCheckResult]: Stem: 55837#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 55838#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 55940#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55941#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55747#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 55748#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56033#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55693#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55694#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55829#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55719#L514 assume !(0 == ~M_E~0); 55720#L514-2 assume !(0 == ~T1_E~0); 56051#L519-1 assume !(0 == ~T2_E~0); 55679#L524-1 assume !(0 == ~T3_E~0); 55680#L529-1 assume !(0 == ~T4_E~0); 55803#L534-1 assume !(0 == ~E_M~0); 56000#L539-1 assume !(0 == ~E_1~0); 56001#L544-1 assume !(0 == ~E_2~0); 56031#L549-1 assume !(0 == ~E_3~0); 56032#L554-1 assume !(0 == ~E_4~0); 55674#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55675#L250 assume !(1 == ~m_pc~0); 55898#L250-2 is_master_triggered_~__retres1~0#1 := 0; 56035#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55818#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 55819#L637 assume !(0 != activate_threads_~tmp~1#1); 55681#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55682#L269 assume !(1 == ~t1_pc~0); 55620#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55798#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55668#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55669#L645 assume !(0 != activate_threads_~tmp___0~0#1); 55867#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55868#L288 assume !(1 == ~t2_pc~0); 55859#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 55860#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55948#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55949#L653 assume !(0 != activate_threads_~tmp___1~0#1); 55994#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55889#L307 assume !(1 == ~t3_pc~0); 55821#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 55822#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55623#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55624#L661 assume !(0 != activate_threads_~tmp___2~0#1); 55835#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55836#L326 assume !(1 == ~t4_pc~0); 55635#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 55636#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55723#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 55724#L669 assume !(0 != activate_threads_~tmp___3~0#1); 55997#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55998#L572 assume !(1 == ~M_E~0); 56036#L572-2 assume !(1 == ~T1_E~0); 55689#L577-1 assume !(1 == ~T2_E~0); 55690#L582-1 assume !(1 == ~T3_E~0); 55978#L587-1 assume !(1 == ~T4_E~0); 55987#L592-1 assume !(1 == ~E_M~0); 55627#L597-1 assume !(1 == ~E_1~0); 55628#L602-1 assume !(1 == ~E_2~0); 55856#L607-1 assume !(1 == ~E_3~0); 55857#L612-1 assume !(1 == ~E_4~0); 55801#L617-1 assume { :end_inline_reset_delta_events } true; 55802#L803-2 [2023-11-28 23:52:04,311 INFO L750 eck$LassoCheckResult]: Loop: 55802#L803-2 assume !false; 59136#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59132#L489-1 assume !false; 59129#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 59126#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 59119#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 59116#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 59112#L428 assume !(0 != eval_~tmp~0#1); 55729#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55730#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55922#L514-3 assume !(0 == ~M_E~0); 55874#L514-5 assume !(0 == ~T1_E~0); 55875#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55974#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55772#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55773#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 55617#L539-3 assume !(0 == ~E_1~0); 55618#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 56053#L549-3 assume !(0 == ~E_3~0); 55825#L554-3 assume !(0 == ~E_4~0); 55826#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55919#L250-18 assume !(1 == ~m_pc~0); 56012#L250-20 is_master_triggered_~__retres1~0#1 := 0; 55932#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55852#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 55853#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55782#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55657#L269-18 assume !(1 == ~t1_pc~0); 55659#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 55736#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55737#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55907#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 55908#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55810#L288-18 assume !(1 == ~t2_pc~0); 55811#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 60163#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60162#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 60161#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60160#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60159#L307-18 assume 1 == ~t3_pc~0; 60157#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 60156#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60155#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 60153#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60102#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60101#L326-18 assume !(1 == ~t4_pc~0); 56068#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 56025#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55876#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 55613#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 55614#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56072#L572-3 assume !(1 == ~M_E~0); 55785#L572-5 assume !(1 == ~T1_E~0); 55786#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58724#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58722#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58720#L592-3 assume !(1 == ~E_M~0); 58717#L597-3 assume !(1 == ~E_1~0); 58714#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 58711#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 58708#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 58705#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 58702#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 58695#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 58050#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 57956#L822 assume !(0 == start_simulation_~tmp~3#1); 57957#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 59233#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 59229#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 59228#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 59227#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 59226#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59225#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 59224#L835 assume !(0 != start_simulation_~tmp___0~1#1); 55802#L803-2 [2023-11-28 23:52:04,312 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:04,312 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2023-11-28 23:52:04,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:04,312 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [383147281] [2023-11-28 23:52:04,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:04,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:04,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:04,322 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:04,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:04,360 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:04,361 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:04,361 INFO L85 PathProgramCache]: Analyzing trace with hash 553707211, now seen corresponding path program 1 times [2023-11-28 23:52:04,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:04,361 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1474456395] [2023-11-28 23:52:04,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:04,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:04,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:04,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:04,395 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:04,395 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1474456395] [2023-11-28 23:52:04,395 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1474456395] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:04,395 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:04,395 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:04,396 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [581315677] [2023-11-28 23:52:04,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:04,396 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:04,396 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:04,396 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:04,397 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:04,397 INFO L87 Difference]: Start difference. First operand 4556 states and 6345 transitions. cyclomatic complexity: 1797 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:04,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:04,468 INFO L93 Difference]: Finished difference Result 6981 states and 9610 transitions. [2023-11-28 23:52:04,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6981 states and 9610 transitions. [2023-11-28 23:52:04,497 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6810 [2023-11-28 23:52:04,523 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6981 states to 6981 states and 9610 transitions. [2023-11-28 23:52:04,523 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6981 [2023-11-28 23:52:04,532 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6981 [2023-11-28 23:52:04,532 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6981 states and 9610 transitions. [2023-11-28 23:52:04,537 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:04,537 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6981 states and 9610 transitions. [2023-11-28 23:52:04,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6981 states and 9610 transitions. [2023-11-28 23:52:04,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6981 to 6977. [2023-11-28 23:52:04,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6977 states, 6977 states have (on average 1.3768095169843773) internal successors, (9606), 6976 states have internal predecessors, (9606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:04,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6977 states to 6977 states and 9606 transitions. [2023-11-28 23:52:04,671 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6977 states and 9606 transitions. [2023-11-28 23:52:04,671 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:04,672 INFO L428 stractBuchiCegarLoop]: Abstraction has 6977 states and 9606 transitions. [2023-11-28 23:52:04,672 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-28 23:52:04,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6977 states and 9606 transitions. [2023-11-28 23:52:04,687 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6806 [2023-11-28 23:52:04,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:04,688 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:04,689 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:04,689 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:04,689 INFO L748 eck$LassoCheckResult]: Stem: 67381#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 67382#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 67499#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67500#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67289#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 67290#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67584#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67234#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67235#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67372#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67264#L514 assume !(0 == ~M_E~0); 67265#L514-2 assume !(0 == ~T1_E~0); 67610#L519-1 assume !(0 == ~T2_E~0); 67222#L524-1 assume !(0 == ~T3_E~0); 67223#L529-1 assume !(0 == ~T4_E~0); 67346#L534-1 assume 0 == ~E_M~0;~E_M~0 := 1; 67615#L539-1 assume !(0 == ~E_1~0); 67579#L544-1 assume !(0 == ~E_2~0); 67580#L549-1 assume !(0 == ~E_3~0); 67620#L554-1 assume !(0 == ~E_4~0); 67621#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67449#L250 assume !(1 == ~m_pc~0); 67450#L250-2 is_master_triggered_~__retres1~0#1 := 0; 67611#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67361#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67362#L637 assume !(0 != activate_threads_~tmp~1#1); 67224#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67225#L269 assume !(1 == ~t1_pc~0); 67700#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 67459#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67213#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 67214#L645 assume !(0 != activate_threads_~tmp___0~0#1); 67413#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67414#L288 assume !(1 == ~t2_pc~0); 67522#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 67697#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67696#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 67695#L653 assume !(0 != activate_threads_~tmp___1~0#1); 67598#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67599#L307 assume !(1 == ~t3_pc~0); 67693#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 67495#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67496#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 67692#L661 assume !(0 != activate_threads_~tmp___2~0#1); 67691#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67690#L326 assume !(1 == ~t4_pc~0); 67689#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67688#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67687#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 67686#L669 assume !(0 != activate_threads_~tmp___3~0#1); 67685#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67684#L572 assume !(1 == ~M_E~0); 67683#L572-2 assume !(1 == ~T1_E~0); 67682#L577-1 assume !(1 == ~T2_E~0); 67681#L582-1 assume !(1 == ~T3_E~0); 67680#L587-1 assume !(1 == ~T4_E~0); 67645#L592-1 assume 1 == ~E_M~0;~E_M~0 := 2; 67176#L597-1 assume !(1 == ~E_1~0); 67177#L602-1 assume !(1 == ~E_2~0); 67404#L607-1 assume !(1 == ~E_3~0); 67405#L612-1 assume !(1 == ~E_4~0); 67344#L617-1 assume { :end_inline_reset_delta_events } true; 67345#L803-2 [2023-11-28 23:52:04,689 INFO L750 eck$LassoCheckResult]: Loop: 67345#L803-2 assume !false; 68212#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68062#L489-1 assume !false; 68205#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 68200#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 68194#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 68191#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 68192#L428 assume !(0 != eval_~tmp~0#1); 68567#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68925#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68921#L514-3 assume !(0 == ~M_E~0); 68918#L514-5 assume !(0 == ~T1_E~0); 68917#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 68916#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68915#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68913#L534-3 assume !(0 == ~E_M~0); 68912#L539-3 assume !(0 == ~E_1~0); 68910#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68908#L549-3 assume !(0 == ~E_3~0); 68902#L554-3 assume !(0 == ~E_4~0); 68899#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68896#L250-18 assume !(1 == ~m_pc~0); 68893#L250-20 is_master_triggered_~__retres1~0#1 := 0; 68890#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68887#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 68884#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68881#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68799#L269-18 assume !(1 == ~t1_pc~0); 68796#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 68794#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68792#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68790#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 68788#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68785#L288-18 assume !(1 == ~t2_pc~0); 68783#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 68781#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68779#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68777#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 68775#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68773#L307-18 assume !(1 == ~t3_pc~0); 68771#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 68768#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68766#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68764#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 68762#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68759#L326-18 assume !(1 == ~t4_pc~0); 68757#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 68755#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68753#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68751#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 68749#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68747#L572-3 assume !(1 == ~M_E~0); 68708#L572-5 assume !(1 == ~T1_E~0); 68744#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68742#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68740#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68734#L592-3 assume !(1 == ~E_M~0); 68732#L597-3 assume !(1 == ~E_1~0); 68730#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 68728#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 68726#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68724#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 68722#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 68716#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 68714#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 68712#L822 assume !(0 == start_simulation_~tmp~3#1); 68709#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 68232#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 68227#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 68224#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 68225#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 68645#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68643#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 68214#L835 assume !(0 != start_simulation_~tmp___0~1#1); 67345#L803-2 [2023-11-28 23:52:04,689 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:04,690 INFO L85 PathProgramCache]: Analyzing trace with hash 1842238409, now seen corresponding path program 1 times [2023-11-28 23:52:04,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:04,690 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2048281505] [2023-11-28 23:52:04,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:04,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:04,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:04,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:04,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:04,728 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2048281505] [2023-11-28 23:52:04,728 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2048281505] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:04,728 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:04,728 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:04,728 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [328891580] [2023-11-28 23:52:04,728 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:04,728 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:04,729 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:04,729 INFO L85 PathProgramCache]: Analyzing trace with hash -2129111218, now seen corresponding path program 1 times [2023-11-28 23:52:04,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:04,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [819376690] [2023-11-28 23:52:04,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:04,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:04,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:04,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:04,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:04,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [819376690] [2023-11-28 23:52:04,781 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [819376690] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:04,781 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:04,781 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 23:52:04,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2097993437] [2023-11-28 23:52:04,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:04,782 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:04,782 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:04,782 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-28 23:52:04,782 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-28 23:52:04,783 INFO L87 Difference]: Start difference. First operand 6977 states and 9606 transitions. cyclomatic complexity: 2637 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:04,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:04,908 INFO L93 Difference]: Finished difference Result 9400 states and 12933 transitions. [2023-11-28 23:52:04,909 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9400 states and 12933 transitions. [2023-11-28 23:52:04,933 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 9019 [2023-11-28 23:52:04,953 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9400 states to 9400 states and 12933 transitions. [2023-11-28 23:52:04,953 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9400 [2023-11-28 23:52:04,958 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9400 [2023-11-28 23:52:04,958 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9400 states and 12933 transitions. [2023-11-28 23:52:04,962 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:04,962 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9400 states and 12933 transitions. [2023-11-28 23:52:04,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9400 states and 12933 transitions. [2023-11-28 23:52:05,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9400 to 6582. [2023-11-28 23:52:05,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6582 states, 6582 states have (on average 1.3773928896991796) internal successors, (9066), 6581 states have internal predecessors, (9066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:05,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6582 states to 6582 states and 9066 transitions. [2023-11-28 23:52:05,048 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6582 states and 9066 transitions. [2023-11-28 23:52:05,049 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-28 23:52:05,049 INFO L428 stractBuchiCegarLoop]: Abstraction has 6582 states and 9066 transitions. [2023-11-28 23:52:05,049 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-28 23:52:05,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6582 states and 9066 transitions. [2023-11-28 23:52:05,064 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6454 [2023-11-28 23:52:05,064 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:05,064 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:05,065 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:05,065 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:05,065 INFO L748 eck$LassoCheckResult]: Stem: 83774#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 83775#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 83886#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 83887#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 83679#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 83680#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83967#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83623#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 83624#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 83765#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 83653#L514 assume !(0 == ~M_E~0); 83654#L514-2 assume !(0 == ~T1_E~0); 83987#L519-1 assume !(0 == ~T2_E~0); 83611#L524-1 assume !(0 == ~T3_E~0); 83612#L529-1 assume !(0 == ~T4_E~0); 83739#L534-1 assume !(0 == ~E_M~0); 83938#L539-1 assume !(0 == ~E_1~0); 83939#L544-1 assume !(0 == ~E_2~0); 83963#L549-1 assume !(0 == ~E_3~0); 83964#L554-1 assume !(0 == ~E_4~0); 83606#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83607#L250 assume !(1 == ~m_pc~0); 83838#L250-2 is_master_triggered_~__retres1~0#1 := 0; 83968#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83753#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 83754#L637 assume !(0 != activate_threads_~tmp~1#1); 83613#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83614#L269 assume !(1 == ~t1_pc~0); 83552#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 83734#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83602#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 83603#L645 assume !(0 != activate_threads_~tmp___0~0#1); 83802#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83803#L288 assume !(1 == ~t2_pc~0); 83798#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 83799#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83892#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 83893#L653 assume !(0 != activate_threads_~tmp___1~0#1); 83934#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83827#L307 assume !(1 == ~t3_pc~0); 83756#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 83757#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83555#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 83556#L661 assume !(0 != activate_threads_~tmp___2~0#1); 83772#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83773#L326 assume !(1 == ~t4_pc~0); 83567#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 83568#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83655#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 83656#L669 assume !(0 != activate_threads_~tmp___3~0#1); 83935#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83936#L572 assume !(1 == ~M_E~0); 83969#L572-2 assume !(1 == ~T1_E~0); 83619#L577-1 assume !(1 == ~T2_E~0); 83620#L582-1 assume !(1 == ~T3_E~0); 83918#L587-1 assume !(1 == ~T4_E~0); 83928#L592-1 assume !(1 == ~E_M~0); 83565#L597-1 assume !(1 == ~E_1~0); 83566#L602-1 assume !(1 == ~E_2~0); 83795#L607-1 assume !(1 == ~E_3~0); 83796#L612-1 assume !(1 == ~E_4~0); 83737#L617-1 assume { :end_inline_reset_delta_events } true; 83738#L803-2 [2023-11-28 23:52:05,065 INFO L750 eck$LassoCheckResult]: Loop: 83738#L803-2 assume !false; 85168#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 84540#L489-1 assume !false; 85162#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 85159#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 85152#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 85149#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 85145#L428 assume !(0 != eval_~tmp~0#1); 85146#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85171#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 85169#L514-3 assume !(0 == ~M_E~0); 85165#L514-5 assume !(0 == ~T1_E~0); 85163#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 85160#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 85153#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85150#L534-3 assume !(0 == ~E_M~0); 85147#L539-3 assume !(0 == ~E_1~0); 85143#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 85138#L549-3 assume !(0 == ~E_3~0); 85134#L554-3 assume !(0 == ~E_4~0); 85132#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85130#L250-18 assume !(1 == ~m_pc~0); 85128#L250-20 is_master_triggered_~__retres1~0#1 := 0; 85126#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85124#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 85121#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 85119#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85117#L269-18 assume !(1 == ~t1_pc~0); 85114#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 85112#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85110#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 85103#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 85102#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85101#L288-18 assume !(1 == ~t2_pc~0); 85100#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 85099#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85098#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 85097#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 85096#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85095#L307-18 assume 1 == ~t3_pc~0; 85093#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 85092#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85091#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 85090#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85088#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85086#L326-18 assume !(1 == ~t4_pc~0); 85084#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 85082#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85080#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 85078#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 85075#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85073#L572-3 assume !(1 == ~M_E~0); 84974#L572-5 assume !(1 == ~T1_E~0); 85070#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 85068#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85066#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85064#L592-3 assume !(1 == ~E_M~0); 85062#L597-3 assume !(1 == ~E_1~0); 85060#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 85059#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 85058#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85057#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 85055#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 85050#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 85049#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 85031#L822 assume !(0 == start_simulation_~tmp~3#1); 85032#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 85202#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 85196#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 85193#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 85190#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 85180#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 85175#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 85173#L835 assume !(0 != start_simulation_~tmp___0~1#1); 83738#L803-2 [2023-11-28 23:52:05,066 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:05,066 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2023-11-28 23:52:05,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:05,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [88054284] [2023-11-28 23:52:05,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:05,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:05,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:05,074 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:05,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:05,124 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:05,124 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:05,124 INFO L85 PathProgramCache]: Analyzing trace with hash 1114406989, now seen corresponding path program 1 times [2023-11-28 23:52:05,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:05,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810387795] [2023-11-28 23:52:05,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:05,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:05,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:05,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:05,189 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:05,189 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [810387795] [2023-11-28 23:52:05,189 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [810387795] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:05,189 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:05,190 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 23:52:05,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8608325] [2023-11-28 23:52:05,190 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:05,190 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:05,190 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:05,191 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-28 23:52:05,191 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-28 23:52:05,192 INFO L87 Difference]: Start difference. First operand 6582 states and 9066 transitions. cyclomatic complexity: 2492 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:05,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:05,332 INFO L93 Difference]: Finished difference Result 11724 states and 15968 transitions. [2023-11-28 23:52:05,332 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11724 states and 15968 transitions. [2023-11-28 23:52:05,391 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11532 [2023-11-28 23:52:05,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11724 states to 11724 states and 15968 transitions. [2023-11-28 23:52:05,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11724 [2023-11-28 23:52:05,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11724 [2023-11-28 23:52:05,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11724 states and 15968 transitions. [2023-11-28 23:52:05,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:05,454 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11724 states and 15968 transitions. [2023-11-28 23:52:05,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11724 states and 15968 transitions. [2023-11-28 23:52:05,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11724 to 6654. [2023-11-28 23:52:05,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6654 states, 6654 states have (on average 1.3733092876465285) internal successors, (9138), 6653 states have internal predecessors, (9138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:05,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6654 states to 6654 states and 9138 transitions. [2023-11-28 23:52:05,581 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6654 states and 9138 transitions. [2023-11-28 23:52:05,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-28 23:52:05,582 INFO L428 stractBuchiCegarLoop]: Abstraction has 6654 states and 9138 transitions. [2023-11-28 23:52:05,582 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-28 23:52:05,583 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6654 states and 9138 transitions. [2023-11-28 23:52:05,631 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6526 [2023-11-28 23:52:05,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:05,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:05,632 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:05,632 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:05,632 INFO L748 eck$LassoCheckResult]: Stem: 102096#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 102097#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 102209#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 102210#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 102001#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 102002#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 102300#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 101947#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 101948#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 102086#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 101975#L514 assume !(0 == ~M_E~0); 101976#L514-2 assume !(0 == ~T1_E~0); 102318#L519-1 assume !(0 == ~T2_E~0); 101933#L524-1 assume !(0 == ~T3_E~0); 101934#L529-1 assume !(0 == ~T4_E~0); 102061#L534-1 assume !(0 == ~E_M~0); 102270#L539-1 assume !(0 == ~E_1~0); 102271#L544-1 assume !(0 == ~E_2~0); 102297#L549-1 assume !(0 == ~E_3~0); 102298#L554-1 assume !(0 == ~E_4~0); 101928#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101929#L250 assume !(1 == ~m_pc~0); 102163#L250-2 is_master_triggered_~__retres1~0#1 := 0; 102301#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102075#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 102076#L637 assume !(0 != activate_threads_~tmp~1#1); 101937#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101938#L269 assume !(1 == ~t1_pc~0); 101875#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 102056#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101924#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 101925#L645 assume !(0 != activate_threads_~tmp___0~0#1); 102126#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102127#L288 assume !(1 == ~t2_pc~0); 102120#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 102121#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102215#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 102216#L653 assume !(0 != activate_threads_~tmp___1~0#1); 102265#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102150#L307 assume !(1 == ~t3_pc~0); 102078#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 102079#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101878#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 101879#L661 assume !(0 != activate_threads_~tmp___2~0#1); 102094#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 102095#L326 assume !(1 == ~t4_pc~0); 101890#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 101891#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 101977#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 101978#L669 assume !(0 != activate_threads_~tmp___3~0#1); 102267#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102268#L572 assume !(1 == ~M_E~0); 102302#L572-2 assume !(1 == ~T1_E~0); 101943#L577-1 assume !(1 == ~T2_E~0); 101944#L582-1 assume !(1 == ~T3_E~0); 102248#L587-1 assume !(1 == ~T4_E~0); 102258#L592-1 assume !(1 == ~E_M~0); 101888#L597-1 assume !(1 == ~E_1~0); 101889#L602-1 assume !(1 == ~E_2~0); 102117#L607-1 assume !(1 == ~E_3~0); 102118#L612-1 assume !(1 == ~E_4~0); 102059#L617-1 assume { :end_inline_reset_delta_events } true; 102060#L803-2 [2023-11-28 23:52:05,632 INFO L750 eck$LassoCheckResult]: Loop: 102060#L803-2 assume !false; 103770#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 103769#L489-1 assume !false; 103768#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 103767#L386 assume !(0 == ~m_st~0); 103764#L390 assume !(0 == ~t1_st~0); 103765#L394 assume !(0 == ~t2_st~0); 103766#L398 assume !(0 == ~t3_st~0); 103762#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 103763#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 103615#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 103616#L428 assume !(0 != eval_~tmp~0#1); 103916#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 103914#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103912#L514-3 assume !(0 == ~M_E~0); 103910#L514-5 assume !(0 == ~T1_E~0); 103908#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 103906#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103904#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 103902#L534-3 assume !(0 == ~E_M~0); 103900#L539-3 assume !(0 == ~E_1~0); 103898#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 103896#L549-3 assume !(0 == ~E_3~0); 103894#L554-3 assume !(0 == ~E_4~0); 103892#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103890#L250-18 assume !(1 == ~m_pc~0); 103888#L250-20 is_master_triggered_~__retres1~0#1 := 0; 103886#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103884#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 103882#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 103880#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103878#L269-18 assume !(1 == ~t1_pc~0); 103874#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 103872#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103870#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 103868#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 103866#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103864#L288-18 assume !(1 == ~t2_pc~0); 103862#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 103860#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103858#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 103856#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 103854#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103852#L307-18 assume 1 == ~t3_pc~0; 103849#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 103846#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103844#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 103842#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 103840#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103838#L326-18 assume !(1 == ~t4_pc~0); 103836#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 103834#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103832#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 103830#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 103828#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103826#L572-3 assume !(1 == ~M_E~0); 103823#L572-5 assume !(1 == ~T1_E~0); 103822#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 103821#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 103820#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 103819#L592-3 assume !(1 == ~E_M~0); 103818#L597-3 assume !(1 == ~E_1~0); 103817#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 103816#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 103815#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 103814#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 103813#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 103806#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 103803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 103800#L822 assume !(0 == start_simulation_~tmp~3#1); 103797#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 103795#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 103790#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 103788#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 103784#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 103782#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 103780#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 103777#L835 assume !(0 != start_simulation_~tmp___0~1#1); 102060#L803-2 [2023-11-28 23:52:05,633 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:05,633 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2023-11-28 23:52:05,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:05,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793798447] [2023-11-28 23:52:05,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:05,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:05,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:05,643 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:05,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:05,661 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:05,661 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:05,662 INFO L85 PathProgramCache]: Analyzing trace with hash 2571329, now seen corresponding path program 1 times [2023-11-28 23:52:05,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:05,662 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1173640100] [2023-11-28 23:52:05,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:05,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:05,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:05,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:05,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:05,733 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1173640100] [2023-11-28 23:52:05,733 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1173640100] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:05,733 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:05,733 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 23:52:05,733 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1368262713] [2023-11-28 23:52:05,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:05,734 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:05,734 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:05,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-28 23:52:05,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-28 23:52:05,734 INFO L87 Difference]: Start difference. First operand 6654 states and 9138 transitions. cyclomatic complexity: 2492 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:05,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:05,905 INFO L93 Difference]: Finished difference Result 10614 states and 14401 transitions. [2023-11-28 23:52:05,905 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10614 states and 14401 transitions. [2023-11-28 23:52:05,944 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10454 [2023-11-28 23:52:05,977 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10614 states to 10614 states and 14401 transitions. [2023-11-28 23:52:05,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10614 [2023-11-28 23:52:05,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10614 [2023-11-28 23:52:05,984 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10614 states and 14401 transitions. [2023-11-28 23:52:05,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:05,991 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10614 states and 14401 transitions. [2023-11-28 23:52:05,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10614 states and 14401 transitions. [2023-11-28 23:52:06,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10614 to 6774. [2023-11-28 23:52:06,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6774 states, 6774 states have (on average 1.3553291998819015) internal successors, (9181), 6773 states have internal predecessors, (9181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:06,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6774 states to 6774 states and 9181 transitions. [2023-11-28 23:52:06,090 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6774 states and 9181 transitions. [2023-11-28 23:52:06,124 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-28 23:52:06,125 INFO L428 stractBuchiCegarLoop]: Abstraction has 6774 states and 9181 transitions. [2023-11-28 23:52:06,125 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-28 23:52:06,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6774 states and 9181 transitions. [2023-11-28 23:52:06,135 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6646 [2023-11-28 23:52:06,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:06,135 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:06,136 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:06,136 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:06,136 INFO L748 eck$LassoCheckResult]: Stem: 119375#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 119376#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 119488#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 119489#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 119283#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 119284#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 119581#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 119229#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 119230#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 119364#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 119257#L514 assume !(0 == ~M_E~0); 119258#L514-2 assume !(0 == ~T1_E~0); 119598#L519-1 assume !(0 == ~T2_E~0); 119215#L524-1 assume !(0 == ~T3_E~0); 119216#L529-1 assume !(0 == ~T4_E~0); 119340#L534-1 assume !(0 == ~E_M~0); 119544#L539-1 assume !(0 == ~E_1~0); 119545#L544-1 assume !(0 == ~E_2~0); 119577#L549-1 assume !(0 == ~E_3~0); 119578#L554-1 assume !(0 == ~E_4~0); 119210#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119211#L250 assume !(1 == ~m_pc~0); 119443#L250-2 is_master_triggered_~__retres1~0#1 := 0; 119582#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119353#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 119354#L637 assume !(0 != activate_threads_~tmp~1#1); 119219#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119220#L269 assume !(1 == ~t1_pc~0); 119155#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 119335#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119206#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 119207#L645 assume !(0 != activate_threads_~tmp___0~0#1); 119408#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119409#L288 assume !(1 == ~t2_pc~0); 119401#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 119402#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119494#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 119495#L653 assume !(0 != activate_threads_~tmp___1~0#1); 119539#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119432#L307 assume !(1 == ~t3_pc~0); 119356#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 119357#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119158#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 119159#L661 assume !(0 != activate_threads_~tmp___2~0#1); 119373#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119374#L326 assume !(1 == ~t4_pc~0); 119170#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 119171#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119259#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 119260#L669 assume !(0 != activate_threads_~tmp___3~0#1); 119541#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119542#L572 assume !(1 == ~M_E~0); 119583#L572-2 assume !(1 == ~T1_E~0); 119225#L577-1 assume !(1 == ~T2_E~0); 119226#L582-1 assume !(1 == ~T3_E~0); 119523#L587-1 assume !(1 == ~T4_E~0); 119533#L592-1 assume !(1 == ~E_M~0); 119168#L597-1 assume !(1 == ~E_1~0); 119169#L602-1 assume !(1 == ~E_2~0); 119398#L607-1 assume !(1 == ~E_3~0); 119399#L612-1 assume !(1 == ~E_4~0); 119338#L617-1 assume { :end_inline_reset_delta_events } true; 119339#L803-2 [2023-11-28 23:52:06,137 INFO L750 eck$LassoCheckResult]: Loop: 119339#L803-2 assume !false; 121064#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 121063#L489-1 assume !false; 121061#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 121055#L386 assume !(0 == ~m_st~0); 121052#L390 assume !(0 == ~t1_st~0); 121053#L394 assume !(0 == ~t2_st~0); 121054#L398 assume !(0 == ~t3_st~0); 121050#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 121051#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 120819#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 120820#L428 assume !(0 != eval_~tmp~0#1); 121300#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 121298#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 121296#L514-3 assume !(0 == ~M_E~0); 121294#L514-5 assume !(0 == ~T1_E~0); 121292#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 121290#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 121288#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 121286#L534-3 assume !(0 == ~E_M~0); 121284#L539-3 assume !(0 == ~E_1~0); 121282#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 121280#L549-3 assume !(0 == ~E_3~0); 121278#L554-3 assume !(0 == ~E_4~0); 121276#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121274#L250-18 assume !(1 == ~m_pc~0); 121272#L250-20 is_master_triggered_~__retres1~0#1 := 0; 121270#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121266#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 121263#L637-18 assume !(0 != activate_threads_~tmp~1#1); 121261#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121258#L269-18 assume !(1 == ~t1_pc~0); 121253#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 121250#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121247#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 121244#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 121240#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121237#L288-18 assume !(1 == ~t2_pc~0); 121234#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 121231#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121228#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 121225#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 121222#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 121219#L307-18 assume !(1 == ~t3_pc~0); 121215#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 121209#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 121205#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 121201#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 121197#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 121192#L326-18 assume !(1 == ~t4_pc~0); 121187#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 121183#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121179#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 121175#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 121171#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 121167#L572-3 assume !(1 == ~M_E~0); 121162#L572-5 assume !(1 == ~T1_E~0); 121159#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 121156#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 121153#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 121149#L592-3 assume !(1 == ~E_M~0); 121145#L597-3 assume !(1 == ~E_1~0); 121141#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 121136#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 121132#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 121128#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 121124#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 121116#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 121112#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 121108#L822 assume !(0 == start_simulation_~tmp~3#1); 121105#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 121097#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 121091#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 121088#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 121083#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 121080#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 121077#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 121073#L835 assume !(0 != start_simulation_~tmp___0~1#1); 119339#L803-2 [2023-11-28 23:52:06,137 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:06,137 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 4 times [2023-11-28 23:52:06,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:06,137 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1989409815] [2023-11-28 23:52:06,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:06,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:06,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:06,147 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:06,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:06,164 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:06,165 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:06,165 INFO L85 PathProgramCache]: Analyzing trace with hash 1038501700, now seen corresponding path program 1 times [2023-11-28 23:52:06,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:06,165 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [121327422] [2023-11-28 23:52:06,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:06,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:06,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:06,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:06,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:06,193 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [121327422] [2023-11-28 23:52:06,193 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [121327422] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:06,193 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:06,193 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:06,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [133343782] [2023-11-28 23:52:06,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:06,193 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 23:52:06,194 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:06,194 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:06,194 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:06,194 INFO L87 Difference]: Start difference. First operand 6774 states and 9181 transitions. cyclomatic complexity: 2415 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:06,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:06,255 INFO L93 Difference]: Finished difference Result 10652 states and 14255 transitions. [2023-11-28 23:52:06,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10652 states and 14255 transitions. [2023-11-28 23:52:06,292 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10490 [2023-11-28 23:52:06,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10652 states to 10652 states and 14255 transitions. [2023-11-28 23:52:06,327 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10652 [2023-11-28 23:52:06,334 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10652 [2023-11-28 23:52:06,334 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10652 states and 14255 transitions. [2023-11-28 23:52:06,340 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:06,340 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10652 states and 14255 transitions. [2023-11-28 23:52:06,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10652 states and 14255 transitions. [2023-11-28 23:52:06,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10652 to 10396. [2023-11-28 23:52:06,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10396 states, 10396 states have (on average 1.338880338591766) internal successors, (13919), 10395 states have internal predecessors, (13919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:06,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10396 states to 10396 states and 13919 transitions. [2023-11-28 23:52:06,536 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10396 states and 13919 transitions. [2023-11-28 23:52:06,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:06,539 INFO L428 stractBuchiCegarLoop]: Abstraction has 10396 states and 13919 transitions. [2023-11-28 23:52:06,539 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-28 23:52:06,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10396 states and 13919 transitions. [2023-11-28 23:52:06,567 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10234 [2023-11-28 23:52:06,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:06,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:06,568 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:06,568 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:06,569 INFO L748 eck$LassoCheckResult]: Stem: 136811#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 136812#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 136925#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 136926#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 136714#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 136715#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 137017#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 136658#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 136659#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 136801#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 136686#L514 assume !(0 == ~M_E~0); 136687#L514-2 assume !(0 == ~T1_E~0); 137034#L519-1 assume !(0 == ~T2_E~0); 136646#L524-1 assume !(0 == ~T3_E~0); 136647#L529-1 assume !(0 == ~T4_E~0); 136773#L534-1 assume !(0 == ~E_M~0); 136982#L539-1 assume !(0 == ~E_1~0); 136983#L544-1 assume !(0 == ~E_2~0); 137013#L549-1 assume !(0 == ~E_3~0); 137014#L554-1 assume !(0 == ~E_4~0); 136641#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136642#L250 assume !(1 == ~m_pc~0); 136876#L250-2 is_master_triggered_~__retres1~0#1 := 0; 137018#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 136789#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 136790#L637 assume !(0 != activate_threads_~tmp~1#1); 136648#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136649#L269 assume !(1 == ~t1_pc~0); 136587#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 136768#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136637#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 136638#L645 assume !(0 != activate_threads_~tmp___0~0#1); 136841#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 136842#L288 assume !(1 == ~t2_pc~0); 136835#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 136836#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 136931#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 136932#L653 assume !(0 != activate_threads_~tmp___1~0#1); 136976#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 136864#L307 assume !(1 == ~t3_pc~0); 136792#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 136793#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136590#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 136591#L661 assume !(0 != activate_threads_~tmp___2~0#1); 136809#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 136810#L326 assume !(1 == ~t4_pc~0); 136602#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 136603#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 136688#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 136689#L669 assume !(0 != activate_threads_~tmp___3~0#1); 136979#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 136980#L572 assume !(1 == ~M_E~0); 137019#L572-2 assume !(1 == ~T1_E~0); 136654#L577-1 assume !(1 == ~T2_E~0); 136655#L582-1 assume !(1 == ~T3_E~0); 136960#L587-1 assume !(1 == ~T4_E~0); 136969#L592-1 assume !(1 == ~E_M~0); 136600#L597-1 assume !(1 == ~E_1~0); 136601#L602-1 assume !(1 == ~E_2~0); 136832#L607-1 assume !(1 == ~E_3~0); 136833#L612-1 assume !(1 == ~E_4~0); 136771#L617-1 assume { :end_inline_reset_delta_events } true; 136772#L803-2 assume !false; 137849#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 137822#L489-1 [2023-11-28 23:52:06,569 INFO L750 eck$LassoCheckResult]: Loop: 137822#L489-1 assume !false; 137818#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 137819#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 138186#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 138184#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 138182#L428 assume 0 != eval_~tmp~0#1; 138181#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 138177#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 138176#L436-2 havoc eval_~tmp_ndt_1~0#1; 138174#L433-1 assume !(0 == ~t1_st~0); 137913#L447-1 assume !(0 == ~t2_st~0); 137912#L461-1 assume !(0 == ~t3_st~0); 137851#L475-1 assume !(0 == ~t4_st~0); 137822#L489-1 [2023-11-28 23:52:06,572 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:06,572 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2023-11-28 23:52:06,573 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:06,573 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [361919639] [2023-11-28 23:52:06,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:06,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:06,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:06,584 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:06,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:06,601 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:06,602 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:06,602 INFO L85 PathProgramCache]: Analyzing trace with hash 1561748980, now seen corresponding path program 1 times [2023-11-28 23:52:06,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:06,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241732278] [2023-11-28 23:52:06,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:06,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:06,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:06,606 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:06,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:06,610 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:06,610 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:06,611 INFO L85 PathProgramCache]: Analyzing trace with hash 1479320330, now seen corresponding path program 1 times [2023-11-28 23:52:06,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:06,611 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619084617] [2023-11-28 23:52:06,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:06,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:06,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:06,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:06,649 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:06,649 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1619084617] [2023-11-28 23:52:06,649 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1619084617] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:06,649 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:06,649 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:06,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1282043321] [2023-11-28 23:52:06,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:06,788 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:06,789 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:06,789 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:06,789 INFO L87 Difference]: Start difference. First operand 10396 states and 13919 transitions. cyclomatic complexity: 3535 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:06,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:06,873 INFO L93 Difference]: Finished difference Result 16722 states and 22211 transitions. [2023-11-28 23:52:06,874 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16722 states and 22211 transitions. [2023-11-28 23:52:06,955 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 16404 [2023-11-28 23:52:07,023 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16722 states to 16722 states and 22211 transitions. [2023-11-28 23:52:07,023 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16722 [2023-11-28 23:52:07,034 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16722 [2023-11-28 23:52:07,034 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16722 states and 22211 transitions. [2023-11-28 23:52:07,049 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:07,049 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16722 states and 22211 transitions. [2023-11-28 23:52:07,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16722 states and 22211 transitions. [2023-11-28 23:52:07,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16722 to 16722. [2023-11-28 23:52:07,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16722 states, 16722 states have (on average 1.328250209305107) internal successors, (22211), 16721 states have internal predecessors, (22211), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:07,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16722 states to 16722 states and 22211 transitions. [2023-11-28 23:52:07,301 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16722 states and 22211 transitions. [2023-11-28 23:52:07,301 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:07,302 INFO L428 stractBuchiCegarLoop]: Abstraction has 16722 states and 22211 transitions. [2023-11-28 23:52:07,302 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-28 23:52:07,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16722 states and 22211 transitions. [2023-11-28 23:52:07,361 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 16404 [2023-11-28 23:52:07,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:07,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:07,363 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:07,363 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:07,363 INFO L748 eck$LassoCheckResult]: Stem: 163937#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 163938#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 164044#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 164045#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 163840#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 163841#L353-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 164126#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 163784#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 163785#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 163926#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 163810#L514 assume !(0 == ~M_E~0); 163811#L514-2 assume !(0 == ~T1_E~0); 164150#L519-1 assume !(0 == ~T2_E~0); 163772#L524-1 assume !(0 == ~T3_E~0); 163773#L529-1 assume !(0 == ~T4_E~0); 163900#L534-1 assume !(0 == ~E_M~0); 164101#L539-1 assume !(0 == ~E_1~0); 164102#L544-1 assume !(0 == ~E_2~0); 164124#L549-1 assume !(0 == ~E_3~0); 164125#L554-1 assume !(0 == ~E_4~0); 163767#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 163768#L250 assume !(1 == ~m_pc~0); 164002#L250-2 is_master_triggered_~__retres1~0#1 := 0; 164129#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163915#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 163916#L637 assume !(0 != activate_threads_~tmp~1#1); 163774#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163775#L269 assume !(1 == ~t1_pc~0); 163713#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 163895#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163761#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 163762#L645 assume !(0 != activate_threads_~tmp___0~0#1); 163967#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163968#L288 assume !(1 == ~t2_pc~0); 163960#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 163961#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 164052#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 164053#L653 assume !(0 != activate_threads_~tmp___1~0#1); 164096#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163990#L307 assume !(1 == ~t3_pc~0); 163918#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 163919#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163716#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 163717#L661 assume !(0 != activate_threads_~tmp___2~0#1); 163935#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163936#L326 assume !(1 == ~t4_pc~0); 163728#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 163729#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 163814#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 163815#L669 assume !(0 != activate_threads_~tmp___3~0#1); 164098#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 164099#L572 assume !(1 == ~M_E~0); 164130#L572-2 assume !(1 == ~T1_E~0); 163780#L577-1 assume !(1 == ~T2_E~0); 163781#L582-1 assume !(1 == ~T3_E~0); 164079#L587-1 assume !(1 == ~T4_E~0); 164089#L592-1 assume !(1 == ~E_M~0); 163720#L597-1 assume !(1 == ~E_1~0); 163721#L602-1 assume !(1 == ~E_2~0); 164203#L607-1 assume !(1 == ~E_3~0); 164986#L612-1 assume !(1 == ~E_4~0); 164983#L617-1 assume { :end_inline_reset_delta_events } true; 164981#L803-2 assume !false; 164918#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 164916#L489-1 [2023-11-28 23:52:07,363 INFO L750 eck$LassoCheckResult]: Loop: 164916#L489-1 assume !false; 164914#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 164911#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 164909#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 164907#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 164906#L428 assume 0 != eval_~tmp~0#1; 164904#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 164900#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 164898#L436-2 havoc eval_~tmp_ndt_1~0#1; 164895#L433-1 assume !(0 == ~t1_st~0); 164890#L447-1 assume !(0 == ~t2_st~0); 164891#L461-1 assume !(0 == ~t3_st~0); 164920#L475-1 assume !(0 == ~t4_st~0); 164916#L489-1 [2023-11-28 23:52:07,364 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:07,364 INFO L85 PathProgramCache]: Analyzing trace with hash 600428717, now seen corresponding path program 1 times [2023-11-28 23:52:07,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:07,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347480357] [2023-11-28 23:52:07,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:07,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:07,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:07,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:07,395 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:07,395 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347480357] [2023-11-28 23:52:07,395 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347480357] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:07,395 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:07,395 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:07,396 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [819577443] [2023-11-28 23:52:07,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:07,396 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 23:52:07,396 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:07,396 INFO L85 PathProgramCache]: Analyzing trace with hash 1561748980, now seen corresponding path program 2 times [2023-11-28 23:52:07,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:07,397 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678295376] [2023-11-28 23:52:07,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:07,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:07,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:07,401 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:07,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:07,405 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:07,474 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:07,475 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:07,475 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:07,475 INFO L87 Difference]: Start difference. First operand 16722 states and 22211 transitions. cyclomatic complexity: 5501 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:07,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:07,593 INFO L93 Difference]: Finished difference Result 16662 states and 22132 transitions. [2023-11-28 23:52:07,593 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16662 states and 22132 transitions. [2023-11-28 23:52:07,655 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 16404 [2023-11-28 23:52:07,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16662 states to 16662 states and 22132 transitions. [2023-11-28 23:52:07,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16662 [2023-11-28 23:52:07,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16662 [2023-11-28 23:52:07,715 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16662 states and 22132 transitions. [2023-11-28 23:52:07,727 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:07,727 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16662 states and 22132 transitions. [2023-11-28 23:52:07,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16662 states and 22132 transitions. [2023-11-28 23:52:07,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16662 to 16662. [2023-11-28 23:52:07,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16662 states, 16662 states have (on average 1.3282919217380866) internal successors, (22132), 16661 states have internal predecessors, (22132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:07,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16662 states to 16662 states and 22132 transitions. [2023-11-28 23:52:07,909 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16662 states and 22132 transitions. [2023-11-28 23:52:07,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:07,910 INFO L428 stractBuchiCegarLoop]: Abstraction has 16662 states and 22132 transitions. [2023-11-28 23:52:07,910 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-28 23:52:07,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16662 states and 22132 transitions. [2023-11-28 23:52:07,955 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 16404 [2023-11-28 23:52:07,955 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:07,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:07,956 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:07,956 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:07,957 INFO L748 eck$LassoCheckResult]: Stem: 197329#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 197330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 197437#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 197438#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 197231#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 197232#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 197517#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 197174#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 197175#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 197319#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 197201#L514 assume !(0 == ~M_E~0); 197202#L514-2 assume !(0 == ~T1_E~0); 197539#L519-1 assume !(0 == ~T2_E~0); 197162#L524-1 assume !(0 == ~T3_E~0); 197163#L529-1 assume !(0 == ~T4_E~0); 197292#L534-1 assume !(0 == ~E_M~0); 197488#L539-1 assume !(0 == ~E_1~0); 197489#L544-1 assume !(0 == ~E_2~0); 197515#L549-1 assume !(0 == ~E_3~0); 197516#L554-1 assume !(0 == ~E_4~0); 197157#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 197158#L250 assume !(1 == ~m_pc~0); 197394#L250-2 is_master_triggered_~__retres1~0#1 := 0; 197519#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 197306#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 197307#L637 assume !(0 != activate_threads_~tmp~1#1); 197164#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 197165#L269 assume !(1 == ~t1_pc~0); 197103#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 197287#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 197151#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 197152#L645 assume !(0 != activate_threads_~tmp___0~0#1); 197359#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 197360#L288 assume !(1 == ~t2_pc~0); 197353#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 197354#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 197445#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 197446#L653 assume !(0 != activate_threads_~tmp___1~0#1); 197483#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 197382#L307 assume !(1 == ~t3_pc~0); 197309#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 197310#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 197106#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 197107#L661 assume !(0 != activate_threads_~tmp___2~0#1); 197327#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 197328#L326 assume !(1 == ~t4_pc~0); 197118#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 197119#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 197205#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 197206#L669 assume !(0 != activate_threads_~tmp___3~0#1); 197485#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 197486#L572 assume !(1 == ~M_E~0); 197520#L572-2 assume !(1 == ~T1_E~0); 197170#L577-1 assume !(1 == ~T2_E~0); 197171#L582-1 assume !(1 == ~T3_E~0); 197468#L587-1 assume !(1 == ~T4_E~0); 197476#L592-1 assume !(1 == ~E_M~0); 197112#L597-1 assume !(1 == ~E_1~0); 197113#L602-1 assume !(1 == ~E_2~0); 197350#L607-1 assume !(1 == ~E_3~0); 197351#L612-1 assume !(1 == ~E_4~0); 197290#L617-1 assume { :end_inline_reset_delta_events } true; 197291#L803-2 assume !false; 198542#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 198536#L489-1 [2023-11-28 23:52:07,957 INFO L750 eck$LassoCheckResult]: Loop: 198536#L489-1 assume !false; 198529#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 198522#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 198515#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 198508#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 198504#L428 assume 0 != eval_~tmp~0#1; 198496#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 198466#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 198465#L436-2 havoc eval_~tmp_ndt_1~0#1; 198464#L433-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 198448#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 198445#L450-2 havoc eval_~tmp_ndt_2~0#1; 198436#L447-1 assume !(0 == ~t2_st~0); 198437#L461-1 assume !(0 == ~t3_st~0); 198544#L475-1 assume !(0 == ~t4_st~0); 198536#L489-1 [2023-11-28 23:52:07,957 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:07,957 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 2 times [2023-11-28 23:52:07,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:07,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149688258] [2023-11-28 23:52:07,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:07,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:07,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:07,967 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:07,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:07,983 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:07,983 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:07,984 INFO L85 PathProgramCache]: Analyzing trace with hash 1594291277, now seen corresponding path program 1 times [2023-11-28 23:52:07,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:07,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1049981786] [2023-11-28 23:52:07,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:07,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:07,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:07,988 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:07,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:07,991 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:07,992 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:07,992 INFO L85 PathProgramCache]: Analyzing trace with hash -310230045, now seen corresponding path program 1 times [2023-11-28 23:52:07,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:07,992 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [253984017] [2023-11-28 23:52:07,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:07,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:08,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:08,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:08,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:08,031 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [253984017] [2023-11-28 23:52:08,031 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [253984017] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:08,031 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:08,031 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:08,031 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1393437853] [2023-11-28 23:52:08,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:08,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:08,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:08,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:08,102 INFO L87 Difference]: Start difference. First operand 16662 states and 22132 transitions. cyclomatic complexity: 5482 Second operand has 3 states, 3 states have (on average 26.333333333333332) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:08,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:08,256 INFO L93 Difference]: Finished difference Result 19491 states and 25805 transitions. [2023-11-28 23:52:08,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19491 states and 25805 transitions. [2023-11-28 23:52:08,321 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 19169 [2023-11-28 23:52:08,362 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19491 states to 19491 states and 25805 transitions. [2023-11-28 23:52:08,362 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19491 [2023-11-28 23:52:08,373 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19491 [2023-11-28 23:52:08,374 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19491 states and 25805 transitions. [2023-11-28 23:52:08,393 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:08,393 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19491 states and 25805 transitions. [2023-11-28 23:52:08,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19491 states and 25805 transitions. [2023-11-28 23:52:08,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19491 to 18721. [2023-11-28 23:52:08,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18721 states, 18721 states have (on average 1.3255167993162758) internal successors, (24815), 18720 states have internal predecessors, (24815), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:08,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18721 states to 18721 states and 24815 transitions. [2023-11-28 23:52:08,597 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18721 states and 24815 transitions. [2023-11-28 23:52:08,597 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:08,598 INFO L428 stractBuchiCegarLoop]: Abstraction has 18721 states and 24815 transitions. [2023-11-28 23:52:08,598 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-28 23:52:08,598 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18721 states and 24815 transitions. [2023-11-28 23:52:08,650 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 18399 [2023-11-28 23:52:08,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:08,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:08,651 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:08,651 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:08,652 INFO L748 eck$LassoCheckResult]: Stem: 233493#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 233494#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 233610#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 233611#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 233394#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 233395#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 233699#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 233337#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 233338#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 233481#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 233366#L514 assume !(0 == ~M_E~0); 233367#L514-2 assume !(0 == ~T1_E~0); 233725#L519-1 assume !(0 == ~T2_E~0); 233323#L524-1 assume !(0 == ~T3_E~0); 233324#L529-1 assume !(0 == ~T4_E~0); 233454#L534-1 assume !(0 == ~E_M~0); 233667#L539-1 assume !(0 == ~E_1~0); 233668#L544-1 assume !(0 == ~E_2~0); 233695#L549-1 assume !(0 == ~E_3~0); 233696#L554-1 assume !(0 == ~E_4~0); 233318#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 233319#L250 assume !(1 == ~m_pc~0); 233561#L250-2 is_master_triggered_~__retres1~0#1 := 0; 233700#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 233469#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 233470#L637 assume !(0 != activate_threads_~tmp~1#1); 233327#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 233328#L269 assume !(1 == ~t1_pc~0); 233264#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 233449#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 233312#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 233313#L645 assume !(0 != activate_threads_~tmp___0~0#1); 233524#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 233525#L288 assume !(1 == ~t2_pc~0); 233517#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 233518#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 233617#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 233618#L653 assume !(0 != activate_threads_~tmp___1~0#1); 233662#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233549#L307 assume !(1 == ~t3_pc~0); 233472#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 233473#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 233267#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 233268#L661 assume !(0 != activate_threads_~tmp___2~0#1); 233491#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 233492#L326 assume !(1 == ~t4_pc~0); 233279#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 233280#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 233368#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 233369#L669 assume !(0 != activate_threads_~tmp___3~0#1); 233664#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 233665#L572 assume !(1 == ~M_E~0); 233701#L572-2 assume !(1 == ~T1_E~0); 233333#L577-1 assume !(1 == ~T2_E~0); 233334#L582-1 assume !(1 == ~T3_E~0); 233647#L587-1 assume !(1 == ~T4_E~0); 233656#L592-1 assume !(1 == ~E_M~0); 233273#L597-1 assume !(1 == ~E_1~0); 233274#L602-1 assume !(1 == ~E_2~0); 233514#L607-1 assume !(1 == ~E_3~0); 233515#L612-1 assume !(1 == ~E_4~0); 233452#L617-1 assume { :end_inline_reset_delta_events } true; 233453#L803-2 assume !false; 236254#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 236248#L489-1 [2023-11-28 23:52:08,652 INFO L750 eck$LassoCheckResult]: Loop: 236248#L489-1 assume !false; 236240#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 236233#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 236228#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 236220#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 236215#L428 assume 0 != eval_~tmp~0#1; 236209#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 236202#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 236195#L436-2 havoc eval_~tmp_ndt_1~0#1; 236031#L433-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 236032#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 236024#L450-2 havoc eval_~tmp_ndt_2~0#1; 236025#L447-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 236017#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 236018#L464-2 havoc eval_~tmp_ndt_3~0#1; 236277#L461-1 assume !(0 == ~t3_st~0); 236256#L475-1 assume !(0 == ~t4_st~0); 236248#L489-1 [2023-11-28 23:52:08,652 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:08,653 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 3 times [2023-11-28 23:52:08,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:08,653 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498164262] [2023-11-28 23:52:08,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:08,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:08,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:08,663 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:08,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:08,679 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:08,679 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:08,679 INFO L85 PathProgramCache]: Analyzing trace with hash -1337685132, now seen corresponding path program 1 times [2023-11-28 23:52:08,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:08,680 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380311555] [2023-11-28 23:52:08,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:08,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:08,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:08,683 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:08,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:08,687 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:08,687 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:08,687 INFO L85 PathProgramCache]: Analyzing trace with hash -1926607478, now seen corresponding path program 1 times [2023-11-28 23:52:08,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:08,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345771515] [2023-11-28 23:52:08,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:08,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:08,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:08,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:08,726 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:08,726 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345771515] [2023-11-28 23:52:08,726 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1345771515] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:08,727 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:08,727 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 23:52:08,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1631415072] [2023-11-28 23:52:08,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:08,801 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:08,802 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:08,802 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:08,802 INFO L87 Difference]: Start difference. First operand 18721 states and 24815 transitions. cyclomatic complexity: 6107 Second operand has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:09,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:09,000 INFO L93 Difference]: Finished difference Result 33042 states and 43580 transitions. [2023-11-28 23:52:09,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33042 states and 43580 transitions. [2023-11-28 23:52:09,099 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 32464 [2023-11-28 23:52:09,157 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33042 states to 33042 states and 43580 transitions. [2023-11-28 23:52:09,157 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33042 [2023-11-28 23:52:09,175 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33042 [2023-11-28 23:52:09,175 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33042 states and 43580 transitions. [2023-11-28 23:52:09,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:09,191 INFO L218 hiAutomatonCegarLoop]: Abstraction has 33042 states and 43580 transitions. [2023-11-28 23:52:09,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33042 states and 43580 transitions. [2023-11-28 23:52:09,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33042 to 31886. [2023-11-28 23:52:09,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31886 states, 31886 states have (on average 1.3235275669572852) internal successors, (42202), 31885 states have internal predecessors, (42202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:09,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31886 states to 31886 states and 42202 transitions. [2023-11-28 23:52:09,612 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31886 states and 42202 transitions. [2023-11-28 23:52:09,612 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:09,612 INFO L428 stractBuchiCegarLoop]: Abstraction has 31886 states and 42202 transitions. [2023-11-28 23:52:09,612 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-28 23:52:09,613 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31886 states and 42202 transitions. [2023-11-28 23:52:09,694 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 31308 [2023-11-28 23:52:09,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:09,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:09,694 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:09,694 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:09,695 INFO L748 eck$LassoCheckResult]: Stem: 285269#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 285270#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 285390#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 285391#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 285165#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 285166#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 285486#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 285108#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 285109#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 285257#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 285138#L514 assume !(0 == ~M_E~0); 285139#L514-2 assume !(0 == ~T1_E~0); 285506#L519-1 assume !(0 == ~T2_E~0); 285094#L524-1 assume !(0 == ~T3_E~0); 285095#L529-1 assume !(0 == ~T4_E~0); 285229#L534-1 assume !(0 == ~E_M~0); 285454#L539-1 assume !(0 == ~E_1~0); 285455#L544-1 assume !(0 == ~E_2~0); 285482#L549-1 assume !(0 == ~E_3~0); 285483#L554-1 assume !(0 == ~E_4~0); 285089#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 285090#L250 assume !(1 == ~m_pc~0); 285345#L250-2 is_master_triggered_~__retres1~0#1 := 0; 285487#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 285244#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 285245#L637 assume !(0 != activate_threads_~tmp~1#1); 285098#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 285099#L269 assume !(1 == ~t1_pc~0); 285035#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 285224#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 285085#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 285086#L645 assume !(0 != activate_threads_~tmp___0~0#1); 285304#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 285305#L288 assume !(1 == ~t2_pc~0); 285294#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 285295#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 285396#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 285397#L653 assume !(0 != activate_threads_~tmp___1~0#1); 285449#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 285328#L307 assume !(1 == ~t3_pc~0); 285247#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 285248#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 285038#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 285039#L661 assume !(0 != activate_threads_~tmp___2~0#1); 285267#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 285268#L326 assume !(1 == ~t4_pc~0); 285050#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 285051#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 285140#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 285141#L669 assume !(0 != activate_threads_~tmp___3~0#1); 285451#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 285452#L572 assume !(1 == ~M_E~0); 285488#L572-2 assume !(1 == ~T1_E~0); 285104#L577-1 assume !(1 == ~T2_E~0); 285105#L582-1 assume !(1 == ~T3_E~0); 285433#L587-1 assume !(1 == ~T4_E~0); 285442#L592-1 assume !(1 == ~E_M~0); 285048#L597-1 assume !(1 == ~E_1~0); 285049#L602-1 assume !(1 == ~E_2~0); 285291#L607-1 assume !(1 == ~E_3~0); 285292#L612-1 assume !(1 == ~E_4~0); 285227#L617-1 assume { :end_inline_reset_delta_events } true; 285228#L803-2 assume !false; 289378#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 289375#L489-1 [2023-11-28 23:52:09,695 INFO L750 eck$LassoCheckResult]: Loop: 289375#L489-1 assume !false; 289372#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 289367#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 289364#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 289361#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 289358#L428 assume 0 != eval_~tmp~0#1; 289351#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 289346#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 289343#L436-2 havoc eval_~tmp_ndt_1~0#1; 289324#L433-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 289322#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 289321#L450-2 havoc eval_~tmp_ndt_2~0#1; 289320#L447-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 289318#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 289317#L464-2 havoc eval_~tmp_ndt_3~0#1; 289316#L461-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 289251#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 289315#L478-2 havoc eval_~tmp_ndt_4~0#1; 289380#L475-1 assume !(0 == ~t4_st~0); 289375#L489-1 [2023-11-28 23:52:09,695 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:09,695 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 4 times [2023-11-28 23:52:09,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:09,695 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402009783] [2023-11-28 23:52:09,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:09,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:09,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:09,707 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:09,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:09,726 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:09,726 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:09,726 INFO L85 PathProgramCache]: Analyzing trace with hash -1324933107, now seen corresponding path program 1 times [2023-11-28 23:52:09,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:09,727 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20041035] [2023-11-28 23:52:09,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:09,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:09,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:09,731 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:09,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:09,736 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:09,736 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:09,736 INFO L85 PathProgramCache]: Analyzing trace with hash -343624541, now seen corresponding path program 1 times [2023-11-28 23:52:09,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:09,737 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942545762] [2023-11-28 23:52:09,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:09,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:09,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 23:52:09,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 23:52:09,783 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 23:52:09,783 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942545762] [2023-11-28 23:52:09,783 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [942545762] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 23:52:09,783 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 23:52:09,784 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 23:52:09,784 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143717067] [2023-11-28 23:52:09,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 23:52:09,964 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 23:52:09,965 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 23:52:09,965 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 23:52:09,965 INFO L87 Difference]: Start difference. First operand 31886 states and 42202 transitions. cyclomatic complexity: 10329 Second operand has 3 states, 2 states have (on average 41.5) internal successors, (83), 3 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:10,075 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 23:52:10,075 INFO L93 Difference]: Finished difference Result 37559 states and 49485 transitions. [2023-11-28 23:52:10,075 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37559 states and 49485 transitions. [2023-11-28 23:52:10,200 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 36677 [2023-11-28 23:52:10,298 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37559 states to 37559 states and 49485 transitions. [2023-11-28 23:52:10,298 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37559 [2023-11-28 23:52:10,321 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37559 [2023-11-28 23:52:10,321 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37559 states and 49485 transitions. [2023-11-28 23:52:10,341 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 23:52:10,341 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37559 states and 49485 transitions. [2023-11-28 23:52:10,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37559 states and 49485 transitions. [2023-11-28 23:52:10,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37559 to 37271. [2023-11-28 23:52:10,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37271 states, 37271 states have (on average 1.3199806820316062) internal successors, (49197), 37270 states have internal predecessors, (49197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 23:52:10,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37271 states to 37271 states and 49197 transitions. [2023-11-28 23:52:10,917 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37271 states and 49197 transitions. [2023-11-28 23:52:10,918 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 23:52:10,918 INFO L428 stractBuchiCegarLoop]: Abstraction has 37271 states and 49197 transitions. [2023-11-28 23:52:10,918 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-28 23:52:10,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37271 states and 49197 transitions. [2023-11-28 23:52:10,997 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 36389 [2023-11-28 23:52:10,997 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 23:52:10,997 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 23:52:10,998 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:10,998 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 23:52:10,998 INFO L748 eck$LassoCheckResult]: Stem: 354714#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 354715#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 354839#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 354840#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 354617#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 354618#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 354932#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 354561#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 354562#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 354703#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 354590#L514 assume !(0 == ~M_E~0); 354591#L514-2 assume !(0 == ~T1_E~0); 354957#L519-1 assume !(0 == ~T2_E~0); 354549#L524-1 assume !(0 == ~T3_E~0); 354550#L529-1 assume !(0 == ~T4_E~0); 354676#L534-1 assume !(0 == ~E_M~0); 354900#L539-1 assume !(0 == ~E_1~0); 354901#L544-1 assume !(0 == ~E_2~0); 354928#L549-1 assume !(0 == ~E_3~0); 354929#L554-1 assume !(0 == ~E_4~0); 354544#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 354545#L250 assume !(1 == ~m_pc~0); 354789#L250-2 is_master_triggered_~__retres1~0#1 := 0; 354933#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 354690#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 354691#L637 assume !(0 != activate_threads_~tmp~1#1); 354551#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 354552#L269 assume !(1 == ~t1_pc~0); 354489#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 354671#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 354540#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 354541#L645 assume !(0 != activate_threads_~tmp___0~0#1); 354747#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 354748#L288 assume !(1 == ~t2_pc~0); 354740#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 354741#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 354845#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 354846#L653 assume !(0 != activate_threads_~tmp___1~0#1); 354896#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 354769#L307 assume !(1 == ~t3_pc~0); 354693#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 354694#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 354492#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 354493#L661 assume !(0 != activate_threads_~tmp___2~0#1); 354712#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 354713#L326 assume !(1 == ~t4_pc~0); 354504#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 354505#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 354592#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 354593#L669 assume !(0 != activate_threads_~tmp___3~0#1); 354897#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 354898#L572 assume !(1 == ~M_E~0); 354934#L572-2 assume !(1 == ~T1_E~0); 354557#L577-1 assume !(1 == ~T2_E~0); 354558#L582-1 assume !(1 == ~T3_E~0); 354881#L587-1 assume !(1 == ~T4_E~0); 354890#L592-1 assume !(1 == ~E_M~0); 354502#L597-1 assume !(1 == ~E_1~0); 354503#L602-1 assume !(1 == ~E_2~0); 354737#L607-1 assume !(1 == ~E_3~0); 354738#L612-1 assume !(1 == ~E_4~0); 354674#L617-1 assume { :end_inline_reset_delta_events } true; 354675#L803-2 assume !false; 363307#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 363304#L489-1 [2023-11-28 23:52:10,998 INFO L750 eck$LassoCheckResult]: Loop: 363304#L489-1 assume !false; 363302#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 363300#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 363297#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 363295#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 363293#L428 assume 0 != eval_~tmp~0#1; 363294#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 364105#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 364085#L436-2 havoc eval_~tmp_ndt_1~0#1; 360271#L433-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 360268#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 360266#L450-2 havoc eval_~tmp_ndt_2~0#1; 360264#L447-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 360261#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 360259#L464-2 havoc eval_~tmp_ndt_3~0#1; 360256#L461-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 360117#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 360254#L478-2 havoc eval_~tmp_ndt_4~0#1; 363607#L475-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 363310#L492 assume !(0 != eval_~tmp_ndt_5~0#1); 363308#L492-2 havoc eval_~tmp_ndt_5~0#1; 363304#L489-1 [2023-11-28 23:52:10,999 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:10,999 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 5 times [2023-11-28 23:52:10,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:10,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [526767295] [2023-11-28 23:52:10,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:10,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:11,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:11,009 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:11,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:11,025 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:11,026 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:11,026 INFO L85 PathProgramCache]: Analyzing trace with hash -1950508812, now seen corresponding path program 1 times [2023-11-28 23:52:11,026 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:11,026 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977887863] [2023-11-28 23:52:11,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:11,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:11,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:11,030 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:11,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:11,034 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:11,034 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 23:52:11,034 INFO L85 PathProgramCache]: Analyzing trace with hash 489185290, now seen corresponding path program 1 times [2023-11-28 23:52:11,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 23:52:11,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1858454010] [2023-11-28 23:52:11,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 23:52:11,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 23:52:11,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:11,045 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:11,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:11,060 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 23:52:12,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:12,555 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 23:52:12,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 23:52:12,723 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.11 11:52:12 BoogieIcfgContainer [2023-11-28 23:52:12,723 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-28 23:52:12,724 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-28 23:52:12,724 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-28 23:52:12,724 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-28 23:52:12,725 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 11:52:00" (3/4) ... [2023-11-28 23:52:12,726 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-28 23:52:12,821 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/witness.graphml [2023-11-28 23:52:12,821 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-28 23:52:12,822 INFO L158 Benchmark]: Toolchain (without parser) took 14156.37ms. Allocated memory was 159.4MB in the beginning and 3.5GB in the end (delta: 3.4GB). Free memory was 127.4MB in the beginning and 2.8GB in the end (delta: -2.7GB). Peak memory consumption was 645.9MB. Max. memory is 16.1GB. [2023-11-28 23:52:12,822 INFO L158 Benchmark]: CDTParser took 0.16ms. Allocated memory is still 113.2MB. Free memory is still 86.1MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-28 23:52:12,823 INFO L158 Benchmark]: CACSL2BoogieTranslator took 305.61ms. Allocated memory is still 159.4MB. Free memory was 127.4MB in the beginning and 112.1MB in the end (delta: 15.3MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-28 23:52:12,823 INFO L158 Benchmark]: Boogie Procedure Inliner took 71.66ms. Allocated memory is still 159.4MB. Free memory was 112.1MB in the beginning and 107.2MB in the end (delta: 4.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-28 23:52:12,823 INFO L158 Benchmark]: Boogie Preprocessor took 90.16ms. Allocated memory is still 159.4MB. Free memory was 107.2MB in the beginning and 102.3MB in the end (delta: 4.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-28 23:52:12,824 INFO L158 Benchmark]: RCFGBuilder took 958.15ms. Allocated memory is still 159.4MB. Free memory was 102.3MB in the beginning and 82.4MB in the end (delta: 19.9MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2023-11-28 23:52:12,824 INFO L158 Benchmark]: BuchiAutomizer took 12628.11ms. Allocated memory was 159.4MB in the beginning and 3.5GB in the end (delta: 3.4GB). Free memory was 82.4MB in the beginning and 2.8GB in the end (delta: -2.8GB). Peak memory consumption was 595.8MB. Max. memory is 16.1GB. [2023-11-28 23:52:12,825 INFO L158 Benchmark]: Witness Printer took 97.81ms. Allocated memory is still 3.5GB. Free memory was 2.8GB in the beginning and 2.8GB in the end (delta: 9.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2023-11-28 23:52:12,827 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16ms. Allocated memory is still 113.2MB. Free memory is still 86.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 305.61ms. Allocated memory is still 159.4MB. Free memory was 127.4MB in the beginning and 112.1MB in the end (delta: 15.3MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 71.66ms. Allocated memory is still 159.4MB. Free memory was 112.1MB in the beginning and 107.2MB in the end (delta: 4.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 90.16ms. Allocated memory is still 159.4MB. Free memory was 107.2MB in the beginning and 102.3MB in the end (delta: 4.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 958.15ms. Allocated memory is still 159.4MB. Free memory was 102.3MB in the beginning and 82.4MB in the end (delta: 19.9MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 12628.11ms. Allocated memory was 159.4MB in the beginning and 3.5GB in the end (delta: 3.4GB). Free memory was 82.4MB in the beginning and 2.8GB in the end (delta: -2.8GB). Peak memory consumption was 595.8MB. Max. memory is 16.1GB. * Witness Printer took 97.81ms. Allocated memory is still 3.5GB. Free memory was 2.8GB in the beginning and 2.8GB in the end (delta: 9.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 37271 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 12.4s and 24 iterations. TraceHistogramMax:1. Analysis of lassos took 4.5s. Construction of modules took 0.8s. Büchi inclusion checks took 6.3s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 3.0s AutomataMinimizationTime, 23 MinimizatonAttempts, 19812 StatesRemovedByMinimization, 16 NontrivialMinimizations. Non-live state removal took 1.5s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 15669 SdHoareTripleChecker+Valid, 1.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 15669 mSDsluCounter, 29915 SdHoareTripleChecker+Invalid, 0.8s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 13568 mSDsCounter, 257 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 773 IncrementalHoareTripleChecker+Invalid, 1030 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 257 mSolverCounterUnsat, 16347 mSDtfsCounter, 773 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 423]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L848] int __retres1 ; [L852] CALL init_model() [L760] m_i = 1 [L761] t1_i = 1 [L762] t2_i = 1 [L763] t3_i = 1 [L764] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L852] RET init_model() [L853] CALL start_simulation() [L789] int kernel_st ; [L790] int tmp ; [L791] int tmp___0 ; [L795] kernel_st = 0 [L796] FCALL update_channels() [L797] CALL init_threads() [L353] COND TRUE m_i == 1 [L354] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L358] COND TRUE t1_i == 1 [L359] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L363] COND TRUE t2_i == 1 [L364] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L368] COND TRUE t3_i == 1 [L369] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L373] COND TRUE t4_i == 1 [L374] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L797] RET init_threads() [L798] CALL fire_delta_events() [L514] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L519] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L524] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L529] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L534] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L539] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L544] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L549] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L554] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L559] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L798] RET fire_delta_events() [L799] CALL activate_threads() [L627] int tmp ; [L628] int tmp___0 ; [L629] int tmp___1 ; [L630] int tmp___2 ; [L631] int tmp___3 ; [L635] CALL, EXPR is_master_triggered() [L247] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L250] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L260] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L635] RET, EXPR is_master_triggered() [L635] tmp = is_master_triggered() [L637] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L643] CALL, EXPR is_transmit1_triggered() [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L269] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L279] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] RET, EXPR is_transmit1_triggered() [L643] tmp___0 = is_transmit1_triggered() [L645] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L651] CALL, EXPR is_transmit2_triggered() [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L288] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L298] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] RET, EXPR is_transmit2_triggered() [L651] tmp___1 = is_transmit2_triggered() [L653] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L659] CALL, EXPR is_transmit3_triggered() [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L307] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L317] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] RET, EXPR is_transmit3_triggered() [L659] tmp___2 = is_transmit3_triggered() [L661] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L667] CALL, EXPR is_transmit4_triggered() [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L326] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L336] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] RET, EXPR is_transmit4_triggered() [L667] tmp___3 = is_transmit4_triggered() [L669] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L799] RET activate_threads() [L800] CALL reset_delta_events() [L572] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L577] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L582] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L587] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L592] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L597] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L602] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L607] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L612] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L617] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L800] RET reset_delta_events() [L803] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L806] kernel_st = 1 [L807] CALL eval() [L419] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L423] COND TRUE 1 [L426] CALL, EXPR exists_runnable_thread() [L383] int __retres1 ; [L386] COND TRUE m_st == 0 [L387] __retres1 = 1 [L414] return (__retres1); [L426] RET, EXPR exists_runnable_thread() [L426] tmp = exists_runnable_thread() [L428] COND TRUE \read(tmp) [L433] COND TRUE m_st == 0 [L434] int tmp_ndt_1; [L435] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L436] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L433-L444] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L447] COND TRUE t1_st == 0 [L448] int tmp_ndt_2; [L449] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L450] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L447-L458] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L461] COND TRUE t2_st == 0 [L462] int tmp_ndt_3; [L463] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L464] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L461-L472] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L475] COND TRUE t3_st == 0 [L476] int tmp_ndt_4; [L477] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L478] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L475-L486] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L489] COND TRUE t4_st == 0 [L490] int tmp_ndt_5; [L491] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L492] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L489-L500] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 423]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L848] int __retres1 ; [L852] CALL init_model() [L760] m_i = 1 [L761] t1_i = 1 [L762] t2_i = 1 [L763] t3_i = 1 [L764] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L852] RET init_model() [L853] CALL start_simulation() [L789] int kernel_st ; [L790] int tmp ; [L791] int tmp___0 ; [L795] kernel_st = 0 [L796] FCALL update_channels() [L797] CALL init_threads() [L353] COND TRUE m_i == 1 [L354] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L358] COND TRUE t1_i == 1 [L359] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L363] COND TRUE t2_i == 1 [L364] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L368] COND TRUE t3_i == 1 [L369] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L373] COND TRUE t4_i == 1 [L374] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L797] RET init_threads() [L798] CALL fire_delta_events() [L514] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L519] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L524] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L529] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L534] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L539] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L544] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L549] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L554] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L559] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L798] RET fire_delta_events() [L799] CALL activate_threads() [L627] int tmp ; [L628] int tmp___0 ; [L629] int tmp___1 ; [L630] int tmp___2 ; [L631] int tmp___3 ; [L635] CALL, EXPR is_master_triggered() [L247] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L250] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L260] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L635] RET, EXPR is_master_triggered() [L635] tmp = is_master_triggered() [L637] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L643] CALL, EXPR is_transmit1_triggered() [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L269] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L279] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] RET, EXPR is_transmit1_triggered() [L643] tmp___0 = is_transmit1_triggered() [L645] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L651] CALL, EXPR is_transmit2_triggered() [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L288] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L298] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] RET, EXPR is_transmit2_triggered() [L651] tmp___1 = is_transmit2_triggered() [L653] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L659] CALL, EXPR is_transmit3_triggered() [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L307] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L317] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] RET, EXPR is_transmit3_triggered() [L659] tmp___2 = is_transmit3_triggered() [L661] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L667] CALL, EXPR is_transmit4_triggered() [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L326] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L336] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] RET, EXPR is_transmit4_triggered() [L667] tmp___3 = is_transmit4_triggered() [L669] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L799] RET activate_threads() [L800] CALL reset_delta_events() [L572] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L577] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L582] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L587] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L592] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L597] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L602] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L607] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L612] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L617] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L800] RET reset_delta_events() [L803] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L806] kernel_st = 1 [L807] CALL eval() [L419] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L423] COND TRUE 1 [L426] CALL, EXPR exists_runnable_thread() [L383] int __retres1 ; [L386] COND TRUE m_st == 0 [L387] __retres1 = 1 [L414] return (__retres1); [L426] RET, EXPR exists_runnable_thread() [L426] tmp = exists_runnable_thread() [L428] COND TRUE \read(tmp) [L433] COND TRUE m_st == 0 [L434] int tmp_ndt_1; [L435] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L436] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L433-L444] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L447] COND TRUE t1_st == 0 [L448] int tmp_ndt_2; [L449] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L450] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L447-L458] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L461] COND TRUE t2_st == 0 [L462] int tmp_ndt_3; [L463] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L464] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L461-L472] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L475] COND TRUE t3_st == 0 [L476] int tmp_ndt_4; [L477] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L478] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L475-L486] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L489] COND TRUE t4_st == 0 [L490] int tmp_ndt_5; [L491] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L492] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L489-L500] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-28 23:52:12,972 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_428865fd-39d4-4e33-9eeb-45199a4c0bba/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)