./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-29 04:14:55,799 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-29 04:14:55,880 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-29 04:14:55,884 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-29 04:14:55,885 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-29 04:14:55,908 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-29 04:14:55,909 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-29 04:14:55,910 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-29 04:14:55,910 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-29 04:14:55,911 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-29 04:14:55,912 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-29 04:14:55,912 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-29 04:14:55,913 INFO L153 SettingsManager]: * Use SBE=true [2023-11-29 04:14:55,913 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-29 04:14:55,914 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-29 04:14:55,914 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-29 04:14:55,915 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-29 04:14:55,915 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-29 04:14:55,916 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-29 04:14:55,916 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-29 04:14:55,917 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-29 04:14:55,917 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-29 04:14:55,918 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-29 04:14:55,918 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-29 04:14:55,919 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-29 04:14:55,919 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-29 04:14:55,920 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-29 04:14:55,920 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-29 04:14:55,920 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-29 04:14:55,921 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-29 04:14:55,921 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-29 04:14:55,921 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-29 04:14:55,922 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-29 04:14:55,922 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-29 04:14:55,923 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-29 04:14:55,923 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-29 04:14:55,923 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-29 04:14:55,924 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-29 04:14:55,924 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 [2023-11-29 04:14:56,159 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-29 04:14:56,179 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-29 04:14:56,183 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-29 04:14:56,184 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-29 04:14:56,184 INFO L274 PluginConnector]: CDTParser initialized [2023-11-29 04:14:56,186 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2023-11-29 04:14:58,964 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-29 04:14:59,156 INFO L384 CDTParser]: Found 1 translation units. [2023-11-29 04:14:59,157 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2023-11-29 04:14:59,170 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/data/c7e5887fb/5618b6f3109b485aae98a1f31c85ee08/FLAGfb75a9efa [2023-11-29 04:14:59,184 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/data/c7e5887fb/5618b6f3109b485aae98a1f31c85ee08 [2023-11-29 04:14:59,187 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-29 04:14:59,189 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-29 04:14:59,190 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-29 04:14:59,190 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-29 04:14:59,195 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-29 04:14:59,196 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 04:14:59" (1/1) ... [2023-11-29 04:14:59,197 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5ae04121 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59, skipping insertion in model container [2023-11-29 04:14:59,198 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 04:14:59" (1/1) ... [2023-11-29 04:14:59,246 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-29 04:14:59,461 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 04:14:59,475 INFO L202 MainTranslator]: Completed pre-run [2023-11-29 04:14:59,523 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 04:14:59,543 INFO L206 MainTranslator]: Completed translation [2023-11-29 04:14:59,543 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59 WrapperNode [2023-11-29 04:14:59,543 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-29 04:14:59,544 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-29 04:14:59,545 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-29 04:14:59,545 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-29 04:14:59,552 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59" (1/1) ... [2023-11-29 04:14:59,564 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59" (1/1) ... [2023-11-29 04:14:59,621 INFO L138 Inliner]: procedures = 40, calls = 50, calls flagged for inlining = 45, calls inlined = 114, statements flattened = 1665 [2023-11-29 04:14:59,622 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-29 04:14:59,623 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-29 04:14:59,623 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-29 04:14:59,623 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-29 04:14:59,635 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59" (1/1) ... [2023-11-29 04:14:59,635 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59" (1/1) ... [2023-11-29 04:14:59,643 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59" (1/1) ... [2023-11-29 04:14:59,669 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-29 04:14:59,669 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59" (1/1) ... [2023-11-29 04:14:59,670 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59" (1/1) ... [2023-11-29 04:14:59,695 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59" (1/1) ... [2023-11-29 04:14:59,714 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59" (1/1) ... [2023-11-29 04:14:59,718 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59" (1/1) ... [2023-11-29 04:14:59,725 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59" (1/1) ... [2023-11-29 04:14:59,734 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-29 04:14:59,735 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-29 04:14:59,736 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-29 04:14:59,736 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-29 04:14:59,737 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59" (1/1) ... [2023-11-29 04:14:59,743 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:14:59,756 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:14:59,768 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:14:59,774 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-29 04:14:59,803 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-29 04:14:59,803 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-29 04:14:59,804 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-29 04:14:59,804 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-29 04:14:59,893 INFO L241 CfgBuilder]: Building ICFG [2023-11-29 04:14:59,895 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-29 04:15:00,866 INFO L282 CfgBuilder]: Performing block encoding [2023-11-29 04:15:00,893 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-29 04:15:00,894 INFO L309 CfgBuilder]: Removed 9 assume(true) statements. [2023-11-29 04:15:00,896 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 04:15:00 BoogieIcfgContainer [2023-11-29 04:15:00,896 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-29 04:15:00,897 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-29 04:15:00,897 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-29 04:15:00,901 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-29 04:15:00,901 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 04:15:00,902 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.11 04:14:59" (1/3) ... [2023-11-29 04:15:00,902 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2e6e11cc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 04:15:00, skipping insertion in model container [2023-11-29 04:15:00,902 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 04:15:00,902 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:14:59" (2/3) ... [2023-11-29 04:15:00,903 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2e6e11cc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 04:15:00, skipping insertion in model container [2023-11-29 04:15:00,903 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 04:15:00,903 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 04:15:00" (3/3) ... [2023-11-29 04:15:00,904 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-2.c [2023-11-29 04:15:00,968 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-29 04:15:00,968 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-29 04:15:00,968 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-29 04:15:00,968 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-29 04:15:00,968 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-29 04:15:00,968 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-29 04:15:00,968 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-29 04:15:00,968 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-29 04:15:00,977 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:01,029 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 600 [2023-11-29 04:15:01,029 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:01,029 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:01,042 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:01,042 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:01,043 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-29 04:15:01,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:01,055 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 600 [2023-11-29 04:15:01,055 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:01,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:01,060 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:01,060 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:01,067 INFO L748 eck$LassoCheckResult]: Stem: 216#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 578#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 324#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 573#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91#L475true assume !(1 == ~m_i~0);~m_st~0 := 2; 561#L475-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 323#L480-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 628#L485-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 263#L490-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 126#L495-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 467#L500-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 80#L505-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 536#L684true assume !(0 == ~M_E~0); 451#L684-2true assume !(0 == ~T1_E~0); 291#L689-1true assume !(0 == ~T2_E~0); 671#L694-1true assume !(0 == ~T3_E~0); 290#L699-1true assume !(0 == ~T4_E~0); 445#L704-1true assume !(0 == ~T5_E~0); 249#L709-1true assume !(0 == ~T6_E~0); 205#L714-1true assume 0 == ~E_M~0;~E_M~0 := 1; 410#L719-1true assume !(0 == ~E_1~0); 595#L724-1true assume !(0 == ~E_2~0); 65#L729-1true assume !(0 == ~E_3~0); 569#L734-1true assume !(0 == ~E_4~0); 503#L739-1true assume !(0 == ~E_5~0); 179#L744-1true assume !(0 == ~E_6~0); 411#L749-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43#L334true assume !(1 == ~m_pc~0); 244#L334-2true is_master_triggered_~__retres1~0#1 := 0; 514#L345true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 182#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 161#L849true assume !(0 != activate_threads_~tmp~1#1); 375#L849-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125#L353true assume 1 == ~t1_pc~0; 603#L354true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 327#L364true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 302#L857true assume !(0 != activate_threads_~tmp___0~0#1); 94#L857-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567#L372true assume !(1 == ~t2_pc~0); 167#L372-2true is_transmit2_triggered_~__retres1~2#1 := 0; 240#L383true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 328#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 488#L865true assume !(0 != activate_threads_~tmp___1~0#1); 38#L865-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 463#L391true assume 1 == ~t3_pc~0; 586#L392true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 114#L402true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 401#L873true assume !(0 != activate_threads_~tmp___2~0#1); 164#L873-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 485#L410true assume 1 == ~t4_pc~0; 602#L411true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 380#L421true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 490#L881true assume !(0 != activate_threads_~tmp___3~0#1); 169#L881-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 284#L429true assume !(1 == ~t5_pc~0); 68#L429-2true is_transmit5_triggered_~__retres1~5#1 := 0; 660#L440true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 189#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 349#L889true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 372#L889-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 159#L448true assume 1 == ~t6_pc~0; 88#L449true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 346#L459true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 314#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 541#L897true assume !(0 != activate_threads_~tmp___5~0#1); 648#L897-2true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 640#L762true assume !(1 == ~M_E~0); 193#L762-2true assume !(1 == ~T1_E~0); 600#L767-1true assume !(1 == ~T2_E~0); 550#L772-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 373#L777-1true assume !(1 == ~T4_E~0); 276#L782-1true assume !(1 == ~T5_E~0); 83#L787-1true assume !(1 == ~T6_E~0); 82#L792-1true assume !(1 == ~E_M~0); 106#L797-1true assume !(1 == ~E_1~0); 429#L802-1true assume !(1 == ~E_2~0); 247#L807-1true assume !(1 == ~E_3~0); 498#L812-1true assume 1 == ~E_4~0;~E_4~0 := 2; 619#L817-1true assume !(1 == ~E_5~0); 292#L822-1true assume !(1 == ~E_6~0); 512#L827-1true assume { :end_inline_reset_delta_events } true; 162#L1053-2true [2023-11-29 04:15:01,070 INFO L750 eck$LassoCheckResult]: Loop: 162#L1053-2true assume !false; 487#L1054true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 376#L659-1true assume false; 110#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 507#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 266#L684-3true assume 0 == ~M_E~0;~M_E~0 := 1; 438#L684-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 2#L689-3true assume !(0 == ~T2_E~0); 191#L694-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 28#L699-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 359#L704-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 492#L709-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 337#L714-3true assume 0 == ~E_M~0;~E_M~0 := 1; 186#L719-3true assume 0 == ~E_1~0;~E_1~0 := 1; 25#L724-3true assume 0 == ~E_2~0;~E_2~0 := 1; 318#L729-3true assume !(0 == ~E_3~0); 382#L734-3true assume 0 == ~E_4~0;~E_4~0 := 1; 363#L739-3true assume 0 == ~E_5~0;~E_5~0 := 1; 542#L744-3true assume 0 == ~E_6~0;~E_6~0 := 1; 494#L749-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31#L334-24true assume 1 == ~m_pc~0; 310#L335-8true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 332#L345-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121#is_master_triggered_returnLabel#9true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17#L849-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 625#L849-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 361#L353-24true assume !(1 == ~t1_pc~0); 634#L353-26true is_transmit1_triggered_~__retres1~1#1 := 0; 556#L364-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 553#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 589#L857-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39#L857-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72#L372-24true assume 1 == ~t2_pc~0; 22#L373-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 230#L383-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 679#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 535#L865-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 662#L865-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 207#L391-24true assume !(1 == ~t3_pc~0); 633#L391-26true is_transmit3_triggered_~__retres1~3#1 := 0; 412#L402-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 362#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 277#L873-24true assume !(0 != activate_threads_~tmp___2~0#1); 254#L873-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 141#L410-24true assume 1 == ~t4_pc~0; 107#L411-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 386#L421-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 493#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 168#L881-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 81#L881-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 139#L429-24true assume 1 == ~t5_pc~0; 282#L430-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 385#L440-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 255#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 109#L889-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 223#L889-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79#L448-24true assume 1 == ~t6_pc~0; 112#L449-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 74#L459-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 175#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 520#L897-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 285#L897-26true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 511#L762-3true assume 1 == ~M_E~0;~M_E~0 := 2; 251#L762-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 580#L767-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 668#L772-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 546#L777-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 69#L782-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 647#L787-3true assume !(1 == ~T6_E~0); 394#L792-3true assume 1 == ~E_M~0;~E_M~0 := 2; 206#L797-3true assume 1 == ~E_1~0;~E_1~0 := 2; 453#L802-3true assume 1 == ~E_2~0;~E_2~0 := 2; 664#L807-3true assume 1 == ~E_3~0;~E_3~0 := 2; 315#L812-3true assume 1 == ~E_4~0;~E_4~0 := 2; 506#L817-3true assume 1 == ~E_5~0;~E_5~0 := 2; 404#L822-3true assume 1 == ~E_6~0;~E_6~0 := 2; 388#L827-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 221#L518-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 389#L555-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 301#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 620#L1072true assume !(0 == start_simulation_~tmp~3#1); 151#L1072-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 502#L518-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 75#L555-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 49#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 34#L1027true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 605#L1034true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 524#stop_simulation_returnLabel#1true start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 407#L1085true assume !(0 != start_simulation_~tmp___0~1#1); 162#L1053-2true [2023-11-29 04:15:01,077 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:01,077 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2023-11-29 04:15:01,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:01,085 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683001109] [2023-11-29 04:15:01,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:01,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:01,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:01,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:01,305 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:01,306 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683001109] [2023-11-29 04:15:01,306 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [683001109] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:01,306 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:01,307 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:01,308 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1435030915] [2023-11-29 04:15:01,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:01,312 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:01,313 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:01,313 INFO L85 PathProgramCache]: Analyzing trace with hash 1316317370, now seen corresponding path program 1 times [2023-11-29 04:15:01,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:01,314 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973526733] [2023-11-29 04:15:01,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:01,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:01,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:01,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:01,360 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:01,360 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1973526733] [2023-11-29 04:15:01,360 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1973526733] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:01,361 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:01,361 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:15:01,361 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [761799570] [2023-11-29 04:15:01,361 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:01,362 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:01,363 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:01,389 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:01,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:01,392 INFO L87 Difference]: Start difference. First operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:01,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:01,452 INFO L93 Difference]: Finished difference Result 693 states and 1031 transitions. [2023-11-29 04:15:01,454 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1031 transitions. [2023-11-29 04:15:01,460 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-29 04:15:01,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 688 states and 1026 transitions. [2023-11-29 04:15:01,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2023-11-29 04:15:01,472 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2023-11-29 04:15:01,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1026 transitions. [2023-11-29 04:15:01,477 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:01,477 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1026 transitions. [2023-11-29 04:15:01,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1026 transitions. [2023-11-29 04:15:01,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2023-11-29 04:15:01,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4912790697674418) internal successors, (1026), 687 states have internal predecessors, (1026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:01,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1026 transitions. [2023-11-29 04:15:01,557 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1026 transitions. [2023-11-29 04:15:01,558 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:01,561 INFO L428 stractBuchiCegarLoop]: Abstraction has 688 states and 1026 transitions. [2023-11-29 04:15:01,562 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-29 04:15:01,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1026 transitions. [2023-11-29 04:15:01,566 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-29 04:15:01,566 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:01,566 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:01,568 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:01,569 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:01,569 INFO L748 eck$LassoCheckResult]: Stem: 1789#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1915#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1916#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1583#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1584#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1911#L480-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1912#L485-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1843#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1637#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1638#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1561#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1562#L684 assume !(0 == ~M_E~0); 2013#L684-2 assume !(0 == ~T1_E~0); 1872#L689-1 assume !(0 == ~T2_E~0); 1873#L694-1 assume !(0 == ~T3_E~0); 1870#L699-1 assume !(0 == ~T4_E~0); 1871#L704-1 assume !(0 == ~T5_E~0); 1828#L709-1 assume !(0 == ~T6_E~0); 1767#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1768#L719-1 assume !(0 == ~E_1~0); 1987#L724-1 assume !(0 == ~E_2~0); 1533#L729-1 assume !(0 == ~E_3~0); 1534#L734-1 assume !(0 == ~E_4~0); 2040#L739-1 assume !(0 == ~E_5~0); 1730#L744-1 assume !(0 == ~E_6~0); 1731#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1490#L334 assume !(1 == ~m_pc~0); 1491#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1820#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1733#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1701#L849 assume !(0 != activate_threads_~tmp~1#1); 1702#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1634#L353 assume 1 == ~t1_pc~0; 1635#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1917#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1505#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1506#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1586#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1587#L372 assume !(1 == ~t2_pc~0); 1690#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1689#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1815#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1918#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1479#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1480#L391 assume 1 == ~t3_pc~0; 2024#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1402#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1428#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1429#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1708#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1709#L410 assume 1 == ~t4_pc~0; 2031#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1932#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1600#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1601#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1717#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1718#L429 assume !(1 == ~t5_pc~0); 1539#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1540#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1743#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1744#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1935#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1700#L448 assume 1 == ~t6_pc~0; 1574#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1575#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1903#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1904#L897 assume !(0 != activate_threads_~tmp___5~0#1); 2059#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2082#L762 assume !(1 == ~M_E~0); 1747#L762-2 assume !(1 == ~T1_E~0); 1748#L767-1 assume !(1 == ~T2_E~0); 2064#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1963#L777-1 assume !(1 == ~T4_E~0); 1858#L782-1 assume !(1 == ~T5_E~0); 1565#L787-1 assume !(1 == ~T6_E~0); 1563#L792-1 assume !(1 == ~E_M~0); 1564#L797-1 assume !(1 == ~E_1~0); 1606#L802-1 assume !(1 == ~E_2~0); 1824#L807-1 assume !(1 == ~E_3~0); 1825#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2035#L817-1 assume !(1 == ~E_5~0); 1876#L822-1 assume !(1 == ~E_6~0); 1877#L827-1 assume { :end_inline_reset_delta_events } true; 1703#L1053-2 [2023-11-29 04:15:01,570 INFO L750 eck$LassoCheckResult]: Loop: 1703#L1053-2 assume !false; 1704#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1679#L659-1 assume !false; 1668#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1669#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1671#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1937#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1938#L570 assume !(0 != eval_~tmp~0#1); 1611#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1612#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1849#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1850#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1397#L689-3 assume !(0 == ~T2_E~0); 1398#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1457#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1458#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1944#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1929#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1742#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1450#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1451#L729-3 assume !(0 == ~E_3~0); 1908#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1950#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1951#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2033#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1464#L334-24 assume !(1 == ~m_pc~0); 1465#L334-26 is_master_triggered_~__retres1~0#1 := 0; 1604#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1629#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1436#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1437#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1945#L353-24 assume 1 == ~t1_pc~0; 1946#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1975#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2065#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2066#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1481#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1482#L372-24 assume 1 == ~t2_pc~0; 1443#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1444#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1803#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2052#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2053#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1772#L391-24 assume !(1 == ~t3_pc~0); 1773#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1988#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1948#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1859#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 1834#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1667#L410-24 assume 1 == ~t4_pc~0; 1605#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1531#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1968#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1713#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1559#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1560#L429-24 assume 1 == ~t5_pc~0; 1664#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1863#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1835#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1609#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1610#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1554#L448-24 assume 1 == ~t6_pc~0; 1555#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1548#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1549#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1724#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1866#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1867#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1832#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1833#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2071#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2061#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1541#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1542#L787-3 assume !(1 == ~T6_E~0); 1976#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1769#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1770#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2015#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1901#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1902#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1982#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1972#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1796#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1441#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1888#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1889#L1072 assume !(0 == start_simulation_~tmp~3#1); 1684#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1685#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1550#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1504#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1469#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1470#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2047#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1985#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1703#L1053-2 [2023-11-29 04:15:01,570 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:01,571 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2023-11-29 04:15:01,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:01,571 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1727515711] [2023-11-29 04:15:01,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:01,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:01,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:01,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:01,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:01,641 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1727515711] [2023-11-29 04:15:01,641 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1727515711] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:01,641 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:01,641 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:01,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805062423] [2023-11-29 04:15:01,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:01,642 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:01,643 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:01,643 INFO L85 PathProgramCache]: Analyzing trace with hash 1886177719, now seen corresponding path program 1 times [2023-11-29 04:15:01,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:01,644 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768349261] [2023-11-29 04:15:01,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:01,644 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:01,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:01,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:01,724 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:01,724 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1768349261] [2023-11-29 04:15:01,725 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1768349261] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:01,725 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:01,725 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:01,725 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [559402442] [2023-11-29 04:15:01,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:01,726 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:01,726 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:01,727 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:01,727 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:01,727 INFO L87 Difference]: Start difference. First operand 688 states and 1026 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:01,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:01,744 INFO L93 Difference]: Finished difference Result 688 states and 1025 transitions. [2023-11-29 04:15:01,744 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1025 transitions. [2023-11-29 04:15:01,749 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-29 04:15:01,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1025 transitions. [2023-11-29 04:15:01,754 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2023-11-29 04:15:01,755 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2023-11-29 04:15:01,755 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1025 transitions. [2023-11-29 04:15:01,756 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:01,756 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1025 transitions. [2023-11-29 04:15:01,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1025 transitions. [2023-11-29 04:15:01,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2023-11-29 04:15:01,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.489825581395349) internal successors, (1025), 687 states have internal predecessors, (1025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:01,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1025 transitions. [2023-11-29 04:15:01,770 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1025 transitions. [2023-11-29 04:15:01,770 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:01,771 INFO L428 stractBuchiCegarLoop]: Abstraction has 688 states and 1025 transitions. [2023-11-29 04:15:01,771 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-29 04:15:01,771 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1025 transitions. [2023-11-29 04:15:01,776 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-29 04:15:01,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:01,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:01,778 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:01,778 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:01,779 INFO L748 eck$LassoCheckResult]: Stem: 3170#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3171#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3296#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3297#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2964#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 2965#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3294#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3295#L485-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3226#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3020#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3021#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2942#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2943#L684 assume !(0 == ~M_E~0); 3396#L684-2 assume !(0 == ~T1_E~0); 3255#L689-1 assume !(0 == ~T2_E~0); 3256#L694-1 assume !(0 == ~T3_E~0); 3253#L699-1 assume !(0 == ~T4_E~0); 3254#L704-1 assume !(0 == ~T5_E~0); 3211#L709-1 assume !(0 == ~T6_E~0); 3150#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3151#L719-1 assume !(0 == ~E_1~0); 3370#L724-1 assume !(0 == ~E_2~0); 2916#L729-1 assume !(0 == ~E_3~0); 2917#L734-1 assume !(0 == ~E_4~0); 3423#L739-1 assume !(0 == ~E_5~0); 3113#L744-1 assume !(0 == ~E_6~0); 3114#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2873#L334 assume !(1 == ~m_pc~0); 2874#L334-2 is_master_triggered_~__retres1~0#1 := 0; 3203#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3115#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3084#L849 assume !(0 != activate_threads_~tmp~1#1); 3085#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3017#L353 assume 1 == ~t1_pc~0; 3018#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3300#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2888#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2889#L857 assume !(0 != activate_threads_~tmp___0~0#1); 2969#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2970#L372 assume !(1 == ~t2_pc~0); 3073#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3072#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3198#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3301#L865 assume !(0 != activate_threads_~tmp___1~0#1); 2862#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2863#L391 assume 1 == ~t3_pc~0; 3405#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2785#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2811#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2812#L873 assume !(0 != activate_threads_~tmp___2~0#1); 3091#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3092#L410 assume 1 == ~t4_pc~0; 3413#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3314#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2983#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2984#L881 assume !(0 != activate_threads_~tmp___3~0#1); 3097#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3098#L429 assume !(1 == ~t5_pc~0); 2922#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2923#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3126#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3127#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3318#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3083#L448 assume 1 == ~t6_pc~0; 2957#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2958#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3284#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3285#L897 assume !(0 != activate_threads_~tmp___5~0#1); 3442#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3465#L762 assume !(1 == ~M_E~0); 3130#L762-2 assume !(1 == ~T1_E~0); 3131#L767-1 assume !(1 == ~T2_E~0); 3447#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3346#L777-1 assume !(1 == ~T4_E~0); 3241#L782-1 assume !(1 == ~T5_E~0); 2948#L787-1 assume !(1 == ~T6_E~0); 2946#L792-1 assume !(1 == ~E_M~0); 2947#L797-1 assume !(1 == ~E_1~0); 2988#L802-1 assume !(1 == ~E_2~0); 3207#L807-1 assume !(1 == ~E_3~0); 3208#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3418#L817-1 assume !(1 == ~E_5~0); 3257#L822-1 assume !(1 == ~E_6~0); 3258#L827-1 assume { :end_inline_reset_delta_events } true; 3086#L1053-2 [2023-11-29 04:15:01,779 INFO L750 eck$LassoCheckResult]: Loop: 3086#L1053-2 assume !false; 3087#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3062#L659-1 assume !false; 3051#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3052#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3054#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3320#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3321#L570 assume !(0 != eval_~tmp~0#1); 2994#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2995#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3230#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3231#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2780#L689-3 assume !(0 == ~T2_E~0); 2781#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2840#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2841#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3327#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3310#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3120#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2833#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2834#L729-3 assume !(0 == ~E_3~0); 3290#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3333#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3334#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3416#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2847#L334-24 assume !(1 == ~m_pc~0); 2848#L334-26 is_master_triggered_~__retres1~0#1 := 0; 2987#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3012#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2817#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2818#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3329#L353-24 assume 1 == ~t1_pc~0; 3330#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3358#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3448#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3449#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2864#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2865#L372-24 assume 1 == ~t2_pc~0; 2826#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2827#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3186#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3436#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3437#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3155#L391-24 assume !(1 == ~t3_pc~0); 3156#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 3371#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3332#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3242#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 3220#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3050#L410-24 assume !(1 == ~t4_pc~0); 2913#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 2914#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3351#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3096#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2944#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2945#L429-24 assume !(1 == ~t5_pc~0); 3046#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 3246#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3221#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2992#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2993#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2939#L448-24 assume 1 == ~t6_pc~0; 2940#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2931#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2932#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3107#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3249#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3250#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3215#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3216#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3454#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3444#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2924#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2925#L787-3 assume !(1 == ~T6_E~0); 3359#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3152#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3153#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3398#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3286#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3287#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3365#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3355#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3179#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2824#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3271#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3272#L1072 assume !(0 == start_simulation_~tmp~3#1); 3067#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3068#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2933#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2887#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 2854#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2855#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3430#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3368#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 3086#L1053-2 [2023-11-29 04:15:01,780 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:01,780 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2023-11-29 04:15:01,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:01,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680988742] [2023-11-29 04:15:01,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:01,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:01,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:01,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:01,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:01,830 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [680988742] [2023-11-29 04:15:01,830 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [680988742] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:01,830 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:01,831 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:01,831 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2117915867] [2023-11-29 04:15:01,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:01,831 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:01,832 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:01,832 INFO L85 PathProgramCache]: Analyzing trace with hash 55771641, now seen corresponding path program 1 times [2023-11-29 04:15:01,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:01,833 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232289569] [2023-11-29 04:15:01,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:01,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:01,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:01,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:01,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:01,912 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1232289569] [2023-11-29 04:15:01,912 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1232289569] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:01,913 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:01,913 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:01,913 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [697054490] [2023-11-29 04:15:01,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:01,914 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:01,914 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:01,915 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:01,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:01,915 INFO L87 Difference]: Start difference. First operand 688 states and 1025 transitions. cyclomatic complexity: 338 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:01,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:01,938 INFO L93 Difference]: Finished difference Result 688 states and 1024 transitions. [2023-11-29 04:15:01,939 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1024 transitions. [2023-11-29 04:15:01,943 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-29 04:15:01,948 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1024 transitions. [2023-11-29 04:15:01,948 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2023-11-29 04:15:01,949 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2023-11-29 04:15:01,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1024 transitions. [2023-11-29 04:15:01,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:01,950 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1024 transitions. [2023-11-29 04:15:01,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1024 transitions. [2023-11-29 04:15:01,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2023-11-29 04:15:01,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4883720930232558) internal successors, (1024), 687 states have internal predecessors, (1024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:01,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1024 transitions. [2023-11-29 04:15:01,963 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1024 transitions. [2023-11-29 04:15:01,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:01,964 INFO L428 stractBuchiCegarLoop]: Abstraction has 688 states and 1024 transitions. [2023-11-29 04:15:01,965 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-29 04:15:01,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1024 transitions. [2023-11-29 04:15:01,968 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-29 04:15:01,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:01,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:01,970 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:01,970 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:01,971 INFO L748 eck$LassoCheckResult]: Stem: 4553#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4554#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4679#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4680#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4347#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 4348#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4677#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4678#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4609#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4403#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4404#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4325#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4326#L684 assume !(0 == ~M_E~0); 4779#L684-2 assume !(0 == ~T1_E~0); 4638#L689-1 assume !(0 == ~T2_E~0); 4639#L694-1 assume !(0 == ~T3_E~0); 4636#L699-1 assume !(0 == ~T4_E~0); 4637#L704-1 assume !(0 == ~T5_E~0); 4594#L709-1 assume !(0 == ~T6_E~0); 4533#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4534#L719-1 assume !(0 == ~E_1~0); 4753#L724-1 assume !(0 == ~E_2~0); 4299#L729-1 assume !(0 == ~E_3~0); 4300#L734-1 assume !(0 == ~E_4~0); 4806#L739-1 assume !(0 == ~E_5~0); 4496#L744-1 assume !(0 == ~E_6~0); 4497#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4256#L334 assume !(1 == ~m_pc~0); 4257#L334-2 is_master_triggered_~__retres1~0#1 := 0; 4586#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4498#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4467#L849 assume !(0 != activate_threads_~tmp~1#1); 4468#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4400#L353 assume 1 == ~t1_pc~0; 4401#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4683#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4271#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4272#L857 assume !(0 != activate_threads_~tmp___0~0#1); 4352#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4353#L372 assume !(1 == ~t2_pc~0); 4456#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4455#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4581#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4684#L865 assume !(0 != activate_threads_~tmp___1~0#1); 4245#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4246#L391 assume 1 == ~t3_pc~0; 4788#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4168#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4194#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4195#L873 assume !(0 != activate_threads_~tmp___2~0#1); 4474#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4475#L410 assume 1 == ~t4_pc~0; 4797#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4697#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4366#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4367#L881 assume !(0 != activate_threads_~tmp___3~0#1); 4480#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4481#L429 assume !(1 == ~t5_pc~0); 4305#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4306#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4509#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4510#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4701#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4466#L448 assume 1 == ~t6_pc~0; 4340#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4341#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4667#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4668#L897 assume !(0 != activate_threads_~tmp___5~0#1); 4825#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4848#L762 assume !(1 == ~M_E~0); 4513#L762-2 assume !(1 == ~T1_E~0); 4514#L767-1 assume !(1 == ~T2_E~0); 4830#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4729#L777-1 assume !(1 == ~T4_E~0); 4624#L782-1 assume !(1 == ~T5_E~0); 4331#L787-1 assume !(1 == ~T6_E~0); 4329#L792-1 assume !(1 == ~E_M~0); 4330#L797-1 assume !(1 == ~E_1~0); 4371#L802-1 assume !(1 == ~E_2~0); 4590#L807-1 assume !(1 == ~E_3~0); 4591#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4801#L817-1 assume !(1 == ~E_5~0); 4642#L822-1 assume !(1 == ~E_6~0); 4643#L827-1 assume { :end_inline_reset_delta_events } true; 4469#L1053-2 [2023-11-29 04:15:01,972 INFO L750 eck$LassoCheckResult]: Loop: 4469#L1053-2 assume !false; 4470#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4445#L659-1 assume !false; 4434#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4435#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4437#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4703#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4704#L570 assume !(0 != eval_~tmp~0#1); 4377#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4378#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4615#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4616#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4163#L689-3 assume !(0 == ~T2_E~0); 4164#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4223#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4224#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4710#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4693#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4503#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4216#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4217#L729-3 assume !(0 == ~E_3~0); 4673#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4716#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4717#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4799#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4230#L334-24 assume !(1 == ~m_pc~0); 4231#L334-26 is_master_triggered_~__retres1~0#1 := 0; 4370#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4395#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4200#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4201#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4712#L353-24 assume 1 == ~t1_pc~0; 4713#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4741#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4831#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4832#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4247#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4248#L372-24 assume 1 == ~t2_pc~0; 4209#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4210#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4569#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4819#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4820#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4538#L391-24 assume !(1 == ~t3_pc~0); 4539#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 4754#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4715#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4625#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 4603#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4433#L410-24 assume 1 == ~t4_pc~0; 4372#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4297#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4734#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4479#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4327#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4328#L429-24 assume !(1 == ~t5_pc~0); 4429#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 4629#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4604#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4375#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4376#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4322#L448-24 assume 1 == ~t6_pc~0; 4323#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4314#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4315#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4490#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4632#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4633#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4598#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4599#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4837#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4827#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4307#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4308#L787-3 assume !(1 == ~T6_E~0); 4742#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4535#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4536#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4781#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4669#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4670#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4748#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4738#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4562#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4207#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4654#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4655#L1072 assume !(0 == start_simulation_~tmp~3#1); 4450#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4451#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4316#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4270#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 4237#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4238#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4813#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4751#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 4469#L1053-2 [2023-11-29 04:15:01,972 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:01,972 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2023-11-29 04:15:01,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:01,973 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390493340] [2023-11-29 04:15:01,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:01,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:01,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:02,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:02,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:02,020 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390493340] [2023-11-29 04:15:02,021 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390493340] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:02,021 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:02,021 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:02,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [680425743] [2023-11-29 04:15:02,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:02,022 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:02,022 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:02,023 INFO L85 PathProgramCache]: Analyzing trace with hash 929249336, now seen corresponding path program 1 times [2023-11-29 04:15:02,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:02,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1346788954] [2023-11-29 04:15:02,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:02,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:02,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:02,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:02,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:02,080 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1346788954] [2023-11-29 04:15:02,080 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1346788954] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:02,080 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:02,080 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:02,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [964152341] [2023-11-29 04:15:02,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:02,081 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:02,082 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:02,082 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:02,083 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:02,083 INFO L87 Difference]: Start difference. First operand 688 states and 1024 transitions. cyclomatic complexity: 337 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:02,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:02,100 INFO L93 Difference]: Finished difference Result 688 states and 1023 transitions. [2023-11-29 04:15:02,100 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1023 transitions. [2023-11-29 04:15:02,106 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-29 04:15:02,110 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1023 transitions. [2023-11-29 04:15:02,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2023-11-29 04:15:02,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2023-11-29 04:15:02,111 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1023 transitions. [2023-11-29 04:15:02,112 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:02,112 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1023 transitions. [2023-11-29 04:15:02,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1023 transitions. [2023-11-29 04:15:02,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2023-11-29 04:15:02,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4869186046511629) internal successors, (1023), 687 states have internal predecessors, (1023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:02,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1023 transitions. [2023-11-29 04:15:02,122 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1023 transitions. [2023-11-29 04:15:02,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:02,123 INFO L428 stractBuchiCegarLoop]: Abstraction has 688 states and 1023 transitions. [2023-11-29 04:15:02,123 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-29 04:15:02,123 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1023 transitions. [2023-11-29 04:15:02,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-29 04:15:02,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:02,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:02,129 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:02,129 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:02,129 INFO L748 eck$LassoCheckResult]: Stem: 5938#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 5939#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6064#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6065#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5733#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 5734#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6060#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6061#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5992#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5786#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5787#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5710#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5711#L684 assume !(0 == ~M_E~0); 6163#L684-2 assume !(0 == ~T1_E~0); 6021#L689-1 assume !(0 == ~T2_E~0); 6022#L694-1 assume !(0 == ~T3_E~0); 6019#L699-1 assume !(0 == ~T4_E~0); 6020#L704-1 assume !(0 == ~T5_E~0); 5977#L709-1 assume !(0 == ~T6_E~0); 5916#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 5917#L719-1 assume !(0 == ~E_1~0); 6136#L724-1 assume !(0 == ~E_2~0); 5682#L729-1 assume !(0 == ~E_3~0); 5683#L734-1 assume !(0 == ~E_4~0); 6189#L739-1 assume !(0 == ~E_5~0); 5879#L744-1 assume !(0 == ~E_6~0); 5880#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5639#L334 assume !(1 == ~m_pc~0); 5640#L334-2 is_master_triggered_~__retres1~0#1 := 0; 5969#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5882#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5850#L849 assume !(0 != activate_threads_~tmp~1#1); 5851#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5783#L353 assume 1 == ~t1_pc~0; 5784#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6066#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5654#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5655#L857 assume !(0 != activate_threads_~tmp___0~0#1); 5735#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5736#L372 assume !(1 == ~t2_pc~0); 5839#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5838#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5964#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6067#L865 assume !(0 != activate_threads_~tmp___1~0#1); 5628#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5629#L391 assume 1 == ~t3_pc~0; 6173#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5551#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5577#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5578#L873 assume !(0 != activate_threads_~tmp___2~0#1); 5857#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5858#L410 assume 1 == ~t4_pc~0; 6180#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6081#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5749#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5750#L881 assume !(0 != activate_threads_~tmp___3~0#1); 5866#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5867#L429 assume !(1 == ~t5_pc~0); 5688#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5689#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5892#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5893#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6084#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5849#L448 assume 1 == ~t6_pc~0; 5723#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5724#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6052#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6053#L897 assume !(0 != activate_threads_~tmp___5~0#1); 6208#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6231#L762 assume !(1 == ~M_E~0); 5896#L762-2 assume !(1 == ~T1_E~0); 5897#L767-1 assume !(1 == ~T2_E~0); 6213#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6112#L777-1 assume !(1 == ~T4_E~0); 6007#L782-1 assume !(1 == ~T5_E~0); 5714#L787-1 assume !(1 == ~T6_E~0); 5712#L792-1 assume !(1 == ~E_M~0); 5713#L797-1 assume !(1 == ~E_1~0); 5755#L802-1 assume !(1 == ~E_2~0); 5973#L807-1 assume !(1 == ~E_3~0); 5974#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6184#L817-1 assume !(1 == ~E_5~0); 6025#L822-1 assume !(1 == ~E_6~0); 6026#L827-1 assume { :end_inline_reset_delta_events } true; 5852#L1053-2 [2023-11-29 04:15:02,130 INFO L750 eck$LassoCheckResult]: Loop: 5852#L1053-2 assume !false; 5853#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5828#L659-1 assume !false; 5817#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5818#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5820#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6086#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6087#L570 assume !(0 != eval_~tmp~0#1); 5762#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5763#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5998#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5999#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5546#L689-3 assume !(0 == ~T2_E~0); 5547#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5606#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5607#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6093#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6078#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5891#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5599#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5600#L729-3 assume !(0 == ~E_3~0); 6057#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6099#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6100#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6182#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5613#L334-24 assume !(1 == ~m_pc~0); 5614#L334-26 is_master_triggered_~__retres1~0#1 := 0; 5753#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5778#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5583#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5584#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6094#L353-24 assume !(1 == ~t1_pc~0); 6096#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 6124#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6214#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6215#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5630#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5631#L372-24 assume 1 == ~t2_pc~0; 5592#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5593#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5952#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6201#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6202#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5921#L391-24 assume !(1 == ~t3_pc~0); 5922#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 6137#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6097#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6008#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 5983#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5816#L410-24 assume 1 == ~t4_pc~0; 5754#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5680#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6117#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5862#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5708#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5709#L429-24 assume !(1 == ~t5_pc~0); 5812#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 6012#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5984#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5758#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5759#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5703#L448-24 assume 1 == ~t6_pc~0; 5704#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5697#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5698#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5873#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6015#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6016#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5981#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5982#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6220#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6210#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5690#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5691#L787-3 assume !(1 == ~T6_E~0); 6125#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5918#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5919#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6164#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6050#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6051#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6131#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6121#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5945#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5590#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6037#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6038#L1072 assume !(0 == start_simulation_~tmp~3#1); 5833#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5834#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5699#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5653#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 5620#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5621#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6196#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6134#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 5852#L1053-2 [2023-11-29 04:15:02,130 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:02,130 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2023-11-29 04:15:02,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:02,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111038227] [2023-11-29 04:15:02,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:02,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:02,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:02,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:02,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:02,166 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111038227] [2023-11-29 04:15:02,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2111038227] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:02,167 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:02,167 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:02,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1507481939] [2023-11-29 04:15:02,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:02,167 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:02,168 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:02,168 INFO L85 PathProgramCache]: Analyzing trace with hash 1506177977, now seen corresponding path program 1 times [2023-11-29 04:15:02,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:02,168 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611406066] [2023-11-29 04:15:02,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:02,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:02,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:02,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:02,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:02,206 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1611406066] [2023-11-29 04:15:02,207 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1611406066] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:02,207 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:02,207 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:02,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114663728] [2023-11-29 04:15:02,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:02,207 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:02,208 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:02,208 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:02,208 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:02,208 INFO L87 Difference]: Start difference. First operand 688 states and 1023 transitions. cyclomatic complexity: 336 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:02,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:02,233 INFO L93 Difference]: Finished difference Result 688 states and 1022 transitions. [2023-11-29 04:15:02,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1022 transitions. [2023-11-29 04:15:02,237 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-29 04:15:02,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1022 transitions. [2023-11-29 04:15:02,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2023-11-29 04:15:02,242 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2023-11-29 04:15:02,242 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1022 transitions. [2023-11-29 04:15:02,242 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:02,242 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1022 transitions. [2023-11-29 04:15:02,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1022 transitions. [2023-11-29 04:15:02,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2023-11-29 04:15:02,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4854651162790697) internal successors, (1022), 687 states have internal predecessors, (1022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:02,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1022 transitions. [2023-11-29 04:15:02,252 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1022 transitions. [2023-11-29 04:15:02,252 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:02,253 INFO L428 stractBuchiCegarLoop]: Abstraction has 688 states and 1022 transitions. [2023-11-29 04:15:02,253 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-29 04:15:02,253 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1022 transitions. [2023-11-29 04:15:02,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-29 04:15:02,256 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:02,257 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:02,257 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:02,258 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:02,258 INFO L748 eck$LassoCheckResult]: Stem: 7319#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7445#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7446#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7113#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 7114#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7443#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7444#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7375#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7169#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7170#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7091#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7092#L684 assume !(0 == ~M_E~0); 7545#L684-2 assume !(0 == ~T1_E~0); 7404#L689-1 assume !(0 == ~T2_E~0); 7405#L694-1 assume !(0 == ~T3_E~0); 7402#L699-1 assume !(0 == ~T4_E~0); 7403#L704-1 assume !(0 == ~T5_E~0); 7360#L709-1 assume !(0 == ~T6_E~0); 7299#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7300#L719-1 assume !(0 == ~E_1~0); 7519#L724-1 assume !(0 == ~E_2~0); 7065#L729-1 assume !(0 == ~E_3~0); 7066#L734-1 assume !(0 == ~E_4~0); 7572#L739-1 assume !(0 == ~E_5~0); 7262#L744-1 assume !(0 == ~E_6~0); 7263#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7022#L334 assume !(1 == ~m_pc~0); 7023#L334-2 is_master_triggered_~__retres1~0#1 := 0; 7352#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7264#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7233#L849 assume !(0 != activate_threads_~tmp~1#1); 7234#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7166#L353 assume 1 == ~t1_pc~0; 7167#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7449#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7037#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7038#L857 assume !(0 != activate_threads_~tmp___0~0#1); 7118#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7119#L372 assume !(1 == ~t2_pc~0); 7222#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7221#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7347#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7450#L865 assume !(0 != activate_threads_~tmp___1~0#1); 7011#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7012#L391 assume 1 == ~t3_pc~0; 7554#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6934#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6960#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6961#L873 assume !(0 != activate_threads_~tmp___2~0#1); 7240#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7241#L410 assume 1 == ~t4_pc~0; 7562#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7463#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7132#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7133#L881 assume !(0 != activate_threads_~tmp___3~0#1); 7246#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7247#L429 assume !(1 == ~t5_pc~0); 7071#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7072#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7275#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7276#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7467#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7232#L448 assume 1 == ~t6_pc~0; 7106#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7107#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7433#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7434#L897 assume !(0 != activate_threads_~tmp___5~0#1); 7591#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7614#L762 assume !(1 == ~M_E~0); 7279#L762-2 assume !(1 == ~T1_E~0); 7280#L767-1 assume !(1 == ~T2_E~0); 7596#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7495#L777-1 assume !(1 == ~T4_E~0); 7390#L782-1 assume !(1 == ~T5_E~0); 7097#L787-1 assume !(1 == ~T6_E~0); 7095#L792-1 assume !(1 == ~E_M~0); 7096#L797-1 assume !(1 == ~E_1~0); 7137#L802-1 assume !(1 == ~E_2~0); 7356#L807-1 assume !(1 == ~E_3~0); 7357#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7567#L817-1 assume !(1 == ~E_5~0); 7406#L822-1 assume !(1 == ~E_6~0); 7407#L827-1 assume { :end_inline_reset_delta_events } true; 7235#L1053-2 [2023-11-29 04:15:02,258 INFO L750 eck$LassoCheckResult]: Loop: 7235#L1053-2 assume !false; 7236#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7211#L659-1 assume !false; 7200#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7201#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7203#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7469#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7470#L570 assume !(0 != eval_~tmp~0#1); 7143#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7144#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7379#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7380#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6929#L689-3 assume !(0 == ~T2_E~0); 6930#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6989#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6990#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7476#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7459#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7269#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6982#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6983#L729-3 assume !(0 == ~E_3~0); 7439#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7482#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7483#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7565#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6996#L334-24 assume !(1 == ~m_pc~0); 6997#L334-26 is_master_triggered_~__retres1~0#1 := 0; 7136#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7161#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6966#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6967#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7478#L353-24 assume 1 == ~t1_pc~0; 7479#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7507#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7597#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7598#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7013#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7014#L372-24 assume !(1 == ~t2_pc~0); 6977#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 6976#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7335#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7585#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7586#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7304#L391-24 assume !(1 == ~t3_pc~0); 7305#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 7520#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7481#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7391#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 7369#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7199#L410-24 assume 1 == ~t4_pc~0; 7138#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7063#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7500#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7245#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7093#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7094#L429-24 assume !(1 == ~t5_pc~0); 7195#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 7395#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7370#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7141#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7142#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7088#L448-24 assume 1 == ~t6_pc~0; 7089#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7080#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7081#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7256#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7398#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7399#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7364#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7365#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7603#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7593#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7073#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7074#L787-3 assume !(1 == ~T6_E~0); 7508#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7301#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7302#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7547#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7435#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7436#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7514#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7504#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7328#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6973#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7420#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7421#L1072 assume !(0 == start_simulation_~tmp~3#1); 7216#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7217#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7082#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7036#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 7003#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7004#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7579#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 7517#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 7235#L1053-2 [2023-11-29 04:15:02,259 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:02,259 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2023-11-29 04:15:02,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:02,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460520844] [2023-11-29 04:15:02,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:02,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:02,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:02,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:02,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:02,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1460520844] [2023-11-29 04:15:02,290 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1460520844] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:02,290 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:02,290 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:02,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1645216786] [2023-11-29 04:15:02,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:02,291 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:02,292 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:02,292 INFO L85 PathProgramCache]: Analyzing trace with hash 1169516665, now seen corresponding path program 1 times [2023-11-29 04:15:02,292 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:02,292 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557934116] [2023-11-29 04:15:02,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:02,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:02,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:02,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:02,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:02,330 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557934116] [2023-11-29 04:15:02,331 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [557934116] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:02,331 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:02,331 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:02,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728221820] [2023-11-29 04:15:02,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:02,332 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:02,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:02,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:02,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:02,333 INFO L87 Difference]: Start difference. First operand 688 states and 1022 transitions. cyclomatic complexity: 335 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:02,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:02,349 INFO L93 Difference]: Finished difference Result 688 states and 1021 transitions. [2023-11-29 04:15:02,349 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1021 transitions. [2023-11-29 04:15:02,352 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-29 04:15:02,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1021 transitions. [2023-11-29 04:15:02,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2023-11-29 04:15:02,357 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2023-11-29 04:15:02,357 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1021 transitions. [2023-11-29 04:15:02,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:02,358 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1021 transitions. [2023-11-29 04:15:02,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1021 transitions. [2023-11-29 04:15:02,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2023-11-29 04:15:02,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4840116279069768) internal successors, (1021), 687 states have internal predecessors, (1021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:02,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1021 transitions. [2023-11-29 04:15:02,367 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1021 transitions. [2023-11-29 04:15:02,368 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:02,368 INFO L428 stractBuchiCegarLoop]: Abstraction has 688 states and 1021 transitions. [2023-11-29 04:15:02,369 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-29 04:15:02,369 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1021 transitions. [2023-11-29 04:15:02,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-29 04:15:02,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:02,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:02,374 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:02,374 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:02,374 INFO L748 eck$LassoCheckResult]: Stem: 8702#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8703#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8828#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8829#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8496#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 8497#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8826#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8827#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8758#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8552#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8553#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8474#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8475#L684 assume !(0 == ~M_E~0); 8928#L684-2 assume !(0 == ~T1_E~0); 8787#L689-1 assume !(0 == ~T2_E~0); 8788#L694-1 assume !(0 == ~T3_E~0); 8785#L699-1 assume !(0 == ~T4_E~0); 8786#L704-1 assume !(0 == ~T5_E~0); 8743#L709-1 assume !(0 == ~T6_E~0); 8682#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8683#L719-1 assume !(0 == ~E_1~0); 8902#L724-1 assume !(0 == ~E_2~0); 8448#L729-1 assume !(0 == ~E_3~0); 8449#L734-1 assume !(0 == ~E_4~0); 8955#L739-1 assume !(0 == ~E_5~0); 8645#L744-1 assume !(0 == ~E_6~0); 8646#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8405#L334 assume !(1 == ~m_pc~0); 8406#L334-2 is_master_triggered_~__retres1~0#1 := 0; 8735#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8647#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8616#L849 assume !(0 != activate_threads_~tmp~1#1); 8617#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8549#L353 assume 1 == ~t1_pc~0; 8550#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8832#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8420#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8421#L857 assume !(0 != activate_threads_~tmp___0~0#1); 8501#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8502#L372 assume !(1 == ~t2_pc~0); 8605#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8604#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8730#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8833#L865 assume !(0 != activate_threads_~tmp___1~0#1); 8394#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8395#L391 assume 1 == ~t3_pc~0; 8937#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8317#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8343#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8344#L873 assume !(0 != activate_threads_~tmp___2~0#1); 8623#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8624#L410 assume 1 == ~t4_pc~0; 8946#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8846#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8515#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8516#L881 assume !(0 != activate_threads_~tmp___3~0#1); 8629#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8630#L429 assume !(1 == ~t5_pc~0); 8454#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8455#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8658#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8659#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8850#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8615#L448 assume 1 == ~t6_pc~0; 8489#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8490#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8818#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8819#L897 assume !(0 != activate_threads_~tmp___5~0#1); 8974#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8997#L762 assume !(1 == ~M_E~0); 8662#L762-2 assume !(1 == ~T1_E~0); 8663#L767-1 assume !(1 == ~T2_E~0); 8979#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8878#L777-1 assume !(1 == ~T4_E~0); 8773#L782-1 assume !(1 == ~T5_E~0); 8480#L787-1 assume !(1 == ~T6_E~0); 8478#L792-1 assume !(1 == ~E_M~0); 8479#L797-1 assume !(1 == ~E_1~0); 8520#L802-1 assume !(1 == ~E_2~0); 8739#L807-1 assume !(1 == ~E_3~0); 8740#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8950#L817-1 assume !(1 == ~E_5~0); 8791#L822-1 assume !(1 == ~E_6~0); 8792#L827-1 assume { :end_inline_reset_delta_events } true; 8618#L1053-2 [2023-11-29 04:15:02,375 INFO L750 eck$LassoCheckResult]: Loop: 8618#L1053-2 assume !false; 8619#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8594#L659-1 assume !false; 8583#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8584#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8586#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8852#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8853#L570 assume !(0 != eval_~tmp~0#1); 8526#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8527#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8764#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8765#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8312#L689-3 assume !(0 == ~T2_E~0); 8313#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8372#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8373#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8859#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8842#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8652#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8365#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8366#L729-3 assume !(0 == ~E_3~0); 8822#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8865#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8866#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8948#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8379#L334-24 assume !(1 == ~m_pc~0); 8380#L334-26 is_master_triggered_~__retres1~0#1 := 0; 8519#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8544#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8349#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8350#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8861#L353-24 assume 1 == ~t1_pc~0; 8862#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8890#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8980#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8981#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8396#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8397#L372-24 assume 1 == ~t2_pc~0; 8358#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8359#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8718#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8968#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8969#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8687#L391-24 assume !(1 == ~t3_pc~0); 8688#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 8903#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8864#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8774#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 8753#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8582#L410-24 assume 1 == ~t4_pc~0; 8521#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8446#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8883#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8628#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8476#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8477#L429-24 assume !(1 == ~t5_pc~0); 8578#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 8778#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8749#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8522#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8523#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8468#L448-24 assume 1 == ~t6_pc~0; 8469#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8463#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8464#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8639#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8781#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8782#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8747#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8748#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8986#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8976#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8456#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8457#L787-3 assume !(1 == ~T6_E~0); 8891#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8684#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8685#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8930#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8816#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8817#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8897#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8887#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8710#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8354#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 8804#L1072 assume !(0 == start_simulation_~tmp~3#1); 8599#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8600#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8465#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8419#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 8384#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8385#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8962#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8900#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 8618#L1053-2 [2023-11-29 04:15:02,375 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:02,375 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2023-11-29 04:15:02,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:02,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023722910] [2023-11-29 04:15:02,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:02,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:02,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:02,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:02,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:02,432 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2023722910] [2023-11-29 04:15:02,432 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2023722910] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:02,432 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:02,433 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:02,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462860839] [2023-11-29 04:15:02,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:02,433 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:02,433 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:02,434 INFO L85 PathProgramCache]: Analyzing trace with hash 929249336, now seen corresponding path program 2 times [2023-11-29 04:15:02,434 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:02,434 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2004738552] [2023-11-29 04:15:02,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:02,434 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:02,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:02,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:02,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:02,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2004738552] [2023-11-29 04:15:02,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2004738552] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:02,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:02,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:02,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [421482296] [2023-11-29 04:15:02,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:02,468 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:02,468 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:02,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:15:02,469 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:15:02,469 INFO L87 Difference]: Start difference. First operand 688 states and 1021 transitions. cyclomatic complexity: 334 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:02,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:02,612 INFO L93 Difference]: Finished difference Result 1184 states and 1752 transitions. [2023-11-29 04:15:02,612 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1184 states and 1752 transitions. [2023-11-29 04:15:02,639 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1078 [2023-11-29 04:15:02,648 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1184 states to 1184 states and 1752 transitions. [2023-11-29 04:15:02,648 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1184 [2023-11-29 04:15:02,650 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1184 [2023-11-29 04:15:02,650 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1184 states and 1752 transitions. [2023-11-29 04:15:02,651 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:02,651 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1184 states and 1752 transitions. [2023-11-29 04:15:02,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1184 states and 1752 transitions. [2023-11-29 04:15:02,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1184 to 1183. [2023-11-29 04:15:02,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1183 states, 1183 states have (on average 1.4801352493660187) internal successors, (1751), 1182 states have internal predecessors, (1751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:02,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1183 states to 1183 states and 1751 transitions. [2023-11-29 04:15:02,677 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1183 states and 1751 transitions. [2023-11-29 04:15:02,678 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 04:15:02,678 INFO L428 stractBuchiCegarLoop]: Abstraction has 1183 states and 1751 transitions. [2023-11-29 04:15:02,679 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-29 04:15:02,679 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1183 states and 1751 transitions. [2023-11-29 04:15:02,685 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1078 [2023-11-29 04:15:02,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:02,685 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:02,687 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:02,687 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:02,687 INFO L748 eck$LassoCheckResult]: Stem: 10586#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10718#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10719#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10380#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 10381#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10716#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10717#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10646#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10436#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10437#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10357#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10358#L684 assume !(0 == ~M_E~0); 10823#L684-2 assume !(0 == ~T1_E~0); 10676#L689-1 assume !(0 == ~T2_E~0); 10677#L694-1 assume !(0 == ~T3_E~0); 10674#L699-1 assume !(0 == ~T4_E~0); 10675#L704-1 assume !(0 == ~T5_E~0); 10631#L709-1 assume !(0 == ~T6_E~0); 10566#L714-1 assume !(0 == ~E_M~0); 10567#L719-1 assume !(0 == ~E_1~0); 10795#L724-1 assume !(0 == ~E_2~0); 10331#L729-1 assume !(0 == ~E_3~0); 10332#L734-1 assume !(0 == ~E_4~0); 10851#L739-1 assume !(0 == ~E_5~0); 10529#L744-1 assume !(0 == ~E_6~0); 10530#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10287#L334 assume !(1 == ~m_pc~0); 10288#L334-2 is_master_triggered_~__retres1~0#1 := 0; 10623#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10531#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10500#L849 assume !(0 != activate_threads_~tmp~1#1); 10501#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10433#L353 assume 1 == ~t1_pc~0; 10434#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10722#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10303#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10304#L857 assume !(0 != activate_threads_~tmp___0~0#1); 10385#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10386#L372 assume !(1 == ~t2_pc~0); 10489#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10488#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10617#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10723#L865 assume !(0 != activate_threads_~tmp___1~0#1); 10276#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10277#L391 assume 1 == ~t3_pc~0; 10832#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10199#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10225#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10226#L873 assume !(0 != activate_threads_~tmp___2~0#1); 10507#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10508#L410 assume 1 == ~t4_pc~0; 10840#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10736#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10399#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10400#L881 assume !(0 != activate_threads_~tmp___3~0#1); 10513#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10514#L429 assume !(1 == ~t5_pc~0); 10337#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10338#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10542#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10543#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10741#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10499#L448 assume 1 == ~t6_pc~0; 10373#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10374#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10706#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10707#L897 assume !(0 != activate_threads_~tmp___5~0#1); 10872#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10899#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 10546#L762-2 assume !(1 == ~T1_E~0); 10547#L767-1 assume !(1 == ~T2_E~0); 10977#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10974#L777-1 assume !(1 == ~T4_E~0); 10972#L782-1 assume !(1 == ~T5_E~0); 10970#L787-1 assume !(1 == ~T6_E~0); 10968#L792-1 assume !(1 == ~E_M~0); 10362#L797-1 assume !(1 == ~E_1~0); 10963#L802-1 assume !(1 == ~E_2~0); 10961#L807-1 assume !(1 == ~E_3~0); 10959#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10958#L817-1 assume !(1 == ~E_5~0); 10942#L822-1 assume !(1 == ~E_6~0); 10934#L827-1 assume { :end_inline_reset_delta_events } true; 10929#L1053-2 [2023-11-29 04:15:02,687 INFO L750 eck$LassoCheckResult]: Loop: 10929#L1053-2 assume !false; 10842#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10478#L659-1 assume !false; 10467#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10468#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10470#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10743#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10744#L570 assume !(0 != eval_~tmp~0#1); 10788#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10909#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10907#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10908#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11370#L689-3 assume !(0 == ~T2_E~0); 11369#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11368#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11367#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11366#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11365#L714-3 assume !(0 == ~E_M~0); 11364#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11363#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11362#L729-3 assume !(0 == ~E_3~0); 11361#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11360#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11359#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11358#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11357#L334-24 assume !(1 == ~m_pc~0); 11355#L334-26 is_master_triggered_~__retres1~0#1 := 0; 11354#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11353#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11352#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11351#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11350#L353-24 assume 1 == ~t1_pc~0; 11348#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11347#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11346#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11345#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11344#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11343#L372-24 assume !(1 == ~t2_pc~0); 11341#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 11340#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11339#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11338#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11337#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11336#L391-24 assume 1 == ~t3_pc~0; 11334#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11333#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11332#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11331#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 11330#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11329#L410-24 assume !(1 == ~t4_pc~0); 11328#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 11326#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11325#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11324#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11323#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11322#L429-24 assume !(1 == ~t5_pc~0); 11320#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 11318#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11315#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11313#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11311#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11309#L448-24 assume 1 == ~t6_pc~0; 11306#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11304#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11301#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11299#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11297#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11296#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10854#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11295#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11294#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11293#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11292#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11291#L787-3 assume !(1 == ~T6_E~0); 11290#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10783#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11289#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11288#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10708#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10709#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10790#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10778#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10597#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10238#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10692#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 10693#L1072 assume !(0 == start_simulation_~tmp~3#1); 10483#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10484#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10348#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10301#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 10302#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10978#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10943#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 10935#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 10929#L1053-2 [2023-11-29 04:15:02,688 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:02,688 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2023-11-29 04:15:02,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:02,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418856540] [2023-11-29 04:15:02,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:02,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:02,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:02,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:02,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:02,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418856540] [2023-11-29 04:15:02,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418856540] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:02,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:02,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:15:02,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1642171638] [2023-11-29 04:15:02,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:02,739 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:02,739 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:02,739 INFO L85 PathProgramCache]: Analyzing trace with hash -1871021509, now seen corresponding path program 1 times [2023-11-29 04:15:02,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:02,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400807636] [2023-11-29 04:15:02,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:02,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:02,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:02,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:02,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:02,784 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400807636] [2023-11-29 04:15:02,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1400807636] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:02,784 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:02,785 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:02,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635069609] [2023-11-29 04:15:02,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:02,785 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:02,785 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:02,786 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:02,786 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:02,786 INFO L87 Difference]: Start difference. First operand 1183 states and 1751 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:02,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:02,864 INFO L93 Difference]: Finished difference Result 2142 states and 3143 transitions. [2023-11-29 04:15:02,864 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2142 states and 3143 transitions. [2023-11-29 04:15:02,881 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2034 [2023-11-29 04:15:02,897 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2142 states to 2142 states and 3143 transitions. [2023-11-29 04:15:02,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2142 [2023-11-29 04:15:02,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2142 [2023-11-29 04:15:02,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2142 states and 3143 transitions. [2023-11-29 04:15:02,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:02,903 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2142 states and 3143 transitions. [2023-11-29 04:15:02,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2142 states and 3143 transitions. [2023-11-29 04:15:02,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2142 to 2138. [2023-11-29 04:15:02,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2138 states, 2138 states have (on average 1.4681945743685687) internal successors, (3139), 2137 states have internal predecessors, (3139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:02,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2138 states to 2138 states and 3139 transitions. [2023-11-29 04:15:02,953 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2138 states and 3139 transitions. [2023-11-29 04:15:02,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:02,954 INFO L428 stractBuchiCegarLoop]: Abstraction has 2138 states and 3139 transitions. [2023-11-29 04:15:02,955 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-29 04:15:02,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2138 states and 3139 transitions. [2023-11-29 04:15:02,967 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2030 [2023-11-29 04:15:02,967 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:02,967 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:02,969 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:02,969 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:02,969 INFO L748 eck$LassoCheckResult]: Stem: 13932#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 13933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 14067#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14068#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13715#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 13716#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14063#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14064#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13988#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13770#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13771#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13692#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13693#L684 assume !(0 == ~M_E~0); 14181#L684-2 assume !(0 == ~T1_E~0); 14023#L689-1 assume !(0 == ~T2_E~0); 14024#L694-1 assume !(0 == ~T3_E~0); 14021#L699-1 assume !(0 == ~T4_E~0); 14022#L704-1 assume !(0 == ~T5_E~0); 13972#L709-1 assume !(0 == ~T6_E~0); 13910#L714-1 assume !(0 == ~E_M~0); 13911#L719-1 assume !(0 == ~E_1~0); 14151#L724-1 assume !(0 == ~E_2~0); 13662#L729-1 assume !(0 == ~E_3~0); 13663#L734-1 assume !(0 == ~E_4~0); 14219#L739-1 assume !(0 == ~E_5~0); 13873#L744-1 assume !(0 == ~E_6~0); 13874#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13619#L334 assume !(1 == ~m_pc~0); 13620#L334-2 is_master_triggered_~__retres1~0#1 := 0; 13964#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13876#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13841#L849 assume !(0 != activate_threads_~tmp~1#1); 13842#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13768#L353 assume !(1 == ~t1_pc~0); 13769#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14069#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13634#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13635#L857 assume !(0 != activate_threads_~tmp___0~0#1); 13719#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13720#L372 assume !(1 == ~t2_pc~0); 13828#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13827#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13959#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14070#L865 assume !(0 != activate_threads_~tmp___1~0#1); 13607#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13608#L391 assume 1 == ~t3_pc~0; 14194#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13531#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13556#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13557#L873 assume !(0 != activate_threads_~tmp___2~0#1); 13848#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13849#L410 assume 1 == ~t4_pc~0; 14205#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14087#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13734#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13735#L881 assume !(0 != activate_threads_~tmp___3~0#1); 13858#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13859#L429 assume !(1 == ~t5_pc~0); 13668#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13669#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13886#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13887#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14091#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13838#L448 assume 1 == ~t6_pc~0; 13706#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13707#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14054#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14055#L897 assume !(0 != activate_threads_~tmp___5~0#1); 14243#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14282#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 14283#L762-2 assume !(1 == ~T1_E~0); 15334#L767-1 assume !(1 == ~T2_E~0); 15332#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15330#L777-1 assume !(1 == ~T4_E~0); 15329#L782-1 assume !(1 == ~T5_E~0); 15327#L787-1 assume !(1 == ~T6_E~0); 15325#L792-1 assume !(1 == ~E_M~0); 13695#L797-1 assume !(1 == ~E_1~0); 15322#L802-1 assume !(1 == ~E_2~0); 15320#L807-1 assume !(1 == ~E_3~0); 15319#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15318#L817-1 assume !(1 == ~E_5~0); 15317#L822-1 assume !(1 == ~E_6~0); 15263#L827-1 assume { :end_inline_reset_delta_events } true; 13843#L1053-2 [2023-11-29 04:15:02,969 INFO L750 eck$LassoCheckResult]: Loop: 13843#L1053-2 assume !false; 13844#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15216#L659-1 assume !false; 15215#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15213#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15207#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15206#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14142#L570 assume !(0 != eval_~tmp~0#1); 13745#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13746#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14222#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15202#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15663#L689-3 assume !(0 == ~T2_E~0); 15662#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15661#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15660#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15659#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15658#L714-3 assume !(0 == ~E_M~0); 15657#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15656#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15655#L729-3 assume !(0 == ~E_3~0); 15654#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15653#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15652#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15651#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15650#L334-24 assume !(1 == ~m_pc~0); 15648#L334-26 is_master_triggered_~__retres1~0#1 := 0; 15647#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15646#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15645#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15644#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15643#L353-24 assume !(1 == ~t1_pc~0); 15642#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 15641#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15640#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15639#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15638#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15637#L372-24 assume !(1 == ~t2_pc~0); 15635#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 15634#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15581#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15580#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15579#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15578#L391-24 assume 1 == ~t3_pc~0; 15576#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15575#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15574#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15573#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 15572#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15571#L410-24 assume 1 == ~t4_pc~0; 15569#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15568#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15567#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15566#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15564#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15562#L429-24 assume !(1 == ~t5_pc~0); 15559#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 14124#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13979#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13743#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13744#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13941#L448-24 assume 1 == ~t6_pc~0; 15547#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15545#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13866#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13867#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14015#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14016#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14223#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15534#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14291#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14292#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15529#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14284#L787-3 assume !(1 == ~T6_E~0); 14285#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14137#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15527#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15526#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15525#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15524#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15523#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15522#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15517#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15514#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15513#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 14278#L1072 assume !(0 == start_simulation_~tmp~3#1); 14279#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14217#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 13679#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 13633#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 13597#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13598#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15265#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 15264#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 13843#L1053-2 [2023-11-29 04:15:02,970 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:02,970 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2023-11-29 04:15:02,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:02,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982271930] [2023-11-29 04:15:02,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:02,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:02,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:03,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:03,029 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:03,029 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982271930] [2023-11-29 04:15:03,029 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [982271930] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:03,029 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:03,029 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:15:03,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1024676072] [2023-11-29 04:15:03,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:03,030 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:03,030 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:03,030 INFO L85 PathProgramCache]: Analyzing trace with hash -420615173, now seen corresponding path program 1 times [2023-11-29 04:15:03,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:03,030 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284128506] [2023-11-29 04:15:03,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:03,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:03,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:03,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:03,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:03,088 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284128506] [2023-11-29 04:15:03,088 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [284128506] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:03,088 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:03,088 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:03,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [60485160] [2023-11-29 04:15:03,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:03,089 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:03,089 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:03,089 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:03,090 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:03,090 INFO L87 Difference]: Start difference. First operand 2138 states and 3139 transitions. cyclomatic complexity: 1005 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:03,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:03,188 INFO L93 Difference]: Finished difference Result 3935 states and 5736 transitions. [2023-11-29 04:15:03,188 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3935 states and 5736 transitions. [2023-11-29 04:15:03,217 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3820 [2023-11-29 04:15:03,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3935 states to 3935 states and 5736 transitions. [2023-11-29 04:15:03,246 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3935 [2023-11-29 04:15:03,251 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3935 [2023-11-29 04:15:03,251 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3935 states and 5736 transitions. [2023-11-29 04:15:03,256 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:03,256 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3935 states and 5736 transitions. [2023-11-29 04:15:03,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3935 states and 5736 transitions. [2023-11-29 04:15:03,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3935 to 3927. [2023-11-29 04:15:03,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3927 states, 3927 states have (on average 1.458619811560988) internal successors, (5728), 3926 states have internal predecessors, (5728), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:03,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3927 states to 3927 states and 5728 transitions. [2023-11-29 04:15:03,342 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3927 states and 5728 transitions. [2023-11-29 04:15:03,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:03,343 INFO L428 stractBuchiCegarLoop]: Abstraction has 3927 states and 5728 transitions. [2023-11-29 04:15:03,343 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-29 04:15:03,343 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3927 states and 5728 transitions. [2023-11-29 04:15:03,359 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3812 [2023-11-29 04:15:03,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:03,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:03,361 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:03,361 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:03,361 INFO L748 eck$LassoCheckResult]: Stem: 20011#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 20012#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 20153#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20154#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19794#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 19795#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20149#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20150#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20069#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19848#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19849#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19770#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19771#L684 assume !(0 == ~M_E~0); 20278#L684-2 assume !(0 == ~T1_E~0); 20105#L689-1 assume !(0 == ~T2_E~0); 20106#L694-1 assume !(0 == ~T3_E~0); 20103#L699-1 assume !(0 == ~T4_E~0); 20104#L704-1 assume !(0 == ~T5_E~0); 20054#L709-1 assume !(0 == ~T6_E~0); 19985#L714-1 assume !(0 == ~E_M~0); 19986#L719-1 assume !(0 == ~E_1~0); 20239#L724-1 assume !(0 == ~E_2~0); 19742#L729-1 assume !(0 == ~E_3~0); 19743#L734-1 assume !(0 == ~E_4~0); 20324#L739-1 assume !(0 == ~E_5~0); 19944#L744-1 assume !(0 == ~E_6~0); 19945#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19698#L334 assume !(1 == ~m_pc~0); 19699#L334-2 is_master_triggered_~__retres1~0#1 := 0; 20043#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19948#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19914#L849 assume !(0 != activate_threads_~tmp~1#1); 19915#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19844#L353 assume !(1 == ~t1_pc~0); 19845#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20155#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19713#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19714#L857 assume !(0 != activate_threads_~tmp___0~0#1); 19796#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19797#L372 assume !(1 == ~t2_pc~0); 19903#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19902#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20037#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20156#L865 assume !(0 != activate_threads_~tmp___1~0#1); 19687#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19688#L391 assume !(1 == ~t3_pc~0); 19610#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19611#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19636#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19637#L873 assume !(0 != activate_threads_~tmp___2~0#1); 19921#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19922#L410 assume 1 == ~t4_pc~0; 20307#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20171#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19810#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19811#L881 assume !(0 != activate_threads_~tmp___3~0#1); 19931#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19932#L429 assume !(1 == ~t5_pc~0); 19748#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 19749#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19959#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19960#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20175#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19913#L448 assume 1 == ~t6_pc~0; 19784#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19785#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20140#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20141#L897 assume !(0 != activate_threads_~tmp___5~0#1); 20352#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20406#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 19966#L762-2 assume !(1 == ~T1_E~0); 19967#L767-1 assume !(1 == ~T2_E~0); 20383#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22291#L777-1 assume !(1 == ~T4_E~0); 22288#L782-1 assume !(1 == ~T5_E~0); 22286#L787-1 assume !(1 == ~T6_E~0); 22284#L792-1 assume !(1 == ~E_M~0); 19773#L797-1 assume !(1 == ~E_1~0); 22281#L802-1 assume !(1 == ~E_2~0); 22279#L807-1 assume !(1 == ~E_3~0); 22276#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 22274#L817-1 assume !(1 == ~E_5~0); 22272#L822-1 assume !(1 == ~E_6~0); 22263#L827-1 assume { :end_inline_reset_delta_events } true; 22155#L1053-2 [2023-11-29 04:15:03,361 INFO L750 eck$LassoCheckResult]: Loop: 22155#L1053-2 assume !false; 22142#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22136#L659-1 assume !false; 22134#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 22122#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 22113#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 22109#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22103#L570 assume !(0 != eval_~tmp~0#1); 22104#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22732#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22730#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22728#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22725#L689-3 assume !(0 == ~T2_E~0); 22723#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22721#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22719#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22717#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22715#L714-3 assume !(0 == ~E_M~0); 22712#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22710#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22708#L729-3 assume !(0 == ~E_3~0); 22706#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22704#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22702#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22699#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22697#L334-24 assume !(1 == ~m_pc~0); 22693#L334-26 is_master_triggered_~__retres1~0#1 := 0; 22691#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22682#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22681#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22679#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22677#L353-24 assume !(1 == ~t1_pc~0); 22676#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 22675#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22673#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22642#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22641#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22640#L372-24 assume !(1 == ~t2_pc~0); 22638#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 22637#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22636#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22635#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22634#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22633#L391-24 assume !(1 == ~t3_pc~0); 22632#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 22631#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22630#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22629#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 22628#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22627#L410-24 assume 1 == ~t4_pc~0; 22625#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22624#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22623#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22622#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22621#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22620#L429-24 assume !(1 == ~t5_pc~0); 22618#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 22617#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22616#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22615#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22614#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22613#L448-24 assume 1 == ~t6_pc~0; 22611#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22610#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22609#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22608#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22607#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22606#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20330#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22605#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22604#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22603#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22602#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20409#L787-3 assume !(1 == ~T6_E~0); 20223#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19987#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19988#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22594#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22591#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20327#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20328#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22585#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 22447#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 22442#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 22438#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 22437#L1072 assume !(0 == start_simulation_~tmp~3#1); 22436#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 22352#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 22344#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 22341#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 22338#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22335#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22331#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 22264#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 22155#L1053-2 [2023-11-29 04:15:03,362 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:03,362 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2023-11-29 04:15:03,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:03,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745005941] [2023-11-29 04:15:03,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:03,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:03,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:03,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:03,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:03,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745005941] [2023-11-29 04:15:03,410 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [745005941] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:03,410 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:03,410 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:15:03,410 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [853080668] [2023-11-29 04:15:03,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:03,411 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:03,411 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:03,411 INFO L85 PathProgramCache]: Analyzing trace with hash 1773510908, now seen corresponding path program 1 times [2023-11-29 04:15:03,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:03,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577880970] [2023-11-29 04:15:03,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:03,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:03,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:03,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:03,452 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:03,452 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577880970] [2023-11-29 04:15:03,452 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [577880970] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:03,452 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:03,452 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:03,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1531125832] [2023-11-29 04:15:03,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:03,453 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:03,453 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:03,453 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:03,454 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:03,454 INFO L87 Difference]: Start difference. First operand 3927 states and 5728 transitions. cyclomatic complexity: 1809 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:03,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:03,576 INFO L93 Difference]: Finished difference Result 7294 states and 10581 transitions. [2023-11-29 04:15:03,576 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7294 states and 10581 transitions. [2023-11-29 04:15:03,606 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7152 [2023-11-29 04:15:03,645 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7294 states to 7294 states and 10581 transitions. [2023-11-29 04:15:03,645 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7294 [2023-11-29 04:15:03,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7294 [2023-11-29 04:15:03,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7294 states and 10581 transitions. [2023-11-29 04:15:03,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:03,658 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7294 states and 10581 transitions. [2023-11-29 04:15:03,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7294 states and 10581 transitions. [2023-11-29 04:15:03,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7294 to 7278. [2023-11-29 04:15:03,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7278 states, 7278 states have (on average 1.4516350645781808) internal successors, (10565), 7277 states have internal predecessors, (10565), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:03,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7278 states to 7278 states and 10565 transitions. [2023-11-29 04:15:03,770 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7278 states and 10565 transitions. [2023-11-29 04:15:03,771 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:03,771 INFO L428 stractBuchiCegarLoop]: Abstraction has 7278 states and 10565 transitions. [2023-11-29 04:15:03,771 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-29 04:15:03,772 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7278 states and 10565 transitions. [2023-11-29 04:15:03,790 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7136 [2023-11-29 04:15:03,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:03,790 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:03,791 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:03,792 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:03,792 INFO L748 eck$LassoCheckResult]: Stem: 31230#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 31231#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 31365#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31366#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31018#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 31019#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31363#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31364#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31288#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31074#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31075#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30995#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30996#L684 assume !(0 == ~M_E~0); 31482#L684-2 assume !(0 == ~T1_E~0); 31322#L689-1 assume !(0 == ~T2_E~0); 31323#L694-1 assume !(0 == ~T3_E~0); 31320#L699-1 assume !(0 == ~T4_E~0); 31321#L704-1 assume !(0 == ~T5_E~0); 31271#L709-1 assume !(0 == ~T6_E~0); 31211#L714-1 assume !(0 == ~E_M~0); 31212#L719-1 assume !(0 == ~E_1~0); 31450#L724-1 assume !(0 == ~E_2~0); 30969#L729-1 assume !(0 == ~E_3~0); 30970#L734-1 assume !(0 == ~E_4~0); 31513#L739-1 assume !(0 == ~E_5~0); 31171#L744-1 assume !(0 == ~E_6~0); 31172#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30926#L334 assume !(1 == ~m_pc~0); 30927#L334-2 is_master_triggered_~__retres1~0#1 := 0; 31263#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31173#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31141#L849 assume !(0 != activate_threads_~tmp~1#1); 31142#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31072#L353 assume !(1 == ~t1_pc~0); 31073#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31369#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30941#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30942#L857 assume !(0 != activate_threads_~tmp___0~0#1); 31023#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31024#L372 assume !(1 == ~t2_pc~0); 31128#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31127#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31258#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31370#L865 assume !(0 != activate_threads_~tmp___1~0#1); 30915#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30916#L391 assume !(1 == ~t3_pc~0); 30838#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30839#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30864#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30865#L873 assume !(0 != activate_threads_~tmp___2~0#1); 31148#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31149#L410 assume !(1 == ~t4_pc~0); 31380#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31381#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31038#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31039#L881 assume !(0 != activate_threads_~tmp___3~0#1); 31154#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31155#L429 assume !(1 == ~t5_pc~0); 30975#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 30976#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31184#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31185#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31388#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31138#L448 assume 1 == ~t6_pc~0; 31011#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31012#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31353#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31354#L897 assume !(0 != activate_threads_~tmp___5~0#1); 31539#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31584#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 31585#L762-2 assume !(1 == ~T1_E~0); 33412#L767-1 assume !(1 == ~T2_E~0); 33410#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33408#L777-1 assume !(1 == ~T4_E~0); 33406#L782-1 assume !(1 == ~T5_E~0); 33404#L787-1 assume !(1 == ~T6_E~0); 33402#L792-1 assume !(1 == ~E_M~0); 31000#L797-1 assume !(1 == ~E_1~0); 33399#L802-1 assume !(1 == ~E_2~0); 33397#L807-1 assume !(1 == ~E_3~0); 33395#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33393#L817-1 assume !(1 == ~E_5~0); 33391#L822-1 assume !(1 == ~E_6~0); 31517#L827-1 assume { :end_inline_reset_delta_events } true; 31518#L1053-2 [2023-11-29 04:15:03,792 INFO L750 eck$LassoCheckResult]: Loop: 31518#L1053-2 assume !false; 34268#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34263#L659-1 assume !false; 34261#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 34128#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 34121#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 34119#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34116#L570 assume !(0 != eval_~tmp~0#1); 34117#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35683#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35680#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35677#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35674#L689-3 assume !(0 == ~T2_E~0); 35671#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35667#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35665#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35662#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35613#L714-3 assume !(0 == ~E_M~0); 35610#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35608#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35351#L729-3 assume !(0 == ~E_3~0); 35350#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35349#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35348#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35347#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35346#L334-24 assume 1 == ~m_pc~0; 35344#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35341#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35339#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 35337#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35335#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35333#L353-24 assume !(1 == ~t1_pc~0); 35331#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 35329#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35327#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 35324#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35322#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35320#L372-24 assume !(1 == ~t2_pc~0); 35317#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 35315#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35313#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 35312#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35309#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35307#L391-24 assume !(1 == ~t3_pc~0); 35305#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 35303#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35301#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35299#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 35297#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35295#L410-24 assume !(1 == ~t4_pc~0); 35293#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 35291#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35289#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 35287#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35284#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35282#L429-24 assume 1 == ~t5_pc~0; 35280#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35277#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35275#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35273#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35272#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35271#L448-24 assume 1 == ~t6_pc~0; 35269#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35087#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35084#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35082#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35080#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35078#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33651#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35075#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35072#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34976#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34966#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34961#L787-3 assume !(1 == ~T6_E~0); 34955#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33615#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34938#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34933#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34926#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34919#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34914#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34910#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 34812#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 34805#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 34800#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 34795#L1072 assume !(0 == start_simulation_~tmp~3#1); 34787#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 34288#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 34281#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 34279#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 34277#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34275#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34273#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 34271#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 31518#L1053-2 [2023-11-29 04:15:03,792 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:03,792 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2023-11-29 04:15:03,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:03,793 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [208492382] [2023-11-29 04:15:03,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:03,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:03,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:03,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:03,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:03,886 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [208492382] [2023-11-29 04:15:03,887 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [208492382] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:03,887 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:03,887 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:15:03,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1661515496] [2023-11-29 04:15:03,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:03,887 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:03,888 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:03,888 INFO L85 PathProgramCache]: Analyzing trace with hash 719332731, now seen corresponding path program 1 times [2023-11-29 04:15:03,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:03,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1622373650] [2023-11-29 04:15:03,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:03,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:03,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:03,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:03,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:03,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1622373650] [2023-11-29 04:15:03,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1622373650] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:03,925 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:03,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:03,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1204596647] [2023-11-29 04:15:03,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:03,926 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:03,926 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:03,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:15:03,927 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:15:03,927 INFO L87 Difference]: Start difference. First operand 7278 states and 10565 transitions. cyclomatic complexity: 3303 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:04,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:04,202 INFO L93 Difference]: Finished difference Result 15022 states and 21574 transitions. [2023-11-29 04:15:04,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15022 states and 21574 transitions. [2023-11-29 04:15:04,259 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14792 [2023-11-29 04:15:04,318 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15022 states to 15022 states and 21574 transitions. [2023-11-29 04:15:04,318 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15022 [2023-11-29 04:15:04,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15022 [2023-11-29 04:15:04,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15022 states and 21574 transitions. [2023-11-29 04:15:04,392 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:04,393 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15022 states and 21574 transitions. [2023-11-29 04:15:04,409 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15022 states and 21574 transitions. [2023-11-29 04:15:04,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15022 to 7593. [2023-11-29 04:15:04,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7593 states, 7593 states have (on average 1.4328987225075727) internal successors, (10880), 7592 states have internal predecessors, (10880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:04,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7593 states to 7593 states and 10880 transitions. [2023-11-29 04:15:04,539 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7593 states and 10880 transitions. [2023-11-29 04:15:04,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:15:04,539 INFO L428 stractBuchiCegarLoop]: Abstraction has 7593 states and 10880 transitions. [2023-11-29 04:15:04,540 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-29 04:15:04,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7593 states and 10880 transitions. [2023-11-29 04:15:04,559 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7448 [2023-11-29 04:15:04,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:04,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:04,560 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:04,560 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:04,560 INFO L748 eck$LassoCheckResult]: Stem: 53544#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 53545#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 53679#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53680#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53332#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 53333#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53677#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53678#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53606#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53389#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53390#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53309#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53310#L684 assume !(0 == ~M_E~0); 53799#L684-2 assume !(0 == ~T1_E~0); 53635#L689-1 assume !(0 == ~T2_E~0); 53636#L694-1 assume !(0 == ~T3_E~0); 53633#L699-1 assume !(0 == ~T4_E~0); 53634#L704-1 assume !(0 == ~T5_E~0); 53591#L709-1 assume !(0 == ~T6_E~0); 53523#L714-1 assume !(0 == ~E_M~0); 53524#L719-1 assume !(0 == ~E_1~0); 53768#L724-1 assume !(0 == ~E_2~0); 53283#L729-1 assume !(0 == ~E_3~0); 53284#L734-1 assume !(0 == ~E_4~0); 53834#L739-1 assume !(0 == ~E_5~0); 53485#L744-1 assume !(0 == ~E_6~0); 53486#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53239#L334 assume !(1 == ~m_pc~0); 53240#L334-2 is_master_triggered_~__retres1~0#1 := 0; 53583#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53487#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 53456#L849 assume !(0 != activate_threads_~tmp~1#1); 53457#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53387#L353 assume !(1 == ~t1_pc~0); 53388#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53684#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53254#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53255#L857 assume !(0 != activate_threads_~tmp___0~0#1); 53338#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53339#L372 assume !(1 == ~t2_pc~0); 53445#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 53444#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53578#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 53685#L865 assume !(0 != activate_threads_~tmp___1~0#1); 53228#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53229#L391 assume !(1 == ~t3_pc~0); 53151#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53152#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53177#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 53178#L873 assume !(0 != activate_threads_~tmp___2~0#1); 53463#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53464#L410 assume !(1 == ~t4_pc~0); 53696#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 53697#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53352#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53353#L881 assume !(0 != activate_threads_~tmp___3~0#1); 53470#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53471#L429 assume !(1 == ~t5_pc~0); 53289#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 53290#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53930#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53704#L889 assume !(0 != activate_threads_~tmp___4~0#1); 53705#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53455#L448 assume 1 == ~t6_pc~0; 53325#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53326#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53667#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53668#L897 assume !(0 != activate_threads_~tmp___5~0#1); 53869#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53921#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 53922#L762-2 assume !(1 == ~T1_E~0); 56838#L767-1 assume !(1 == ~T2_E~0); 56837#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56836#L777-1 assume !(1 == ~T4_E~0); 56835#L782-1 assume !(1 == ~T5_E~0); 56834#L787-1 assume !(1 == ~T6_E~0); 56833#L792-1 assume !(1 == ~E_M~0); 53314#L797-1 assume !(1 == ~E_1~0); 56832#L802-1 assume !(1 == ~E_2~0); 56831#L807-1 assume !(1 == ~E_3~0); 56829#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 56826#L817-1 assume !(1 == ~E_5~0); 56824#L822-1 assume !(1 == ~E_6~0); 53842#L827-1 assume { :end_inline_reset_delta_events } true; 53843#L1053-2 [2023-11-29 04:15:04,561 INFO L750 eck$LassoCheckResult]: Loop: 53843#L1053-2 assume !false; 55853#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 55850#L659-1 assume !false; 55838#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 55839#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 55668#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 55669#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 55660#L570 assume !(0 != eval_~tmp~0#1); 55662#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56940#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56939#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 56938#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 56937#L689-3 assume !(0 == ~T2_E~0); 56936#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 56935#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56934#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 56933#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 56932#L714-3 assume !(0 == ~E_M~0); 56931#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 56930#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 56929#L729-3 assume !(0 == ~E_3~0); 56928#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 56927#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 56926#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 56925#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56924#L334-24 assume !(1 == ~m_pc~0); 56922#L334-26 is_master_triggered_~__retres1~0#1 := 0; 56921#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56920#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 56919#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 56918#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56917#L353-24 assume !(1 == ~t1_pc~0); 56916#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 56915#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56914#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 56913#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 56912#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56911#L372-24 assume !(1 == ~t2_pc~0); 56909#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 56908#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56907#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56906#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 56905#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56904#L391-24 assume !(1 == ~t3_pc~0); 56903#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 56902#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56901#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56900#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 56899#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56898#L410-24 assume !(1 == ~t4_pc~0); 56897#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 56896#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56895#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 56894#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56893#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56892#L429-24 assume 1 == ~t5_pc~0; 56890#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56888#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56886#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 56884#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 56881#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56878#L448-24 assume 1 == ~t6_pc~0; 56876#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 56871#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56868#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56863#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56860#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56859#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53841#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56858#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56857#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56856#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56855#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56854#L787-3 assume !(1 == ~T6_E~0); 56853#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53753#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 56852#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 56851#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 56850#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 56849#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 56848#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 56847#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 56842#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 56839#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 56799#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 56798#L1072 assume !(0 == start_simulation_~tmp~3#1); 55976#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 55966#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 55960#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 55956#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 55948#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55944#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55894#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 55881#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 53843#L1053-2 [2023-11-29 04:15:04,561 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:04,561 INFO L85 PathProgramCache]: Analyzing trace with hash 1099430922, now seen corresponding path program 1 times [2023-11-29 04:15:04,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:04,561 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2054077232] [2023-11-29 04:15:04,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:04,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:04,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:04,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:04,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:04,632 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2054077232] [2023-11-29 04:15:04,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2054077232] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:04,633 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:04,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:15:04,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1334800206] [2023-11-29 04:15:04,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:04,633 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:04,634 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:04,634 INFO L85 PathProgramCache]: Analyzing trace with hash 1856961596, now seen corresponding path program 1 times [2023-11-29 04:15:04,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:04,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747467283] [2023-11-29 04:15:04,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:04,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:04,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:04,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:04,667 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:04,667 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [747467283] [2023-11-29 04:15:04,667 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [747467283] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:04,667 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:04,667 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:04,667 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [925145281] [2023-11-29 04:15:04,667 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:04,668 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:04,668 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:04,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:04,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:04,668 INFO L87 Difference]: Start difference. First operand 7593 states and 10880 transitions. cyclomatic complexity: 3303 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:04,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:04,783 INFO L93 Difference]: Finished difference Result 14548 states and 20713 transitions. [2023-11-29 04:15:04,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14548 states and 20713 transitions. [2023-11-29 04:15:04,857 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14332 [2023-11-29 04:15:04,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14548 states to 14548 states and 20713 transitions. [2023-11-29 04:15:04,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14548 [2023-11-29 04:15:04,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14548 [2023-11-29 04:15:04,898 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14548 states and 20713 transitions. [2023-11-29 04:15:04,906 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:04,906 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14548 states and 20713 transitions. [2023-11-29 04:15:04,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14548 states and 20713 transitions. [2023-11-29 04:15:05,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14548 to 14516. [2023-11-29 04:15:05,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14516 states, 14516 states have (on average 1.424703775144668) internal successors, (20681), 14515 states have internal predecessors, (20681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:05,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14516 states to 14516 states and 20681 transitions. [2023-11-29 04:15:05,261 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14516 states and 20681 transitions. [2023-11-29 04:15:05,261 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:05,263 INFO L428 stractBuchiCegarLoop]: Abstraction has 14516 states and 20681 transitions. [2023-11-29 04:15:05,263 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-29 04:15:05,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14516 states and 20681 transitions. [2023-11-29 04:15:05,316 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14300 [2023-11-29 04:15:05,316 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:05,316 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:05,318 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:05,318 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:05,319 INFO L748 eck$LassoCheckResult]: Stem: 75696#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 75697#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 75841#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75842#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75479#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 75480#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75837#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75838#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75758#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75536#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75537#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75458#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75459#L684 assume !(0 == ~M_E~0); 75965#L684-2 assume !(0 == ~T1_E~0); 75793#L689-1 assume !(0 == ~T2_E~0); 75794#L694-1 assume !(0 == ~T3_E~0); 75791#L699-1 assume !(0 == ~T4_E~0); 75792#L704-1 assume !(0 == ~T5_E~0); 75742#L709-1 assume !(0 == ~T6_E~0); 75671#L714-1 assume !(0 == ~E_M~0); 75672#L719-1 assume !(0 == ~E_1~0); 75928#L724-1 assume !(0 == ~E_2~0); 75428#L729-1 assume !(0 == ~E_3~0); 75429#L734-1 assume !(0 == ~E_4~0); 76005#L739-1 assume !(0 == ~E_5~0); 75629#L744-1 assume !(0 == ~E_6~0); 75630#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75385#L334 assume !(1 == ~m_pc~0); 75386#L334-2 is_master_triggered_~__retres1~0#1 := 0; 75731#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75634#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75597#L849 assume !(0 != activate_threads_~tmp~1#1); 75598#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75532#L353 assume !(1 == ~t1_pc~0); 75533#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75843#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75400#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75401#L857 assume !(0 != activate_threads_~tmp___0~0#1); 75481#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75482#L372 assume !(1 == ~t2_pc~0); 75586#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 75585#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75725#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 75844#L865 assume !(0 != activate_threads_~tmp___1~0#1); 75374#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75375#L391 assume !(1 == ~t3_pc~0); 75299#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 75300#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75324#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 75325#L873 assume !(0 != activate_threads_~tmp___2~0#1); 75604#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75605#L410 assume !(1 == ~t4_pc~0); 75859#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 75860#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75496#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75497#L881 assume !(0 != activate_threads_~tmp___3~0#1); 75614#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75615#L429 assume !(1 == ~t5_pc~0); 75434#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 75435#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75644#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 75645#L889 assume !(0 != activate_threads_~tmp___4~0#1); 75864#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75596#L448 assume !(1 == ~t6_pc~0); 75515#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 75516#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75828#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75829#L897 assume !(0 != activate_threads_~tmp___5~0#1); 76035#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76082#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 75651#L762-2 assume !(1 == ~T1_E~0); 75652#L767-1 assume !(1 == ~T2_E~0); 76041#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75894#L777-1 assume !(1 == ~T4_E~0); 75777#L782-1 assume !(1 == ~T5_E~0); 75462#L787-1 assume !(1 == ~T6_E~0); 75460#L792-1 assume !(1 == ~E_M~0); 75461#L797-1 assume !(1 == ~E_1~0); 75502#L802-1 assume !(1 == ~E_2~0); 75735#L807-1 assume !(1 == ~E_3~0); 75736#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 76002#L817-1 assume !(1 == ~E_5~0); 75797#L822-1 assume !(1 == ~E_6~0); 75798#L827-1 assume { :end_inline_reset_delta_events } true; 85238#L1053-2 [2023-11-29 04:15:05,319 INFO L750 eck$LassoCheckResult]: Loop: 85238#L1053-2 assume !false; 85229#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85220#L659-1 assume !false; 85217#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 84984#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 84972#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 84965#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 84959#L570 assume !(0 != eval_~tmp~0#1); 84960#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 86780#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 86778#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 86776#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 86774#L689-3 assume !(0 == ~T2_E~0); 86772#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 86770#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 86768#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 86766#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 86764#L714-3 assume !(0 == ~E_M~0); 86762#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 86760#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 86758#L729-3 assume !(0 == ~E_3~0); 86756#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 86754#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86752#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 86749#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86747#L334-24 assume 1 == ~m_pc~0; 86745#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 86742#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86740#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 86738#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 86736#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86734#L353-24 assume !(1 == ~t1_pc~0); 86732#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 86730#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86728#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 86726#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 86723#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86721#L372-24 assume 1 == ~t2_pc~0; 86719#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 86716#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86714#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 86712#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86710#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86708#L391-24 assume !(1 == ~t3_pc~0); 86706#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 86704#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86702#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 86700#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 86698#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86696#L410-24 assume !(1 == ~t4_pc~0); 86694#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 86692#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86690#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 86686#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 86684#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86682#L429-24 assume !(1 == ~t5_pc~0); 86678#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 86675#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86673#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 86671#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 86668#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86666#L448-24 assume !(1 == ~t6_pc~0); 86664#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 86662#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86660#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 86659#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86658#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86656#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 86651#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86649#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86647#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86645#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86643#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86641#L787-3 assume !(1 == ~T6_E~0); 86638#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 86634#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 86632#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 86630#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86628#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 86626#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86623#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86621#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 86608#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 86604#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 86602#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 86599#L1072 assume !(0 == start_simulation_~tmp~3#1); 86597#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 86469#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 86455#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 86446#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 86441#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86437#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86433#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 85248#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 85238#L1053-2 [2023-11-29 04:15:05,319 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:05,319 INFO L85 PathProgramCache]: Analyzing trace with hash 125941963, now seen corresponding path program 1 times [2023-11-29 04:15:05,320 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:05,320 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1701064205] [2023-11-29 04:15:05,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:05,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:05,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:05,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:05,430 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:05,430 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1701064205] [2023-11-29 04:15:05,430 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1701064205] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:05,430 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:05,430 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:15:05,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1913832668] [2023-11-29 04:15:05,431 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:05,431 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:05,431 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:05,431 INFO L85 PathProgramCache]: Analyzing trace with hash 1396541054, now seen corresponding path program 1 times [2023-11-29 04:15:05,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:05,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58343167] [2023-11-29 04:15:05,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:05,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:05,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:05,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:05,500 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:05,500 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58343167] [2023-11-29 04:15:05,500 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [58343167] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:05,500 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:05,501 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:05,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [370021272] [2023-11-29 04:15:05,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:05,501 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:05,501 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:05,502 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:05,502 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:05,502 INFO L87 Difference]: Start difference. First operand 14516 states and 20681 transitions. cyclomatic complexity: 6197 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:05,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:05,636 INFO L93 Difference]: Finished difference Result 21621 states and 30826 transitions. [2023-11-29 04:15:05,636 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21621 states and 30826 transitions. [2023-11-29 04:15:05,721 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21356 [2023-11-29 04:15:05,833 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21621 states to 21621 states and 30826 transitions. [2023-11-29 04:15:05,833 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21621 [2023-11-29 04:15:05,851 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21621 [2023-11-29 04:15:05,852 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21621 states and 30826 transitions. [2023-11-29 04:15:05,867 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:05,867 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21621 states and 30826 transitions. [2023-11-29 04:15:05,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21621 states and 30826 transitions. [2023-11-29 04:15:06,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21621 to 15146. [2023-11-29 04:15:06,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15146 states, 15146 states have (on average 1.4282979004357585) internal successors, (21633), 15145 states have internal predecessors, (21633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:06,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15146 states to 15146 states and 21633 transitions. [2023-11-29 04:15:06,223 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15146 states and 21633 transitions. [2023-11-29 04:15:06,224 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:06,224 INFO L428 stractBuchiCegarLoop]: Abstraction has 15146 states and 21633 transitions. [2023-11-29 04:15:06,225 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-29 04:15:06,225 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15146 states and 21633 transitions. [2023-11-29 04:15:06,277 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14944 [2023-11-29 04:15:06,277 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:06,277 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:06,279 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:06,279 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:06,279 INFO L748 eck$LassoCheckResult]: Stem: 111837#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 111838#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 111979#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 111980#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 111623#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 111624#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 111975#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 111976#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 111900#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 111679#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 111680#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 111603#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 111604#L684 assume !(0 == ~M_E~0); 112107#L684-2 assume !(0 == ~T1_E~0); 111932#L689-1 assume !(0 == ~T2_E~0); 111933#L694-1 assume !(0 == ~T3_E~0); 111930#L699-1 assume !(0 == ~T4_E~0); 111931#L704-1 assume !(0 == ~T5_E~0); 111885#L709-1 assume !(0 == ~T6_E~0); 111813#L714-1 assume !(0 == ~E_M~0); 111814#L719-1 assume !(0 == ~E_1~0); 112068#L724-1 assume !(0 == ~E_2~0); 111575#L729-1 assume !(0 == ~E_3~0); 111576#L734-1 assume !(0 == ~E_4~0); 112144#L739-1 assume !(0 == ~E_5~0); 111773#L744-1 assume !(0 == ~E_6~0); 111774#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 111531#L334 assume !(1 == ~m_pc~0); 111532#L334-2 is_master_triggered_~__retres1~0#1 := 0; 111874#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 111777#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 111744#L849 assume !(0 != activate_threads_~tmp~1#1); 111745#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111675#L353 assume !(1 == ~t1_pc~0); 111676#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 111981#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 111546#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 111547#L857 assume !(0 != activate_threads_~tmp___0~0#1); 111625#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111626#L372 assume !(1 == ~t2_pc~0); 111731#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 111730#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111868#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 111982#L865 assume !(0 != activate_threads_~tmp___1~0#1); 111520#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 111521#L391 assume !(1 == ~t3_pc~0); 111443#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 111444#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111469#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 111470#L873 assume !(0 != activate_threads_~tmp___2~0#1); 111751#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111752#L410 assume !(1 == ~t4_pc~0); 111998#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 111999#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 111639#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 111640#L881 assume !(0 != activate_threads_~tmp___3~0#1); 111759#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 111760#L429 assume !(1 == ~t5_pc~0); 111581#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 111582#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 111788#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 111789#L889 assume !(0 != activate_threads_~tmp___4~0#1); 112003#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 111743#L448 assume !(1 == ~t6_pc~0); 111658#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 111659#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111966#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 111967#L897 assume !(0 != activate_threads_~tmp___5~0#1); 112174#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112225#L762 assume !(1 == ~M_E~0); 111793#L762-2 assume !(1 == ~T1_E~0); 111794#L767-1 assume !(1 == ~T2_E~0); 112180#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112035#L777-1 assume !(1 == ~T4_E~0); 111915#L782-1 assume !(1 == ~T5_E~0); 111607#L787-1 assume !(1 == ~T6_E~0); 111605#L792-1 assume !(1 == ~E_M~0); 111606#L797-1 assume !(1 == ~E_1~0); 111645#L802-1 assume !(1 == ~E_2~0); 111878#L807-1 assume !(1 == ~E_3~0); 111879#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 112139#L817-1 assume !(1 == ~E_5~0); 111936#L822-1 assume !(1 == ~E_6~0); 111937#L827-1 assume { :end_inline_reset_delta_events } true; 112152#L1053-2 [2023-11-29 04:15:06,280 INFO L750 eck$LassoCheckResult]: Loop: 112152#L1053-2 assume !false; 122114#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 122082#L659-1 assume !false; 122103#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 122094#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 122084#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 122080#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 122077#L570 assume !(0 != eval_~tmp~0#1); 122078#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 123591#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 123589#L684-3 assume !(0 == ~M_E~0); 123587#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 123585#L689-3 assume !(0 == ~T2_E~0); 123582#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 123580#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 123578#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 123576#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 123574#L714-3 assume !(0 == ~E_M~0); 123572#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 123570#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 123568#L729-3 assume !(0 == ~E_3~0); 123567#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 123566#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 123564#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 123562#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123534#L334-24 assume 1 == ~m_pc~0; 123525#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 123517#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123509#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 123502#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 123496#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123493#L353-24 assume !(1 == ~t1_pc~0); 123490#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 123481#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123478#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 123475#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 123471#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123468#L372-24 assume !(1 == ~t2_pc~0); 123463#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 123460#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123457#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 123454#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 123451#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123448#L391-24 assume !(1 == ~t3_pc~0); 123444#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 123441#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123438#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 123435#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 123432#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123429#L410-24 assume !(1 == ~t4_pc~0); 123425#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 123422#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123419#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 123416#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 123413#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123408#L429-24 assume !(1 == ~t5_pc~0); 123401#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 123395#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123389#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 123382#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 123374#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 123367#L448-24 assume !(1 == ~t6_pc~0); 123360#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 123355#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 122845#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 122828#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 122825#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122812#L762-3 assume !(1 == ~M_E~0); 115396#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 122800#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 122792#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 122787#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 122782#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 122775#L787-3 assume !(1 == ~T6_E~0); 122766#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 122503#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 120633#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 120632#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 120631#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 120630#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 120629#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 120628#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 120623#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 118281#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 118272#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 115607#L1072 assume !(0 == start_simulation_~tmp~3#1); 115608#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 122161#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 122152#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 122148#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 122144#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 122139#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 122134#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 122129#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 112152#L1053-2 [2023-11-29 04:15:06,280 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:06,280 INFO L85 PathProgramCache]: Analyzing trace with hash -1153921715, now seen corresponding path program 1 times [2023-11-29 04:15:06,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:06,281 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121923472] [2023-11-29 04:15:06,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:06,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:06,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:06,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:06,354 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:06,354 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2121923472] [2023-11-29 04:15:06,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2121923472] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:06,354 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:06,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:06,355 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753809678] [2023-11-29 04:15:06,355 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:06,355 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:06,356 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:06,356 INFO L85 PathProgramCache]: Analyzing trace with hash 1680905471, now seen corresponding path program 1 times [2023-11-29 04:15:06,356 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:06,356 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56587594] [2023-11-29 04:15:06,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:06,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:06,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:06,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:06,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:06,407 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [56587594] [2023-11-29 04:15:06,407 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [56587594] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:06,407 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:06,408 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:06,408 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18437573] [2023-11-29 04:15:06,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:06,408 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:06,409 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:06,409 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:15:06,409 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:15:06,409 INFO L87 Difference]: Start difference. First operand 15146 states and 21633 transitions. cyclomatic complexity: 6503 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:06,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:06,627 INFO L93 Difference]: Finished difference Result 24188 states and 34429 transitions. [2023-11-29 04:15:06,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24188 states and 34429 transitions. [2023-11-29 04:15:06,748 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23856 [2023-11-29 04:15:06,848 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24188 states to 24188 states and 34429 transitions. [2023-11-29 04:15:06,848 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24188 [2023-11-29 04:15:06,864 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24188 [2023-11-29 04:15:06,865 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24188 states and 34429 transitions. [2023-11-29 04:15:06,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:06,889 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24188 states and 34429 transitions. [2023-11-29 04:15:06,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24188 states and 34429 transitions. [2023-11-29 04:15:07,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24188 to 17289. [2023-11-29 04:15:07,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17289 states, 17289 states have (on average 1.427497252588351) internal successors, (24680), 17288 states have internal predecessors, (24680), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:07,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17289 states to 17289 states and 24680 transitions. [2023-11-29 04:15:07,241 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17289 states and 24680 transitions. [2023-11-29 04:15:07,242 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 04:15:07,242 INFO L428 stractBuchiCegarLoop]: Abstraction has 17289 states and 24680 transitions. [2023-11-29 04:15:07,242 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-29 04:15:07,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17289 states and 24680 transitions. [2023-11-29 04:15:07,360 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17024 [2023-11-29 04:15:07,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:07,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:07,362 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:07,362 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:07,362 INFO L748 eck$LassoCheckResult]: Stem: 151185#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 151186#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 151318#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 151319#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 150967#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 150968#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 151314#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 151315#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 151240#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 151024#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 151025#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 150947#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 150948#L684 assume !(0 == ~M_E~0); 151444#L684-2 assume !(0 == ~T1_E~0); 151273#L689-1 assume !(0 == ~T2_E~0); 151274#L694-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 151271#L699-1 assume !(0 == ~T4_E~0); 151272#L704-1 assume !(0 == ~T5_E~0); 151227#L709-1 assume !(0 == ~T6_E~0); 151228#L714-1 assume !(0 == ~E_M~0); 151596#L719-1 assume !(0 == ~E_1~0); 151537#L724-1 assume !(0 == ~E_2~0); 151538#L729-1 assume !(0 == ~E_3~0); 151528#L734-1 assume !(0 == ~E_4~0); 151481#L739-1 assume !(0 == ~E_5~0); 151482#L744-1 assume !(0 == ~E_6~0); 151594#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 150876#L334 assume !(1 == ~m_pc~0); 150877#L334-2 is_master_triggered_~__retres1~0#1 := 0; 151216#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 151486#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 151088#L849 assume !(0 != activate_threads_~tmp~1#1); 151089#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 151590#L353 assume !(1 == ~t1_pc~0); 151589#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 151320#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 150891#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 150892#L857 assume !(0 != activate_threads_~tmp___0~0#1); 150969#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 150970#L372 assume !(1 == ~t2_pc~0); 151077#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 151076#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 151211#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 151586#L865 assume !(0 != activate_threads_~tmp___1~0#1); 150865#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 150866#L391 assume !(1 == ~t3_pc~0); 151458#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 151584#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 151583#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 151582#L873 assume !(0 != activate_threads_~tmp___2~0#1); 151095#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 151096#L410 assume !(1 == ~t4_pc~0); 151469#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 151378#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 150984#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 150985#L881 assume !(0 != activate_threads_~tmp___3~0#1); 151473#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 151263#L429 assume !(1 == ~t5_pc~0); 150925#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 150926#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 151133#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 151134#L889 assume !(0 != activate_threads_~tmp___4~0#1); 151341#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 151087#L448 assume !(1 == ~t6_pc~0); 151003#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 151004#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 151306#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 151307#L897 assume !(0 != activate_threads_~tmp___5~0#1); 151561#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 151562#L762 assume !(1 == ~M_E~0); 151570#L762-2 assume !(1 == ~T1_E~0); 151540#L767-1 assume !(1 == ~T2_E~0); 151541#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 151373#L777-1 assume !(1 == ~T4_E~0); 151255#L782-1 assume !(1 == ~T5_E~0); 150951#L787-1 assume !(1 == ~T6_E~0); 150949#L792-1 assume !(1 == ~E_M~0); 150950#L797-1 assume !(1 == ~E_1~0); 150990#L802-1 assume !(1 == ~E_2~0); 151220#L807-1 assume !(1 == ~E_3~0); 151221#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 151478#L817-1 assume !(1 == ~E_5~0); 151277#L822-1 assume !(1 == ~E_6~0); 151278#L827-1 assume { :end_inline_reset_delta_events } true; 151485#L1053-2 [2023-11-29 04:15:07,363 INFO L750 eck$LassoCheckResult]: Loop: 151485#L1053-2 assume !false; 154751#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 154741#L659-1 assume !false; 154739#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 154285#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 154278#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 154276#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 154273#L570 assume !(0 != eval_~tmp~0#1); 154271#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 154270#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 154267#L684-3 assume !(0 == ~M_E~0); 154266#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 154263#L689-3 assume !(0 == ~T2_E~0); 154258#L694-3 assume !(0 == ~T3_E~0); 154259#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 155524#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 155520#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 155517#L714-3 assume !(0 == ~E_M~0); 155514#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 155511#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 155508#L729-3 assume !(0 == ~E_3~0); 155505#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 155502#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 155499#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 155496#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 155493#L334-24 assume !(1 == ~m_pc~0); 155488#L334-26 is_master_triggered_~__retres1~0#1 := 0; 155484#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 155480#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 155476#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 155473#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 155470#L353-24 assume !(1 == ~t1_pc~0); 155466#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 155463#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 155459#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 155455#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 155451#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 155448#L372-24 assume 1 == ~t2_pc~0; 155446#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 155443#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 155440#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 155438#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 155423#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 155421#L391-24 assume !(1 == ~t3_pc~0); 155419#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 155415#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 155413#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 155411#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 154386#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154383#L410-24 assume !(1 == ~t4_pc~0); 154381#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 154379#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 154377#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 154374#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 154372#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 154370#L429-24 assume 1 == ~t5_pc~0; 154368#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 154369#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 154470#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 154359#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 154357#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 154355#L448-24 assume !(1 == ~t6_pc~0); 154353#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 154351#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 154349#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 154346#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 154344#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 154342#L762-3 assume !(1 == ~M_E~0); 153850#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 154339#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 154196#L772-3 assume !(1 == ~T3_E~0); 154191#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 154190#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 154163#L787-3 assume !(1 == ~T6_E~0); 154160#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 154158#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 154157#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 154156#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 154155#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 154154#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 154153#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 154152#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 154095#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 154088#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 154073#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 154043#L1072 assume !(0 == start_simulation_~tmp~3#1); 154044#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 155110#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 155103#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 155101#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 155087#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 155079#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 155071#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 155070#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 151485#L1053-2 [2023-11-29 04:15:07,363 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:07,363 INFO L85 PathProgramCache]: Analyzing trace with hash -661295541, now seen corresponding path program 1 times [2023-11-29 04:15:07,363 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:07,363 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226716245] [2023-11-29 04:15:07,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:07,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:07,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:07,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:07,415 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:07,416 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [226716245] [2023-11-29 04:15:07,416 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [226716245] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:07,416 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:07,416 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:07,416 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [694539503] [2023-11-29 04:15:07,416 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:07,416 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:07,417 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:07,417 INFO L85 PathProgramCache]: Analyzing trace with hash -1107617988, now seen corresponding path program 1 times [2023-11-29 04:15:07,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:07,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997650029] [2023-11-29 04:15:07,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:07,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:07,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:07,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:07,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:07,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1997650029] [2023-11-29 04:15:07,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1997650029] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:07,455 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:07,455 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:07,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [826923499] [2023-11-29 04:15:07,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:07,456 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:07,456 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:07,456 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:15:07,456 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:15:07,457 INFO L87 Difference]: Start difference. First operand 17289 states and 24680 transitions. cyclomatic complexity: 7407 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:07,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:07,568 INFO L93 Difference]: Finished difference Result 22034 states and 31247 transitions. [2023-11-29 04:15:07,568 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22034 states and 31247 transitions. [2023-11-29 04:15:07,657 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21776 [2023-11-29 04:15:07,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22034 states to 22034 states and 31247 transitions. [2023-11-29 04:15:07,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22034 [2023-11-29 04:15:07,744 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22034 [2023-11-29 04:15:07,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22034 states and 31247 transitions. [2023-11-29 04:15:07,762 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:07,762 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22034 states and 31247 transitions. [2023-11-29 04:15:07,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22034 states and 31247 transitions. [2023-11-29 04:15:07,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22034 to 15146. [2023-11-29 04:15:08,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15146 states, 15146 states have (on average 1.4218275452264624) internal successors, (21535), 15145 states have internal predecessors, (21535), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:08,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15146 states to 15146 states and 21535 transitions. [2023-11-29 04:15:08,037 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15146 states and 21535 transitions. [2023-11-29 04:15:08,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 04:15:08,038 INFO L428 stractBuchiCegarLoop]: Abstraction has 15146 states and 21535 transitions. [2023-11-29 04:15:08,038 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-29 04:15:08,038 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15146 states and 21535 transitions. [2023-11-29 04:15:08,083 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14944 [2023-11-29 04:15:08,083 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:08,083 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:08,085 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:08,085 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:08,085 INFO L748 eck$LassoCheckResult]: Stem: 190515#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 190516#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 190650#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 190651#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 190298#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 190299#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 190648#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 190649#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 190578#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 190358#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 190359#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 190279#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 190280#L684 assume !(0 == ~M_E~0); 190773#L684-2 assume !(0 == ~T1_E~0); 190609#L689-1 assume !(0 == ~T2_E~0); 190610#L694-1 assume !(0 == ~T3_E~0); 190607#L699-1 assume !(0 == ~T4_E~0); 190608#L704-1 assume !(0 == ~T5_E~0); 190563#L709-1 assume !(0 == ~T6_E~0); 190496#L714-1 assume !(0 == ~E_M~0); 190497#L719-1 assume !(0 == ~E_1~0); 190742#L724-1 assume !(0 == ~E_2~0); 190251#L729-1 assume !(0 == ~E_3~0); 190252#L734-1 assume !(0 == ~E_4~0); 190803#L739-1 assume !(0 == ~E_5~0); 190454#L744-1 assume !(0 == ~E_6~0); 190455#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 190207#L334 assume !(1 == ~m_pc~0); 190208#L334-2 is_master_triggered_~__retres1~0#1 := 0; 190555#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 190457#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 190425#L849 assume !(0 != activate_threads_~tmp~1#1); 190426#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 190356#L353 assume !(1 == ~t1_pc~0); 190357#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 190654#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 190222#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 190223#L857 assume !(0 != activate_threads_~tmp___0~0#1); 190303#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 190304#L372 assume !(1 == ~t2_pc~0); 190412#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 190411#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 190549#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 190655#L865 assume !(0 != activate_threads_~tmp___1~0#1); 190196#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 190197#L391 assume !(1 == ~t3_pc~0); 190120#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 190121#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 190146#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 190147#L873 assume !(0 != activate_threads_~tmp___2~0#1); 190432#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 190433#L410 assume !(1 == ~t4_pc~0); 190666#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 190667#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 190318#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 190319#L881 assume !(0 != activate_threads_~tmp___3~0#1); 190438#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 190439#L429 assume !(1 == ~t5_pc~0); 190257#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 190258#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 190468#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 190469#L889 assume !(0 != activate_threads_~tmp___4~0#1); 190672#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 190422#L448 assume !(1 == ~t6_pc~0); 190339#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 190340#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 190638#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 190639#L897 assume !(0 != activate_threads_~tmp___5~0#1); 190827#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 190875#L762 assume !(1 == ~M_E~0); 190476#L762-2 assume !(1 == ~T1_E~0); 190477#L767-1 assume !(1 == ~T2_E~0); 190833#L772-1 assume !(1 == ~T3_E~0); 190703#L777-1 assume !(1 == ~T4_E~0); 190594#L782-1 assume !(1 == ~T5_E~0); 190285#L787-1 assume !(1 == ~T6_E~0); 190283#L792-1 assume !(1 == ~E_M~0); 190284#L797-1 assume !(1 == ~E_1~0); 190323#L802-1 assume !(1 == ~E_2~0); 190559#L807-1 assume !(1 == ~E_3~0); 190560#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 190798#L817-1 assume !(1 == ~E_5~0); 190611#L822-1 assume !(1 == ~E_6~0); 190612#L827-1 assume { :end_inline_reset_delta_events } true; 190808#L1053-2 [2023-11-29 04:15:08,085 INFO L750 eck$LassoCheckResult]: Loop: 190808#L1053-2 assume !false; 202968#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 201631#L659-1 assume !false; 199509#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 199298#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 199246#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 199242#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 199239#L570 assume !(0 != eval_~tmp~0#1); 199237#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 199225#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 199218#L684-3 assume !(0 == ~M_E~0); 199208#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 199200#L689-3 assume !(0 == ~T2_E~0); 199198#L694-3 assume !(0 == ~T3_E~0); 199196#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 199193#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 199191#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 199189#L714-3 assume !(0 == ~E_M~0); 199187#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 199185#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 199183#L729-3 assume !(0 == ~E_3~0); 199173#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 199169#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 199165#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 199160#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199156#L334-24 assume 1 == ~m_pc~0; 199152#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 199147#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 199143#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 199139#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 199135#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 199131#L353-24 assume !(1 == ~t1_pc~0); 199127#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 199123#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 199117#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 199112#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 199107#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 199102#L372-24 assume 1 == ~t2_pc~0; 199098#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 199093#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 199088#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 199084#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 199080#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 199075#L391-24 assume !(1 == ~t3_pc~0); 199071#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 199067#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 199063#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 199059#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 199055#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 199050#L410-24 assume !(1 == ~t4_pc~0); 199046#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 199042#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 199038#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 199034#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 199030#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 199025#L429-24 assume !(1 == ~t5_pc~0); 199021#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 199017#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 199011#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 199005#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 199002#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 198999#L448-24 assume !(1 == ~t6_pc~0); 198997#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 198995#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 198993#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 198983#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 198979#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 198944#L762-3 assume !(1 == ~M_E~0); 195568#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 198938#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 198934#L772-3 assume !(1 == ~T3_E~0); 198930#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 198926#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 198922#L787-3 assume !(1 == ~T6_E~0); 198918#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 198913#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 198909#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 198906#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 198903#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 198899#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 198896#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 198894#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 198886#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 198639#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 198253#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 193750#L1072 assume !(0 == start_simulation_~tmp~3#1); 193751#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 203074#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 203067#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 203065#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 203063#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 203061#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 203059#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 203057#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 190808#L1053-2 [2023-11-29 04:15:08,086 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:08,086 INFO L85 PathProgramCache]: Analyzing trace with hash -895756277, now seen corresponding path program 1 times [2023-11-29 04:15:08,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:08,086 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764929663] [2023-11-29 04:15:08,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:08,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:08,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:08,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:08,144 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:08,145 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764929663] [2023-11-29 04:15:08,145 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764929663] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:08,145 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:08,145 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:08,145 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288222089] [2023-11-29 04:15:08,145 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:08,146 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:08,146 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:08,146 INFO L85 PathProgramCache]: Analyzing trace with hash 248786558, now seen corresponding path program 1 times [2023-11-29 04:15:08,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:08,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535000500] [2023-11-29 04:15:08,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:08,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:08,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:08,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:08,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:08,183 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535000500] [2023-11-29 04:15:08,184 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535000500] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:08,184 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:08,184 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:08,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533454662] [2023-11-29 04:15:08,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:08,184 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:08,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:08,185 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:15:08,185 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:15:08,185 INFO L87 Difference]: Start difference. First operand 15146 states and 21535 transitions. cyclomatic complexity: 6405 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:08,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:08,350 INFO L93 Difference]: Finished difference Result 23948 states and 33803 transitions. [2023-11-29 04:15:08,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23948 states and 33803 transitions. [2023-11-29 04:15:08,443 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23616 [2023-11-29 04:15:08,609 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23948 states to 23948 states and 33803 transitions. [2023-11-29 04:15:08,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23948 [2023-11-29 04:15:08,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23948 [2023-11-29 04:15:08,634 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23948 states and 33803 transitions. [2023-11-29 04:15:08,663 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:08,663 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23948 states and 33803 transitions. [2023-11-29 04:15:08,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23948 states and 33803 transitions. [2023-11-29 04:15:08,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23948 to 17289. [2023-11-29 04:15:08,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17289 states, 17289 states have (on average 1.4158135230493378) internal successors, (24478), 17288 states have internal predecessors, (24478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:08,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17289 states to 17289 states and 24478 transitions. [2023-11-29 04:15:08,934 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17289 states and 24478 transitions. [2023-11-29 04:15:08,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 04:15:08,935 INFO L428 stractBuchiCegarLoop]: Abstraction has 17289 states and 24478 transitions. [2023-11-29 04:15:08,935 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-29 04:15:08,935 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17289 states and 24478 transitions. [2023-11-29 04:15:08,982 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17024 [2023-11-29 04:15:08,982 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:08,983 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:08,984 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:08,984 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:08,984 INFO L748 eck$LassoCheckResult]: Stem: 229621#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 229622#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 229761#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 229762#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 229402#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 229403#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 229759#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 229760#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 229681#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 229460#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 229461#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 229382#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 229383#L684 assume !(0 == ~M_E~0); 229892#L684-2 assume !(0 == ~T1_E~0); 229715#L689-1 assume !(0 == ~T2_E~0); 229716#L694-1 assume !(0 == ~T3_E~0); 229713#L699-1 assume !(0 == ~T4_E~0); 229714#L704-1 assume !(0 == ~T5_E~0); 229666#L709-1 assume !(0 == ~T6_E~0); 229604#L714-1 assume !(0 == ~E_M~0); 229605#L719-1 assume !(0 == ~E_1~0); 229861#L724-1 assume !(0 == ~E_2~0); 229354#L729-1 assume !(0 == ~E_3~0); 229355#L734-1 assume 0 == ~E_4~0;~E_4~0 := 1; 229933#L739-1 assume !(0 == ~E_5~0); 229562#L744-1 assume !(0 == ~E_6~0); 229563#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 229310#L334 assume !(1 == ~m_pc~0); 229311#L334-2 is_master_triggered_~__retres1~0#1 := 0; 229658#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 229565#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 229566#L849 assume !(0 != activate_threads_~tmp~1#1); 230073#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 230072#L353 assume !(1 == ~t1_pc~0); 230071#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 229765#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 229325#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 229326#L857 assume !(0 != activate_threads_~tmp___0~0#1); 230069#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 229986#L372 assume !(1 == ~t2_pc~0); 229987#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 230068#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 229766#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 229767#L865 assume !(0 != activate_threads_~tmp___1~0#1); 229920#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 230066#L391 assume !(1 == ~t3_pc~0); 229224#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 229225#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 229249#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 229250#L873 assume !(0 != activate_threads_~tmp___2~0#1); 229854#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 230062#L410 assume !(1 == ~t4_pc~0); 229779#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 229780#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 229421#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 229422#L881 assume !(0 != activate_threads_~tmp___3~0#1); 229922#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 229705#L429 assume !(1 == ~t5_pc~0); 229706#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 230057#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 230055#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 230053#L889 assume !(0 != activate_threads_~tmp___4~0#1); 230052#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 229528#L448 assume !(1 == ~t6_pc~0); 229441#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 229442#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 229785#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 229960#L897 assume !(0 != activate_threads_~tmp___5~0#1); 229961#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 230026#L762 assume !(1 == ~M_E~0); 229583#L762-2 assume !(1 == ~T1_E~0); 229584#L767-1 assume !(1 == ~T2_E~0); 229969#L772-1 assume !(1 == ~T3_E~0); 229820#L777-1 assume !(1 == ~T4_E~0); 229821#L782-1 assume !(1 == ~T5_E~0); 229388#L787-1 assume !(1 == ~T6_E~0); 229389#L792-1 assume !(1 == ~E_M~0); 230047#L797-1 assume !(1 == ~E_1~0); 230046#L802-1 assume !(1 == ~E_2~0); 230045#L807-1 assume !(1 == ~E_3~0); 230044#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 229928#L817-1 assume !(1 == ~E_5~0); 229717#L822-1 assume !(1 == ~E_6~0); 229718#L827-1 assume { :end_inline_reset_delta_events } true; 229941#L1053-2 [2023-11-29 04:15:08,985 INFO L750 eck$LassoCheckResult]: Loop: 229941#L1053-2 assume !false; 233140#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 233131#L659-1 assume !false; 232617#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 232606#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 232599#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 232598#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 232589#L570 assume !(0 != eval_~tmp~0#1); 232587#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 232585#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 232582#L684-3 assume !(0 == ~M_E~0); 232580#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 232578#L689-3 assume !(0 == ~T2_E~0); 232576#L694-3 assume !(0 == ~T3_E~0); 232574#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 232572#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 232570#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 232568#L714-3 assume !(0 == ~E_M~0); 232557#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 232555#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 232554#L729-3 assume !(0 == ~E_3~0); 232551#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 232550#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 232549#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 232548#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 232547#L334-24 assume 1 == ~m_pc~0; 232546#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 232544#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 232543#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 232542#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 232541#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 232540#L353-24 assume !(1 == ~t1_pc~0); 232539#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 232538#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 232537#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 232536#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 232535#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 232534#L372-24 assume 1 == ~t2_pc~0; 232533#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 232531#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 232530#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 232529#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 232528#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 232527#L391-24 assume !(1 == ~t3_pc~0); 232526#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 232525#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 232524#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 232523#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 232522#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 232521#L410-24 assume !(1 == ~t4_pc~0); 232520#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 232519#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 232518#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 232517#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 232516#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 232515#L429-24 assume !(1 == ~t5_pc~0); 232514#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 232512#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 232510#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 232508#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 232506#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 232505#L448-24 assume !(1 == ~t6_pc~0); 232504#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 232503#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 232502#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 232501#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 232500#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 232499#L762-3 assume !(1 == ~M_E~0); 232102#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 232498#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 232497#L772-3 assume !(1 == ~T3_E~0); 232496#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 232495#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 232494#L787-3 assume !(1 == ~T6_E~0); 232493#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 232492#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 232491#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 232490#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 232488#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 232485#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 232482#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 232479#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 232472#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 232419#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 232417#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 232370#L1072 assume !(0 == start_simulation_~tmp~3#1); 232371#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 233177#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 233170#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 233168#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 233166#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 233164#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 233162#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 233160#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 229941#L1053-2 [2023-11-29 04:15:08,985 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:08,985 INFO L85 PathProgramCache]: Analyzing trace with hash 1437636361, now seen corresponding path program 1 times [2023-11-29 04:15:08,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:08,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867307854] [2023-11-29 04:15:08,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:08,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:08,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:09,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:09,033 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:09,033 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [867307854] [2023-11-29 04:15:09,033 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [867307854] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:09,033 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:09,033 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:09,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1310106655] [2023-11-29 04:15:09,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:09,034 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:09,034 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:09,034 INFO L85 PathProgramCache]: Analyzing trace with hash 248786558, now seen corresponding path program 2 times [2023-11-29 04:15:09,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:09,035 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683651297] [2023-11-29 04:15:09,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:09,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:09,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:09,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:09,072 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:09,072 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1683651297] [2023-11-29 04:15:09,072 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1683651297] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:09,072 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:09,072 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:09,072 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1362845989] [2023-11-29 04:15:09,073 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:09,073 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:09,073 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:09,073 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:15:09,073 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:15:09,074 INFO L87 Difference]: Start difference. First operand 17289 states and 24478 transitions. cyclomatic complexity: 7205 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:09,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:09,210 INFO L93 Difference]: Finished difference Result 21622 states and 30409 transitions. [2023-11-29 04:15:09,210 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21622 states and 30409 transitions. [2023-11-29 04:15:09,288 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21356 [2023-11-29 04:15:09,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21622 states to 21622 states and 30409 transitions. [2023-11-29 04:15:09,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21622 [2023-11-29 04:15:09,349 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21622 [2023-11-29 04:15:09,349 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21622 states and 30409 transitions. [2023-11-29 04:15:09,367 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:09,368 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21622 states and 30409 transitions. [2023-11-29 04:15:09,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21622 states and 30409 transitions. [2023-11-29 04:15:09,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21622 to 15146. [2023-11-29 04:15:09,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15146 states, 15146 states have (on average 1.4084906906113825) internal successors, (21333), 15145 states have internal predecessors, (21333), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:09,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15146 states to 15146 states and 21333 transitions. [2023-11-29 04:15:09,639 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15146 states and 21333 transitions. [2023-11-29 04:15:09,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 04:15:09,639 INFO L428 stractBuchiCegarLoop]: Abstraction has 15146 states and 21333 transitions. [2023-11-29 04:15:09,640 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-29 04:15:09,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15146 states and 21333 transitions. [2023-11-29 04:15:09,671 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14944 [2023-11-29 04:15:09,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:09,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:09,672 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:09,672 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:09,673 INFO L748 eck$LassoCheckResult]: Stem: 268543#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 268544#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 268682#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 268683#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 268324#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 268325#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 268678#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 268679#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 268604#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 268383#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 268384#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 268304#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 268305#L684 assume !(0 == ~M_E~0); 268797#L684-2 assume !(0 == ~T1_E~0); 268635#L689-1 assume !(0 == ~T2_E~0); 268636#L694-1 assume !(0 == ~T3_E~0); 268633#L699-1 assume !(0 == ~T4_E~0); 268634#L704-1 assume !(0 == ~T5_E~0); 268590#L709-1 assume !(0 == ~T6_E~0); 268522#L714-1 assume !(0 == ~E_M~0); 268523#L719-1 assume !(0 == ~E_1~0); 268763#L724-1 assume !(0 == ~E_2~0); 268275#L729-1 assume !(0 == ~E_3~0); 268276#L734-1 assume !(0 == ~E_4~0); 268832#L739-1 assume !(0 == ~E_5~0); 268483#L744-1 assume !(0 == ~E_6~0); 268484#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 268231#L334 assume !(1 == ~m_pc~0); 268232#L334-2 is_master_triggered_~__retres1~0#1 := 0; 268579#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 268486#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 268452#L849 assume !(0 != activate_threads_~tmp~1#1); 268453#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 268379#L353 assume !(1 == ~t1_pc~0); 268380#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 268684#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 268246#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 268247#L857 assume !(0 != activate_threads_~tmp___0~0#1); 268326#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 268327#L372 assume !(1 == ~t2_pc~0); 268439#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 268438#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 268572#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 268685#L865 assume !(0 != activate_threads_~tmp___1~0#1); 268220#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 268221#L391 assume !(1 == ~t3_pc~0); 268145#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 268146#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 268170#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 268171#L873 assume !(0 != activate_threads_~tmp___2~0#1); 268459#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 268460#L410 assume !(1 == ~t4_pc~0); 268697#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 268698#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 268340#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 268341#L881 assume !(0 != activate_threads_~tmp___3~0#1); 268468#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 268469#L429 assume !(1 == ~t5_pc~0); 268281#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 268282#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 268497#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 268498#L889 assume !(0 != activate_threads_~tmp___4~0#1); 268701#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 268451#L448 assume !(1 == ~t6_pc~0); 268362#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 268363#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 268669#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 268670#L897 assume !(0 != activate_threads_~tmp___5~0#1); 268856#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 268900#L762 assume !(1 == ~M_E~0); 268502#L762-2 assume !(1 == ~T1_E~0); 268503#L767-1 assume !(1 == ~T2_E~0); 268861#L772-1 assume !(1 == ~T3_E~0); 268731#L777-1 assume !(1 == ~T4_E~0); 268620#L782-1 assume !(1 == ~T5_E~0); 268308#L787-1 assume !(1 == ~T6_E~0); 268306#L792-1 assume !(1 == ~E_M~0); 268307#L797-1 assume !(1 == ~E_1~0); 268346#L802-1 assume !(1 == ~E_2~0); 268583#L807-1 assume !(1 == ~E_3~0); 268584#L812-1 assume !(1 == ~E_4~0); 268829#L817-1 assume !(1 == ~E_5~0); 268637#L822-1 assume !(1 == ~E_6~0); 268638#L827-1 assume { :end_inline_reset_delta_events } true; 268836#L1053-2 [2023-11-29 04:15:09,673 INFO L750 eck$LassoCheckResult]: Loop: 268836#L1053-2 assume !false; 273034#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 273029#L659-1 assume !false; 273025#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 273022#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 273015#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 273013#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 273010#L570 assume !(0 != eval_~tmp~0#1); 273008#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 273006#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 273004#L684-3 assume !(0 == ~M_E~0); 273002#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 273000#L689-3 assume !(0 == ~T2_E~0); 272998#L694-3 assume !(0 == ~T3_E~0); 272996#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 272994#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 272992#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 272990#L714-3 assume !(0 == ~E_M~0); 272988#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 272986#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 272984#L729-3 assume !(0 == ~E_3~0); 272981#L734-3 assume !(0 == ~E_4~0); 272979#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 272977#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 272975#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 272973#L334-24 assume !(1 == ~m_pc~0); 272970#L334-26 is_master_triggered_~__retres1~0#1 := 0; 272967#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 272965#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 272963#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 272961#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 272959#L353-24 assume !(1 == ~t1_pc~0); 272957#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 272954#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 272952#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 272950#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 272948#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 272946#L372-24 assume 1 == ~t2_pc~0; 272944#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 272941#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 272939#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 272937#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 272935#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 272933#L391-24 assume !(1 == ~t3_pc~0); 272931#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 272929#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 272927#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 272925#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 272923#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 272921#L410-24 assume !(1 == ~t4_pc~0); 272917#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 272915#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 272913#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 272911#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 272908#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 272906#L429-24 assume !(1 == ~t5_pc~0); 272902#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 272900#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 272898#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 272896#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 272893#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 272891#L448-24 assume !(1 == ~t6_pc~0); 272889#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 272888#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 272886#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 272884#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 272882#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 272880#L762-3 assume !(1 == ~M_E~0); 270727#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 272877#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 272875#L772-3 assume !(1 == ~T3_E~0); 272873#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 272871#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 272869#L787-3 assume !(1 == ~T6_E~0); 272867#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 272865#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 272863#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 272862#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 272861#L812-3 assume !(1 == ~E_4~0); 272860#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 272859#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 272858#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 272853#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 272843#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 272841#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 270805#L1072 assume !(0 == start_simulation_~tmp~3#1); 270806#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 273055#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 273048#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 273047#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 273046#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 273045#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 273044#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 273043#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 268836#L1053-2 [2023-11-29 04:15:09,674 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:09,674 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2023-11-29 04:15:09,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:09,674 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [361833923] [2023-11-29 04:15:09,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:09,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:09,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:09,686 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:09,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:09,737 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:09,738 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:09,738 INFO L85 PathProgramCache]: Analyzing trace with hash -1545695489, now seen corresponding path program 1 times [2023-11-29 04:15:09,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:09,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [384643308] [2023-11-29 04:15:09,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:09,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:09,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:09,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:09,776 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:09,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [384643308] [2023-11-29 04:15:09,776 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [384643308] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:09,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:09,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:09,777 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1929387257] [2023-11-29 04:15:09,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:09,777 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:09,777 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:09,777 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:09,777 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:09,778 INFO L87 Difference]: Start difference. First operand 15146 states and 21333 transitions. cyclomatic complexity: 6203 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:09,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:09,846 INFO L93 Difference]: Finished difference Result 17289 states and 24330 transitions. [2023-11-29 04:15:09,846 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17289 states and 24330 transitions. [2023-11-29 04:15:09,911 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17024 [2023-11-29 04:15:09,943 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17289 states to 17289 states and 24330 transitions. [2023-11-29 04:15:09,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17289 [2023-11-29 04:15:09,951 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17289 [2023-11-29 04:15:09,951 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17289 states and 24330 transitions. [2023-11-29 04:15:09,957 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:09,957 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17289 states and 24330 transitions. [2023-11-29 04:15:09,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17289 states and 24330 transitions. [2023-11-29 04:15:10,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17289 to 17289. [2023-11-29 04:15:10,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17289 states, 17289 states have (on average 1.407253166753427) internal successors, (24330), 17288 states have internal predecessors, (24330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:10,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17289 states to 17289 states and 24330 transitions. [2023-11-29 04:15:10,132 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17289 states and 24330 transitions. [2023-11-29 04:15:10,133 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:10,133 INFO L428 stractBuchiCegarLoop]: Abstraction has 17289 states and 24330 transitions. [2023-11-29 04:15:10,133 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-29 04:15:10,133 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17289 states and 24330 transitions. [2023-11-29 04:15:10,177 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17024 [2023-11-29 04:15:10,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:10,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:10,179 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:10,179 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:10,179 INFO L748 eck$LassoCheckResult]: Stem: 300978#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 300979#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 301118#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 301119#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 300767#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 300768#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 301114#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 301115#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 301038#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 300823#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 300824#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 300747#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 300748#L684 assume !(0 == ~M_E~0); 301247#L684-2 assume !(0 == ~T1_E~0); 301071#L689-1 assume !(0 == ~T2_E~0); 301072#L694-1 assume !(0 == ~T3_E~0); 301069#L699-1 assume !(0 == ~T4_E~0); 301070#L704-1 assume !(0 == ~T5_E~0); 301023#L709-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 300955#L714-1 assume !(0 == ~E_M~0); 300956#L719-1 assume !(0 == ~E_1~0); 301215#L724-1 assume !(0 == ~E_2~0); 300719#L729-1 assume !(0 == ~E_3~0); 300720#L734-1 assume !(0 == ~E_4~0); 301423#L739-1 assume !(0 == ~E_5~0); 301422#L744-1 assume !(0 == ~E_6~0); 301421#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 300674#L334 assume !(1 == ~m_pc~0); 300675#L334-2 is_master_triggered_~__retres1~0#1 := 0; 301012#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 300917#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 300918#L849 assume !(0 != activate_threads_~tmp~1#1); 301416#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 301415#L353 assume !(1 == ~t1_pc~0); 301414#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 301122#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 300689#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 300690#L857 assume !(0 != activate_threads_~tmp___0~0#1); 301412#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 301332#L372 assume !(1 == ~t2_pc~0); 301333#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 301411#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 301123#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 301124#L865 assume !(0 != activate_threads_~tmp___1~0#1); 301274#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 301409#L391 assume !(1 == ~t3_pc~0); 301408#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 301407#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 301406#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 301405#L873 assume !(0 != activate_threads_~tmp___2~0#1); 300893#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 300894#L410 assume !(1 == ~t4_pc~0); 301272#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 301403#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 301402#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 301401#L881 assume !(0 != activate_threads_~tmp___3~0#1); 301400#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 301061#L429 assume !(1 == ~t5_pc~0); 301062#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 301398#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 301396#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 301394#L889 assume !(0 != activate_threads_~tmp___4~0#1); 301393#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 300885#L448 assume !(1 == ~t6_pc~0); 300802#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 300803#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 301142#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 301390#L897 assume !(0 != activate_threads_~tmp___5~0#1); 301369#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 301365#L762 assume !(1 == ~M_E~0); 300936#L762-2 assume !(1 == ~T1_E~0); 300937#L767-1 assume !(1 == ~T2_E~0); 301320#L772-1 assume !(1 == ~T3_E~0); 301174#L777-1 assume !(1 == ~T4_E~0); 301053#L782-1 assume !(1 == ~T5_E~0); 300751#L787-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 300749#L792-1 assume !(1 == ~E_M~0); 300750#L797-1 assume !(1 == ~E_1~0); 300789#L802-1 assume !(1 == ~E_2~0); 301016#L807-1 assume !(1 == ~E_3~0); 301017#L812-1 assume !(1 == ~E_4~0); 301285#L817-1 assume !(1 == ~E_5~0); 301073#L822-1 assume !(1 == ~E_6~0); 301074#L827-1 assume { :end_inline_reset_delta_events } true; 301292#L1053-2 [2023-11-29 04:15:10,179 INFO L750 eck$LassoCheckResult]: Loop: 301292#L1053-2 assume !false; 313471#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 311371#L659-1 assume !false; 313469#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 307538#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 307532#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 307530#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 307528#L570 assume !(0 != eval_~tmp~0#1); 307529#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 315254#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 315249#L684-3 assume !(0 == ~M_E~0); 315244#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 315239#L689-3 assume !(0 == ~T2_E~0); 315232#L694-3 assume !(0 == ~T3_E~0); 315225#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 315218#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 315210#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 315205#L714-3 assume !(0 == ~E_M~0); 315198#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 315193#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 315187#L729-3 assume !(0 == ~E_3~0); 315181#L734-3 assume !(0 == ~E_4~0); 315175#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 315169#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 315160#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 315155#L334-24 assume !(1 == ~m_pc~0); 315149#L334-26 is_master_triggered_~__retres1~0#1 := 0; 315147#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 315145#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 315143#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 315138#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 315134#L353-24 assume !(1 == ~t1_pc~0); 315129#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 315124#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 315119#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 315114#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 315109#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 315104#L372-24 assume !(1 == ~t2_pc~0); 315073#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 315071#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 315069#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 315067#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 315065#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 315063#L391-24 assume !(1 == ~t3_pc~0); 315061#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 315059#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 315057#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 315055#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 315053#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 315042#L410-24 assume !(1 == ~t4_pc~0); 315034#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 315026#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 315018#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 315012#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 315006#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 314997#L429-24 assume 1 == ~t5_pc~0; 314990#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 314983#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 314976#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 314968#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 314962#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 314958#L448-24 assume !(1 == ~t6_pc~0); 314952#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 314946#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 314940#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 314934#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 314928#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 314921#L762-3 assume !(1 == ~M_E~0); 314874#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 314908#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 314901#L772-3 assume !(1 == ~T3_E~0); 314895#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 314890#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 314884#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 314881#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 314879#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 314877#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 314875#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 314872#L812-3 assume !(1 == ~E_4~0); 314870#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 314868#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 314866#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 314856#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 314851#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 314849#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 314846#L1072 assume !(0 == start_simulation_~tmp~3#1); 314847#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 313492#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 313484#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 313482#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 313480#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 313478#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 313476#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 313474#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 301292#L1053-2 [2023-11-29 04:15:10,180 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:10,180 INFO L85 PathProgramCache]: Analyzing trace with hash -843787639, now seen corresponding path program 1 times [2023-11-29 04:15:10,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:10,180 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [639551120] [2023-11-29 04:15:10,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:10,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:10,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:10,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:10,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:10,225 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [639551120] [2023-11-29 04:15:10,225 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [639551120] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:10,225 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:10,225 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:10,225 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86874447] [2023-11-29 04:15:10,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:10,226 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:10,226 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:10,226 INFO L85 PathProgramCache]: Analyzing trace with hash 72803899, now seen corresponding path program 1 times [2023-11-29 04:15:10,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:10,226 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053064724] [2023-11-29 04:15:10,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:10,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:10,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:10,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:10,283 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:10,283 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2053064724] [2023-11-29 04:15:10,283 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2053064724] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:10,283 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:10,284 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:15:10,284 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [385359823] [2023-11-29 04:15:10,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:10,284 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:10,285 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:10,285 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:15:10,285 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:15:10,285 INFO L87 Difference]: Start difference. First operand 17289 states and 24330 transitions. cyclomatic complexity: 7057 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:10,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:10,525 INFO L93 Difference]: Finished difference Result 22042 states and 30930 transitions. [2023-11-29 04:15:10,525 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22042 states and 30930 transitions. [2023-11-29 04:15:10,583 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21776 [2023-11-29 04:15:10,617 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22042 states to 22042 states and 30930 transitions. [2023-11-29 04:15:10,617 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22042 [2023-11-29 04:15:10,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22042 [2023-11-29 04:15:10,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22042 states and 30930 transitions. [2023-11-29 04:15:10,632 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:10,632 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22042 states and 30930 transitions. [2023-11-29 04:15:10,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22042 states and 30930 transitions. [2023-11-29 04:15:10,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22042 to 15146. [2023-11-29 04:15:10,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15146 states, 15146 states have (on average 1.4063118975307012) internal successors, (21300), 15145 states have internal predecessors, (21300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:10,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15146 states to 15146 states and 21300 transitions. [2023-11-29 04:15:10,800 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15146 states and 21300 transitions. [2023-11-29 04:15:10,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 04:15:10,801 INFO L428 stractBuchiCegarLoop]: Abstraction has 15146 states and 21300 transitions. [2023-11-29 04:15:10,801 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-29 04:15:10,801 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15146 states and 21300 transitions. [2023-11-29 04:15:10,842 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14944 [2023-11-29 04:15:10,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:10,843 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:10,844 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:10,844 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:10,844 INFO L748 eck$LassoCheckResult]: Stem: 340325#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 340326#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 340459#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 340460#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 340107#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 340108#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 340455#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 340456#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 340380#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 340166#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 340167#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 340087#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 340088#L684 assume !(0 == ~M_E~0); 340576#L684-2 assume !(0 == ~T1_E~0); 340413#L689-1 assume !(0 == ~T2_E~0); 340414#L694-1 assume !(0 == ~T3_E~0); 340411#L699-1 assume !(0 == ~T4_E~0); 340412#L704-1 assume !(0 == ~T5_E~0); 340367#L709-1 assume !(0 == ~T6_E~0); 340304#L714-1 assume !(0 == ~E_M~0); 340305#L719-1 assume !(0 == ~E_1~0); 340544#L724-1 assume !(0 == ~E_2~0); 340060#L729-1 assume !(0 == ~E_3~0); 340061#L734-1 assume !(0 == ~E_4~0); 340611#L739-1 assume !(0 == ~E_5~0); 340263#L744-1 assume !(0 == ~E_6~0); 340264#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 340016#L334 assume !(1 == ~m_pc~0); 340017#L334-2 is_master_triggered_~__retres1~0#1 := 0; 340356#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 340266#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 340232#L849 assume !(0 != activate_threads_~tmp~1#1); 340233#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 340162#L353 assume !(1 == ~t1_pc~0); 340163#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 340461#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 340031#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 340032#L857 assume !(0 != activate_threads_~tmp___0~0#1); 340109#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 340110#L372 assume !(1 == ~t2_pc~0); 340219#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 340218#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 340351#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 340462#L865 assume !(0 != activate_threads_~tmp___1~0#1); 340005#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 340006#L391 assume !(1 == ~t3_pc~0); 339929#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 339930#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 339954#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 339955#L873 assume !(0 != activate_threads_~tmp___2~0#1); 340239#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 340240#L410 assume !(1 == ~t4_pc~0); 340474#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 340475#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 340123#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 340124#L881 assume !(0 != activate_threads_~tmp___3~0#1); 340249#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 340250#L429 assume !(1 == ~t5_pc~0); 340066#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 340067#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 340276#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 340277#L889 assume !(0 != activate_threads_~tmp___4~0#1); 340478#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 340231#L448 assume !(1 == ~t6_pc~0); 340145#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 340146#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 340447#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 340448#L897 assume !(0 != activate_threads_~tmp___5~0#1); 340638#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 340677#L762 assume !(1 == ~M_E~0); 340285#L762-2 assume !(1 == ~T1_E~0); 340286#L767-1 assume !(1 == ~T2_E~0); 340643#L772-1 assume !(1 == ~T3_E~0); 340506#L777-1 assume !(1 == ~T4_E~0); 340396#L782-1 assume !(1 == ~T5_E~0); 340091#L787-1 assume !(1 == ~T6_E~0); 340089#L792-1 assume !(1 == ~E_M~0); 340090#L797-1 assume !(1 == ~E_1~0); 340129#L802-1 assume !(1 == ~E_2~0); 340360#L807-1 assume !(1 == ~E_3~0); 340361#L812-1 assume !(1 == ~E_4~0); 340608#L817-1 assume !(1 == ~E_5~0); 340417#L822-1 assume !(1 == ~E_6~0); 340418#L827-1 assume { :end_inline_reset_delta_events } true; 340617#L1053-2 [2023-11-29 04:15:10,845 INFO L750 eck$LassoCheckResult]: Loop: 340617#L1053-2 assume !false; 342242#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 342234#L659-1 assume !false; 342228#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 342109#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 342102#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 342100#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 342098#L570 assume !(0 != eval_~tmp~0#1); 342096#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 342094#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 342092#L684-3 assume !(0 == ~M_E~0); 342081#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 342071#L689-3 assume !(0 == ~T2_E~0); 342062#L694-3 assume !(0 == ~T3_E~0); 342022#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 342005#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 342000#L709-3 assume !(0 == ~T6_E~0); 341993#L714-3 assume !(0 == ~E_M~0); 341979#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 341971#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 341964#L729-3 assume !(0 == ~E_3~0); 341957#L734-3 assume !(0 == ~E_4~0); 341951#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 341946#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 341944#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 341942#L334-24 assume !(1 == ~m_pc~0); 341933#L334-26 is_master_triggered_~__retres1~0#1 := 0; 341931#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 341929#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 341926#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 341924#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 341922#L353-24 assume !(1 == ~t1_pc~0); 341920#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 341918#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 341916#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 341914#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 341912#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 341910#L372-24 assume 1 == ~t2_pc~0; 341908#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 341905#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 341903#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 341901#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 341899#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 341897#L391-24 assume !(1 == ~t3_pc~0); 341895#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 341893#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 341891#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 341889#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 341886#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 341884#L410-24 assume !(1 == ~t4_pc~0); 341882#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 341880#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 341878#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 341876#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 341874#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 341872#L429-24 assume 1 == ~t5_pc~0; 341869#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 341866#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 341863#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 341860#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 341857#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 341855#L448-24 assume !(1 == ~t6_pc~0); 341853#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 341851#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 341849#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 341847#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 341844#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 341842#L762-3 assume !(1 == ~M_E~0); 341578#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 341839#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 341837#L772-3 assume !(1 == ~T3_E~0); 341835#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 341833#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 341831#L787-3 assume !(1 == ~T6_E~0); 341829#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 341827#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 341825#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 341823#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 341820#L812-3 assume !(1 == ~E_4~0); 341817#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 341814#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 341811#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 341805#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 341799#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 341797#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 341764#L1072 assume !(0 == start_simulation_~tmp~3#1); 341765#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 342305#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 342295#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 342288#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 342281#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 342273#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 342267#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 342260#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 340617#L1053-2 [2023-11-29 04:15:10,845 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:10,845 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2023-11-29 04:15:10,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:10,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1314687364] [2023-11-29 04:15:10,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:10,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:10,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:10,857 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:10,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:10,887 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:10,888 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:10,888 INFO L85 PathProgramCache]: Analyzing trace with hash 1094272058, now seen corresponding path program 1 times [2023-11-29 04:15:10,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:10,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909398] [2023-11-29 04:15:10,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:10,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:10,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:10,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:10,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:10,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909398] [2023-11-29 04:15:10,941 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909398] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:10,942 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:10,942 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:15:10,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647367423] [2023-11-29 04:15:10,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:10,942 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:10,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:10,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:15:10,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:15:10,943 INFO L87 Difference]: Start difference. First operand 15146 states and 21300 transitions. cyclomatic complexity: 6170 Second operand has 5 states, 5 states have (on average 18.8) internal successors, (94), 5 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:11,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:11,130 INFO L93 Difference]: Finished difference Result 27322 states and 37916 transitions. [2023-11-29 04:15:11,130 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27322 states and 37916 transitions. [2023-11-29 04:15:11,214 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27008 [2023-11-29 04:15:11,266 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27322 states to 27322 states and 37916 transitions. [2023-11-29 04:15:11,266 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27322 [2023-11-29 04:15:11,278 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27322 [2023-11-29 04:15:11,278 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27322 states and 37916 transitions. [2023-11-29 04:15:11,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:11,289 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27322 states and 37916 transitions. [2023-11-29 04:15:11,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27322 states and 37916 transitions. [2023-11-29 04:15:11,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27322 to 15242. [2023-11-29 04:15:11,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15242 states, 15242 states have (on average 1.403752788347986) internal successors, (21396), 15241 states have internal predecessors, (21396), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:11,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15242 states to 15242 states and 21396 transitions. [2023-11-29 04:15:11,528 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15242 states and 21396 transitions. [2023-11-29 04:15:11,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-29 04:15:11,529 INFO L428 stractBuchiCegarLoop]: Abstraction has 15242 states and 21396 transitions. [2023-11-29 04:15:11,529 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-29 04:15:11,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15242 states and 21396 transitions. [2023-11-29 04:15:11,559 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15040 [2023-11-29 04:15:11,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:11,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:11,560 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:11,560 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:11,560 INFO L748 eck$LassoCheckResult]: Stem: 382811#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 382812#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 382951#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 382952#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 382593#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 382594#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 382949#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 382950#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 382874#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 382653#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 382654#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 382574#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 382575#L684 assume !(0 == ~M_E~0); 383076#L684-2 assume !(0 == ~T1_E~0); 382907#L689-1 assume !(0 == ~T2_E~0); 382908#L694-1 assume !(0 == ~T3_E~0); 382905#L699-1 assume !(0 == ~T4_E~0); 382906#L704-1 assume !(0 == ~T5_E~0); 382858#L709-1 assume !(0 == ~T6_E~0); 382791#L714-1 assume !(0 == ~E_M~0); 382792#L719-1 assume !(0 == ~E_1~0); 383044#L724-1 assume !(0 == ~E_2~0); 382543#L729-1 assume !(0 == ~E_3~0); 382544#L734-1 assume !(0 == ~E_4~0); 383120#L739-1 assume !(0 == ~E_5~0); 382751#L744-1 assume !(0 == ~E_6~0); 382752#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 382500#L334 assume !(1 == ~m_pc~0); 382501#L334-2 is_master_triggered_~__retres1~0#1 := 0; 382850#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 382753#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 382718#L849 assume !(0 != activate_threads_~tmp~1#1); 382719#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 382651#L353 assume !(1 == ~t1_pc~0); 382652#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 382955#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 382515#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 382516#L857 assume !(0 != activate_threads_~tmp___0~0#1); 382598#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 382599#L372 assume !(1 == ~t2_pc~0); 382707#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 382706#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 382843#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 382956#L865 assume !(0 != activate_threads_~tmp___1~0#1); 382489#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 382490#L391 assume !(1 == ~t3_pc~0); 382414#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 382415#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 382439#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 382440#L873 assume !(0 != activate_threads_~tmp___2~0#1); 382725#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 382726#L410 assume !(1 == ~t4_pc~0); 382969#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 382970#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 382612#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 382613#L881 assume !(0 != activate_threads_~tmp___3~0#1); 382732#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 382733#L429 assume !(1 == ~t5_pc~0); 382549#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 382550#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 382764#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 382765#L889 assume !(0 != activate_threads_~tmp___4~0#1); 382975#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 382717#L448 assume !(1 == ~t6_pc~0); 382633#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 382634#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 382939#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 382940#L897 assume !(0 != activate_threads_~tmp___5~0#1); 383152#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 383206#L762 assume !(1 == ~M_E~0); 382771#L762-2 assume !(1 == ~T1_E~0); 382772#L767-1 assume !(1 == ~T2_E~0); 383158#L772-1 assume !(1 == ~T3_E~0); 383006#L777-1 assume !(1 == ~T4_E~0); 382890#L782-1 assume !(1 == ~T5_E~0); 382580#L787-1 assume !(1 == ~T6_E~0); 382578#L792-1 assume !(1 == ~E_M~0); 382579#L797-1 assume !(1 == ~E_1~0); 382617#L802-1 assume !(1 == ~E_2~0); 382854#L807-1 assume !(1 == ~E_3~0); 382855#L812-1 assume !(1 == ~E_4~0); 383114#L817-1 assume !(1 == ~E_5~0); 382909#L822-1 assume !(1 == ~E_6~0); 382910#L827-1 assume { :end_inline_reset_delta_events } true; 383128#L1053-2 [2023-11-29 04:15:11,561 INFO L750 eck$LassoCheckResult]: Loop: 383128#L1053-2 assume !false; 390019#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 389883#L659-1 assume !false; 390018#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 390014#L518 assume !(0 == ~m_st~0); 390015#L522 assume !(0 == ~t1_st~0); 390010#L526 assume !(0 == ~t2_st~0); 390011#L530 assume !(0 == ~t3_st~0); 390013#L534 assume !(0 == ~t4_st~0); 390008#L538 assume !(0 == ~t5_st~0); 390009#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 390012#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 386620#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 386621#L570 assume !(0 != eval_~tmp~0#1); 390195#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 390193#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 390191#L684-3 assume !(0 == ~M_E~0); 390189#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 390187#L689-3 assume !(0 == ~T2_E~0); 390185#L694-3 assume !(0 == ~T3_E~0); 390183#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 390181#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 390179#L709-3 assume !(0 == ~T6_E~0); 390177#L714-3 assume !(0 == ~E_M~0); 390175#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 390173#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 390171#L729-3 assume !(0 == ~E_3~0); 390169#L734-3 assume !(0 == ~E_4~0); 390167#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 390165#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 390163#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 390161#L334-24 assume 1 == ~m_pc~0; 390159#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 390155#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 390153#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 390151#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 390149#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 390147#L353-24 assume !(1 == ~t1_pc~0); 390145#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 390143#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 390141#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 390139#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 390137#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 390135#L372-24 assume 1 == ~t2_pc~0; 390133#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 390129#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 390127#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 390125#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 390123#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 390121#L391-24 assume !(1 == ~t3_pc~0); 390119#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 390117#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 390115#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 390113#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 390111#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 390109#L410-24 assume !(1 == ~t4_pc~0); 390107#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 390105#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 390103#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 390101#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 390099#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 390097#L429-24 assume !(1 == ~t5_pc~0); 390095#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 390091#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 390087#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 390083#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 390079#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 390077#L448-24 assume !(1 == ~t6_pc~0); 390075#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 390073#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 390071#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 390069#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 390067#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 390065#L762-3 assume !(1 == ~M_E~0); 390062#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 390061#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 390060#L772-3 assume !(1 == ~T3_E~0); 390059#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 390058#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 390057#L787-3 assume !(1 == ~T6_E~0); 390056#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 390055#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 390054#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 390053#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 390052#L812-3 assume !(1 == ~E_4~0); 390051#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 390050#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 390049#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 390045#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 390040#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 390038#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 390035#L1072 assume !(0 == start_simulation_~tmp~3#1); 390033#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 390031#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 390025#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 390024#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 390023#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 390022#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 390021#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 390020#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 383128#L1053-2 [2023-11-29 04:15:11,561 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:11,561 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2023-11-29 04:15:11,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:11,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583091128] [2023-11-29 04:15:11,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:11,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:11,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:11,573 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:11,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:11,599 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:11,599 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:11,599 INFO L85 PathProgramCache]: Analyzing trace with hash 182585611, now seen corresponding path program 1 times [2023-11-29 04:15:11,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:11,600 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [112273635] [2023-11-29 04:15:11,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:11,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:11,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:11,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:11,672 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:11,672 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [112273635] [2023-11-29 04:15:11,672 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [112273635] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:11,672 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:11,672 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:15:11,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [348536645] [2023-11-29 04:15:11,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:11,673 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:11,673 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:11,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:15:11,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:15:11,674 INFO L87 Difference]: Start difference. First operand 15242 states and 21396 transitions. cyclomatic complexity: 6170 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:11,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:11,927 INFO L93 Difference]: Finished difference Result 27186 states and 37523 transitions. [2023-11-29 04:15:11,927 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27186 states and 37523 transitions. [2023-11-29 04:15:12,004 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 26944 [2023-11-29 04:15:12,056 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27186 states to 27186 states and 37523 transitions. [2023-11-29 04:15:12,056 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27186 [2023-11-29 04:15:12,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27186 [2023-11-29 04:15:12,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27186 states and 37523 transitions. [2023-11-29 04:15:12,079 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:12,079 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27186 states and 37523 transitions. [2023-11-29 04:15:12,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27186 states and 37523 transitions. [2023-11-29 04:15:12,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27186 to 15578. [2023-11-29 04:15:12,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15578 states, 15578 states have (on average 1.3888175632301965) internal successors, (21635), 15577 states have internal predecessors, (21635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:12,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15578 states to 15578 states and 21635 transitions. [2023-11-29 04:15:12,217 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15578 states and 21635 transitions. [2023-11-29 04:15:12,218 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:15:12,218 INFO L428 stractBuchiCegarLoop]: Abstraction has 15578 states and 21635 transitions. [2023-11-29 04:15:12,218 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-29 04:15:12,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15578 states and 21635 transitions. [2023-11-29 04:15:12,248 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15376 [2023-11-29 04:15:12,249 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:12,249 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:12,250 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:12,250 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:12,250 INFO L748 eck$LassoCheckResult]: Stem: 425254#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 425255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 425392#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 425393#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 425031#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 425032#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 425390#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 425391#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 425315#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 425093#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 425094#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 425012#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 425013#L684 assume !(0 == ~M_E~0); 425520#L684-2 assume !(0 == ~T1_E~0); 425347#L689-1 assume !(0 == ~T2_E~0); 425348#L694-1 assume !(0 == ~T3_E~0); 425345#L699-1 assume !(0 == ~T4_E~0); 425346#L704-1 assume !(0 == ~T5_E~0); 425300#L709-1 assume !(0 == ~T6_E~0); 425236#L714-1 assume !(0 == ~E_M~0); 425237#L719-1 assume !(0 == ~E_1~0); 425487#L724-1 assume !(0 == ~E_2~0); 424985#L729-1 assume !(0 == ~E_3~0); 424986#L734-1 assume !(0 == ~E_4~0); 425561#L739-1 assume !(0 == ~E_5~0); 425192#L744-1 assume !(0 == ~E_6~0); 425193#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 424940#L334 assume !(1 == ~m_pc~0); 424941#L334-2 is_master_triggered_~__retres1~0#1 := 0; 425292#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 425194#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 425162#L849 assume !(0 != activate_threads_~tmp~1#1); 425163#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 425091#L353 assume !(1 == ~t1_pc~0); 425092#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 425396#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 424956#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 424957#L857 assume !(0 != activate_threads_~tmp___0~0#1); 425036#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 425037#L372 assume !(1 == ~t2_pc~0); 425150#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 425149#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 425286#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 425397#L865 assume !(0 != activate_threads_~tmp___1~0#1); 424929#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 424930#L391 assume !(1 == ~t3_pc~0); 424854#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 424855#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 424879#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 424880#L873 assume !(0 != activate_threads_~tmp___2~0#1); 425169#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 425170#L410 assume !(1 == ~t4_pc~0); 425411#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 425412#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 425051#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 425052#L881 assume !(0 != activate_threads_~tmp___3~0#1); 425175#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 425176#L429 assume !(1 == ~t5_pc~0); 424991#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 424992#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 425206#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 425207#L889 assume !(0 != activate_threads_~tmp___4~0#1); 425418#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 425160#L448 assume !(1 == ~t6_pc~0); 425073#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 425074#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 425380#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 425381#L897 assume !(0 != activate_threads_~tmp___5~0#1); 425586#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 425639#L762 assume !(1 == ~M_E~0); 425214#L762-2 assume !(1 == ~T1_E~0); 425215#L767-1 assume !(1 == ~T2_E~0); 425592#L772-1 assume !(1 == ~T3_E~0); 425449#L777-1 assume !(1 == ~T4_E~0); 425332#L782-1 assume !(1 == ~T5_E~0); 425018#L787-1 assume !(1 == ~T6_E~0); 425016#L792-1 assume !(1 == ~E_M~0); 425017#L797-1 assume !(1 == ~E_1~0); 425056#L802-1 assume !(1 == ~E_2~0); 425296#L807-1 assume !(1 == ~E_3~0); 425297#L812-1 assume !(1 == ~E_4~0); 425556#L817-1 assume !(1 == ~E_5~0); 425349#L822-1 assume !(1 == ~E_6~0); 425350#L827-1 assume { :end_inline_reset_delta_events } true; 425565#L1053-2 [2023-11-29 04:15:12,250 INFO L750 eck$LassoCheckResult]: Loop: 425565#L1053-2 assume !false; 431861#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 430586#L659-1 assume !false; 431860#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 431858#L518 assume !(0 == ~m_st~0); 431859#L522 assume !(0 == ~t1_st~0); 431855#L526 assume !(0 == ~t2_st~0); 431856#L530 assume !(0 == ~t3_st~0); 431857#L534 assume !(0 == ~t4_st~0); 431853#L538 assume !(0 == ~t5_st~0); 431854#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 431852#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 431260#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 431261#L570 assume !(0 != eval_~tmp~0#1); 431851#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 431850#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 431849#L684-3 assume !(0 == ~M_E~0); 431848#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 431847#L689-3 assume !(0 == ~T2_E~0); 431846#L694-3 assume !(0 == ~T3_E~0); 431845#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 431844#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 431843#L709-3 assume !(0 == ~T6_E~0); 431842#L714-3 assume !(0 == ~E_M~0); 431841#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 431840#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 431839#L729-3 assume !(0 == ~E_3~0); 431838#L734-3 assume !(0 == ~E_4~0); 431837#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 431836#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 431835#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 431834#L334-24 assume !(1 == ~m_pc~0); 431832#L334-26 is_master_triggered_~__retres1~0#1 := 0; 431831#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 431830#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 431829#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 431828#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 431827#L353-24 assume !(1 == ~t1_pc~0); 431826#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 431825#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 431824#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 431823#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 431822#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 431821#L372-24 assume 1 == ~t2_pc~0; 431820#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 431818#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 431817#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 431816#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 431815#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 431814#L391-24 assume !(1 == ~t3_pc~0); 431813#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 431812#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 431811#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 431810#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 431809#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 431808#L410-24 assume !(1 == ~t4_pc~0); 431807#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 431806#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 431805#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 431804#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 431803#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 431802#L429-24 assume 1 == ~t5_pc~0; 431800#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 431798#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 431796#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 431794#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 431793#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 431792#L448-24 assume !(1 == ~t6_pc~0); 431791#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 431790#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 431789#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 431788#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 431786#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 431784#L762-3 assume !(1 == ~M_E~0); 431652#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 431781#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 431779#L772-3 assume !(1 == ~T3_E~0); 431777#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 431775#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 431773#L787-3 assume !(1 == ~T6_E~0); 431771#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 431769#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 431767#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 431765#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 431763#L812-3 assume !(1 == ~E_4~0); 431761#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 431759#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 431757#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 431751#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 431747#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 431744#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 431741#L1072 assume !(0 == start_simulation_~tmp~3#1); 431742#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 431873#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 431867#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 431866#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 431865#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 431864#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 431863#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 431862#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 425565#L1053-2 [2023-11-29 04:15:12,251 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:12,251 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2023-11-29 04:15:12,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:12,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1577454152] [2023-11-29 04:15:12,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:12,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:12,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:12,264 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:12,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:12,289 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:12,289 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:12,289 INFO L85 PathProgramCache]: Analyzing trace with hash -613119157, now seen corresponding path program 1 times [2023-11-29 04:15:12,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:12,290 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022767077] [2023-11-29 04:15:12,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:12,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:12,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:12,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:12,360 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:12,360 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2022767077] [2023-11-29 04:15:12,361 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2022767077] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:12,361 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:12,361 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:15:12,361 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402689385] [2023-11-29 04:15:12,361 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:12,361 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:12,361 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:12,362 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:15:12,362 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:15:12,362 INFO L87 Difference]: Start difference. First operand 15578 states and 21635 transitions. cyclomatic complexity: 6073 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:12,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:12,620 INFO L93 Difference]: Finished difference Result 40064 states and 54326 transitions. [2023-11-29 04:15:12,620 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40064 states and 54326 transitions. [2023-11-29 04:15:12,761 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 39648 [2023-11-29 04:15:12,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40064 states to 40064 states and 54326 transitions. [2023-11-29 04:15:12,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40064 [2023-11-29 04:15:12,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40064 [2023-11-29 04:15:12,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40064 states and 54326 transitions. [2023-11-29 04:15:12,892 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:12,892 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40064 states and 54326 transitions. [2023-11-29 04:15:12,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40064 states and 54326 transitions. [2023-11-29 04:15:13,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40064 to 16205. [2023-11-29 04:15:13,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16205 states, 16205 states have (on average 1.3737735266892934) internal successors, (22262), 16204 states have internal predecessors, (22262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:13,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16205 states to 16205 states and 22262 transitions. [2023-11-29 04:15:13,130 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16205 states and 22262 transitions. [2023-11-29 04:15:13,131 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:15:13,131 INFO L428 stractBuchiCegarLoop]: Abstraction has 16205 states and 22262 transitions. [2023-11-29 04:15:13,131 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-29 04:15:13,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16205 states and 22262 transitions. [2023-11-29 04:15:13,176 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16000 [2023-11-29 04:15:13,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:13,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:13,177 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:13,177 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:13,178 INFO L748 eck$LassoCheckResult]: Stem: 480916#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 480917#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 481059#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 481060#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 480689#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 480690#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 481055#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 481056#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 480977#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 480750#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 480751#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 480669#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 480670#L684 assume !(0 == ~M_E~0); 481189#L684-2 assume !(0 == ~T1_E~0); 481008#L689-1 assume !(0 == ~T2_E~0); 481009#L694-1 assume !(0 == ~T3_E~0); 481006#L699-1 assume !(0 == ~T4_E~0); 481007#L704-1 assume !(0 == ~T5_E~0); 480964#L709-1 assume !(0 == ~T6_E~0); 480893#L714-1 assume !(0 == ~E_M~0); 480894#L719-1 assume !(0 == ~E_1~0); 481154#L724-1 assume !(0 == ~E_2~0); 480641#L729-1 assume !(0 == ~E_3~0); 480642#L734-1 assume !(0 == ~E_4~0); 481223#L739-1 assume !(0 == ~E_5~0); 480851#L744-1 assume !(0 == ~E_6~0); 480852#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 480596#L334 assume !(1 == ~m_pc~0); 480597#L334-2 is_master_triggered_~__retres1~0#1 := 0; 480953#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 481230#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 480820#L849 assume !(0 != activate_threads_~tmp~1#1); 480821#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 480746#L353 assume !(1 == ~t1_pc~0); 480747#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 481062#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 480611#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 480612#L857 assume !(0 != activate_threads_~tmp___0~0#1); 480691#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 480692#L372 assume !(1 == ~t2_pc~0); 480808#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 480807#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 480947#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 481063#L865 assume !(0 != activate_threads_~tmp___1~0#1); 480585#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 480586#L391 assume !(1 == ~t3_pc~0); 480508#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 480509#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 480534#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 480535#L873 assume !(0 != activate_threads_~tmp___2~0#1); 480827#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 480828#L410 assume !(1 == ~t4_pc~0); 481078#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 481079#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 480708#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 480709#L881 assume !(0 != activate_threads_~tmp___3~0#1); 480837#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 480838#L429 assume !(1 == ~t5_pc~0); 480647#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 480648#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 480865#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 480866#L889 assume !(0 != activate_threads_~tmp___4~0#1); 481084#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 480819#L448 assume !(1 == ~t6_pc~0); 480728#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 480729#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 481046#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 481047#L897 assume !(0 != activate_threads_~tmp___5~0#1); 481257#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 481318#L762 assume !(1 == ~M_E~0); 480874#L762-2 assume !(1 == ~T1_E~0); 480875#L767-1 assume !(1 == ~T2_E~0); 481264#L772-1 assume !(1 == ~T3_E~0); 481121#L777-1 assume !(1 == ~T4_E~0); 480993#L782-1 assume !(1 == ~T5_E~0); 480673#L787-1 assume !(1 == ~T6_E~0); 480671#L792-1 assume !(1 == ~E_M~0); 480672#L797-1 assume !(1 == ~E_1~0); 480715#L802-1 assume !(1 == ~E_2~0); 480957#L807-1 assume !(1 == ~E_3~0); 480958#L812-1 assume !(1 == ~E_4~0); 481220#L817-1 assume !(1 == ~E_5~0); 481012#L822-1 assume !(1 == ~E_6~0); 481013#L827-1 assume { :end_inline_reset_delta_events } true; 481229#L1053-2 [2023-11-29 04:15:13,178 INFO L750 eck$LassoCheckResult]: Loop: 481229#L1053-2 assume !false; 488172#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 488166#L659-1 assume !false; 488159#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 488154#L518 assume !(0 == ~m_st~0); 488155#L522 assume !(0 == ~t1_st~0); 488151#L526 assume !(0 == ~t2_st~0); 488152#L530 assume !(0 == ~t3_st~0); 488153#L534 assume !(0 == ~t4_st~0); 488150#L538 assume !(0 == ~t5_st~0); 488149#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 488145#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 487609#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 487610#L570 assume !(0 != eval_~tmp~0#1); 488112#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 488111#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 488110#L684-3 assume !(0 == ~M_E~0); 488109#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 488108#L689-3 assume !(0 == ~T2_E~0); 488107#L694-3 assume !(0 == ~T3_E~0); 488106#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 488105#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 488104#L709-3 assume !(0 == ~T6_E~0); 488103#L714-3 assume !(0 == ~E_M~0); 488102#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 488101#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 488100#L729-3 assume !(0 == ~E_3~0); 488099#L734-3 assume !(0 == ~E_4~0); 488098#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 488097#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 488096#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 488095#L334-24 assume !(1 == ~m_pc~0); 488094#L334-26 is_master_triggered_~__retres1~0#1 := 0; 488092#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 488090#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 488088#L849-24 assume !(0 != activate_threads_~tmp~1#1); 488082#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 488077#L353-24 assume !(1 == ~t1_pc~0); 488039#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 488034#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 488029#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 488024#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 488019#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 488002#L372-24 assume 1 == ~t2_pc~0; 487993#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 487986#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 487979#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 487973#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 487967#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 487961#L391-24 assume !(1 == ~t3_pc~0); 487955#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 487948#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 487942#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 487936#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 487930#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 487921#L410-24 assume !(1 == ~t4_pc~0); 487915#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 487908#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 487902#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 487896#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 487838#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 487834#L429-24 assume 1 == ~t5_pc~0; 487831#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 487829#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 487827#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 487808#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 487801#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 487795#L448-24 assume !(1 == ~t6_pc~0); 487789#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 486428#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 486418#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 486416#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 486388#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 486387#L762-3 assume !(1 == ~M_E~0); 486109#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 486386#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 486385#L772-3 assume !(1 == ~T3_E~0); 486384#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 486383#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 486382#L787-3 assume !(1 == ~T6_E~0); 486381#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 486380#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 486379#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 486378#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 486377#L812-3 assume !(1 == ~E_4~0); 486376#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 486375#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 486374#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 486369#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 486366#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 486365#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 486363#L1072 assume !(0 == start_simulation_~tmp~3#1); 486364#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 488203#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 488196#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 488194#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 488191#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 488186#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 488183#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 488180#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 481229#L1053-2 [2023-11-29 04:15:13,179 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:13,179 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 5 times [2023-11-29 04:15:13,179 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:13,179 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738655743] [2023-11-29 04:15:13,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:13,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:13,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:13,190 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:13,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:13,211 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:13,212 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:13,212 INFO L85 PathProgramCache]: Analyzing trace with hash 1995668301, now seen corresponding path program 1 times [2023-11-29 04:15:13,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:13,212 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312114606] [2023-11-29 04:15:13,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:13,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:13,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:13,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:13,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:13,248 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312114606] [2023-11-29 04:15:13,248 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1312114606] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:13,248 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:13,248 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:13,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302484583] [2023-11-29 04:15:13,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:13,249 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:13,249 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:13,249 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:13,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:13,250 INFO L87 Difference]: Start difference. First operand 16205 states and 22262 transitions. cyclomatic complexity: 6073 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:13,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:13,381 INFO L93 Difference]: Finished difference Result 30301 states and 41054 transitions. [2023-11-29 04:15:13,381 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30301 states and 41054 transitions. [2023-11-29 04:15:13,488 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29984 [2023-11-29 04:15:13,558 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30301 states to 30301 states and 41054 transitions. [2023-11-29 04:15:13,558 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30301 [2023-11-29 04:15:13,573 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30301 [2023-11-29 04:15:13,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30301 states and 41054 transitions. [2023-11-29 04:15:13,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:13,587 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30301 states and 41054 transitions. [2023-11-29 04:15:13,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30301 states and 41054 transitions. [2023-11-29 04:15:13,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30301 to 28813. [2023-11-29 04:15:13,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28813 states, 28813 states have (on average 1.358761670079478) internal successors, (39150), 28812 states have internal predecessors, (39150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:13,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28813 states to 28813 states and 39150 transitions. [2023-11-29 04:15:13,878 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28813 states and 39150 transitions. [2023-11-29 04:15:13,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:13,879 INFO L428 stractBuchiCegarLoop]: Abstraction has 28813 states and 39150 transitions. [2023-11-29 04:15:13,879 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-29 04:15:13,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28813 states and 39150 transitions. [2023-11-29 04:15:14,062 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28496 [2023-11-29 04:15:14,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:14,063 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:14,064 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:14,064 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:14,064 INFO L748 eck$LassoCheckResult]: Stem: 527422#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 527423#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 527565#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 527566#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 527198#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 527199#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 527561#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 527562#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 527485#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 527260#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 527261#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 527181#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 527182#L684 assume !(0 == ~M_E~0); 527704#L684-2 assume !(0 == ~T1_E~0); 527517#L689-1 assume !(0 == ~T2_E~0); 527518#L694-1 assume !(0 == ~T3_E~0); 527515#L699-1 assume !(0 == ~T4_E~0); 527516#L704-1 assume !(0 == ~T5_E~0); 527467#L709-1 assume !(0 == ~T6_E~0); 527402#L714-1 assume !(0 == ~E_M~0); 527403#L719-1 assume !(0 == ~E_1~0); 527668#L724-1 assume !(0 == ~E_2~0); 527152#L729-1 assume !(0 == ~E_3~0); 527153#L734-1 assume !(0 == ~E_4~0); 527741#L739-1 assume !(0 == ~E_5~0); 527362#L744-1 assume !(0 == ~E_6~0); 527363#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 527107#L334 assume !(1 == ~m_pc~0); 527108#L334-2 is_master_triggered_~__retres1~0#1 := 0; 527458#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 527850#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 527331#L849 assume !(0 != activate_threads_~tmp~1#1); 527332#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 527258#L353 assume !(1 == ~t1_pc~0); 527259#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 527568#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 527122#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 527123#L857 assume !(0 != activate_threads_~tmp___0~0#1); 527203#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 527204#L372 assume !(1 == ~t2_pc~0); 527318#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 527317#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 527453#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 527569#L865 assume !(0 != activate_threads_~tmp___1~0#1); 527096#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 527097#L391 assume !(1 == ~t3_pc~0); 527020#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 527021#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 527045#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 527046#L873 assume !(0 != activate_threads_~tmp___2~0#1); 527338#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 527339#L410 assume !(1 == ~t4_pc~0); 527583#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 527584#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 527219#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 527220#L881 assume !(0 != activate_threads_~tmp___3~0#1); 527344#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 527345#L429 assume !(1 == ~t5_pc~0); 527158#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 527159#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 527376#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 527377#L889 assume !(0 != activate_threads_~tmp___4~0#1); 527593#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 527328#L448 assume !(1 == ~t6_pc~0); 527241#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 527242#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 527552#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 527553#L897 assume !(0 != activate_threads_~tmp___5~0#1); 527769#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 527824#L762 assume !(1 == ~M_E~0); 527382#L762-2 assume !(1 == ~T1_E~0); 527383#L767-1 assume !(1 == ~T2_E~0); 527774#L772-1 assume !(1 == ~T3_E~0); 527629#L777-1 assume !(1 == ~T4_E~0); 527501#L782-1 assume !(1 == ~T5_E~0); 527185#L787-1 assume !(1 == ~T6_E~0); 527183#L792-1 assume !(1 == ~E_M~0); 527184#L797-1 assume !(1 == ~E_1~0); 527225#L802-1 assume !(1 == ~E_2~0); 527462#L807-1 assume !(1 == ~E_3~0); 527463#L812-1 assume !(1 == ~E_4~0); 527736#L817-1 assume !(1 == ~E_5~0); 527519#L822-1 assume !(1 == ~E_6~0); 527520#L827-1 assume { :end_inline_reset_delta_events } true; 527747#L1053-2 [2023-11-29 04:15:14,065 INFO L750 eck$LassoCheckResult]: Loop: 527747#L1053-2 assume !false; 530680#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 530675#L659-1 assume !false; 530672#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 530669#L518 assume !(0 == ~m_st~0); 530670#L522 assume !(0 == ~t1_st~0); 532376#L526 assume !(0 == ~t2_st~0); 532374#L530 assume !(0 == ~t3_st~0); 532371#L534 assume !(0 == ~t4_st~0); 532369#L538 assume !(0 == ~t5_st~0); 532366#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 532363#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 532361#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 532359#L570 assume !(0 != eval_~tmp~0#1); 532357#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 532355#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 532351#L684-3 assume !(0 == ~M_E~0); 532349#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 532347#L689-3 assume !(0 == ~T2_E~0); 532346#L694-3 assume !(0 == ~T3_E~0); 532343#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 532340#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 532338#L709-3 assume !(0 == ~T6_E~0); 532336#L714-3 assume !(0 == ~E_M~0); 532333#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 532331#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 532329#L729-3 assume !(0 == ~E_3~0); 532327#L734-3 assume !(0 == ~E_4~0); 532325#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 532323#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 532321#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 532319#L334-24 assume 1 == ~m_pc~0; 532316#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 532314#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 532312#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 532309#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 532307#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 532305#L353-24 assume !(1 == ~t1_pc~0); 532303#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 532301#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 532299#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 532297#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 532294#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 532292#L372-24 assume !(1 == ~t2_pc~0); 532289#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 532288#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 532287#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 532285#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 532283#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 532281#L391-24 assume !(1 == ~t3_pc~0); 532279#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 532277#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 532187#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 532177#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 532169#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 532159#L410-24 assume !(1 == ~t4_pc~0); 532148#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 532138#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 532129#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 532116#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 532105#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 532097#L429-24 assume 1 == ~t5_pc~0; 532093#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 532089#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 531942#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 531909#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 531889#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 531880#L448-24 assume !(1 == ~t6_pc~0); 531871#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 531862#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 531856#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 531850#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 531846#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 531839#L762-3 assume !(1 == ~M_E~0); 531829#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 531824#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 531818#L772-3 assume !(1 == ~T3_E~0); 530735#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 530731#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 530729#L787-3 assume !(1 == ~T6_E~0); 530727#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 530725#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 530722#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 530720#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 530718#L812-3 assume !(1 == ~E_4~0); 530715#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 530713#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 530711#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 530708#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 530706#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 530704#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 530701#L1072 assume !(0 == start_simulation_~tmp~3#1); 530698#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 530695#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 530693#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 530691#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 530689#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 530687#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 530685#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 530683#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 527747#L1053-2 [2023-11-29 04:15:14,065 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:14,065 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 6 times [2023-11-29 04:15:14,065 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:14,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820425492] [2023-11-29 04:15:14,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:14,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:14,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:14,079 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:14,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:14,098 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:14,098 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:14,098 INFO L85 PathProgramCache]: Analyzing trace with hash -1510480693, now seen corresponding path program 1 times [2023-11-29 04:15:14,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:14,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249125062] [2023-11-29 04:15:14,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:14,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:14,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:14,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:14,162 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:14,162 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249125062] [2023-11-29 04:15:14,162 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1249125062] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:14,162 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:14,163 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:15:14,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [513716501] [2023-11-29 04:15:14,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:14,163 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:14,163 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:14,164 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:15:14,164 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:15:14,164 INFO L87 Difference]: Start difference. First operand 28813 states and 39150 transitions. cyclomatic complexity: 10353 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:14,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:14,547 INFO L93 Difference]: Finished difference Result 68217 states and 91089 transitions. [2023-11-29 04:15:14,547 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68217 states and 91089 transitions. [2023-11-29 04:15:14,795 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 67600 [2023-11-29 04:15:14,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68217 states to 68217 states and 91089 transitions. [2023-11-29 04:15:14,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68217 [2023-11-29 04:15:14,983 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68217 [2023-11-29 04:15:14,983 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68217 states and 91089 transitions. [2023-11-29 04:15:15,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:15,017 INFO L218 hiAutomatonCegarLoop]: Abstraction has 68217 states and 91089 transitions. [2023-11-29 04:15:15,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68217 states and 91089 transitions. [2023-11-29 04:15:15,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68217 to 29968. [2023-11-29 04:15:15,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29968 states, 29968 states have (on average 1.3449345969033635) internal successors, (40305), 29967 states have internal predecessors, (40305), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:15,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29968 states to 29968 states and 40305 transitions. [2023-11-29 04:15:15,414 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29968 states and 40305 transitions. [2023-11-29 04:15:15,415 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:15:15,415 INFO L428 stractBuchiCegarLoop]: Abstraction has 29968 states and 40305 transitions. [2023-11-29 04:15:15,415 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-29 04:15:15,415 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29968 states and 40305 transitions. [2023-11-29 04:15:15,493 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29648 [2023-11-29 04:15:15,493 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:15,493 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:15,495 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:15,495 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:15,495 INFO L748 eck$LassoCheckResult]: Stem: 624466#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 624467#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 624614#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 624615#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 624244#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 624245#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 624612#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 624613#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 624533#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 624305#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 624306#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 624225#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 624226#L684 assume !(0 == ~M_E~0); 624752#L684-2 assume !(0 == ~T1_E~0); 624567#L689-1 assume !(0 == ~T2_E~0); 624568#L694-1 assume !(0 == ~T3_E~0); 624565#L699-1 assume !(0 == ~T4_E~0); 624566#L704-1 assume !(0 == ~T5_E~0); 624515#L709-1 assume !(0 == ~T6_E~0); 624448#L714-1 assume !(0 == ~E_M~0); 624449#L719-1 assume !(0 == ~E_1~0); 624708#L724-1 assume !(0 == ~E_2~0); 624195#L729-1 assume !(0 == ~E_3~0); 624196#L734-1 assume !(0 == ~E_4~0); 624792#L739-1 assume !(0 == ~E_5~0); 624405#L744-1 assume !(0 == ~E_6~0); 624406#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 624151#L334 assume !(1 == ~m_pc~0); 624152#L334-2 is_master_triggered_~__retres1~0#1 := 0; 624506#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 624408#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 624375#L849 assume !(0 != activate_threads_~tmp~1#1); 624376#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 624303#L353 assume !(1 == ~t1_pc~0); 624304#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 624618#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 624166#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 624167#L857 assume !(0 != activate_threads_~tmp___0~0#1); 624249#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 624250#L372 assume !(1 == ~t2_pc~0); 624362#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 624386#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 624501#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 624778#L865 assume !(0 != activate_threads_~tmp___1~0#1); 624139#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 624140#L391 assume !(1 == ~t3_pc~0); 624062#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 624063#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 624088#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 624089#L873 assume !(0 != activate_threads_~tmp___2~0#1); 624382#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 624383#L410 assume !(1 == ~t4_pc~0); 624633#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 624634#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 624266#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 624267#L881 assume !(0 != activate_threads_~tmp___3~0#1); 624388#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 624389#L429 assume !(1 == ~t5_pc~0); 624201#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 624202#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 624420#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 624421#L889 assume !(0 != activate_threads_~tmp___4~0#1); 624641#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 624372#L448 assume !(1 == ~t6_pc~0); 624285#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 624286#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 624600#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 624601#L897 assume !(0 != activate_threads_~tmp___5~0#1); 624824#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 624885#L762 assume !(1 == ~M_E~0); 624428#L762-2 assume !(1 == ~T1_E~0); 624429#L767-1 assume !(1 == ~T2_E~0); 624834#L772-1 assume !(1 == ~T3_E~0); 624674#L777-1 assume !(1 == ~T4_E~0); 624550#L782-1 assume !(1 == ~T5_E~0); 624231#L787-1 assume !(1 == ~T6_E~0); 624229#L792-1 assume !(1 == ~E_M~0); 624230#L797-1 assume !(1 == ~E_1~0); 624271#L802-1 assume !(1 == ~E_2~0); 624510#L807-1 assume !(1 == ~E_3~0); 624511#L812-1 assume !(1 == ~E_4~0); 624785#L817-1 assume !(1 == ~E_5~0); 624569#L822-1 assume !(1 == ~E_6~0); 624570#L827-1 assume { :end_inline_reset_delta_events } true; 624800#L1053-2 [2023-11-29 04:15:15,495 INFO L750 eck$LassoCheckResult]: Loop: 624800#L1053-2 assume !false; 631382#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 631376#L659-1 assume !false; 631373#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 631369#L518 assume !(0 == ~m_st~0); 631370#L522 assume !(0 == ~t1_st~0); 631621#L526 assume !(0 == ~t2_st~0); 631620#L530 assume !(0 == ~t3_st~0); 631619#L534 assume !(0 == ~t4_st~0); 631618#L538 assume !(0 == ~t5_st~0); 631616#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 631615#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 631614#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 631612#L570 assume !(0 != eval_~tmp~0#1); 631611#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 631610#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 631609#L684-3 assume !(0 == ~M_E~0); 631608#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 631607#L689-3 assume !(0 == ~T2_E~0); 631606#L694-3 assume !(0 == ~T3_E~0); 631605#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 631604#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 631603#L709-3 assume !(0 == ~T6_E~0); 631602#L714-3 assume !(0 == ~E_M~0); 631601#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 631600#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 631599#L729-3 assume !(0 == ~E_3~0); 631598#L734-3 assume !(0 == ~E_4~0); 631597#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 631596#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 631595#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 631594#L334-24 assume 1 == ~m_pc~0; 631592#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 631591#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 631590#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 631588#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 631587#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 631586#L353-24 assume !(1 == ~t1_pc~0); 631585#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 631584#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 631583#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 631582#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 631581#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 631580#L372-24 assume !(1 == ~t2_pc~0); 631579#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 631577#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 631575#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 631573#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 631570#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 631568#L391-24 assume !(1 == ~t3_pc~0); 631566#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 631564#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 631562#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 631560#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 631558#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 631556#L410-24 assume !(1 == ~t4_pc~0); 631554#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 631552#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 631549#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 631547#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 631545#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 631490#L429-24 assume !(1 == ~t5_pc~0); 631486#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 631484#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 631482#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 631480#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 631476#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 631474#L448-24 assume !(1 == ~t6_pc~0); 631472#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 631470#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 631468#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 631466#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 631464#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 631462#L762-3 assume !(1 == ~M_E~0); 631459#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 631458#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 631457#L772-3 assume !(1 == ~T3_E~0); 631455#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 631452#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 631450#L787-3 assume !(1 == ~T6_E~0); 631448#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 631446#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 631444#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 631442#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 631440#L812-3 assume !(1 == ~E_4~0); 631438#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 631436#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 631434#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 631431#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 631429#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 631427#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 631424#L1072 assume !(0 == start_simulation_~tmp~3#1); 631422#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 631420#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 631417#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 631413#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 631410#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 631405#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 631401#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 631395#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 624800#L1053-2 [2023-11-29 04:15:15,496 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:15,496 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 7 times [2023-11-29 04:15:15,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:15,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [391115022] [2023-11-29 04:15:15,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:15,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:15,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:15,505 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:15,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:15,523 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:15,523 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:15,524 INFO L85 PathProgramCache]: Analyzing trace with hash 1427453392, now seen corresponding path program 1 times [2023-11-29 04:15:15,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:15,524 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388283766] [2023-11-29 04:15:15,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:15,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:15,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:15,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:15,586 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:15,586 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1388283766] [2023-11-29 04:15:15,586 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1388283766] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:15,586 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:15,586 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:15:15,586 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86012281] [2023-11-29 04:15:15,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:15,587 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:15,587 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:15,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:15:15,587 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:15:15,588 INFO L87 Difference]: Start difference. First operand 29968 states and 40305 transitions. cyclomatic complexity: 10353 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:15,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:15,842 INFO L93 Difference]: Finished difference Result 35352 states and 47100 transitions. [2023-11-29 04:15:15,842 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35352 states and 47100 transitions. [2023-11-29 04:15:15,969 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 35000 [2023-11-29 04:15:16,049 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35352 states to 35352 states and 47100 transitions. [2023-11-29 04:15:16,049 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35352 [2023-11-29 04:15:16,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35352 [2023-11-29 04:15:16,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35352 states and 47100 transitions. [2023-11-29 04:15:16,085 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:16,085 INFO L218 hiAutomatonCegarLoop]: Abstraction has 35352 states and 47100 transitions. [2023-11-29 04:15:16,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35352 states and 47100 transitions. [2023-11-29 04:15:16,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35352 to 30016. [2023-11-29 04:15:16,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30016 states, 30016 states have (on average 1.3320895522388059) internal successors, (39984), 30015 states have internal predecessors, (39984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:16,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30016 states to 30016 states and 39984 transitions. [2023-11-29 04:15:16,411 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30016 states and 39984 transitions. [2023-11-29 04:15:16,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:15:16,412 INFO L428 stractBuchiCegarLoop]: Abstraction has 30016 states and 39984 transitions. [2023-11-29 04:15:16,412 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-29 04:15:16,412 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30016 states and 39984 transitions. [2023-11-29 04:15:16,491 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29696 [2023-11-29 04:15:16,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:16,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:16,492 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:16,492 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:16,493 INFO L748 eck$LassoCheckResult]: Stem: 689804#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 689805#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 689951#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 689952#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 689576#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 689577#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 689947#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 689948#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 689865#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 689634#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 689635#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 689556#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 689557#L684 assume !(0 == ~M_E~0); 690076#L684-2 assume !(0 == ~T1_E~0); 689897#L689-1 assume !(0 == ~T2_E~0); 689898#L694-1 assume !(0 == ~T3_E~0); 689895#L699-1 assume !(0 == ~T4_E~0); 689896#L704-1 assume !(0 == ~T5_E~0); 689851#L709-1 assume !(0 == ~T6_E~0); 689779#L714-1 assume !(0 == ~E_M~0); 689780#L719-1 assume !(0 == ~E_1~0); 690045#L724-1 assume !(0 == ~E_2~0); 689525#L729-1 assume !(0 == ~E_3~0); 689526#L734-1 assume !(0 == ~E_4~0); 690117#L739-1 assume !(0 == ~E_5~0); 689736#L744-1 assume !(0 == ~E_6~0); 689737#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 689480#L334 assume !(1 == ~m_pc~0); 689481#L334-2 is_master_triggered_~__retres1~0#1 := 0; 689839#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 690241#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 689704#L849 assume !(0 != activate_threads_~tmp~1#1); 689705#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 689630#L353 assume !(1 == ~t1_pc~0); 689631#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 689953#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 689496#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 689497#L857 assume !(0 != activate_threads_~tmp___0~0#1); 689578#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 689579#L372 assume !(1 == ~t2_pc~0); 689691#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 689716#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 689954#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 689955#L865 assume !(0 != activate_threads_~tmp___1~0#1); 689469#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 689470#L391 assume !(1 == ~t3_pc~0); 689394#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 689395#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 689419#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 689420#L873 assume !(0 != activate_threads_~tmp___2~0#1); 689711#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 689712#L410 assume !(1 == ~t4_pc~0); 689970#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 689971#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 689593#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 689594#L881 assume !(0 != activate_threads_~tmp___3~0#1); 689722#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 689723#L429 assume !(1 == ~t5_pc~0); 689531#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 689532#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 689753#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 689754#L889 assume !(0 != activate_threads_~tmp___4~0#1); 689976#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 689703#L448 assume !(1 == ~t6_pc~0); 689612#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 689613#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 689937#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 689938#L897 assume !(0 != activate_threads_~tmp___5~0#1); 690146#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 690216#L762 assume !(1 == ~M_E~0); 689760#L762-2 assume !(1 == ~T1_E~0); 689761#L767-1 assume !(1 == ~T2_E~0); 690156#L772-1 assume !(1 == ~T3_E~0); 690008#L777-1 assume !(1 == ~T4_E~0); 689880#L782-1 assume !(1 == ~T5_E~0); 689560#L787-1 assume !(1 == ~T6_E~0); 689558#L792-1 assume !(1 == ~E_M~0); 689559#L797-1 assume !(1 == ~E_1~0); 689599#L802-1 assume !(1 == ~E_2~0); 689843#L807-1 assume !(1 == ~E_3~0); 689844#L812-1 assume !(1 == ~E_4~0); 690114#L817-1 assume !(1 == ~E_5~0); 689901#L822-1 assume !(1 == ~E_6~0); 689902#L827-1 assume { :end_inline_reset_delta_events } true; 690121#L1053-2 [2023-11-29 04:15:16,493 INFO L750 eck$LassoCheckResult]: Loop: 690121#L1053-2 assume !false; 695110#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 695106#L659-1 assume !false; 695105#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 695103#L518 assume !(0 == ~m_st~0); 695104#L522 assume !(0 == ~t1_st~0); 695795#L526 assume !(0 == ~t2_st~0); 695796#L530 assume !(0 == ~t3_st~0); 695798#L534 assume !(0 == ~t4_st~0); 695793#L538 assume !(0 == ~t5_st~0); 695794#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 695797#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 695787#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 695788#L570 assume !(0 != eval_~tmp~0#1); 699644#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 699643#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 699642#L684-3 assume !(0 == ~M_E~0); 699641#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 699640#L689-3 assume !(0 == ~T2_E~0); 699639#L694-3 assume !(0 == ~T3_E~0); 699638#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 699637#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 699636#L709-3 assume !(0 == ~T6_E~0); 699635#L714-3 assume !(0 == ~E_M~0); 699634#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 699633#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 699632#L729-3 assume !(0 == ~E_3~0); 699631#L734-3 assume !(0 == ~E_4~0); 699630#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 699629#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 699628#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 699627#L334-24 assume 1 == ~m_pc~0; 699625#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 699626#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 699617#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 699618#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 703188#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 703187#L353-24 assume !(1 == ~t1_pc~0); 703186#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 703185#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 703184#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 703183#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 703182#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 703181#L372-24 assume 1 == ~t2_pc~0; 703179#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 703177#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 703175#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 703173#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 703172#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 703170#L391-24 assume !(1 == ~t3_pc~0); 703168#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 703166#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 703165#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 703163#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 701133#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 701132#L410-24 assume !(1 == ~t4_pc~0); 701128#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 701124#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 701123#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 701122#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 701121#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 695199#L429-24 assume !(1 == ~t5_pc~0); 695195#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 695193#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 695191#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 695188#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 695185#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 695183#L448-24 assume !(1 == ~t6_pc~0); 695181#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 695179#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 695177#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 695175#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 695173#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 695169#L762-3 assume !(1 == ~M_E~0); 692867#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 695166#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 695163#L772-3 assume !(1 == ~T3_E~0); 695162#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 695161#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 695159#L787-3 assume !(1 == ~T6_E~0); 695157#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 695155#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 695153#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 695151#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 695149#L812-3 assume !(1 == ~E_4~0); 695147#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 695145#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 695143#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 695140#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 695138#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 695136#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 695135#L1072 assume !(0 == start_simulation_~tmp~3#1); 695132#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 695130#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 695129#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 695125#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 695121#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 695120#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 695118#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 695114#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 690121#L1053-2 [2023-11-29 04:15:16,493 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:16,493 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 8 times [2023-11-29 04:15:16,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:16,494 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677237743] [2023-11-29 04:15:16,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:16,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:16,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:16,506 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:16,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:16,532 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:16,533 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:16,533 INFO L85 PathProgramCache]: Analyzing trace with hash 1166932111, now seen corresponding path program 1 times [2023-11-29 04:15:16,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:16,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844427679] [2023-11-29 04:15:16,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:16,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:16,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:16,596 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:16,596 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:16,596 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844427679] [2023-11-29 04:15:16,596 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [844427679] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:16,596 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:16,596 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:15:16,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [286658236] [2023-11-29 04:15:16,597 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:16,597 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:16,597 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:16,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:15:16,598 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:15:16,598 INFO L87 Difference]: Start difference. First operand 30016 states and 39984 transitions. cyclomatic complexity: 9984 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:16,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:16,905 INFO L93 Difference]: Finished difference Result 45656 states and 60239 transitions. [2023-11-29 04:15:16,906 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45656 states and 60239 transitions. [2023-11-29 04:15:17,195 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 45256 [2023-11-29 04:15:17,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45656 states to 45656 states and 60239 transitions. [2023-11-29 04:15:17,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45656 [2023-11-29 04:15:17,276 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45656 [2023-11-29 04:15:17,276 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45656 states and 60239 transitions. [2023-11-29 04:15:17,290 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:15:17,290 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45656 states and 60239 transitions. [2023-11-29 04:15:17,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45656 states and 60239 transitions. [2023-11-29 04:15:17,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45656 to 30640. [2023-11-29 04:15:17,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30640 states, 30640 states have (on average 1.3195496083550913) internal successors, (40431), 30639 states have internal predecessors, (40431), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:17,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30640 states to 30640 states and 40431 transitions. [2023-11-29 04:15:17,537 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30640 states and 40431 transitions. [2023-11-29 04:15:17,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:15:17,538 INFO L428 stractBuchiCegarLoop]: Abstraction has 30640 states and 40431 transitions. [2023-11-29 04:15:17,538 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-29 04:15:17,538 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30640 states and 40431 transitions. [2023-11-29 04:15:17,601 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30320 [2023-11-29 04:15:17,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:17,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:17,603 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:17,603 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:17,603 INFO L748 eck$LassoCheckResult]: Stem: 765478#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 765479#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 765622#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 765623#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 765257#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 765258#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 765618#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 765619#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 765537#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 765317#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 765318#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 765237#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 765238#L684 assume !(0 == ~M_E~0); 765757#L684-2 assume !(0 == ~T1_E~0); 765574#L689-1 assume !(0 == ~T2_E~0); 765575#L694-1 assume !(0 == ~T3_E~0); 765572#L699-1 assume !(0 == ~T4_E~0); 765573#L704-1 assume !(0 == ~T5_E~0); 765524#L709-1 assume !(0 == ~T6_E~0); 765457#L714-1 assume !(0 == ~E_M~0); 765458#L719-1 assume !(0 == ~E_1~0); 765718#L724-1 assume !(0 == ~E_2~0); 765209#L729-1 assume !(0 == ~E_3~0); 765210#L734-1 assume !(0 == ~E_4~0); 765799#L739-1 assume !(0 == ~E_5~0); 765416#L744-1 assume !(0 == ~E_6~0); 765417#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 765165#L334 assume !(1 == ~m_pc~0); 765166#L334-2 is_master_triggered_~__retres1~0#1 := 0; 765512#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 765900#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 765383#L849 assume !(0 != activate_threads_~tmp~1#1); 765384#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 765313#L353 assume !(1 == ~t1_pc~0); 765314#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 765624#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 765180#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 765181#L857 assume !(0 != activate_threads_~tmp___0~0#1); 765259#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 765260#L372 assume !(1 == ~t2_pc~0); 765369#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 765396#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 765625#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 765626#L865 assume !(0 != activate_threads_~tmp___1~0#1); 765154#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 765155#L391 assume !(1 == ~t3_pc~0); 765078#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 765079#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 765103#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 765104#L873 assume !(0 != activate_threads_~tmp___2~0#1); 765390#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 765391#L410 assume !(1 == ~t4_pc~0); 765639#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 765640#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 765274#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 765275#L881 assume !(0 != activate_threads_~tmp___3~0#1); 765402#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 765403#L429 assume !(1 == ~t5_pc~0); 765215#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 765216#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 765431#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 765432#L889 assume !(0 != activate_threads_~tmp___4~0#1); 765645#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 765382#L448 assume !(1 == ~t6_pc~0); 765295#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 765296#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 765609#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 765610#L897 assume !(0 != activate_threads_~tmp___5~0#1); 765827#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 765880#L762 assume !(1 == ~M_E~0); 765438#L762-2 assume !(1 == ~T1_E~0); 765439#L767-1 assume !(1 == ~T2_E~0); 765832#L772-1 assume !(1 == ~T3_E~0); 765681#L777-1 assume !(1 == ~T4_E~0); 765554#L782-1 assume !(1 == ~T5_E~0); 765241#L787-1 assume !(1 == ~T6_E~0); 765239#L792-1 assume !(1 == ~E_M~0); 765240#L797-1 assume !(1 == ~E_1~0); 765281#L802-1 assume !(1 == ~E_2~0); 765516#L807-1 assume !(1 == ~E_3~0); 765517#L812-1 assume !(1 == ~E_4~0); 765795#L817-1 assume !(1 == ~E_5~0); 765578#L822-1 assume !(1 == ~E_6~0); 765579#L827-1 assume { :end_inline_reset_delta_events } true; 765804#L1053-2 [2023-11-29 04:15:17,603 INFO L750 eck$LassoCheckResult]: Loop: 765804#L1053-2 assume !false; 768071#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 768065#L659-1 assume !false; 768063#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 768060#L518 assume !(0 == ~m_st~0); 768061#L522 assume !(0 == ~t1_st~0); 768540#L526 assume !(0 == ~t2_st~0); 768538#L530 assume !(0 == ~t3_st~0); 768536#L534 assume !(0 == ~t4_st~0); 768534#L538 assume !(0 == ~t5_st~0); 768530#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 768528#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 768526#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 768523#L570 assume !(0 != eval_~tmp~0#1); 768521#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 768519#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 768517#L684-3 assume !(0 == ~M_E~0); 768515#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 768513#L689-3 assume !(0 == ~T2_E~0); 768511#L694-3 assume !(0 == ~T3_E~0); 768509#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 768507#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 768505#L709-3 assume !(0 == ~T6_E~0); 768503#L714-3 assume !(0 == ~E_M~0); 768501#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 768499#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 768497#L729-3 assume !(0 == ~E_3~0); 768495#L734-3 assume !(0 == ~E_4~0); 768493#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 768491#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 768489#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 768487#L334-24 assume 1 == ~m_pc~0; 768483#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 768481#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 768479#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 768475#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 768473#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 768471#L353-24 assume !(1 == ~t1_pc~0); 768469#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 768467#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 768465#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 768463#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 768461#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 768457#L372-24 assume 1 == ~t2_pc~0; 768455#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 768456#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 768579#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 768445#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 768443#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 768441#L391-24 assume !(1 == ~t3_pc~0); 768439#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 768437#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 768435#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 768433#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 768431#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 768429#L410-24 assume !(1 == ~t4_pc~0); 768427#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 768425#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 768423#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 768421#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 768419#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 768415#L429-24 assume !(1 == ~t5_pc~0); 768411#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 768409#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 768407#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 768404#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 768401#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 768399#L448-24 assume !(1 == ~t6_pc~0); 768397#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 768395#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 768393#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 768391#L897-24 assume !(0 != activate_threads_~tmp___5~0#1); 768389#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 768388#L762-3 assume !(1 == ~M_E~0); 768385#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 768383#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 768381#L772-3 assume !(1 == ~T3_E~0); 768379#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 768378#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 768376#L787-3 assume !(1 == ~T6_E~0); 768374#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 768372#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 768370#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 768368#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 768366#L812-3 assume !(1 == ~E_4~0); 768362#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 768360#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 768358#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 768355#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 768352#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 768350#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 768347#L1072 assume !(0 == start_simulation_~tmp~3#1); 768344#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 768341#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 768339#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 768337#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 768335#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 768333#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 768331#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 768329#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 765804#L1053-2 [2023-11-29 04:15:17,603 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:17,604 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 9 times [2023-11-29 04:15:17,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:17,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1618377847] [2023-11-29 04:15:17,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:17,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:17,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:17,613 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:17,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:17,630 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:17,631 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:17,631 INFO L85 PathProgramCache]: Analyzing trace with hash -1741831791, now seen corresponding path program 1 times [2023-11-29 04:15:17,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:17,631 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1579537802] [2023-11-29 04:15:17,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:17,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:17,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:17,640 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:17,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:17,657 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:17,658 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:17,658 INFO L85 PathProgramCache]: Analyzing trace with hash 1849523801, now seen corresponding path program 1 times [2023-11-29 04:15:17,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:17,658 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257742637] [2023-11-29 04:15:17,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:17,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:17,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:17,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:17,696 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:17,696 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1257742637] [2023-11-29 04:15:17,696 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1257742637] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:17,696 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:17,696 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:17,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1448345639] [2023-11-29 04:15:17,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:19,206 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 04:15:19,206 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 04:15:19,206 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 04:15:19,206 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 04:15:19,206 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-29 04:15:19,206 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:19,207 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 04:15:19,207 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 04:15:19,207 INFO L133 ssoRankerPreferences]: Filename of dumped script: token_ring.06.cil-2.c_Iteration27_Loop [2023-11-29 04:15:19,207 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 04:15:19,207 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 04:15:19,227 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,237 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,239 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,241 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,244 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,246 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,250 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,252 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,254 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,256 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,261 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,264 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,266 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,268 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,271 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,273 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,275 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,279 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,281 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,283 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,286 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,288 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,290 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,292 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,294 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,296 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,299 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,301 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,303 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,306 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,308 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,310 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,315 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,319 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,322 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,325 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,327 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,329 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,331 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,332 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,334 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,335 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,337 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,340 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,344 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,346 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,348 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,350 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,353 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,358 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,362 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,367 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,368 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,371 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,372 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,376 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,378 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,380 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,382 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,384 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,387 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,388 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,390 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,391 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,397 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,399 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,400 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,404 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,405 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,407 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,408 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,410 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,411 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,414 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,416 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,418 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,421 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,424 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,428 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,431 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,433 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,434 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,436 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:19,902 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 04:15:19,903 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-29 04:15:19,905 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:19,905 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:19,906 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:19,912 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-29 04:15:19,913 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:19,913 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:19,928 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:19,929 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:19,932 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:19,932 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:19,933 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:19,933 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:19,935 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-29 04:15:19,936 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:19,936 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:19,947 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:19,948 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:19,950 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2023-11-29 04:15:19,950 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:19,950 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:19,951 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:19,952 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-29 04:15:19,953 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:19,953 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:19,965 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:19,966 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:19,969 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2023-11-29 04:15:19,969 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:19,969 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:19,970 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:19,970 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-29 04:15:19,972 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:19,972 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:19,985 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:19,985 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:19,988 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2023-11-29 04:15:19,988 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:19,988 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:19,989 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:19,990 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-29 04:15:19,991 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:19,991 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,003 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,003 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,005 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2023-11-29 04:15:20,008 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,009 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,009 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,010 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-29 04:15:20,012 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,012 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,032 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,032 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,035 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2023-11-29 04:15:20,035 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,035 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,036 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,037 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-29 04:15:20,038 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,038 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,050 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,050 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,054 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:20,054 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,054 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,055 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,064 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-29 04:15:20,065 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,066 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,080 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,080 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,084 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:20,084 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,084 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,089 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,094 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-29 04:15:20,095 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,095 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,110 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,110 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret21#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret21#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,113 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2023-11-29 04:15:20,114 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,114 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,115 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,117 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-29 04:15:20,118 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,118 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,136 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,136 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_4~0=-8} Honda state: {~E_4~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,138 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2023-11-29 04:15:20,139 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,139 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,140 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,140 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-29 04:15:20,142 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,142 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,153 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,153 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Honda state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,155 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2023-11-29 04:15:20,156 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,156 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,157 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,157 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-29 04:15:20,159 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,159 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,170 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,170 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,172 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2023-11-29 04:15:20,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,173 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,173 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,174 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2023-11-29 04:15:20,176 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,176 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,187 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,187 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret16#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret16#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,189 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2023-11-29 04:15:20,190 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,190 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,190 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,191 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2023-11-29 04:15:20,193 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,193 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,210 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,210 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,213 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:20,213 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,213 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,214 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,214 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2023-11-29 04:15:20,216 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,216 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,234 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,234 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_st~0=-1} Honda state: {~t1_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,236 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2023-11-29 04:15:20,236 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,236 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,237 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,238 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2023-11-29 04:15:20,239 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,239 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,250 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,251 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret22#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret22#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,253 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2023-11-29 04:15:20,253 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,253 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,254 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,255 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2023-11-29 04:15:20,256 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,256 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,268 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,268 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,270 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2023-11-29 04:15:20,270 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,271 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,271 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,272 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2023-11-29 04:15:20,273 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,273 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,285 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,285 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet6#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet6#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,287 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2023-11-29 04:15:20,287 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,287 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,288 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,289 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2023-11-29 04:15:20,291 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,291 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,308 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,308 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t5_st~0=4} Honda state: {~t5_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,310 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2023-11-29 04:15:20,311 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,311 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,311 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,312 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2023-11-29 04:15:20,314 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,314 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,325 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,325 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,327 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2023-11-29 04:15:20,328 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,328 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,329 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,330 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2023-11-29 04:15:20,331 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,331 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,344 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,344 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___4~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___4~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,346 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2023-11-29 04:15:20,347 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,347 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,348 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,348 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2023-11-29 04:15:20,350 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,350 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,362 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,362 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Honda state: {ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,364 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2023-11-29 04:15:20,364 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,365 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,365 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,366 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2023-11-29 04:15:20,368 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,368 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,379 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,379 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___2~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,383 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:20,383 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,383 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,384 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,385 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2023-11-29 04:15:20,386 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,386 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,397 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,398 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,400 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2023-11-29 04:15:20,400 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,400 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,401 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,403 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2023-11-29 04:15:20,404 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,404 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,415 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,415 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,418 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Ended with exit code 0 [2023-11-29 04:15:20,418 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,419 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,419 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,420 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2023-11-29 04:15:20,421 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,422 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,434 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,434 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,436 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2023-11-29 04:15:20,436 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,436 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,437 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,438 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2023-11-29 04:15:20,439 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,440 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,451 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,451 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,454 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Ended with exit code 0 [2023-11-29 04:15:20,454 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,454 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,455 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,456 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2023-11-29 04:15:20,457 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,457 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,471 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,471 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,474 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Ended with exit code 0 [2023-11-29 04:15:20,474 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,475 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,475 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,476 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2023-11-29 04:15:20,478 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,478 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,490 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,490 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Honda state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,496 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:20,497 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,497 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,498 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,499 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2023-11-29 04:15:20,500 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,500 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,512 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,512 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,514 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Ended with exit code 0 [2023-11-29 04:15:20,514 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,515 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,515 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,516 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2023-11-29 04:15:20,517 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,518 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,529 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:15:20,529 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet10#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet10#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:15:20,531 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2023-11-29 04:15:20,531 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,532 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,532 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,533 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2023-11-29 04:15:20,534 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:15:20,534 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,548 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:20,548 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,548 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:20,549 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:20,550 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2023-11-29 04:15:20,551 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-29 04:15:20,551 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:15:20,565 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-29 04:15:20,569 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:20,569 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 04:15:20,569 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 04:15:20,569 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 04:15:20,569 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 04:15:20,569 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-29 04:15:20,569 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:20,569 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 04:15:20,569 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 04:15:20,569 INFO L133 ssoRankerPreferences]: Filename of dumped script: token_ring.06.cil-2.c_Iteration27_Loop [2023-11-29 04:15:20,570 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 04:15:20,570 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 04:15:20,574 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,577 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,579 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,582 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,584 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,586 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,588 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,589 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,591 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,593 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,598 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,600 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,602 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,605 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,607 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,609 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,612 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,614 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,617 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,619 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,621 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,623 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,625 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,627 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,628 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,630 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,632 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,634 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,636 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,637 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,640 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,642 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,646 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,650 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,653 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,657 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,659 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,661 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,663 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,664 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,666 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,669 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,670 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,675 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,677 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,682 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,691 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,694 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,700 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,701 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,703 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,707 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,708 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,710 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,712 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,713 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,715 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,720 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,722 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,723 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,724 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,726 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,734 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,736 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,738 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,740 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,742 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,748 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,757 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,762 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,765 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,769 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,771 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,774 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:20,776 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:15:21,288 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 04:15:21,291 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-29 04:15:21,292 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,292 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,293 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,293 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2023-11-29 04:15:21,295 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,305 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,306 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,306 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,306 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,306 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,308 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,308 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,309 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,311 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Ended with exit code 0 [2023-11-29 04:15:21,312 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,312 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,312 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,313 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2023-11-29 04:15:21,315 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,324 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,324 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,325 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,325 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,325 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,325 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,325 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,327 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,329 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Ended with exit code 0 [2023-11-29 04:15:21,329 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,330 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,330 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,331 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2023-11-29 04:15:21,332 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,342 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,342 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,342 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,342 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,342 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,343 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,343 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,345 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,347 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Ended with exit code 0 [2023-11-29 04:15:21,347 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,347 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,348 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,348 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2023-11-29 04:15:21,350 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,360 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,360 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,360 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,360 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,360 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,360 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,360 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,362 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,364 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Ended with exit code 0 [2023-11-29 04:15:21,364 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,364 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,365 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,366 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2023-11-29 04:15:21,367 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,377 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,377 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,377 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,377 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 04:15:21,377 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,378 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 04:15:21,378 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,380 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,382 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Ended with exit code 0 [2023-11-29 04:15:21,382 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,382 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,383 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,384 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Waiting until timeout for monitored process [2023-11-29 04:15:21,386 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,395 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,395 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,396 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,396 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,396 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,396 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,396 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,398 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,401 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:21,401 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,401 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,402 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,403 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Waiting until timeout for monitored process [2023-11-29 04:15:21,405 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,417 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,417 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,417 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,417 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,417 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,417 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,417 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,419 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,421 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Ended with exit code 0 [2023-11-29 04:15:21,421 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,421 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,422 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,423 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Waiting until timeout for monitored process [2023-11-29 04:15:21,425 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,437 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,437 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,437 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,437 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,437 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,437 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,438 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,439 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,442 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Ended with exit code 0 [2023-11-29 04:15:21,442 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,442 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,443 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,444 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Waiting until timeout for monitored process [2023-11-29 04:15:21,445 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,455 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,455 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,455 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,455 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,455 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,456 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,456 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,457 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,459 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Ended with exit code 0 [2023-11-29 04:15:21,459 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,459 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,460 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,461 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Waiting until timeout for monitored process [2023-11-29 04:15:21,462 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,472 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,472 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,472 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,472 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 04:15:21,472 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,473 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 04:15:21,473 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,475 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,478 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Ended with exit code 0 [2023-11-29 04:15:21,478 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,478 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,479 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,480 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Waiting until timeout for monitored process [2023-11-29 04:15:21,481 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,491 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,491 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,491 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,491 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,491 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,492 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,492 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,493 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,495 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Ended with exit code 0 [2023-11-29 04:15:21,496 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,496 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,496 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,497 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Waiting until timeout for monitored process [2023-11-29 04:15:21,499 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,508 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,508 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,508 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,509 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,509 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,509 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,509 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,510 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,513 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Ended with exit code 0 [2023-11-29 04:15:21,513 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,514 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,514 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,515 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Waiting until timeout for monitored process [2023-11-29 04:15:21,517 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,526 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,526 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,526 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,527 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,527 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,527 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,527 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,528 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,530 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Ended with exit code 0 [2023-11-29 04:15:21,530 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,531 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,531 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,532 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Waiting until timeout for monitored process [2023-11-29 04:15:21,533 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,543 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,543 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,543 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,543 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 04:15:21,543 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,544 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 04:15:21,544 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,546 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,548 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:21,548 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,548 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,549 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,549 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Waiting until timeout for monitored process [2023-11-29 04:15:21,551 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,561 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,561 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,561 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,561 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,561 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,561 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,561 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,563 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,565 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:21,565 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,565 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,566 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,566 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Waiting until timeout for monitored process [2023-11-29 04:15:21,568 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,577 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,578 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,578 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,578 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 04:15:21,578 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,579 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 04:15:21,579 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,580 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,582 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:21,582 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,583 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,583 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,584 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Waiting until timeout for monitored process [2023-11-29 04:15:21,586 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,595 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,595 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,595 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,595 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,596 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,596 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,596 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,597 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,599 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Ended with exit code 0 [2023-11-29 04:15:21,599 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,599 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,600 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,601 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Waiting until timeout for monitored process [2023-11-29 04:15:21,602 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,612 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,613 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,613 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,613 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,613 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,613 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,613 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,615 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,617 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Ended with exit code 0 [2023-11-29 04:15:21,617 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,618 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,619 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,620 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Waiting until timeout for monitored process [2023-11-29 04:15:21,621 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,631 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,631 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,631 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,631 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 04:15:21,631 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,632 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 04:15:21,632 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,634 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,636 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Ended with exit code 0 [2023-11-29 04:15:21,636 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,636 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,637 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,638 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Waiting until timeout for monitored process [2023-11-29 04:15:21,640 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,652 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,652 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,652 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,652 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,652 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,652 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,652 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,654 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,656 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Ended with exit code 0 [2023-11-29 04:15:21,656 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,657 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,658 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,660 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Waiting until timeout for monitored process [2023-11-29 04:15:21,661 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,670 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,670 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,671 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,671 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,671 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,671 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,671 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,673 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,675 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:21,675 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,675 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,676 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,677 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Waiting until timeout for monitored process [2023-11-29 04:15:21,678 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,688 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,688 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,688 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,688 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,688 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,689 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,689 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,690 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,692 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Ended with exit code 0 [2023-11-29 04:15:21,692 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,692 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,693 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,694 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Waiting until timeout for monitored process [2023-11-29 04:15:21,695 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,705 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,705 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,705 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,705 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,705 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,705 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,706 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,707 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,709 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Ended with exit code 0 [2023-11-29 04:15:21,709 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,709 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,710 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,711 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Waiting until timeout for monitored process [2023-11-29 04:15:21,712 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,722 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,722 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,722 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,722 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,722 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,723 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,723 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,724 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,726 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:21,726 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,726 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,727 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,728 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Waiting until timeout for monitored process [2023-11-29 04:15:21,729 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,739 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,739 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,739 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,740 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,740 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,740 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,740 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,742 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,744 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:21,744 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,744 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,745 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,745 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Waiting until timeout for monitored process [2023-11-29 04:15:21,747 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,756 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,757 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,757 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,757 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,757 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,757 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,757 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,759 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,761 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Ended with exit code 0 [2023-11-29 04:15:21,761 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,761 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,762 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,762 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (61)] Waiting until timeout for monitored process [2023-11-29 04:15:21,764 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,773 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,773 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,773 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,773 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,773 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,774 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,774 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,775 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,778 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (61)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:21,778 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,778 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,778 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,779 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (62)] Waiting until timeout for monitored process [2023-11-29 04:15:21,781 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,790 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,790 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,791 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,791 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,791 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,791 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,791 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,792 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,794 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (62)] Ended with exit code 0 [2023-11-29 04:15:21,795 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,795 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,795 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,796 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (63)] Waiting until timeout for monitored process [2023-11-29 04:15:21,798 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,808 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,808 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,808 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,808 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,808 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,808 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,809 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,810 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,812 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (63)] Ended with exit code 0 [2023-11-29 04:15:21,812 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,812 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,813 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,814 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (64)] Waiting until timeout for monitored process [2023-11-29 04:15:21,815 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,825 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,825 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,825 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,825 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,825 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,826 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,826 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,827 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,830 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (64)] Ended with exit code 0 [2023-11-29 04:15:21,830 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,830 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,831 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,831 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (65)] Waiting until timeout for monitored process [2023-11-29 04:15:21,833 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,843 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,843 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,843 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,843 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,843 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,844 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,844 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,845 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:15:21,847 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (65)] Ended with exit code 0 [2023-11-29 04:15:21,847 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,847 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,848 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,848 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (66)] Waiting until timeout for monitored process [2023-11-29 04:15:21,850 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:15:21,860 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:15:21,860 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:15:21,860 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:15:21,860 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:15:21,860 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:15:21,861 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:15:21,861 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:15:21,863 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-29 04:15:21,866 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-29 04:15:21,866 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-29 04:15:21,868 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:15:21,868 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:15:21,901 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:15:21,902 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (67)] Waiting until timeout for monitored process [2023-11-29 04:15:21,903 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-29 04:15:21,903 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-29 04:15:21,903 INFO L513 LassoAnalysis]: Proved termination. [2023-11-29 04:15:21,903 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T5_E~0) = -1*~T5_E~0 + 1 Supporting invariants [] [2023-11-29 04:15:21,905 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (66)] Forceful destruction successful, exit code 0 [2023-11-29 04:15:21,907 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-29 04:15:21,924 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:21,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:21,968 INFO L262 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-29 04:15:21,970 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 04:15:22,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:22,105 INFO L262 TraceCheckSpWp]: Trace formula consists of 212 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-29 04:15:22,108 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 04:15:22,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:22,338 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-29 04:15:22,340 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 30640 states and 40431 transitions. cyclomatic complexity: 9807 Second operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:22,698 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 30640 states and 40431 transitions. cyclomatic complexity: 9807. Second operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 61506 states and 81442 transitions. Complement of second has 4 states. [2023-11-29 04:15:22,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-29 04:15:22,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:22,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 980 transitions. [2023-11-29 04:15:22,703 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 980 transitions. Stem has 84 letters. Loop has 100 letters. [2023-11-29 04:15:22,707 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 04:15:22,707 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 980 transitions. Stem has 184 letters. Loop has 100 letters. [2023-11-29 04:15:22,709 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 04:15:22,709 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 980 transitions. Stem has 84 letters. Loop has 200 letters. [2023-11-29 04:15:22,711 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 04:15:22,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61506 states and 81442 transitions. [2023-11-29 04:15:22,973 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30320 [2023-11-29 04:15:23,149 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61506 states to 61506 states and 81442 transitions. [2023-11-29 04:15:23,149 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30641 [2023-11-29 04:15:23,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30802 [2023-11-29 04:15:23,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61506 states and 81442 transitions. [2023-11-29 04:15:23,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 04:15:23,171 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61506 states and 81442 transitions. [2023-11-29 04:15:23,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61506 states and 81442 transitions. [2023-11-29 04:15:23,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61506 to 61345. [2023-11-29 04:15:23,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61345 states, 61345 states have (on average 1.3228951014752628) internal successors, (81153), 61344 states have internal predecessors, (81153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:23,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61345 states to 61345 states and 81153 transitions. [2023-11-29 04:15:23,845 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61345 states and 81153 transitions. [2023-11-29 04:15:23,846 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:23,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:23,846 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:23,846 INFO L87 Difference]: Start difference. First operand 61345 states and 81153 transitions. Second operand has 3 states, 3 states have (on average 61.333333333333336) internal successors, (184), 3 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:24,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:24,181 INFO L93 Difference]: Finished difference Result 64609 states and 84897 transitions. [2023-11-29 04:15:24,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64609 states and 84897 transitions. [2023-11-29 04:15:24,425 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 31952 [2023-11-29 04:15:24,602 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64609 states to 64609 states and 84897 transitions. [2023-11-29 04:15:24,602 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32273 [2023-11-29 04:15:24,619 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32273 [2023-11-29 04:15:24,619 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64609 states and 84897 transitions. [2023-11-29 04:15:24,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 04:15:24,620 INFO L218 hiAutomatonCegarLoop]: Abstraction has 64609 states and 84897 transitions. [2023-11-29 04:15:24,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64609 states and 84897 transitions. [2023-11-29 04:15:25,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64609 to 61345. [2023-11-29 04:15:25,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61345 states, 61345 states have (on average 1.3187219822316407) internal successors, (80897), 61344 states have internal predecessors, (80897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:25,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61345 states to 61345 states and 80897 transitions. [2023-11-29 04:15:25,246 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61345 states and 80897 transitions. [2023-11-29 04:15:25,247 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:25,247 INFO L428 stractBuchiCegarLoop]: Abstraction has 61345 states and 80897 transitions. [2023-11-29 04:15:25,247 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-29 04:15:25,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61345 states and 80897 transitions. [2023-11-29 04:15:25,393 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30320 [2023-11-29 04:15:25,393 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:25,393 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:25,395 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:25,395 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:25,395 INFO L748 eck$LassoCheckResult]: Stem: 984503#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 984504#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 984781#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 984782#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 984092#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 984093#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 984779#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 984780#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 984628#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 984204#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 984205#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 984058#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 984059#L684 assume !(0 == ~M_E~0); 985034#L684-2 assume !(0 == ~T1_E~0); 984693#L689-1 assume !(0 == ~T2_E~0); 984694#L694-1 assume !(0 == ~T3_E~0); 984691#L699-1 assume !(0 == ~T4_E~0); 984692#L704-1 assume !(0 == ~T5_E~0); 984594#L709-1 assume !(0 == ~T6_E~0); 984469#L714-1 assume !(0 == ~E_M~0); 984470#L719-1 assume !(0 == ~E_1~0); 984968#L724-1 assume !(0 == ~E_2~0); 984009#L729-1 assume !(0 == ~E_3~0); 984010#L734-1 assume !(0 == ~E_4~0); 985121#L739-1 assume !(0 == ~E_5~0); 984396#L744-1 assume !(0 == ~E_6~0); 984397#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 983924#L334 assume !(1 == ~m_pc~0); 983925#L334-2 is_master_triggered_~__retres1~0#1 := 0; 984579#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 985338#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 984342#L849 assume !(0 != activate_threads_~tmp~1#1); 984343#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 984202#L353 assume !(1 == ~t1_pc~0); 984203#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 984788#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 983951#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 983952#L857 assume !(0 != activate_threads_~tmp___0~0#1); 984101#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 984102#L372 assume !(1 == ~t2_pc~0); 984317#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 984361#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 984789#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 984790#L865 assume !(0 != activate_threads_~tmp___1~0#1); 983904#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 983905#L391 assume !(1 == ~t3_pc~0); 983755#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 983756#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 983804#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 983805#L873 assume !(0 != activate_threads_~tmp___2~0#1); 984354#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 984355#L410 assume !(1 == ~t4_pc~0); 984816#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 984817#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 984131#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 984132#L881 assume !(0 != activate_threads_~tmp___3~0#1); 984364#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 984365#L429 assume !(1 == ~t5_pc~0); 984019#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 984020#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 985339#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 984827#L889 assume !(0 != activate_threads_~tmp___4~0#1); 984828#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 984337#L448 assume !(1 == ~t6_pc~0); 984168#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 984169#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 984755#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 984756#L897 assume !(0 != activate_threads_~tmp___5~0#1); 985183#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 985278#L762 assume !(1 == ~M_E~0); 984429#L762-2 assume !(1 == ~T1_E~0); 984430#L767-1 assume !(1 == ~T2_E~0); 985193#L772-1 assume !(1 == ~T3_E~0); 984895#L777-1 assume !(1 == ~T4_E~0); 984660#L782-1 assume !(1 == ~T5_E~0); 984066#L787-1 assume !(1 == ~T6_E~0); 984064#L792-1 assume !(1 == ~E_M~0); 984065#L797-1 assume !(1 == ~E_1~0); 984141#L802-1 assume !(1 == ~E_2~0); 984586#L807-1 assume !(1 == ~E_3~0); 984587#L812-1 assume !(1 == ~E_4~0); 985109#L817-1 assume !(1 == ~E_5~0); 984695#L822-1 assume !(1 == ~E_6~0); 984696#L827-1 assume { :end_inline_reset_delta_events } true; 985131#L1053-2 assume !false; 998347#L1054 [2023-11-29 04:15:25,396 INFO L750 eck$LassoCheckResult]: Loop: 998347#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 998214#L659-1 assume !false; 998343#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 998341#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 998338#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 998336#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 998334#L570 assume 0 != eval_~tmp~0#1; 998325#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 997940#L578 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1; 997941#L74 assume 0 == ~m_pc~0; 1002994#L99-1 assume !false; 1002993#L86 havoc master_#t~nondet4#1;~token~0 := master_#t~nondet4#1;havoc master_#t~nondet4#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1002992#L334-3 assume 1 == ~m_pc~0; 1002990#L335-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1002991#L345-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1003002#is_master_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1002982#L849-3 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1002980#L849-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1002978#L353-3 assume !(1 == ~t1_pc~0); 1002976#L353-5 is_transmit1_triggered_~__retres1~1#1 := 0; 1002974#L364-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1002972#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1002971#L857-3 assume !(0 != activate_threads_~tmp___0~0#1); 1002970#L857-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1002969#L372-3 assume !(1 == ~t2_pc~0); 1002968#L372-5 is_transmit2_triggered_~__retres1~2#1 := 0; 1002966#L383-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1002964#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1002961#L865-3 assume !(0 != activate_threads_~tmp___1~0#1); 1002960#L865-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1002958#L391-3 assume !(1 == ~t3_pc~0); 1002954#L391-5 is_transmit3_triggered_~__retres1~3#1 := 0; 1001227#L402-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1001225#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1001223#L873-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1001219#L873-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1001217#L410-3 assume !(1 == ~t4_pc~0); 1001215#L410-5 is_transmit4_triggered_~__retres1~4#1 := 0; 1001208#L421-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1001206#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1001204#L881-3 assume !(0 != activate_threads_~tmp___3~0#1); 1001202#L881-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1001200#L429-3 assume 1 == ~t5_pc~0; 1001198#L430-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1001199#L440-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1003022#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1001189#L889-3 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1001188#L889-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1001186#L448-3 assume !(1 == ~t6_pc~0); 1001184#L448-5 is_transmit6_triggered_~__retres1~6#1 := 0; 1001176#L459-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1001173#is_transmit6_triggered_returnLabel#2 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1001065#L897-3 assume !(0 != activate_threads_~tmp___5~0#1); 1001062#L897-5 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true; 995475#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 995466#master_returnLabel#1 havoc master_#t~nondet4#1;assume { :end_inline_master } true; 995459#L578-2 havoc eval_~tmp_ndt_1~0#1; 995450#L575-1 assume !(0 == ~t1_st~0); 995440#L589-1 assume !(0 == ~t2_st~0); 995432#L603-1 assume !(0 == ~t3_st~0); 995433#L617-1 assume !(0 == ~t4_st~0); 998476#L631-1 assume !(0 == ~t5_st~0); 998477#L645-1 assume !(0 == ~t6_st~0); 999547#L659-1 assume !false; 1001187#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1001185#L518 assume !(0 == ~m_st~0); 1001183#L522 assume !(0 == ~t1_st~0); 1001179#L526 assume !(0 == ~t2_st~0); 1001180#L530 assume !(0 == ~t3_st~0); 1001182#L534 assume !(0 == ~t4_st~0); 1001177#L538 assume !(0 == ~t5_st~0); 1001178#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1001181#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1001171#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1001172#L570 assume !(0 != eval_~tmp~0#1); 1001743#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1001741#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1001739#L684-3 assume !(0 == ~M_E~0); 1001737#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1001735#L689-3 assume !(0 == ~T2_E~0); 1001733#L694-3 assume !(0 == ~T3_E~0); 1001731#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1001729#L704-3 assume !(0 == ~T5_E~0); 1001726#L709-3 assume !(0 == ~T6_E~0); 1001723#L714-3 assume !(0 == ~E_M~0); 1001722#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1001721#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1001720#L729-3 assume !(0 == ~E_3~0); 1001719#L734-3 assume !(0 == ~E_4~0); 1001718#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1001717#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1001716#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1001715#L334-24 assume 1 == ~m_pc~0; 1001713#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1001714#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1001706#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1001707#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1013551#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1013550#L353-24 assume !(1 == ~t1_pc~0); 1013549#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1013548#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1013547#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1013546#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 1013545#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1013544#L372-24 assume !(1 == ~t2_pc~0); 1013543#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1013541#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1013539#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1013537#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 1013535#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1013534#L391-24 assume !(1 == ~t3_pc~0); 1013533#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1013532#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1013531#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1013530#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 1013529#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1013528#L410-24 assume !(1 == ~t4_pc~0); 1013527#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1013526#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1013525#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1013524#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 1013523#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1013522#L429-24 assume !(1 == ~t5_pc~0); 1013521#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 1013519#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1013517#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1013515#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 1013513#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1013512#L448-24 assume !(1 == ~t6_pc~0); 1013511#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1013510#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1013509#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1013508#L897-24 assume !(0 != activate_threads_~tmp___5~0#1); 1013507#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1013506#L762-3 assume !(1 == ~M_E~0); 1012188#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1013505#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1013504#L772-3 assume !(1 == ~T3_E~0); 1013503#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1013502#L782-3 assume !(1 == ~T5_E~0); 1013501#L787-3 assume !(1 == ~T6_E~0); 1013499#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1013497#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1013495#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1013493#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1013491#L812-3 assume !(1 == ~E_4~0); 1013489#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1013487#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1013485#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1013483#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1013481#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1013479#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1013477#L1072 assume !(0 == start_simulation_~tmp~3#1); 1013475#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1013474#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1013473#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1013472#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1013471#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1013470#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1013469#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1013468#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 998349#L1053-2 assume !false; 998347#L1054 [2023-11-29 04:15:25,397 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:25,397 INFO L85 PathProgramCache]: Analyzing trace with hash -1996793376, now seen corresponding path program 1 times [2023-11-29 04:15:25,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:25,397 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140161646] [2023-11-29 04:15:25,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:25,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:25,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:25,411 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:25,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:25,435 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:25,436 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:25,436 INFO L85 PathProgramCache]: Analyzing trace with hash 1962942200, now seen corresponding path program 1 times [2023-11-29 04:15:25,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:25,436 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [887425559] [2023-11-29 04:15:25,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:25,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:25,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:25,487 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:25,487 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:25,487 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [887425559] [2023-11-29 04:15:25,487 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [887425559] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:25,487 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:25,487 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:25,487 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1359878589] [2023-11-29 04:15:25,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:25,488 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:15:25,488 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:25,488 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:25,489 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:25,489 INFO L87 Difference]: Start difference. First operand 61345 states and 80897 transitions. cyclomatic complexity: 19584 Second operand has 3 states, 3 states have (on average 54.0) internal successors, (162), 3 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:25,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:25,735 INFO L93 Difference]: Finished difference Result 74135 states and 96732 transitions. [2023-11-29 04:15:25,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74135 states and 96732 transitions. [2023-11-29 04:15:25,986 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36628 [2023-11-29 04:15:26,149 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74135 states to 74135 states and 96732 transitions. [2023-11-29 04:15:26,149 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37034 [2023-11-29 04:15:26,167 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37034 [2023-11-29 04:15:26,167 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74135 states and 96732 transitions. [2023-11-29 04:15:26,176 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 04:15:26,176 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74135 states and 96732 transitions. [2023-11-29 04:15:26,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74135 states and 96732 transitions. [2023-11-29 04:15:26,782 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (67)] Ended with exit code 0 [2023-11-29 04:15:26,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74135 to 70615. [2023-11-29 04:15:26,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70615 states, 70615 states have (on average 1.3095801175387665) internal successors, (92476), 70614 states have internal predecessors, (92476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:26,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70615 states to 70615 states and 92476 transitions. [2023-11-29 04:15:26,985 INFO L240 hiAutomatonCegarLoop]: Abstraction has 70615 states and 92476 transitions. [2023-11-29 04:15:26,986 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:26,986 INFO L428 stractBuchiCegarLoop]: Abstraction has 70615 states and 92476 transitions. [2023-11-29 04:15:26,986 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-29 04:15:26,986 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70615 states and 92476 transitions. [2023-11-29 04:15:27,110 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 34868 [2023-11-29 04:15:27,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:27,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:27,110 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:27,110 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:27,111 INFO L748 eck$LassoCheckResult]: Stem: 1120001#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1120002#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1120276#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1120277#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1119583#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1119584#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1120270#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1120271#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1120120#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1119695#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1119696#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1119547#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1119548#L684 assume !(0 == ~M_E~0); 1120541#L684-2 assume !(0 == ~T1_E~0); 1120186#L689-1 assume !(0 == ~T2_E~0); 1120187#L694-1 assume !(0 == ~T3_E~0); 1120184#L699-1 assume !(0 == ~T4_E~0); 1120185#L704-1 assume !(0 == ~T5_E~0); 1120094#L709-1 assume !(0 == ~T6_E~0); 1119958#L714-1 assume !(0 == ~E_M~0); 1119959#L719-1 assume !(0 == ~E_1~0); 1120464#L724-1 assume !(0 == ~E_2~0); 1119494#L729-1 assume !(0 == ~E_3~0); 1119495#L734-1 assume !(0 == ~E_4~0); 1120625#L739-1 assume !(0 == ~E_5~0); 1119882#L744-1 assume !(0 == ~E_6~0); 1119883#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1119411#L334 assume !(1 == ~m_pc~0); 1119412#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1120073#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1119887#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1119826#L849 assume !(0 != activate_threads_~tmp~1#1); 1119827#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1119689#L353 assume !(1 == ~t1_pc~0); 1119690#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1120279#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1119437#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1119438#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1119585#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1119586#L372 assume !(1 == ~t2_pc~0); 1119802#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1119846#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1120280#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1120281#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1119391#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1119392#L391 assume !(1 == ~t3_pc~0); 1119241#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1119242#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1119291#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1119292#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1119838#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1119839#L410 assume !(1 == ~t4_pc~0); 1120308#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1120309#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1119614#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1119615#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1119855#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1119856#L429 assume !(1 == ~t5_pc~0); 1119504#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1119505#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1120836#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1120321#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1120322#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1119825#L448 assume !(1 == ~t6_pc~0); 1119655#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1119656#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1120250#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1120251#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1120687#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1120817#L762 assume !(1 == ~M_E~0); 1119921#L762-2 assume !(1 == ~T1_E~0); 1119922#L767-1 assume !(1 == ~T2_E~0); 1120699#L772-1 assume !(1 == ~T3_E~0); 1120390#L777-1 assume !(1 == ~T4_E~0); 1120154#L782-1 assume !(1 == ~T5_E~0); 1119551#L787-1 assume !(1 == ~T6_E~0); 1119549#L792-1 assume !(1 == ~E_M~0); 1119550#L797-1 assume !(1 == ~E_1~0); 1119628#L802-1 assume !(1 == ~E_2~0); 1120080#L807-1 assume !(1 == ~E_3~0); 1120081#L812-1 assume !(1 == ~E_4~0); 1120617#L817-1 assume !(1 == ~E_5~0); 1120192#L822-1 assume !(1 == ~E_6~0); 1120193#L827-1 assume { :end_inline_reset_delta_events } true; 1120638#L1053-2 assume !false; 1139425#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1140489#L659-1 [2023-11-29 04:15:27,111 INFO L750 eck$LassoCheckResult]: Loop: 1140489#L659-1 assume !false; 1140488#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1140487#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1140484#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1140481#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1140482#L570 assume 0 != eval_~tmp~0#1; 1140478#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1140475#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1140476#L578-2 havoc eval_~tmp_ndt_1~0#1; 1144680#L575-1 assume !(0 == ~t1_st~0); 1144676#L589-1 assume !(0 == ~t2_st~0); 1144672#L603-1 assume !(0 == ~t3_st~0); 1144673#L617-1 assume !(0 == ~t4_st~0); 1120498#L631-1 assume !(0 == ~t5_st~0); 1119276#L645-1 assume !(0 == ~t6_st~0); 1140489#L659-1 [2023-11-29 04:15:27,112 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:27,112 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 1 times [2023-11-29 04:15:27,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:27,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [334364032] [2023-11-29 04:15:27,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:27,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:27,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:27,120 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:27,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:27,137 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:27,137 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:27,137 INFO L85 PathProgramCache]: Analyzing trace with hash 1779949543, now seen corresponding path program 1 times [2023-11-29 04:15:27,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:27,137 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1224632749] [2023-11-29 04:15:27,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:27,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:27,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:27,140 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:27,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:27,143 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:27,143 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:27,143 INFO L85 PathProgramCache]: Analyzing trace with hash 1784869629, now seen corresponding path program 1 times [2023-11-29 04:15:27,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:27,144 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277340987] [2023-11-29 04:15:27,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:27,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:27,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:27,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:27,171 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:27,171 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1277340987] [2023-11-29 04:15:27,171 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1277340987] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:27,172 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:27,172 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:27,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758742153] [2023-11-29 04:15:27,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:27,240 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:27,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:27,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:27,241 INFO L87 Difference]: Start difference. First operand 70615 states and 92476 transitions. cyclomatic complexity: 21925 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:27,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:27,669 INFO L93 Difference]: Finished difference Result 131144 states and 170145 transitions. [2023-11-29 04:15:27,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 131144 states and 170145 transitions. [2023-11-29 04:15:28,187 INFO L131 ngComponentsAnalysis]: Automaton has 56 accepting balls. 63112 [2023-11-29 04:15:28,475 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 131144 states to 131144 states and 170145 transitions. [2023-11-29 04:15:28,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65534 [2023-11-29 04:15:28,502 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65534 [2023-11-29 04:15:28,502 INFO L73 IsDeterministic]: Start isDeterministic. Operand 131144 states and 170145 transitions. [2023-11-29 04:15:28,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 04:15:28,509 INFO L218 hiAutomatonCegarLoop]: Abstraction has 131144 states and 170145 transitions. [2023-11-29 04:15:28,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131144 states and 170145 transitions. [2023-11-29 04:15:29,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131144 to 127544. [2023-11-29 04:15:29,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 127544 states, 127544 states have (on average 1.2995123251583767) internal successors, (165745), 127543 states have internal predecessors, (165745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:29,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127544 states to 127544 states and 165745 transitions. [2023-11-29 04:15:29,696 INFO L240 hiAutomatonCegarLoop]: Abstraction has 127544 states and 165745 transitions. [2023-11-29 04:15:29,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:29,697 INFO L428 stractBuchiCegarLoop]: Abstraction has 127544 states and 165745 transitions. [2023-11-29 04:15:29,697 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-29 04:15:29,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 127544 states and 165745 transitions. [2023-11-29 04:15:30,107 INFO L131 ngComponentsAnalysis]: Automaton has 56 accepting balls. 61312 [2023-11-29 04:15:30,107 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:30,107 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:30,108 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:30,108 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:30,108 INFO L748 eck$LassoCheckResult]: Stem: 1321772#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1321773#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1322065#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1322066#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1321344#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1321345#L475-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1322059#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1322060#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1321901#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1321457#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1321458#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1321313#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1321314#L684 assume !(0 == ~M_E~0); 1322335#L684-2 assume !(0 == ~T1_E~0); 1321971#L689-1 assume !(0 == ~T2_E~0); 1321972#L694-1 assume !(0 == ~T3_E~0); 1321969#L699-1 assume !(0 == ~T4_E~0); 1321970#L704-1 assume !(0 == ~T5_E~0); 1321865#L709-1 assume !(0 == ~T6_E~0); 1321729#L714-1 assume !(0 == ~E_M~0); 1321730#L719-1 assume !(0 == ~E_1~0); 1322263#L724-1 assume !(0 == ~E_2~0); 1321260#L729-1 assume !(0 == ~E_3~0); 1321261#L734-1 assume !(0 == ~E_4~0); 1322415#L739-1 assume !(0 == ~E_5~0); 1321655#L744-1 assume !(0 == ~E_6~0); 1321656#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1321176#L334 assume !(1 == ~m_pc~0); 1321177#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1321848#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1321659#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1321596#L849 assume !(0 != activate_threads_~tmp~1#1); 1321597#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1321455#L353 assume !(1 == ~t1_pc~0); 1321456#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1322068#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1321202#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1321203#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1324426#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1324421#L372 assume !(1 == ~t2_pc~0); 1324420#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1324419#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1324418#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1324417#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1324416#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1324415#L391 assume !(1 == ~t3_pc~0); 1324414#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1324413#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1324412#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1324411#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1324410#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1324409#L410 assume !(1 == ~t4_pc~0); 1324408#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1324407#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1324406#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1324405#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1324404#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1324403#L429 assume !(1 == ~t5_pc~0); 1321270#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1321271#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1322623#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1322652#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1322186#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1322187#L448 assume !(1 == ~t6_pc~0); 1321420#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1321421#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1322043#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1322044#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1322607#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1322608#L762 assume !(1 == ~M_E~0); 1321690#L762-2 assume !(1 == ~T1_E~0); 1321691#L767-1 assume !(1 == ~T2_E~0); 1322490#L772-1 assume !(1 == ~T3_E~0); 1322491#L777-1 assume !(1 == ~T4_E~0); 1321936#L782-1 assume !(1 == ~T5_E~0); 1321937#L787-1 assume !(1 == ~T6_E~0); 1321315#L792-1 assume !(1 == ~E_M~0); 1321316#L797-1 assume !(1 == ~E_1~0); 1322294#L802-1 assume !(1 == ~E_2~0); 1322295#L807-1 assume !(1 == ~E_3~0); 1322403#L812-1 assume !(1 == ~E_4~0); 1322404#L817-1 assume !(1 == ~E_5~0); 1324225#L822-1 assume !(1 == ~E_6~0); 1324223#L827-1 assume { :end_inline_reset_delta_events } true; 1323800#L1053-2 assume !false; 1323801#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1401231#L659-1 [2023-11-29 04:15:30,108 INFO L750 eck$LassoCheckResult]: Loop: 1401231#L659-1 assume !false; 1408979#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1408975#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1408973#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1408931#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1408924#L570 assume 0 != eval_~tmp~0#1; 1408919#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1408913#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1387141#L578-2 havoc eval_~tmp_ndt_1~0#1; 1387134#L575-1 assume !(0 == ~t1_st~0); 1387135#L589-1 assume !(0 == ~t2_st~0); 1392020#L603-1 assume !(0 == ~t3_st~0); 1392021#L617-1 assume !(0 == ~t4_st~0); 1394141#L631-1 assume !(0 == ~t5_st~0); 1401230#L645-1 assume !(0 == ~t6_st~0); 1401231#L659-1 [2023-11-29 04:15:30,108 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:30,109 INFO L85 PathProgramCache]: Analyzing trace with hash 1466077101, now seen corresponding path program 1 times [2023-11-29 04:15:30,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:30,109 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008546879] [2023-11-29 04:15:30,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:30,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:30,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:30,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:30,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:30,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008546879] [2023-11-29 04:15:30,129 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008546879] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:30,129 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:30,129 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:30,129 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [433595822] [2023-11-29 04:15:30,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:30,130 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:15:30,130 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:30,130 INFO L85 PathProgramCache]: Analyzing trace with hash 1779949543, now seen corresponding path program 2 times [2023-11-29 04:15:30,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:30,130 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428585522] [2023-11-29 04:15:30,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:30,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:30,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:30,134 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:30,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:30,137 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:30,199 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:30,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:30,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:30,200 INFO L87 Difference]: Start difference. First operand 127544 states and 165745 transitions. cyclomatic complexity: 38313 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:30,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:30,335 INFO L93 Difference]: Finished difference Result 83195 states and 108199 transitions. [2023-11-29 04:15:30,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83195 states and 108199 transitions. [2023-11-29 04:15:30,732 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41122 [2023-11-29 04:15:30,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83195 states to 83195 states and 108199 transitions. [2023-11-29 04:15:30,877 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41572 [2023-11-29 04:15:30,894 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41572 [2023-11-29 04:15:30,895 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83195 states and 108199 transitions. [2023-11-29 04:15:30,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 04:15:30,895 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83195 states and 108199 transitions. [2023-11-29 04:15:30,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83195 states and 108199 transitions. [2023-11-29 04:15:31,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83195 to 83195. [2023-11-29 04:15:31,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83195 states, 83195 states have (on average 1.3005469078670593) internal successors, (108199), 83194 states have internal predecessors, (108199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:31,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83195 states to 83195 states and 108199 transitions. [2023-11-29 04:15:31,562 INFO L240 hiAutomatonCegarLoop]: Abstraction has 83195 states and 108199 transitions. [2023-11-29 04:15:31,562 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:31,563 INFO L428 stractBuchiCegarLoop]: Abstraction has 83195 states and 108199 transitions. [2023-11-29 04:15:31,563 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2023-11-29 04:15:31,563 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83195 states and 108199 transitions. [2023-11-29 04:15:31,709 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41122 [2023-11-29 04:15:31,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:31,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:31,710 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:31,710 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:31,710 INFO L748 eck$LassoCheckResult]: Stem: 1532500#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1532501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1532782#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1532783#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1532089#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1532090#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1532780#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1532781#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1532634#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1532204#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1532205#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1532055#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1532056#L684 assume !(0 == ~M_E~0); 1533047#L684-2 assume !(0 == ~T1_E~0); 1532696#L689-1 assume !(0 == ~T2_E~0); 1532697#L694-1 assume !(0 == ~T3_E~0); 1532694#L699-1 assume !(0 == ~T4_E~0); 1532695#L704-1 assume !(0 == ~T5_E~0); 1532598#L709-1 assume !(0 == ~T6_E~0); 1532466#L714-1 assume !(0 == ~E_M~0); 1532467#L719-1 assume !(0 == ~E_1~0); 1532969#L724-1 assume !(0 == ~E_2~0); 1532007#L729-1 assume !(0 == ~E_3~0); 1532008#L734-1 assume !(0 == ~E_4~0); 1533133#L739-1 assume !(0 == ~E_5~0); 1532396#L744-1 assume !(0 == ~E_6~0); 1532397#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1531922#L334 assume !(1 == ~m_pc~0); 1531923#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1532581#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1532398#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1532337#L849 assume !(0 != activate_threads_~tmp~1#1); 1532338#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1532202#L353 assume !(1 == ~t1_pc~0); 1532203#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1532788#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1531949#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1531950#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1532098#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1532099#L372 assume !(1 == ~t2_pc~0); 1532314#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1532357#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1532789#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1532790#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1531902#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1531903#L391 assume !(1 == ~t3_pc~0); 1531753#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1531754#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1531804#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1531805#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1532349#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1532350#L410 assume !(1 == ~t4_pc~0); 1532814#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1532815#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1532124#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1532125#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1532361#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1532362#L429 assume !(1 == ~t5_pc~0); 1532017#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1532018#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1533325#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1532827#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1532828#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1532334#L448 assume !(1 == ~t6_pc~0); 1532168#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1532169#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1532760#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1532761#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1533195#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1533300#L762 assume !(1 == ~M_E~0); 1532430#L762-2 assume !(1 == ~T1_E~0); 1532431#L767-1 assume !(1 == ~T2_E~0); 1533205#L772-1 assume !(1 == ~T3_E~0); 1532898#L777-1 assume !(1 == ~T4_E~0); 1532664#L782-1 assume !(1 == ~T5_E~0); 1532063#L787-1 assume !(1 == ~T6_E~0); 1532061#L792-1 assume !(1 == ~E_M~0); 1532062#L797-1 assume !(1 == ~E_1~0); 1532134#L802-1 assume !(1 == ~E_2~0); 1532590#L807-1 assume !(1 == ~E_3~0); 1532591#L812-1 assume !(1 == ~E_4~0); 1533120#L817-1 assume !(1 == ~E_5~0); 1532698#L822-1 assume !(1 == ~E_6~0); 1532699#L827-1 assume { :end_inline_reset_delta_events } true; 1533148#L1053-2 assume !false; 1536826#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1594390#L659-1 [2023-11-29 04:15:31,711 INFO L750 eck$LassoCheckResult]: Loop: 1594390#L659-1 assume !false; 1594389#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1594387#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1594385#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1594383#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1594381#L570 assume 0 != eval_~tmp~0#1; 1594379#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1594376#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1594377#L578-2 havoc eval_~tmp_ndt_1~0#1; 1594417#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1594414#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 1594413#L592-2 havoc eval_~tmp_ndt_2~0#1; 1594409#L589-1 assume !(0 == ~t2_st~0); 1594403#L603-1 assume !(0 == ~t3_st~0); 1594401#L617-1 assume !(0 == ~t4_st~0); 1594398#L631-1 assume !(0 == ~t5_st~0); 1594393#L645-1 assume !(0 == ~t6_st~0); 1594390#L659-1 [2023-11-29 04:15:31,711 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:31,711 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 2 times [2023-11-29 04:15:31,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:31,711 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1072137335] [2023-11-29 04:15:31,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:31,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:31,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:31,719 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:31,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:31,927 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:31,928 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:31,928 INFO L85 PathProgramCache]: Analyzing trace with hash -1384180882, now seen corresponding path program 1 times [2023-11-29 04:15:31,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:31,928 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517644255] [2023-11-29 04:15:31,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:31,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:31,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:31,933 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:31,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:31,948 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:31,948 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:31,949 INFO L85 PathProgramCache]: Analyzing trace with hash -950945532, now seen corresponding path program 1 times [2023-11-29 04:15:31,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:31,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019647212] [2023-11-29 04:15:31,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:31,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:31,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:31,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:31,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:31,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019647212] [2023-11-29 04:15:31,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2019647212] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:31,995 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:31,995 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:31,995 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [105291919] [2023-11-29 04:15:31,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:32,068 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:32,068 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:32,068 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:32,068 INFO L87 Difference]: Start difference. First operand 83195 states and 108199 transitions. cyclomatic complexity: 25068 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:32,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:32,371 INFO L93 Difference]: Finished difference Result 156359 states and 202435 transitions. [2023-11-29 04:15:32,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 156359 states and 202435 transitions. [2023-11-29 04:15:33,031 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 77284 [2023-11-29 04:15:33,364 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 156359 states to 156359 states and 202435 transitions. [2023-11-29 04:15:33,364 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78090 [2023-11-29 04:15:33,397 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78090 [2023-11-29 04:15:33,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 156359 states and 202435 transitions. [2023-11-29 04:15:33,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 04:15:33,397 INFO L218 hiAutomatonCegarLoop]: Abstraction has 156359 states and 202435 transitions. [2023-11-29 04:15:33,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156359 states and 202435 transitions. [2023-11-29 04:15:34,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156359 to 149079. [2023-11-29 04:15:34,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149079 states, 149079 states have (on average 1.2993043956559944) internal successors, (193699), 149078 states have internal predecessors, (193699), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:34,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149079 states to 149079 states and 193699 transitions. [2023-11-29 04:15:34,924 INFO L240 hiAutomatonCegarLoop]: Abstraction has 149079 states and 193699 transitions. [2023-11-29 04:15:34,925 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:34,926 INFO L428 stractBuchiCegarLoop]: Abstraction has 149079 states and 193699 transitions. [2023-11-29 04:15:34,926 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2023-11-29 04:15:34,926 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 149079 states and 193699 transitions. [2023-11-29 04:15:35,185 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 73644 [2023-11-29 04:15:35,185 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:35,185 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:35,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:35,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:35,186 INFO L748 eck$LassoCheckResult]: Stem: 1772072#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1772073#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1772373#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1772374#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1771648#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1771649#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1772371#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1772372#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1772208#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1771768#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1771769#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1771614#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1771615#L684 assume !(0 == ~M_E~0); 1772652#L684-2 assume !(0 == ~T1_E~0); 1772278#L689-1 assume !(0 == ~T2_E~0); 1772279#L694-1 assume !(0 == ~T3_E~0); 1772276#L699-1 assume !(0 == ~T4_E~0); 1772277#L704-1 assume !(0 == ~T5_E~0); 1772173#L709-1 assume !(0 == ~T6_E~0); 1772037#L714-1 assume !(0 == ~E_M~0); 1772038#L719-1 assume !(0 == ~E_1~0); 1772573#L724-1 assume !(0 == ~E_2~0); 1771567#L729-1 assume !(0 == ~E_3~0); 1771568#L734-1 assume !(0 == ~E_4~0); 1772760#L739-1 assume !(0 == ~E_5~0); 1771967#L744-1 assume !(0 == ~E_6~0); 1771968#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1771483#L334 assume !(1 == ~m_pc~0); 1771484#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1772156#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1771969#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1771905#L849 assume !(0 != activate_threads_~tmp~1#1); 1771906#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1771766#L353 assume !(1 == ~t1_pc~0); 1771767#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1772381#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1771509#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1771510#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1771656#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1771657#L372 assume !(1 == ~t2_pc~0); 1771882#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1771925#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1772382#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1772383#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1771462#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1771463#L391 assume !(1 == ~t3_pc~0); 1771315#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1771316#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1771364#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1771365#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1771917#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1771918#L410 assume !(1 == ~t4_pc~0); 1772409#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1772410#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1771688#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1771689#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1771929#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1771930#L429 assume !(1 == ~t5_pc~0); 1771577#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1771578#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1773005#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1772421#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1772422#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1771900#L448 assume !(1 == ~t6_pc~0); 1771731#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1771732#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1772348#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1772349#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1772827#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1772979#L762 assume !(1 == ~M_E~0); 1772000#L762-2 assume !(1 == ~T1_E~0); 1772001#L767-1 assume !(1 == ~T2_E~0); 1772846#L772-1 assume !(1 == ~T3_E~0); 1772496#L777-1 assume !(1 == ~T4_E~0); 1772244#L782-1 assume !(1 == ~T5_E~0); 1771622#L787-1 assume !(1 == ~T6_E~0); 1771620#L792-1 assume !(1 == ~E_M~0); 1771621#L797-1 assume !(1 == ~E_1~0); 1771698#L802-1 assume !(1 == ~E_2~0); 1772165#L807-1 assume !(1 == ~E_3~0); 1772166#L812-1 assume !(1 == ~E_4~0); 1772747#L817-1 assume !(1 == ~E_5~0); 1772280#L822-1 assume !(1 == ~E_6~0); 1772281#L827-1 assume { :end_inline_reset_delta_events } true; 1772776#L1053-2 assume !false; 1785193#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1881719#L659-1 [2023-11-29 04:15:35,186 INFO L750 eck$LassoCheckResult]: Loop: 1881719#L659-1 assume !false; 1881717#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1881715#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1881713#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1881711#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1881709#L570 assume 0 != eval_~tmp~0#1; 1881707#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1881704#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1881705#L578-2 havoc eval_~tmp_ndt_1~0#1; 1881789#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1881786#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 1881784#L592-2 havoc eval_~tmp_ndt_2~0#1; 1881782#L589-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1881779#L606 assume !(0 != eval_~tmp_ndt_3~0#1); 1881777#L606-2 havoc eval_~tmp_ndt_3~0#1; 1881762#L603-1 assume !(0 == ~t3_st~0); 1881759#L617-1 assume !(0 == ~t4_st~0); 1881755#L631-1 assume !(0 == ~t5_st~0); 1881724#L645-1 assume !(0 == ~t6_st~0); 1881719#L659-1 [2023-11-29 04:15:35,186 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:35,186 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 3 times [2023-11-29 04:15:35,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:35,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333021144] [2023-11-29 04:15:35,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:35,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:35,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:35,194 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:35,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:35,215 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:35,215 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:35,215 INFO L85 PathProgramCache]: Analyzing trace with hash 1160850791, now seen corresponding path program 1 times [2023-11-29 04:15:35,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:35,215 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098231372] [2023-11-29 04:15:35,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:35,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:35,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:35,219 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:35,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:35,223 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:35,223 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:35,223 INFO L85 PathProgramCache]: Analyzing trace with hash 888194429, now seen corresponding path program 1 times [2023-11-29 04:15:35,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:35,223 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764930770] [2023-11-29 04:15:35,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:35,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:35,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:35,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:35,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:35,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764930770] [2023-11-29 04:15:35,261 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764930770] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:35,261 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:35,261 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:35,261 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [702150] [2023-11-29 04:15:35,261 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:35,340 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:35,340 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:35,340 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:35,340 INFO L87 Difference]: Start difference. First operand 149079 states and 193699 transitions. cyclomatic complexity: 44684 Second operand has 3 states, 3 states have (on average 35.0) internal successors, (105), 3 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:35,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:35,933 INFO L93 Difference]: Finished difference Result 187735 states and 242587 transitions. [2023-11-29 04:15:35,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 187735 states and 242587 transitions. [2023-11-29 04:15:36,515 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 92768 [2023-11-29 04:15:37,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 187735 states to 187735 states and 242587 transitions. [2023-11-29 04:15:37,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 93782 [2023-11-29 04:15:37,071 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 93782 [2023-11-29 04:15:37,071 INFO L73 IsDeterministic]: Start isDeterministic. Operand 187735 states and 242587 transitions. [2023-11-29 04:15:37,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 04:15:37,074 INFO L218 hiAutomatonCegarLoop]: Abstraction has 187735 states and 242587 transitions. [2023-11-29 04:15:37,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187735 states and 242587 transitions. [2023-11-29 04:15:38,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187735 to 181495. [2023-11-29 04:15:38,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 181495 states, 181495 states have (on average 1.295346979255627) internal successors, (235099), 181494 states have internal predecessors, (235099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:38,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 181495 states to 181495 states and 235099 transitions. [2023-11-29 04:15:38,685 INFO L240 hiAutomatonCegarLoop]: Abstraction has 181495 states and 235099 transitions. [2023-11-29 04:15:38,685 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:38,685 INFO L428 stractBuchiCegarLoop]: Abstraction has 181495 states and 235099 transitions. [2023-11-29 04:15:38,685 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2023-11-29 04:15:38,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 181495 states and 235099 transitions. [2023-11-29 04:15:39,007 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 89648 [2023-11-29 04:15:39,007 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:39,007 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:39,008 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:39,008 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:39,008 INFO L748 eck$LassoCheckResult]: Stem: 2108900#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2108901#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2109223#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2109224#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2108473#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 2108474#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2109217#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2109218#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2109046#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2108591#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2108592#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2108443#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2108444#L684 assume !(0 == ~M_E~0); 2109504#L684-2 assume !(0 == ~T1_E~0); 2109119#L689-1 assume !(0 == ~T2_E~0); 2109120#L694-1 assume !(0 == ~T3_E~0); 2109117#L699-1 assume !(0 == ~T4_E~0); 2109118#L704-1 assume !(0 == ~T5_E~0); 2109007#L709-1 assume !(0 == ~T6_E~0); 2108860#L714-1 assume !(0 == ~E_M~0); 2108861#L719-1 assume !(0 == ~E_1~0); 2109426#L724-1 assume !(0 == ~E_2~0); 2108388#L729-1 assume !(0 == ~E_3~0); 2108389#L734-1 assume !(0 == ~E_4~0); 2109602#L739-1 assume !(0 == ~E_5~0); 2108789#L744-1 assume !(0 == ~E_6~0); 2108790#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2108303#L334 assume !(1 == ~m_pc~0); 2108304#L334-2 is_master_triggered_~__retres1~0#1 := 0; 2108990#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2108791#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2108731#L849 assume !(0 != activate_threads_~tmp~1#1); 2108732#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2108589#L353 assume !(1 == ~t1_pc~0); 2108590#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2109225#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2108329#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2108330#L857 assume !(0 != activate_threads_~tmp___0~0#1); 2108482#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2108483#L372 assume !(1 == ~t2_pc~0); 2108706#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2108750#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2109226#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2109227#L865 assume !(0 != activate_threads_~tmp___1~0#1); 2108282#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2108283#L391 assume !(1 == ~t3_pc~0); 2108137#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2108138#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2108186#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2108187#L873 assume !(0 != activate_threads_~tmp___2~0#1); 2108743#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2108744#L410 assume !(1 == ~t4_pc~0); 2109255#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2109256#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2108513#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2108514#L881 assume !(0 != activate_threads_~tmp___3~0#1); 2108753#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2108754#L429 assume !(1 == ~t5_pc~0); 2108398#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2108399#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2109839#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2109266#L889 assume !(0 != activate_threads_~tmp___4~0#1); 2109267#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2108726#L448 assume !(1 == ~t6_pc~0); 2108556#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2108557#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2109199#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2109200#L897 assume !(0 != activate_threads_~tmp___5~0#1); 2109669#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2109812#L762 assume !(1 == ~M_E~0); 2108822#L762-2 assume !(1 == ~T1_E~0); 2108823#L767-1 assume !(1 == ~T2_E~0); 2109684#L772-1 assume !(1 == ~T3_E~0); 2109342#L777-1 assume !(1 == ~T4_E~0); 2109078#L782-1 assume !(1 == ~T5_E~0); 2108447#L787-1 assume !(1 == ~T6_E~0); 2108445#L792-1 assume !(1 == ~E_M~0); 2108446#L797-1 assume !(1 == ~E_1~0); 2108525#L802-1 assume !(1 == ~E_2~0); 2108999#L807-1 assume !(1 == ~E_3~0); 2109000#L812-1 assume !(1 == ~E_4~0); 2109588#L817-1 assume !(1 == ~E_5~0); 2109121#L822-1 assume !(1 == ~E_6~0); 2109122#L827-1 assume { :end_inline_reset_delta_events } true; 2109615#L1053-2 assume !false; 2140104#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2140100#L659-1 [2023-11-29 04:15:39,008 INFO L750 eck$LassoCheckResult]: Loop: 2140100#L659-1 assume !false; 2140098#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2140095#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2140093#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2140091#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2140090#L570 assume 0 != eval_~tmp~0#1; 2140089#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2140087#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 2140088#L578-2 havoc eval_~tmp_ndt_1~0#1; 2140129#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2140127#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 2140125#L592-2 havoc eval_~tmp_ndt_2~0#1; 2140124#L589-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2133124#L606 assume !(0 != eval_~tmp_ndt_3~0#1); 2140120#L606-2 havoc eval_~tmp_ndt_3~0#1; 2140118#L603-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 2140115#L620 assume !(0 != eval_~tmp_ndt_4~0#1); 2140114#L620-2 havoc eval_~tmp_ndt_4~0#1; 2140110#L617-1 assume !(0 == ~t4_st~0); 2140107#L631-1 assume !(0 == ~t5_st~0); 2140102#L645-1 assume !(0 == ~t6_st~0); 2140100#L659-1 [2023-11-29 04:15:39,008 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:39,008 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 4 times [2023-11-29 04:15:39,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:39,009 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903503015] [2023-11-29 04:15:39,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:39,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:39,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:39,017 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:39,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:39,037 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:39,038 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:39,038 INFO L85 PathProgramCache]: Analyzing trace with hash 1515958958, now seen corresponding path program 1 times [2023-11-29 04:15:39,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:39,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552735439] [2023-11-29 04:15:39,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:39,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:39,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:39,041 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:39,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:39,045 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:39,045 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:39,045 INFO L85 PathProgramCache]: Analyzing trace with hash 1486200132, now seen corresponding path program 1 times [2023-11-29 04:15:39,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:39,046 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398429504] [2023-11-29 04:15:39,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:39,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:39,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:39,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:39,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:39,082 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [398429504] [2023-11-29 04:15:39,082 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [398429504] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:39,082 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:39,083 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:39,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [701695982] [2023-11-29 04:15:39,083 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:39,165 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:39,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:39,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:39,166 INFO L87 Difference]: Start difference. First operand 181495 states and 235099 transitions. cyclomatic complexity: 53668 Second operand has 3 states, 3 states have (on average 35.666666666666664) internal successors, (107), 3 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:39,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:39,996 INFO L93 Difference]: Finished difference Result 222431 states and 285877 transitions. [2023-11-29 04:15:39,996 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 222431 states and 285877 transitions. [2023-11-29 04:15:40,985 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 109926 [2023-11-29 04:15:41,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 222431 states to 222431 states and 285877 transitions. [2023-11-29 04:15:41,388 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 111164 [2023-11-29 04:15:41,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 111164 [2023-11-29 04:15:41,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 222431 states and 285877 transitions. [2023-11-29 04:15:41,438 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 04:15:41,438 INFO L218 hiAutomatonCegarLoop]: Abstraction has 222431 states and 285877 transitions. [2023-11-29 04:15:41,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222431 states and 285877 transitions. [2023-11-29 04:15:43,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222431 to 222431. [2023-11-29 04:15:43,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 222431 states, 222431 states have (on average 1.285239017942643) internal successors, (285877), 222430 states have internal predecessors, (285877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:43,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222431 states to 222431 states and 285877 transitions. [2023-11-29 04:15:43,454 INFO L240 hiAutomatonCegarLoop]: Abstraction has 222431 states and 285877 transitions. [2023-11-29 04:15:43,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:43,454 INFO L428 stractBuchiCegarLoop]: Abstraction has 222431 states and 285877 transitions. [2023-11-29 04:15:43,455 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2023-11-29 04:15:43,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 222431 states and 285877 transitions. [2023-11-29 04:15:44,269 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 109926 [2023-11-29 04:15:44,269 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:44,269 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:44,270 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:44,270 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:44,271 INFO L748 eck$LassoCheckResult]: Stem: 2512829#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2512830#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2513118#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2513119#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2512409#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 2512410#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2513116#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2513117#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2512965#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2512522#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2512523#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2512375#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2512376#L684 assume !(0 == ~M_E~0); 2513401#L684-2 assume !(0 == ~T1_E~0); 2513030#L689-1 assume !(0 == ~T2_E~0); 2513031#L694-1 assume !(0 == ~T3_E~0); 2513028#L699-1 assume !(0 == ~T4_E~0); 2513029#L704-1 assume !(0 == ~T5_E~0); 2512930#L709-1 assume !(0 == ~T6_E~0); 2512792#L714-1 assume !(0 == ~E_M~0); 2512793#L719-1 assume !(0 == ~E_1~0); 2513322#L724-1 assume !(0 == ~E_2~0); 2512325#L729-1 assume !(0 == ~E_3~0); 2512326#L734-1 assume !(0 == ~E_4~0); 2513501#L739-1 assume !(0 == ~E_5~0); 2512721#L744-1 assume !(0 == ~E_6~0); 2512722#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2512240#L334 assume !(1 == ~m_pc~0); 2512241#L334-2 is_master_triggered_~__retres1~0#1 := 0; 2512913#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2512724#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2512664#L849 assume !(0 != activate_threads_~tmp~1#1); 2512665#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2512520#L353 assume !(1 == ~t1_pc~0); 2512521#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2513125#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2512266#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2512267#L857 assume !(0 != activate_threads_~tmp___0~0#1); 2512418#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2512419#L372 assume !(1 == ~t2_pc~0); 2512639#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2512683#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2513126#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2513127#L865 assume !(0 != activate_threads_~tmp___1~0#1); 2512220#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2512221#L391 assume !(1 == ~t3_pc~0); 2512071#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2512072#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2512123#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2512124#L873 assume !(0 != activate_threads_~tmp___2~0#1); 2512674#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2512675#L410 assume !(1 == ~t4_pc~0); 2513155#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2513156#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2512446#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2512447#L881 assume !(0 != activate_threads_~tmp___3~0#1); 2512686#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2512687#L429 assume !(1 == ~t5_pc~0); 2512335#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2512336#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2513725#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2513168#L889 assume !(0 != activate_threads_~tmp___4~0#1); 2513169#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2512660#L448 assume !(1 == ~t6_pc~0); 2512487#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2512488#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2513097#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2513098#L897 assume !(0 != activate_threads_~tmp___5~0#1); 2513565#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2513698#L762 assume !(1 == ~M_E~0); 2512753#L762-2 assume !(1 == ~T1_E~0); 2512754#L767-1 assume !(1 == ~T2_E~0); 2513576#L772-1 assume !(1 == ~T3_E~0); 2513242#L777-1 assume !(1 == ~T4_E~0); 2512996#L782-1 assume !(1 == ~T5_E~0); 2512383#L787-1 assume !(1 == ~T6_E~0); 2512381#L792-1 assume !(1 == ~E_M~0); 2512382#L797-1 assume !(1 == ~E_1~0); 2512454#L802-1 assume !(1 == ~E_2~0); 2512922#L807-1 assume !(1 == ~E_3~0); 2512923#L812-1 assume !(1 == ~E_4~0); 2513488#L817-1 assume !(1 == ~E_5~0); 2513032#L822-1 assume !(1 == ~E_6~0); 2513033#L827-1 assume { :end_inline_reset_delta_events } true; 2513517#L1053-2 assume !false; 2528584#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2620575#L659-1 [2023-11-29 04:15:44,271 INFO L750 eck$LassoCheckResult]: Loop: 2620575#L659-1 assume !false; 2620573#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2620571#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2620570#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2620569#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2620567#L570 assume 0 != eval_~tmp~0#1; 2620566#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2620564#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 2620565#L578-2 havoc eval_~tmp_ndt_1~0#1; 2621179#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2621176#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 2621173#L592-2 havoc eval_~tmp_ndt_2~0#1; 2620606#L589-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2620603#L606 assume !(0 != eval_~tmp_ndt_3~0#1); 2620601#L606-2 havoc eval_~tmp_ndt_3~0#1; 2620600#L603-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 2620599#L620 assume !(0 != eval_~tmp_ndt_4~0#1); 2620597#L620-2 havoc eval_~tmp_ndt_4~0#1; 2620594#L617-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 2620591#L634 assume !(0 != eval_~tmp_ndt_5~0#1); 2620589#L634-2 havoc eval_~tmp_ndt_5~0#1; 2620584#L631-1 assume !(0 == ~t5_st~0); 2620579#L645-1 assume !(0 == ~t6_st~0); 2620575#L659-1 [2023-11-29 04:15:44,271 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:44,271 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 5 times [2023-11-29 04:15:44,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:44,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170465210] [2023-11-29 04:15:44,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:44,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:44,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:44,282 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:44,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:44,305 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:44,305 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:44,305 INFO L85 PathProgramCache]: Analyzing trace with hash 650449639, now seen corresponding path program 1 times [2023-11-29 04:15:44,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:44,306 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1496372662] [2023-11-29 04:15:44,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:44,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:44,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:44,310 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:44,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:44,315 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:44,315 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:44,316 INFO L85 PathProgramCache]: Analyzing trace with hash 2116988925, now seen corresponding path program 1 times [2023-11-29 04:15:44,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:44,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964557880] [2023-11-29 04:15:44,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:44,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:44,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:44,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:44,363 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:44,363 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1964557880] [2023-11-29 04:15:44,363 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1964557880] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:44,364 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:44,364 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:15:44,364 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1840424130] [2023-11-29 04:15:44,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:44,449 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:44,450 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:44,450 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:44,450 INFO L87 Difference]: Start difference. First operand 222431 states and 285877 transitions. cyclomatic complexity: 63510 Second operand has 3 states, 3 states have (on average 36.333333333333336) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:45,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:45,775 INFO L93 Difference]: Finished difference Result 398555 states and 510839 transitions. [2023-11-29 04:15:45,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 398555 states and 510839 transitions. [2023-11-29 04:15:47,168 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 196748 [2023-11-29 04:15:48,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 398555 states to 398555 states and 510839 transitions. [2023-11-29 04:15:48,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 199130 [2023-11-29 04:15:48,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 199130 [2023-11-29 04:15:48,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 398555 states and 510839 transitions. [2023-11-29 04:15:48,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 04:15:48,100 INFO L218 hiAutomatonCegarLoop]: Abstraction has 398555 states and 510839 transitions. [2023-11-29 04:15:48,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 398555 states and 510839 transitions. [2023-11-29 04:15:51,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 398555 to 389243. [2023-11-29 04:15:51,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389243 states, 389243 states have (on average 1.2854771954794306) internal successors, (500363), 389242 states have internal predecessors, (500363), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:52,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389243 states to 389243 states and 500363 transitions. [2023-11-29 04:15:52,069 INFO L240 hiAutomatonCegarLoop]: Abstraction has 389243 states and 500363 transitions. [2023-11-29 04:15:52,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:15:52,070 INFO L428 stractBuchiCegarLoop]: Abstraction has 389243 states and 500363 transitions. [2023-11-29 04:15:52,070 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2023-11-29 04:15:52,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389243 states and 500363 transitions. [2023-11-29 04:15:53,289 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 192092 [2023-11-29 04:15:53,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:15:53,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:15:53,290 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:53,290 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:15:53,290 INFO L748 eck$LassoCheckResult]: Stem: 3133822#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3133823#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3134137#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3134138#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3133403#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 3133404#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3134135#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3134136#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3133970#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3133513#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3133514#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3133369#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3133370#L684 assume !(0 == ~M_E~0); 3134452#L684-2 assume !(0 == ~T1_E~0); 3134038#L689-1 assume !(0 == ~T2_E~0); 3134039#L694-1 assume !(0 == ~T3_E~0); 3134036#L699-1 assume !(0 == ~T4_E~0); 3134037#L704-1 assume !(0 == ~T5_E~0); 3133925#L709-1 assume !(0 == ~T6_E~0); 3133784#L714-1 assume !(0 == ~E_M~0); 3133785#L719-1 assume !(0 == ~E_1~0); 3134357#L724-1 assume !(0 == ~E_2~0); 3133316#L729-1 assume !(0 == ~E_3~0); 3133317#L734-1 assume !(0 == ~E_4~0); 3134552#L739-1 assume !(0 == ~E_5~0); 3133708#L744-1 assume !(0 == ~E_6~0); 3133709#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3133231#L334 assume !(1 == ~m_pc~0); 3133232#L334-2 is_master_triggered_~__retres1~0#1 := 0; 3133908#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3133710#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3133653#L849 assume !(0 != activate_threads_~tmp~1#1); 3133654#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3133511#L353 assume !(1 == ~t1_pc~0); 3133512#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3134145#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3133257#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3133258#L857 assume !(0 != activate_threads_~tmp___0~0#1); 3133412#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3133413#L372 assume !(1 == ~t2_pc~0); 3133629#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3133670#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3134146#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3134147#L865 assume !(0 != activate_threads_~tmp___1~0#1); 3133211#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3133212#L391 assume !(1 == ~t3_pc~0); 3133065#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3133066#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3133115#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3133116#L873 assume !(0 != activate_threads_~tmp___2~0#1); 3133663#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3133664#L410 assume !(1 == ~t4_pc~0); 3134178#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3134179#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3133440#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3133441#L881 assume !(0 != activate_threads_~tmp___3~0#1); 3133674#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3133675#L429 assume !(1 == ~t5_pc~0); 3133326#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3133327#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3134782#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3134192#L889 assume !(0 != activate_threads_~tmp___4~0#1); 3134193#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3133649#L448 assume !(1 == ~t6_pc~0); 3133478#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3133479#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3134112#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3134113#L897 assume !(0 != activate_threads_~tmp___5~0#1); 3134626#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3134750#L762 assume !(1 == ~M_E~0); 3133745#L762-2 assume !(1 == ~T1_E~0); 3133746#L767-1 assume !(1 == ~T2_E~0); 3134640#L772-1 assume !(1 == ~T3_E~0); 3134271#L777-1 assume !(1 == ~T4_E~0); 3134003#L782-1 assume !(1 == ~T5_E~0); 3133377#L787-1 assume !(1 == ~T6_E~0); 3133375#L792-1 assume !(1 == ~E_M~0); 3133376#L797-1 assume !(1 == ~E_1~0); 3133448#L802-1 assume !(1 == ~E_2~0); 3133917#L807-1 assume !(1 == ~E_3~0); 3133918#L812-1 assume !(1 == ~E_4~0); 3134539#L817-1 assume !(1 == ~E_5~0); 3134040#L822-1 assume !(1 == ~E_6~0); 3134041#L827-1 assume { :end_inline_reset_delta_events } true; 3134564#L1053-2 assume !false; 3219669#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3219664#L659-1 [2023-11-29 04:15:53,290 INFO L750 eck$LassoCheckResult]: Loop: 3219664#L659-1 assume !false; 3219662#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3219660#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3219658#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3219656#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3219654#L570 assume 0 != eval_~tmp~0#1; 3219652#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 3219648#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 3219649#L578-2 havoc eval_~tmp_ndt_1~0#1; 3220746#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 3220744#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 3220740#L592-2 havoc eval_~tmp_ndt_2~0#1; 3219723#L589-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 3219720#L606 assume !(0 != eval_~tmp_ndt_3~0#1); 3219718#L606-2 havoc eval_~tmp_ndt_3~0#1; 3219714#L603-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 3219711#L620 assume !(0 != eval_~tmp_ndt_4~0#1); 3219709#L620-2 havoc eval_~tmp_ndt_4~0#1; 3219707#L617-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 3219703#L634 assume !(0 != eval_~tmp_ndt_5~0#1); 3219701#L634-2 havoc eval_~tmp_ndt_5~0#1; 3219699#L631-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 3219696#L648 assume !(0 != eval_~tmp_ndt_6~0#1); 3219694#L648-2 havoc eval_~tmp_ndt_6~0#1; 3219667#L645-1 assume !(0 == ~t6_st~0); 3219664#L659-1 [2023-11-29 04:15:53,290 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:53,291 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 6 times [2023-11-29 04:15:53,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:53,291 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1136864552] [2023-11-29 04:15:53,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:53,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:53,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:53,298 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:53,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:53,316 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:53,316 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:53,317 INFO L85 PathProgramCache]: Analyzing trace with hash -1989256722, now seen corresponding path program 1 times [2023-11-29 04:15:53,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:53,317 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1237039294] [2023-11-29 04:15:53,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:53,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:53,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:53,321 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:15:53,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:15:53,325 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:15:53,325 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:15:53,326 INFO L85 PathProgramCache]: Analyzing trace with hash -1394275964, now seen corresponding path program 1 times [2023-11-29 04:15:53,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:15:53,326 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715695905] [2023-11-29 04:15:53,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:15:53,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:15:53,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:15:53,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:15:53,364 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:15:53,364 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715695905] [2023-11-29 04:15:53,364 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1715695905] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:15:53,364 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:15:53,364 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:15:53,364 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1885059057] [2023-11-29 04:15:53,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:15:53,454 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:15:53,455 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:15:53,455 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:15:53,455 INFO L87 Difference]: Start difference. First operand 389243 states and 500363 transitions. cyclomatic complexity: 111184 Second operand has 3 states, 2 states have (on average 55.5) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:15:54,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:15:54,756 INFO L93 Difference]: Finished difference Result 512863 states and 656595 transitions. [2023-11-29 04:15:54,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 512863 states and 656595 transitions. [2023-11-29 04:15:56,989 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 253275 [2023-11-29 04:15:58,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 512863 states to 512863 states and 656595 transitions. [2023-11-29 04:15:58,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 256285 [2023-11-29 04:15:58,373 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 256285 [2023-11-29 04:15:58,374 INFO L73 IsDeterministic]: Start isDeterministic. Operand 512863 states and 656595 transitions. [2023-11-29 04:15:58,375 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 04:15:58,375 INFO L218 hiAutomatonCegarLoop]: Abstraction has 512863 states and 656595 transitions. [2023-11-29 04:15:58,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 512863 states and 656595 transitions. [2023-11-29 04:16:02,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 512863 to 509759. [2023-11-29 04:16:02,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 509759 states, 509759 states have (on average 1.2819606912286001) internal successors, (653491), 509758 states have internal predecessors, (653491), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:16:04,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 509759 states to 509759 states and 653491 transitions. [2023-11-29 04:16:04,233 INFO L240 hiAutomatonCegarLoop]: Abstraction has 509759 states and 653491 transitions. [2023-11-29 04:16:04,233 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:16:04,234 INFO L428 stractBuchiCegarLoop]: Abstraction has 509759 states and 653491 transitions. [2023-11-29 04:16:04,234 INFO L335 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2023-11-29 04:16:04,234 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 509759 states and 653491 transitions. [2023-11-29 04:16:05,273 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 251723 [2023-11-29 04:16:05,273 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:16:05,273 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:16:05,274 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:16:05,274 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:16:05,274 INFO L748 eck$LassoCheckResult]: Stem: 4035941#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4035942#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4036259#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4036260#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4035520#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 4035521#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4036257#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4036258#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4036082#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4035639#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4035640#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4035486#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4035487#L684 assume !(0 == ~M_E~0); 4036572#L684-2 assume !(0 == ~T1_E~0); 4036163#L689-1 assume !(0 == ~T2_E~0); 4036164#L694-1 assume !(0 == ~T3_E~0); 4036161#L699-1 assume !(0 == ~T4_E~0); 4036162#L704-1 assume !(0 == ~T5_E~0); 4036044#L709-1 assume !(0 == ~T6_E~0); 4035901#L714-1 assume !(0 == ~E_M~0); 4035902#L719-1 assume !(0 == ~E_1~0); 4036475#L724-1 assume !(0 == ~E_2~0); 4035432#L729-1 assume !(0 == ~E_3~0); 4035433#L734-1 assume !(0 == ~E_4~0); 4036675#L739-1 assume !(0 == ~E_5~0); 4035830#L744-1 assume !(0 == ~E_6~0); 4035831#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4035348#L334 assume !(1 == ~m_pc~0); 4035349#L334-2 is_master_triggered_~__retres1~0#1 := 0; 4036027#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4035832#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4035771#L849 assume !(0 != activate_threads_~tmp~1#1); 4035772#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4035637#L353 assume !(1 == ~t1_pc~0); 4035638#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4036267#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4035374#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4035375#L857 assume !(0 != activate_threads_~tmp___0~0#1); 4035529#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4035530#L372 assume !(1 == ~t2_pc~0); 4035746#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4035791#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4036013#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4036268#L865 assume !(0 != activate_threads_~tmp___1~0#1); 4035327#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4035328#L391 assume !(1 == ~t3_pc~0); 4035179#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4035180#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4035230#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4035231#L873 assume !(0 != activate_threads_~tmp___2~0#1); 4035781#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4035782#L410 assume !(1 == ~t4_pc~0); 4036297#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4036298#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4035558#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4035559#L881 assume !(0 != activate_threads_~tmp___3~0#1); 4035794#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4035795#L429 assume !(1 == ~t5_pc~0); 4035442#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4035443#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4035854#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4035855#L889 assume !(0 != activate_threads_~tmp___4~0#1); 4036314#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4035767#L448 assume !(1 == ~t6_pc~0); 4035601#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4035602#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4036236#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4036237#L897 assume !(0 != activate_threads_~tmp___5~0#1); 4036749#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4036900#L762 assume !(1 == ~M_E~0); 4035864#L762-2 assume !(1 == ~T1_E~0); 4035865#L767-1 assume !(1 == ~T2_E~0); 4036760#L772-1 assume !(1 == ~T3_E~0); 4036389#L777-1 assume !(1 == ~T4_E~0); 4036118#L782-1 assume !(1 == ~T5_E~0); 4035494#L787-1 assume !(1 == ~T6_E~0); 4035492#L792-1 assume !(1 == ~E_M~0); 4035493#L797-1 assume !(1 == ~E_1~0); 4035568#L802-1 assume !(1 == ~E_2~0); 4036036#L807-1 assume !(1 == ~E_3~0); 4036037#L812-1 assume !(1 == ~E_4~0); 4036660#L817-1 assume !(1 == ~E_5~0); 4036165#L822-1 assume !(1 == ~E_6~0); 4036166#L827-1 assume { :end_inline_reset_delta_events } true; 4036691#L1053-2 assume !false; 4151952#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4268173#L659-1 [2023-11-29 04:16:05,274 INFO L750 eck$LassoCheckResult]: Loop: 4268173#L659-1 assume !false; 4268171#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4268169#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4268168#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4268167#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4268166#L570 assume 0 != eval_~tmp~0#1; 4268165#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 4268163#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 4268160#L578-2 havoc eval_~tmp_ndt_1~0#1; 4268158#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 4268155#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 4268153#L592-2 havoc eval_~tmp_ndt_2~0#1; 4267386#L589-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 4267384#L606 assume !(0 != eval_~tmp_ndt_3~0#1); 4267383#L606-2 havoc eval_~tmp_ndt_3~0#1; 4267382#L603-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 4267379#L620 assume !(0 != eval_~tmp_ndt_4~0#1); 4267377#L620-2 havoc eval_~tmp_ndt_4~0#1; 4267375#L617-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 4267373#L634 assume !(0 != eval_~tmp_ndt_5~0#1); 4267374#L634-2 havoc eval_~tmp_ndt_5~0#1; 4267756#L631-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 4267721#L648 assume !(0 != eval_~tmp_ndt_6~0#1); 4267754#L648-2 havoc eval_~tmp_ndt_6~0#1; 4269117#L645-1 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;havoc eval_#t~nondet12#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 4269115#L662 assume !(0 != eval_~tmp_ndt_7~0#1); 4268175#L662-2 havoc eval_~tmp_ndt_7~0#1; 4268173#L659-1 [2023-11-29 04:16:05,274 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:16:05,274 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 7 times [2023-11-29 04:16:05,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:16:05,274 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113841704] [2023-11-29 04:16:05,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:16:05,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:16:05,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:16:05,284 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:16:05,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:16:05,304 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:16:05,304 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:16:05,304 INFO L85 PathProgramCache]: Analyzing trace with hash -415395737, now seen corresponding path program 1 times [2023-11-29 04:16:05,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:16:05,304 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903553638] [2023-11-29 04:16:05,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:16:05,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:16:05,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:16:05,308 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:16:05,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:16:05,312 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:16:05,313 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:16:05,313 INFO L85 PathProgramCache]: Analyzing trace with hash 130462333, now seen corresponding path program 1 times [2023-11-29 04:16:05,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:16:05,313 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1620190004] [2023-11-29 04:16:05,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:16:05,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:16:05,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:16:05,323 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:16:05,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:16:05,363 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:16:07,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:16:07,328 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:16:07,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:16:07,571 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 29.11 04:16:07 BoogieIcfgContainer [2023-11-29 04:16:07,571 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-29 04:16:07,572 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-29 04:16:07,572 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-29 04:16:07,572 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-29 04:16:07,573 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 04:15:00" (3/4) ... [2023-11-29 04:16:07,575 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-29 04:16:07,721 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/witness.graphml [2023-11-29 04:16:07,721 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-29 04:16:07,722 INFO L158 Benchmark]: Toolchain (without parser) took 68533.72ms. Allocated memory was 148.9MB in the beginning and 14.9GB in the end (delta: 14.7GB). Free memory was 111.2MB in the beginning and 7.3GB in the end (delta: -7.2GB). Peak memory consumption was 7.6GB. Max. memory is 16.1GB. [2023-11-29 04:16:07,722 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 111.1MB. Free memory is still 84.6MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-29 04:16:07,723 INFO L158 Benchmark]: CACSL2BoogieTranslator took 353.74ms. Allocated memory is still 148.9MB. Free memory was 110.8MB in the beginning and 93.4MB in the end (delta: 17.3MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2023-11-29 04:16:07,724 INFO L158 Benchmark]: Boogie Procedure Inliner took 77.56ms. Allocated memory is still 148.9MB. Free memory was 93.4MB in the beginning and 87.6MB in the end (delta: 5.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-29 04:16:07,724 INFO L158 Benchmark]: Boogie Preprocessor took 112.13ms. Allocated memory is still 148.9MB. Free memory was 87.2MB in the beginning and 79.7MB in the end (delta: 7.5MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-29 04:16:07,724 INFO L158 Benchmark]: RCFGBuilder took 1160.49ms. Allocated memory is still 148.9MB. Free memory was 79.7MB in the beginning and 107.2MB in the end (delta: -27.5MB). Peak memory consumption was 31.2MB. Max. memory is 16.1GB. [2023-11-29 04:16:07,725 INFO L158 Benchmark]: BuchiAutomizer took 66674.73ms. Allocated memory was 148.9MB in the beginning and 14.9GB in the end (delta: 14.7GB). Free memory was 107.2MB in the beginning and 7.3GB in the end (delta: -7.2GB). Peak memory consumption was 7.5GB. Max. memory is 16.1GB. [2023-11-29 04:16:07,725 INFO L158 Benchmark]: Witness Printer took 149.59ms. Allocated memory is still 14.9GB. Free memory was 7.3GB in the beginning and 7.3GB in the end (delta: 15.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2023-11-29 04:16:07,730 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 111.1MB. Free memory is still 84.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 353.74ms. Allocated memory is still 148.9MB. Free memory was 110.8MB in the beginning and 93.4MB in the end (delta: 17.3MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 77.56ms. Allocated memory is still 148.9MB. Free memory was 93.4MB in the beginning and 87.6MB in the end (delta: 5.8MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 112.13ms. Allocated memory is still 148.9MB. Free memory was 87.2MB in the beginning and 79.7MB in the end (delta: 7.5MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 1160.49ms. Allocated memory is still 148.9MB. Free memory was 79.7MB in the beginning and 107.2MB in the end (delta: -27.5MB). Peak memory consumption was 31.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 66674.73ms. Allocated memory was 148.9MB in the beginning and 14.9GB in the end (delta: 14.7GB). Free memory was 107.2MB in the beginning and 7.3GB in the end (delta: -7.2GB). Peak memory consumption was 7.5GB. Max. memory is 16.1GB. * Witness Printer took 149.59ms. Allocated memory is still 14.9GB. Free memory was 7.3GB in the beginning and 7.3GB in the end (delta: 15.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 36 terminating modules (35 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function ((-1 * T5_E) + 1) and consists of 3 locations. 35 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 509759 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 66.4s and 36 iterations. TraceHistogramMax:2. Analysis of lassos took 10.7s. Construction of modules took 1.3s. Büchi inclusion checks took 47.4s. Highest rank in rank-based complementation 3. Minimization of det autom 26. Minimization of nondet autom 10. Automata minimization 23.6s AutomataMinimizationTime, 36 MinimizatonAttempts, 191900 StatesRemovedByMinimization, 27 NontrivialMinimizations. Non-live state removal took 15.1s Buchi closure took 0.6s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 40510 SdHoareTripleChecker+Valid, 1.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 40509 mSDsluCounter, 84064 SdHoareTripleChecker+Invalid, 1.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 42426 mSDsCounter, 539 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1595 IncrementalHoareTripleChecker+Invalid, 2134 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 539 mSolverCounterUnsat, 41638 mSDtfsCounter, 1595 mSolverCounterSat, 0.4s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI9 SFLT0 conc6 concLT1 SILN1 SILU0 SILI18 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital190 mio100 ax100 hnf100 lsp5 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 15ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 31 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.5s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 565]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int t6_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int t6_st ; [L38] int m_i ; [L39] int t1_i ; [L40] int t2_i ; [L41] int t3_i ; [L42] int t4_i ; [L43] int t5_i ; [L44] int t6_i ; [L45] int M_E = 2; [L46] int T1_E = 2; [L47] int T2_E = 2; [L48] int T3_E = 2; [L49] int T4_E = 2; [L50] int T5_E = 2; [L51] int T6_E = 2; [L52] int E_M = 2; [L53] int E_1 = 2; [L54] int E_2 = 2; [L55] int E_3 = 2; [L56] int E_4 = 2; [L57] int E_5 = 2; [L58] int E_6 = 2; [L67] int token ; [L69] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, t6_i=0, t6_pc=0, t6_st=0, token=0] [L1098] int __retres1 ; [L1102] CALL init_model() [L1008] m_i = 1 [L1009] t1_i = 1 [L1010] t2_i = 1 [L1011] t3_i = 1 [L1012] t4_i = 1 [L1013] t5_i = 1 [L1014] t6_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1102] RET init_model() [L1103] CALL start_simulation() [L1039] int kernel_st ; [L1040] int tmp ; [L1041] int tmp___0 ; [L1045] kernel_st = 0 [L1046] FCALL update_channels() [L1047] CALL init_threads() [L475] COND TRUE m_i == 1 [L476] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L480] COND TRUE t1_i == 1 [L481] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L485] COND TRUE t2_i == 1 [L486] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L490] COND TRUE t3_i == 1 [L491] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L495] COND TRUE t4_i == 1 [L496] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L500] COND TRUE t5_i == 1 [L501] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L505] COND TRUE t6_i == 1 [L506] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1047] RET init_threads() [L1048] CALL fire_delta_events() [L684] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L689] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L694] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L699] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L704] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L709] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L714] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L719] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L724] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L729] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L734] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L739] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L744] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L749] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1048] RET fire_delta_events() [L1049] CALL activate_threads() [L837] int tmp ; [L838] int tmp___0 ; [L839] int tmp___1 ; [L840] int tmp___2 ; [L841] int tmp___3 ; [L842] int tmp___4 ; [L843] int tmp___5 ; [L847] CALL, EXPR is_master_triggered() [L331] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L334] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L344] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L346] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L847] RET, EXPR is_master_triggered() [L847] tmp = is_master_triggered() [L849] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, token=0] [L855] CALL, EXPR is_transmit1_triggered() [L350] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L353] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L363] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L365] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L855] RET, EXPR is_transmit1_triggered() [L855] tmp___0 = is_transmit1_triggered() [L857] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, token=0] [L863] CALL, EXPR is_transmit2_triggered() [L369] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L372] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L382] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L384] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L863] RET, EXPR is_transmit2_triggered() [L863] tmp___1 = is_transmit2_triggered() [L865] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L871] CALL, EXPR is_transmit3_triggered() [L388] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L391] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L401] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L403] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L871] RET, EXPR is_transmit3_triggered() [L871] tmp___2 = is_transmit3_triggered() [L873] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L879] CALL, EXPR is_transmit4_triggered() [L407] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L410] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L420] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L422] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L879] RET, EXPR is_transmit4_triggered() [L879] tmp___3 = is_transmit4_triggered() [L881] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L887] CALL, EXPR is_transmit5_triggered() [L426] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L429] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L439] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L441] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L887] RET, EXPR is_transmit5_triggered() [L887] tmp___4 = is_transmit5_triggered() [L889] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L895] CALL, EXPR is_transmit6_triggered() [L445] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L448] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L458] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L460] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L895] RET, EXPR is_transmit6_triggered() [L895] tmp___5 = is_transmit6_triggered() [L897] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0, token=0] [L1049] RET activate_threads() [L1050] CALL reset_delta_events() [L762] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L767] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L772] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L777] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L782] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L787] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L792] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L797] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L802] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L807] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L812] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L817] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L822] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L827] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1050] RET reset_delta_events() [L1053] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1056] kernel_st = 1 [L1057] CALL eval() [L561] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] Loop: [L565] COND TRUE 1 [L568] CALL, EXPR exists_runnable_thread() [L515] int __retres1 ; [L518] COND TRUE m_st == 0 [L519] __retres1 = 1 [L556] return (__retres1); [L568] RET, EXPR exists_runnable_thread() [L568] tmp = exists_runnable_thread() [L570] COND TRUE \read(tmp) [L575] COND TRUE m_st == 0 [L576] int tmp_ndt_1; [L577] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L578] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L575-L586] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L589] COND TRUE t1_st == 0 [L590] int tmp_ndt_2; [L591] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L592] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L589-L600] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L603] COND TRUE t2_st == 0 [L604] int tmp_ndt_3; [L605] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L606] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L603-L614] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L617] COND TRUE t3_st == 0 [L618] int tmp_ndt_4; [L619] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L620] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L617-L628] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L631] COND TRUE t4_st == 0 [L632] int tmp_ndt_5; [L633] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L634] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L631-L642] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L645] COND TRUE t5_st == 0 [L646] int tmp_ndt_6; [L647] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L648] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L645-L656] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } [L659] COND TRUE t6_st == 0 [L660] int tmp_ndt_7; [L661] EXPR tmp_ndt_7 = __VERIFIER_nondet_int() [L662] COND FALSE, EXPR !(\read(tmp_ndt_7)) [L659-L670] { int tmp_ndt_7; tmp_ndt_7 = __VERIFIER_nondet_int(); if (tmp_ndt_7) { { t6_st = 1; transmit6(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 565]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int t6_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int t6_st ; [L38] int m_i ; [L39] int t1_i ; [L40] int t2_i ; [L41] int t3_i ; [L42] int t4_i ; [L43] int t5_i ; [L44] int t6_i ; [L45] int M_E = 2; [L46] int T1_E = 2; [L47] int T2_E = 2; [L48] int T3_E = 2; [L49] int T4_E = 2; [L50] int T5_E = 2; [L51] int T6_E = 2; [L52] int E_M = 2; [L53] int E_1 = 2; [L54] int E_2 = 2; [L55] int E_3 = 2; [L56] int E_4 = 2; [L57] int E_5 = 2; [L58] int E_6 = 2; [L67] int token ; [L69] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, t6_i=0, t6_pc=0, t6_st=0, token=0] [L1098] int __retres1 ; [L1102] CALL init_model() [L1008] m_i = 1 [L1009] t1_i = 1 [L1010] t2_i = 1 [L1011] t3_i = 1 [L1012] t4_i = 1 [L1013] t5_i = 1 [L1014] t6_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1102] RET init_model() [L1103] CALL start_simulation() [L1039] int kernel_st ; [L1040] int tmp ; [L1041] int tmp___0 ; [L1045] kernel_st = 0 [L1046] FCALL update_channels() [L1047] CALL init_threads() [L475] COND TRUE m_i == 1 [L476] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L480] COND TRUE t1_i == 1 [L481] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L485] COND TRUE t2_i == 1 [L486] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L490] COND TRUE t3_i == 1 [L491] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L495] COND TRUE t4_i == 1 [L496] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L500] COND TRUE t5_i == 1 [L501] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L505] COND TRUE t6_i == 1 [L506] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1047] RET init_threads() [L1048] CALL fire_delta_events() [L684] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L689] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L694] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L699] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L704] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L709] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L714] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L719] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L724] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L729] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L734] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L739] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L744] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L749] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1048] RET fire_delta_events() [L1049] CALL activate_threads() [L837] int tmp ; [L838] int tmp___0 ; [L839] int tmp___1 ; [L840] int tmp___2 ; [L841] int tmp___3 ; [L842] int tmp___4 ; [L843] int tmp___5 ; [L847] CALL, EXPR is_master_triggered() [L331] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L334] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L344] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L346] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L847] RET, EXPR is_master_triggered() [L847] tmp = is_master_triggered() [L849] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, token=0] [L855] CALL, EXPR is_transmit1_triggered() [L350] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L353] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L363] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L365] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L855] RET, EXPR is_transmit1_triggered() [L855] tmp___0 = is_transmit1_triggered() [L857] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, token=0] [L863] CALL, EXPR is_transmit2_triggered() [L369] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L372] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L382] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L384] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L863] RET, EXPR is_transmit2_triggered() [L863] tmp___1 = is_transmit2_triggered() [L865] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L871] CALL, EXPR is_transmit3_triggered() [L388] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L391] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L401] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L403] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L871] RET, EXPR is_transmit3_triggered() [L871] tmp___2 = is_transmit3_triggered() [L873] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L879] CALL, EXPR is_transmit4_triggered() [L407] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L410] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L420] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L422] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L879] RET, EXPR is_transmit4_triggered() [L879] tmp___3 = is_transmit4_triggered() [L881] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L887] CALL, EXPR is_transmit5_triggered() [L426] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L429] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L439] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L441] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L887] RET, EXPR is_transmit5_triggered() [L887] tmp___4 = is_transmit5_triggered() [L889] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L895] CALL, EXPR is_transmit6_triggered() [L445] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L448] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L458] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L460] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L895] RET, EXPR is_transmit6_triggered() [L895] tmp___5 = is_transmit6_triggered() [L897] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0, token=0] [L1049] RET activate_threads() [L1050] CALL reset_delta_events() [L762] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L767] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L772] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L777] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L782] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L787] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L792] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L797] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L802] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L807] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L812] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L817] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L822] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L827] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1050] RET reset_delta_events() [L1053] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] [L1056] kernel_st = 1 [L1057] CALL eval() [L561] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, token=0] Loop: [L565] COND TRUE 1 [L568] CALL, EXPR exists_runnable_thread() [L515] int __retres1 ; [L518] COND TRUE m_st == 0 [L519] __retres1 = 1 [L556] return (__retres1); [L568] RET, EXPR exists_runnable_thread() [L568] tmp = exists_runnable_thread() [L570] COND TRUE \read(tmp) [L575] COND TRUE m_st == 0 [L576] int tmp_ndt_1; [L577] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L578] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L575-L586] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L589] COND TRUE t1_st == 0 [L590] int tmp_ndt_2; [L591] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L592] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L589-L600] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L603] COND TRUE t2_st == 0 [L604] int tmp_ndt_3; [L605] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L606] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L603-L614] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L617] COND TRUE t3_st == 0 [L618] int tmp_ndt_4; [L619] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L620] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L617-L628] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L631] COND TRUE t4_st == 0 [L632] int tmp_ndt_5; [L633] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L634] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L631-L642] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L645] COND TRUE t5_st == 0 [L646] int tmp_ndt_6; [L647] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L648] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L645-L656] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } [L659] COND TRUE t6_st == 0 [L660] int tmp_ndt_7; [L661] EXPR tmp_ndt_7 = __VERIFIER_nondet_int() [L662] COND FALSE, EXPR !(\read(tmp_ndt_7)) [L659-L670] { int tmp_ndt_7; tmp_ndt_7 = __VERIFIER_nondet_int(); if (tmp_ndt_7) { { t6_st = 1; transmit6(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-29 04:16:07,959 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fb12a762-2a47-4ac2-9da3-2b4260a24803/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)