./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-29 01:34:58,837 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-29 01:34:58,929 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-29 01:34:58,934 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-29 01:34:58,934 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-29 01:34:58,958 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-29 01:34:58,959 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-29 01:34:58,959 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-29 01:34:58,960 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-29 01:34:58,960 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-29 01:34:58,961 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-29 01:34:58,962 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-29 01:34:58,962 INFO L153 SettingsManager]: * Use SBE=true [2023-11-29 01:34:58,963 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-29 01:34:58,963 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-29 01:34:58,964 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-29 01:34:58,964 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-29 01:34:58,965 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-29 01:34:58,965 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-29 01:34:58,966 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-29 01:34:58,966 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-29 01:34:58,967 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-29 01:34:58,968 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-29 01:34:58,968 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-29 01:34:58,969 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-29 01:34:58,969 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-29 01:34:58,970 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-29 01:34:58,970 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-29 01:34:58,971 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-29 01:34:58,971 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-29 01:34:58,972 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-29 01:34:58,972 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-29 01:34:58,972 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-29 01:34:58,973 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-29 01:34:58,973 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-29 01:34:58,973 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-29 01:34:58,973 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-29 01:34:58,974 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-29 01:34:58,974 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b [2023-11-29 01:34:59,195 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-29 01:34:59,215 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-29 01:34:59,217 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-29 01:34:59,218 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-29 01:34:59,219 INFO L274 PluginConnector]: CDTParser initialized [2023-11-29 01:34:59,220 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2023-11-29 01:35:01,907 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-29 01:35:02,126 INFO L384 CDTParser]: Found 1 translation units. [2023-11-29 01:35:02,127 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2023-11-29 01:35:02,141 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya/data/c7f4f245d/def9ce4f45884857883560cbbed75422/FLAGe3181c1a3 [2023-11-29 01:35:02,153 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya/data/c7f4f245d/def9ce4f45884857883560cbbed75422 [2023-11-29 01:35:02,155 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-29 01:35:02,156 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-29 01:35:02,157 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-29 01:35:02,157 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-29 01:35:02,163 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-29 01:35:02,164 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 01:35:02" (1/1) ... [2023-11-29 01:35:02,165 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@404ab011 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02, skipping insertion in model container [2023-11-29 01:35:02,165 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 01:35:02" (1/1) ... [2023-11-29 01:35:02,227 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-29 01:35:02,532 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 01:35:02,551 INFO L202 MainTranslator]: Completed pre-run [2023-11-29 01:35:02,637 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 01:35:02,662 INFO L206 MainTranslator]: Completed translation [2023-11-29 01:35:02,663 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02 WrapperNode [2023-11-29 01:35:02,663 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-29 01:35:02,664 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-29 01:35:02,664 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-29 01:35:02,665 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-29 01:35:02,673 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02" (1/1) ... [2023-11-29 01:35:02,689 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02" (1/1) ... [2023-11-29 01:35:02,781 INFO L138 Inliner]: procedures = 48, calls = 63, calls flagged for inlining = 58, calls inlined = 212, statements flattened = 3223 [2023-11-29 01:35:02,781 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-29 01:35:02,782 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-29 01:35:02,782 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-29 01:35:02,782 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-29 01:35:02,797 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02" (1/1) ... [2023-11-29 01:35:02,797 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02" (1/1) ... [2023-11-29 01:35:02,809 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02" (1/1) ... [2023-11-29 01:35:02,852 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-29 01:35:02,853 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02" (1/1) ... [2023-11-29 01:35:02,853 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02" (1/1) ... [2023-11-29 01:35:02,896 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02" (1/1) ... [2023-11-29 01:35:02,934 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02" (1/1) ... [2023-11-29 01:35:02,941 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02" (1/1) ... [2023-11-29 01:35:02,952 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02" (1/1) ... [2023-11-29 01:35:02,965 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-29 01:35:02,966 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-29 01:35:02,966 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-29 01:35:02,966 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-29 01:35:02,967 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02" (1/1) ... [2023-11-29 01:35:02,974 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:35:02,988 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:35:03,002 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:35:03,005 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1e9525dd-3d26-4915-ab4e-b1c0712d6b3b/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-29 01:35:03,038 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-29 01:35:03,039 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-29 01:35:03,039 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-29 01:35:03,039 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-29 01:35:03,155 INFO L241 CfgBuilder]: Building ICFG [2023-11-29 01:35:03,157 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-29 01:35:04,825 INFO L282 CfgBuilder]: Performing block encoding [2023-11-29 01:35:04,860 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-29 01:35:04,860 INFO L309 CfgBuilder]: Removed 13 assume(true) statements. [2023-11-29 01:35:04,862 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 01:35:04 BoogieIcfgContainer [2023-11-29 01:35:04,863 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-29 01:35:04,864 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-29 01:35:04,864 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-29 01:35:04,867 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-29 01:35:04,867 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:35:04,868 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.11 01:35:02" (1/3) ... [2023-11-29 01:35:04,868 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@28e13007 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 01:35:04, skipping insertion in model container [2023-11-29 01:35:04,868 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:35:04,869 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:35:02" (2/3) ... [2023-11-29 01:35:04,869 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@28e13007 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 01:35:04, skipping insertion in model container [2023-11-29 01:35:04,869 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:35:04,869 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 01:35:04" (3/3) ... [2023-11-29 01:35:04,871 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-1.c [2023-11-29 01:35:04,956 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-29 01:35:04,956 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-29 01:35:04,957 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-29 01:35:04,957 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-29 01:35:04,957 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-29 01:35:04,957 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-29 01:35:04,957 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-29 01:35:04,957 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-29 01:35:04,968 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1387 states, 1386 states have (on average 1.5021645021645023) internal successors, (2082), 1386 states have internal predecessors, (2082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:05,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1244 [2023-11-29 01:35:05,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:05,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:05,052 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:05,053 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:05,053 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-29 01:35:05,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1387 states, 1386 states have (on average 1.5021645021645023) internal successors, (2082), 1386 states have internal predecessors, (2082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:05,077 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1244 [2023-11-29 01:35:05,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:05,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:05,082 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:05,082 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:05,092 INFO L748 eck$LassoCheckResult]: Stem: 205#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1274#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1023#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1268#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1171#L731true assume !(1 == ~m_i~0);~m_st~0 := 2; 1034#L731-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 940#L736-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1010#L741-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1328#L746-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 169#L751-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 229#L756-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 850#L761-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 386#L766-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 335#L771-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 170#L776-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10#L781-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54#L1036true assume !(0 == ~M_E~0); 1043#L1036-2true assume !(0 == ~T1_E~0); 620#L1041-1true assume !(0 == ~T2_E~0); 982#L1046-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 193#L1051-1true assume !(0 == ~T4_E~0); 759#L1056-1true assume !(0 == ~T5_E~0); 814#L1061-1true assume !(0 == ~T6_E~0); 137#L1066-1true assume !(0 == ~T7_E~0); 1166#L1071-1true assume !(0 == ~T8_E~0); 739#L1076-1true assume !(0 == ~T9_E~0); 83#L1081-1true assume !(0 == ~T10_E~0); 300#L1086-1true assume 0 == ~E_M~0;~E_M~0 := 1; 1183#L1091-1true assume !(0 == ~E_1~0); 1045#L1096-1true assume !(0 == ~E_2~0); 1278#L1101-1true assume !(0 == ~E_3~0); 344#L1106-1true assume !(0 == ~E_4~0); 559#L1111-1true assume !(0 == ~E_5~0); 462#L1116-1true assume !(0 == ~E_6~0); 1105#L1121-1true assume !(0 == ~E_7~0); 338#L1126-1true assume 0 == ~E_8~0;~E_8~0 := 1; 539#L1131-1true assume !(0 == ~E_9~0); 629#L1136-1true assume !(0 == ~E_10~0); 905#L1141-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 799#L514true assume 1 == ~m_pc~0; 749#L515true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 348#L525true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 877#is_master_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1117#L1285true assume !(0 != activate_threads_~tmp~1#1); 1204#L1285-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 145#L533true assume !(1 == ~t1_pc~0); 1059#L533-2true is_transmit1_triggered_~__retres1~1#1 := 0; 506#L544true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 919#L1293true assume !(0 != activate_threads_~tmp___0~0#1); 653#L1293-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 909#L552true assume 1 == ~t2_pc~0; 269#L553true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 941#L563true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 340#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 986#L1301true assume !(0 != activate_threads_~tmp___1~0#1); 357#L1301-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 518#L571true assume 1 == ~t3_pc~0; 503#L572true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 691#L582true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 660#L1309true assume !(0 != activate_threads_~tmp___2~0#1); 465#L1309-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48#L590true assume !(1 == ~t4_pc~0); 517#L590-2true is_transmit4_triggered_~__retres1~4#1 := 0; 1300#L601true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1129#L1317true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 676#L1317-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 463#L609true assume 1 == ~t5_pc~0; 1290#L610true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1114#L620true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 881#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1388#L1325true assume !(0 != activate_threads_~tmp___4~0#1); 457#L1325-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1287#L628true assume !(1 == ~t6_pc~0); 540#L628-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1264#L639true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 324#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1194#L1333true assume !(0 != activate_threads_~tmp___5~0#1); 715#L1333-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 859#L647true assume 1 == ~t7_pc~0; 345#L648true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 896#L658true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1294#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 346#L1341true assume !(0 != activate_threads_~tmp___6~0#1); 1257#L1341-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1230#L666true assume !(1 == ~t8_pc~0); 797#L666-2true is_transmit8_triggered_~__retres1~8#1 := 0; 356#L677true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 800#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 482#L1349true assume !(0 != activate_threads_~tmp___7~0#1); 298#L1349-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1147#L685true assume 1 == ~t9_pc~0; 1310#L686true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 920#L696true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 381#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 316#L1357true assume !(0 != activate_threads_~tmp___8~0#1); 1017#L1357-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 599#L704true assume !(1 == ~t10_pc~0); 1102#L704-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1052#L715true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 495#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 71#L1365true assume !(0 != activate_threads_~tmp___9~0#1); 197#L1365-2true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 704#L1154true assume !(1 == ~M_E~0); 1190#L1154-2true assume !(1 == ~T1_E~0); 182#L1159-1true assume !(1 == ~T2_E~0); 1320#L1164-1true assume !(1 == ~T3_E~0); 480#L1169-1true assume !(1 == ~T4_E~0); 382#L1174-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 253#L1179-1true assume !(1 == ~T6_E~0); 174#L1184-1true assume !(1 == ~T7_E~0); 217#L1189-1true assume !(1 == ~T8_E~0); 289#L1194-1true assume !(1 == ~T9_E~0); 1368#L1199-1true assume !(1 == ~T10_E~0); 263#L1204-1true assume !(1 == ~E_M~0); 1225#L1209-1true assume !(1 == ~E_1~0); 672#L1214-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1318#L1219-1true assume !(1 == ~E_3~0); 1200#L1224-1true assume !(1 == ~E_4~0); 500#L1229-1true assume !(1 == ~E_5~0); 117#L1234-1true assume !(1 == ~E_6~0); 786#L1239-1true assume !(1 == ~E_7~0); 143#L1244-1true assume !(1 == ~E_8~0); 836#L1249-1true assume !(1 == ~E_9~0); 747#L1254-1true assume 1 == ~E_10~0;~E_10~0 := 2; 68#L1259-1true assume { :end_inline_reset_delta_events } true; 1179#L1565-2true [2023-11-29 01:35:05,096 INFO L750 eck$LassoCheckResult]: Loop: 1179#L1565-2true assume !false; 680#L1566true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1073#L1011-1true assume false; 811#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 512#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 754#L1036-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1080#L1036-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1316#L1041-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 844#L1046-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1201#L1051-3true assume !(0 == ~T4_E~0); 755#L1056-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 191#L1061-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 192#L1066-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1333#L1071-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1083#L1076-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 65#L1081-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1247#L1086-3true assume 0 == ~E_M~0;~E_M~0 := 1; 88#L1091-3true assume !(0 == ~E_1~0); 1157#L1096-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1012#L1101-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1079#L1106-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1134#L1111-3true assume 0 == ~E_5~0;~E_5~0 := 1; 998#L1116-3true assume 0 == ~E_6~0;~E_6~0 := 1; 609#L1121-3true assume 0 == ~E_7~0;~E_7~0 := 1; 944#L1126-3true assume 0 == ~E_8~0;~E_8~0 := 1; 870#L1131-3true assume !(0 == ~E_9~0); 1311#L1136-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1284#L1141-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 613#L514-36true assume 1 == ~m_pc~0; 1362#L515-12true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 283#L525-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1026#is_master_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 651#L1285-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 221#L1285-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 400#L533-36true assume !(1 == ~t1_pc~0); 751#L533-38true is_transmit1_triggered_~__retres1~1#1 := 0; 969#L544-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1024#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 690#L1293-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 516#L1293-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1377#L552-36true assume !(1 == ~t2_pc~0); 1349#L552-38true is_transmit2_triggered_~__retres1~2#1 := 0; 558#L563-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 857#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1188#L1301-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 203#L1301-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 847#L571-36true assume !(1 == ~t3_pc~0); 975#L571-38true is_transmit3_triggered_~__retres1~3#1 := 0; 254#L582-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 378#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 842#L1309-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 887#L1309-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 238#L590-36true assume 1 == ~t4_pc~0; 705#L591-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1027#L601-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 525#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1323#L1317-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 807#L1317-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1070#L609-36true assume !(1 == ~t5_pc~0); 1340#L609-38true is_transmit5_triggered_~__retres1~5#1 := 0; 520#L620-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 978#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 876#L1325-36true assume !(0 != activate_threads_~tmp___4~0#1); 580#L1325-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 435#L628-36true assume !(1 == ~t6_pc~0); 1144#L628-38true is_transmit6_triggered_~__retres1~6#1 := 0; 1148#L639-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 364#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 760#L1333-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 614#L1333-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1111#L647-36true assume !(1 == ~t7_pc~0); 678#L647-38true is_transmit7_triggered_~__retres1~7#1 := 0; 77#L658-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 948#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85#L1341-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 706#L1341-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 779#L666-36true assume 1 == ~t8_pc~0; 181#L667-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1209#L677-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 604#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1222#L1349-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 268#L1349-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 595#L685-36true assume !(1 == ~t9_pc~0); 132#L685-38true is_transmit9_triggered_~__retres1~9#1 := 0; 888#L696-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 403#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1277#L1357-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 354#L1357-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 363#L704-36true assume !(1 == ~t10_pc~0); 266#L704-38true is_transmit10_triggered_~__retres1~10#1 := 0; 1163#L715-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 305#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 732#L1365-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 139#L1365-38true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1361#L1154-3true assume 1 == ~M_E~0;~M_E~0 := 2; 981#L1154-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 769#L1159-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1335#L1164-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1107#L1169-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 309#L1174-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1196#L1179-3true assume !(1 == ~T6_E~0); 923#L1184-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 78#L1189-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 929#L1194-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 274#L1199-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1371#L1204-3true assume 1 == ~E_M~0;~E_M~0 := 2; 497#L1209-3true assume 1 == ~E_1~0;~E_1~0 := 2; 17#L1214-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1021#L1219-3true assume !(1 == ~E_3~0); 658#L1224-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1382#L1229-3true assume 1 == ~E_5~0;~E_5~0 := 2; 679#L1234-3true assume 1 == ~E_6~0;~E_6~0 := 2; 144#L1239-3true assume 1 == ~E_7~0;~E_7~0 := 2; 535#L1244-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1086#L1249-3true assume 1 == ~E_9~0;~E_9~0 := 2; 999#L1254-3true assume 1 == ~E_10~0;~E_10~0 := 2; 664#L1259-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 763#L794-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1296#L851-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 297#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 618#L1584true assume !(0 == start_simulation_~tmp~3#1); 643#L1584-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 150#L794-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 943#L851-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 32#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 342#L1539true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 987#L1546true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 528#stop_simulation_returnLabel#1true start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1174#L1597true assume !(0 != start_simulation_~tmp___0~1#1); 1179#L1565-2true [2023-11-29 01:35:05,103 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:05,104 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2023-11-29 01:35:05,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:05,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549410229] [2023-11-29 01:35:05,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:05,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:05,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:05,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:05,402 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:05,403 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1549410229] [2023-11-29 01:35:05,403 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1549410229] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:05,403 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:05,404 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:05,405 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435670864] [2023-11-29 01:35:05,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:05,409 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:05,410 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:05,410 INFO L85 PathProgramCache]: Analyzing trace with hash 1329563516, now seen corresponding path program 1 times [2023-11-29 01:35:05,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:05,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558107894] [2023-11-29 01:35:05,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:05,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:05,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:05,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:05,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:05,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558107894] [2023-11-29 01:35:05,475 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [558107894] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:05,475 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:05,475 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:35:05,475 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1628677165] [2023-11-29 01:35:05,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:05,477 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:05,478 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:05,504 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:05,504 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:05,509 INFO L87 Difference]: Start difference. First operand has 1387 states, 1386 states have (on average 1.5021645021645023) internal successors, (2082), 1386 states have internal predecessors, (2082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:05,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:05,586 INFO L93 Difference]: Finished difference Result 1383 states and 2049 transitions. [2023-11-29 01:35:05,587 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1383 states and 2049 transitions. [2023-11-29 01:35:05,621 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:05,637 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1383 states to 1377 states and 2043 transitions. [2023-11-29 01:35:05,638 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-29 01:35:05,641 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-29 01:35:05,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2043 transitions. [2023-11-29 01:35:05,648 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:05,649 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2043 transitions. [2023-11-29 01:35:05,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2043 transitions. [2023-11-29 01:35:05,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-29 01:35:05,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4836601307189543) internal successors, (2043), 1376 states have internal predecessors, (2043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:05,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2043 transitions. [2023-11-29 01:35:05,731 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2043 transitions. [2023-11-29 01:35:05,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:05,735 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2043 transitions. [2023-11-29 01:35:05,736 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-29 01:35:05,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2043 transitions. [2023-11-29 01:35:05,746 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:05,746 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:05,746 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:05,749 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:05,750 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:05,751 INFO L748 eck$LassoCheckResult]: Stem: 3197#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3198#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4074#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4075#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4137#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4078#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4038#L736-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4039#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4067#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3136#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3137#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3242#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3487#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3413#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3138#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2797#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2798#L1036 assume !(0 == ~M_E~0); 2895#L1036-2 assume !(0 == ~T1_E~0); 3800#L1041-1 assume !(0 == ~T2_E~0); 3801#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3172#L1051-1 assume !(0 == ~T4_E~0); 3173#L1056-1 assume !(0 == ~T5_E~0); 3929#L1061-1 assume !(0 == ~T6_E~0); 3067#L1066-1 assume !(0 == ~T7_E~0); 3068#L1071-1 assume !(0 == ~T8_E~0); 3911#L1076-1 assume !(0 == ~T9_E~0); 2957#L1081-1 assume !(0 == ~T10_E~0); 2958#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3358#L1091-1 assume !(0 == ~E_1~0); 4086#L1096-1 assume !(0 == ~E_2~0); 4087#L1101-1 assume !(0 == ~E_3~0); 3426#L1106-1 assume !(0 == ~E_4~0); 3427#L1111-1 assume !(0 == ~E_5~0); 3591#L1116-1 assume !(0 == ~E_6~0); 3592#L1121-1 assume !(0 == ~E_7~0); 3417#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3418#L1131-1 assume !(0 == ~E_9~0); 3693#L1136-1 assume !(0 == ~E_10~0); 3808#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3957#L514 assume 1 == ~m_pc~0; 3922#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3435#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3436#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4009#L1285 assume !(0 != activate_threads_~tmp~1#1); 4122#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3086#L533 assume !(1 == ~t1_pc~0); 3087#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3606#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2852#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2853#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3829#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3830#L552 assume 1 == ~t2_pc~0; 3307#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3308#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3421#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3422#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3453#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3454#L571 assume 1 == ~t3_pc~0; 3646#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3647#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2795#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2796#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3596#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2881#L590 assume !(1 == ~t4_pc~0); 2882#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3654#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2975#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2976#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3857#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3593#L609 assume 1 == ~t5_pc~0; 3594#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4119#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4011#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4012#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3585#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3586#L628 assume !(1 == ~t6_pc~0); 3518#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3517#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3395#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3396#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3891#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3892#L647 assume 1 == ~t7_pc~0; 3428#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3429#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4020#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3433#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3434#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4148#L666 assume !(1 == ~t8_pc~0); 3219#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3220#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3447#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3618#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3356#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3357#L685 assume 1 == ~t9_pc~0; 4127#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4028#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3481#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3385#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3386#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3771#L704 assume !(1 == ~t10_pc~0); 3375#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3374#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3636#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2929#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 2930#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3181#L1154 assume !(1 == ~M_E~0); 3879#L1154-2 assume !(1 == ~T1_E~0); 3155#L1159-1 assume !(1 == ~T2_E~0); 3156#L1164-1 assume !(1 == ~T3_E~0); 3615#L1169-1 assume !(1 == ~T4_E~0); 3482#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3286#L1179-1 assume !(1 == ~T6_E~0); 3140#L1184-1 assume !(1 == ~T7_E~0); 3141#L1189-1 assume !(1 == ~T8_E~0); 3217#L1194-1 assume !(1 == ~T9_E~0); 3344#L1199-1 assume !(1 == ~T10_E~0); 3298#L1204-1 assume !(1 == ~E_M~0); 3299#L1209-1 assume !(1 == ~E_1~0); 3852#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3853#L1219-1 assume !(1 == ~E_3~0); 4141#L1224-1 assume !(1 == ~E_4~0); 3640#L1229-1 assume !(1 == ~E_5~0); 3024#L1234-1 assume !(1 == ~E_6~0); 3025#L1239-1 assume !(1 == ~E_7~0); 3082#L1244-1 assume !(1 == ~E_8~0); 3083#L1249-1 assume !(1 == ~E_9~0); 3920#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2924#L1259-1 assume { :end_inline_reset_delta_events } true; 2925#L1565-2 [2023-11-29 01:35:05,751 INFO L750 eck$LassoCheckResult]: Loop: 2925#L1565-2 assume !false; 3858#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3624#L1011-1 assume !false; 3587#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3360#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3123#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3460#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3152#L866 assume !(0 != eval_~tmp~0#1); 3154#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3657#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3658#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3924#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4103#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3985#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3986#L1051-3 assume !(0 == ~T4_E~0); 3925#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3169#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3170#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3171#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4105#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2916#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2917#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2971#L1091-3 assume !(0 == ~E_1~0); 2972#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4069#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4070#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4102#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4061#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3786#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3787#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4000#L1131-3 assume !(0 == ~E_9~0); 4001#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4153#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3789#L514-36 assume !(1 == ~m_pc~0); 3498#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3333#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3334#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3828#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3226#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3227#L533-36 assume 1 == ~t1_pc~0; 3507#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3603#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4051#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3866#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3663#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3664#L552-36 assume 1 == ~t2_pc~0; 3221#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3222#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3722#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3993#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3193#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3194#L571-36 assume 1 == ~t3_pc~0; 3581#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3284#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3285#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3477#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3984#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3253#L590-36 assume 1 == ~t4_pc~0; 3254#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3880#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3673#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3674#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3963#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3964#L609-36 assume 1 == ~t5_pc~0; 3841#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3666#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3667#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4008#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 3750#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3557#L628-36 assume 1 == ~t6_pc~0; 3405#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3406#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3456#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3457#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3791#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3792#L647-36 assume 1 == ~t7_pc~0; 3715#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2943#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2944#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2961#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2962#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3881#L666-36 assume 1 == ~t8_pc~0; 3149#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3150#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3779#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3780#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3304#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3305#L685-36 assume 1 == ~t9_pc~0; 3766#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3056#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3511#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3512#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3444#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3445#L704-36 assume 1 == ~t10_pc~0; 3043#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3044#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3365#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3366#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3071#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3072#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4055#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3938#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3939#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4116#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3371#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3372#L1179-3 assume !(1 == ~T6_E~0); 4030#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2945#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2946#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3315#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3316#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3635#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2813#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2814#L1219-3 assume !(1 == ~E_3~0); 3835#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3836#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3856#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3084#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3085#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3686#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4062#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3839#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3840#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2893#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3353#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3354#L1584 assume !(0 == start_simulation_~tmp~3#1); 3797#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3098#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2793#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2845#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2846#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3423#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3679#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3680#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 2925#L1565-2 [2023-11-29 01:35:05,752 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:05,752 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2023-11-29 01:35:05,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:05,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [794904551] [2023-11-29 01:35:05,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:05,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:05,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:05,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:05,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:05,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [794904551] [2023-11-29 01:35:05,838 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [794904551] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:05,838 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:05,838 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:05,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [437949377] [2023-11-29 01:35:05,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:05,839 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:05,839 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:05,840 INFO L85 PathProgramCache]: Analyzing trace with hash 642940402, now seen corresponding path program 1 times [2023-11-29 01:35:05,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:05,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738310770] [2023-11-29 01:35:05,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:05,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:05,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:05,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:05,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:05,946 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1738310770] [2023-11-29 01:35:05,946 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1738310770] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:05,946 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:05,946 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:05,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [95709714] [2023-11-29 01:35:05,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:05,947 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:05,947 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:05,948 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:05,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:05,948 INFO L87 Difference]: Start difference. First operand 1377 states and 2043 transitions. cyclomatic complexity: 667 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:05,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:05,984 INFO L93 Difference]: Finished difference Result 1377 states and 2042 transitions. [2023-11-29 01:35:05,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2042 transitions. [2023-11-29 01:35:05,997 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:06,009 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2042 transitions. [2023-11-29 01:35:06,009 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-29 01:35:06,010 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-29 01:35:06,011 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2042 transitions. [2023-11-29 01:35:06,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:06,013 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2042 transitions. [2023-11-29 01:35:06,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2042 transitions. [2023-11-29 01:35:06,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-29 01:35:06,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4829339143064633) internal successors, (2042), 1376 states have internal predecessors, (2042), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:06,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2042 transitions. [2023-11-29 01:35:06,043 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2042 transitions. [2023-11-29 01:35:06,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:06,044 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2042 transitions. [2023-11-29 01:35:06,044 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-29 01:35:06,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2042 transitions. [2023-11-29 01:35:06,053 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:06,053 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:06,053 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:06,056 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:06,056 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:06,057 INFO L748 eck$LassoCheckResult]: Stem: 5958#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5959#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6835#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6836#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6898#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 6839#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6799#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6800#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6828#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5895#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5896#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6003#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6248#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6174#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5897#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5558#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5559#L1036 assume !(0 == ~M_E~0); 5656#L1036-2 assume !(0 == ~T1_E~0); 6561#L1041-1 assume !(0 == ~T2_E~0); 6562#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5933#L1051-1 assume !(0 == ~T4_E~0); 5934#L1056-1 assume !(0 == ~T5_E~0); 6690#L1061-1 assume !(0 == ~T6_E~0); 5828#L1066-1 assume !(0 == ~T7_E~0); 5829#L1071-1 assume !(0 == ~T8_E~0); 6672#L1076-1 assume !(0 == ~T9_E~0); 5718#L1081-1 assume !(0 == ~T10_E~0); 5719#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6119#L1091-1 assume !(0 == ~E_1~0); 6846#L1096-1 assume !(0 == ~E_2~0); 6847#L1101-1 assume !(0 == ~E_3~0); 6187#L1106-1 assume !(0 == ~E_4~0); 6188#L1111-1 assume !(0 == ~E_5~0); 6352#L1116-1 assume !(0 == ~E_6~0); 6353#L1121-1 assume !(0 == ~E_7~0); 6178#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 6179#L1131-1 assume !(0 == ~E_9~0); 6454#L1136-1 assume !(0 == ~E_10~0); 6569#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6718#L514 assume 1 == ~m_pc~0; 6683#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6196#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6197#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6770#L1285 assume !(0 != activate_threads_~tmp~1#1); 6882#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5847#L533 assume !(1 == ~t1_pc~0); 5848#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6367#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5611#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5612#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 6590#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6591#L552 assume 1 == ~t2_pc~0; 6067#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6068#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6182#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6183#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 6209#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6210#L571 assume 1 == ~t3_pc~0; 6405#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6406#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5556#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5557#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 6357#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5642#L590 assume !(1 == ~t4_pc~0); 5643#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6415#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5736#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5737#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6617#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6354#L609 assume 1 == ~t5_pc~0; 6355#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6880#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6772#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6773#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 6346#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6347#L628 assume !(1 == ~t6_pc~0); 6279#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6278#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6155#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6156#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 6652#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6653#L647 assume 1 == ~t7_pc~0; 6189#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6190#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6781#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6192#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 6193#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6909#L666 assume !(1 == ~t8_pc~0); 5980#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5981#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6208#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6378#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 6116#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6117#L685 assume 1 == ~t9_pc~0; 6888#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6789#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6242#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6146#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 6147#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6532#L704 assume !(1 == ~t10_pc~0); 6136#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6135#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6396#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5690#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 5691#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5942#L1154 assume !(1 == ~M_E~0); 6640#L1154-2 assume !(1 == ~T1_E~0); 5916#L1159-1 assume !(1 == ~T2_E~0); 5917#L1164-1 assume !(1 == ~T3_E~0); 6376#L1169-1 assume !(1 == ~T4_E~0); 6243#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6045#L1179-1 assume !(1 == ~T6_E~0); 5901#L1184-1 assume !(1 == ~T7_E~0); 5902#L1189-1 assume !(1 == ~T8_E~0); 5978#L1194-1 assume !(1 == ~T9_E~0); 6103#L1199-1 assume !(1 == ~T10_E~0); 6057#L1204-1 assume !(1 == ~E_M~0); 6058#L1209-1 assume !(1 == ~E_1~0); 6611#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6612#L1219-1 assume !(1 == ~E_3~0); 6902#L1224-1 assume !(1 == ~E_4~0); 6400#L1229-1 assume !(1 == ~E_5~0); 5785#L1234-1 assume !(1 == ~E_6~0); 5786#L1239-1 assume !(1 == ~E_7~0); 5843#L1244-1 assume !(1 == ~E_8~0); 5844#L1249-1 assume !(1 == ~E_9~0); 6681#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 5685#L1259-1 assume { :end_inline_reset_delta_events } true; 5686#L1565-2 [2023-11-29 01:35:06,057 INFO L750 eck$LassoCheckResult]: Loop: 5686#L1565-2 assume !false; 6619#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6384#L1011-1 assume !false; 6348#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6121#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5884#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6221#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5908#L866 assume !(0 != eval_~tmp~0#1); 5910#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6417#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6418#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6685#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6864#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6746#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6747#L1051-3 assume !(0 == ~T4_E~0); 6686#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5930#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5931#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5932#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6866#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5677#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5678#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5728#L1091-3 assume !(0 == ~E_1~0); 5729#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6830#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6831#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6863#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6822#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6547#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6548#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6761#L1131-3 assume !(0 == ~E_9~0); 6762#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6914#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6550#L514-36 assume !(1 == ~m_pc~0); 6259#L514-38 is_master_triggered_~__retres1~0#1 := 0; 6094#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6095#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6589#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5987#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5988#L533-36 assume 1 == ~t1_pc~0; 6268#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6361#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6812#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6627#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6424#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6425#L552-36 assume !(1 == ~t2_pc~0); 5984#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5983#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6483#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6754#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5954#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5955#L571-36 assume 1 == ~t3_pc~0; 6342#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6046#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6047#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6238#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6745#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6017#L590-36 assume 1 == ~t4_pc~0; 6018#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6641#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6434#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6435#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6724#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6725#L609-36 assume 1 == ~t5_pc~0; 6602#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6427#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6428#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6769#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 6511#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6318#L628-36 assume 1 == ~t6_pc~0; 6166#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6167#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6217#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6218#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6552#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6553#L647-36 assume 1 == ~t7_pc~0; 6476#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5704#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5705#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5722#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5723#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6642#L666-36 assume 1 == ~t8_pc~0; 5913#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5914#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6540#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6541#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6065#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6066#L685-36 assume !(1 == ~t9_pc~0); 5816#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 5817#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6272#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6273#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6205#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6206#L704-36 assume 1 == ~t10_pc~0; 5804#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5805#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6126#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6127#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5832#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5833#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6816#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6699#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6700#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6877#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6132#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6133#L1179-3 assume !(1 == ~T6_E~0); 6791#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5706#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5707#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6076#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6077#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6397#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5574#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5575#L1219-3 assume !(1 == ~E_3~0); 6596#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6597#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6618#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5845#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5846#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6451#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6823#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6600#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6601#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5654#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6114#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6115#L1584 assume !(0 == start_simulation_~tmp~3#1); 6558#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5859#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5554#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5606#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 5607#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6185#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6440#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6441#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 5686#L1565-2 [2023-11-29 01:35:06,058 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:06,058 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2023-11-29 01:35:06,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:06,059 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1693270028] [2023-11-29 01:35:06,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:06,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:06,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:06,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:06,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:06,114 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1693270028] [2023-11-29 01:35:06,114 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1693270028] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:06,114 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:06,114 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:06,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1559249856] [2023-11-29 01:35:06,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:06,115 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:06,116 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:06,116 INFO L85 PathProgramCache]: Analyzing trace with hash 1657784244, now seen corresponding path program 1 times [2023-11-29 01:35:06,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:06,117 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162813785] [2023-11-29 01:35:06,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:06,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:06,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:06,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:06,200 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:06,201 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162813785] [2023-11-29 01:35:06,201 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162813785] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:06,201 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:06,201 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:06,201 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2135177347] [2023-11-29 01:35:06,202 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:06,202 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:06,202 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:06,203 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:06,203 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:06,203 INFO L87 Difference]: Start difference. First operand 1377 states and 2042 transitions. cyclomatic complexity: 666 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:06,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:06,229 INFO L93 Difference]: Finished difference Result 1377 states and 2041 transitions. [2023-11-29 01:35:06,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2041 transitions. [2023-11-29 01:35:06,237 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:06,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2041 transitions. [2023-11-29 01:35:06,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-29 01:35:06,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-29 01:35:06,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2041 transitions. [2023-11-29 01:35:06,248 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:06,248 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2041 transitions. [2023-11-29 01:35:06,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2041 transitions. [2023-11-29 01:35:06,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-29 01:35:06,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4822076978939724) internal successors, (2041), 1376 states have internal predecessors, (2041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:06,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2041 transitions. [2023-11-29 01:35:06,270 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2041 transitions. [2023-11-29 01:35:06,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:06,271 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2041 transitions. [2023-11-29 01:35:06,272 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-29 01:35:06,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2041 transitions. [2023-11-29 01:35:06,278 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:06,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:06,278 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:06,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:06,280 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:06,280 INFO L748 eck$LassoCheckResult]: Stem: 8719#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 8720#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9596#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9597#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9659#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 9600#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9560#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9561#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9589#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8656#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8657#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8764#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9009#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8935#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8658#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8319#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8320#L1036 assume !(0 == ~M_E~0); 8417#L1036-2 assume !(0 == ~T1_E~0); 9322#L1041-1 assume !(0 == ~T2_E~0); 9323#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8694#L1051-1 assume !(0 == ~T4_E~0); 8695#L1056-1 assume !(0 == ~T5_E~0); 9451#L1061-1 assume !(0 == ~T6_E~0); 8589#L1066-1 assume !(0 == ~T7_E~0); 8590#L1071-1 assume !(0 == ~T8_E~0); 9433#L1076-1 assume !(0 == ~T9_E~0); 8479#L1081-1 assume !(0 == ~T10_E~0); 8480#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8880#L1091-1 assume !(0 == ~E_1~0); 9607#L1096-1 assume !(0 == ~E_2~0); 9608#L1101-1 assume !(0 == ~E_3~0); 8948#L1106-1 assume !(0 == ~E_4~0); 8949#L1111-1 assume !(0 == ~E_5~0); 9113#L1116-1 assume !(0 == ~E_6~0); 9114#L1121-1 assume !(0 == ~E_7~0); 8939#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8940#L1131-1 assume !(0 == ~E_9~0); 9215#L1136-1 assume !(0 == ~E_10~0); 9330#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9479#L514 assume 1 == ~m_pc~0; 9444#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8957#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8958#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9531#L1285 assume !(0 != activate_threads_~tmp~1#1); 9643#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8608#L533 assume !(1 == ~t1_pc~0); 8609#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9128#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8372#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8373#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 9351#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9352#L552 assume 1 == ~t2_pc~0; 8828#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8829#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8943#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8944#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 8970#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8971#L571 assume 1 == ~t3_pc~0; 9166#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9167#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8317#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8318#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 9118#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8403#L590 assume !(1 == ~t4_pc~0); 8404#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9176#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8497#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8498#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9378#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9115#L609 assume 1 == ~t5_pc~0; 9116#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9641#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9533#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9534#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 9107#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9108#L628 assume !(1 == ~t6_pc~0); 9040#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9039#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8916#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8917#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 9413#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9414#L647 assume 1 == ~t7_pc~0; 8950#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8951#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9542#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8953#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 8954#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9670#L666 assume !(1 == ~t8_pc~0); 8741#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8742#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8969#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9139#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 8877#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8878#L685 assume 1 == ~t9_pc~0; 9649#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9550#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9003#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8907#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 8908#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9293#L704 assume !(1 == ~t10_pc~0); 8897#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8896#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9157#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8451#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 8452#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8703#L1154 assume !(1 == ~M_E~0); 9401#L1154-2 assume !(1 == ~T1_E~0); 8677#L1159-1 assume !(1 == ~T2_E~0); 8678#L1164-1 assume !(1 == ~T3_E~0); 9137#L1169-1 assume !(1 == ~T4_E~0); 9004#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8806#L1179-1 assume !(1 == ~T6_E~0); 8662#L1184-1 assume !(1 == ~T7_E~0); 8663#L1189-1 assume !(1 == ~T8_E~0); 8739#L1194-1 assume !(1 == ~T9_E~0); 8864#L1199-1 assume !(1 == ~T10_E~0); 8818#L1204-1 assume !(1 == ~E_M~0); 8819#L1209-1 assume !(1 == ~E_1~0); 9372#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9373#L1219-1 assume !(1 == ~E_3~0); 9663#L1224-1 assume !(1 == ~E_4~0); 9161#L1229-1 assume !(1 == ~E_5~0); 8546#L1234-1 assume !(1 == ~E_6~0); 8547#L1239-1 assume !(1 == ~E_7~0); 8604#L1244-1 assume !(1 == ~E_8~0); 8605#L1249-1 assume !(1 == ~E_9~0); 9442#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 8446#L1259-1 assume { :end_inline_reset_delta_events } true; 8447#L1565-2 [2023-11-29 01:35:06,280 INFO L750 eck$LassoCheckResult]: Loop: 8447#L1565-2 assume !false; 9380#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9146#L1011-1 assume !false; 9109#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8882#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8645#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8982#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8669#L866 assume !(0 != eval_~tmp~0#1); 8671#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9178#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9179#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9446#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9625#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9507#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9508#L1051-3 assume !(0 == ~T4_E~0); 9447#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8691#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8692#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8693#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9627#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8438#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8439#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8489#L1091-3 assume !(0 == ~E_1~0); 8490#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9591#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9592#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9624#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9583#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9308#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9309#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9522#L1131-3 assume !(0 == ~E_9~0); 9523#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9675#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9311#L514-36 assume 1 == ~m_pc~0; 9312#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8855#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8856#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9350#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8748#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8749#L533-36 assume 1 == ~t1_pc~0; 9029#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9122#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9573#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9388#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9185#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9186#L552-36 assume 1 == ~t2_pc~0; 8743#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8744#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9244#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9515#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8715#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8716#L571-36 assume !(1 == ~t3_pc~0); 9104#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 8807#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8808#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8999#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9506#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8778#L590-36 assume 1 == ~t4_pc~0; 8779#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9402#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9196#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9197#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9485#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9486#L609-36 assume 1 == ~t5_pc~0; 9363#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9188#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9189#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9530#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 9272#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9079#L628-36 assume !(1 == ~t6_pc~0); 8929#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 8928#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8978#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8979#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9313#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9314#L647-36 assume 1 == ~t7_pc~0; 9237#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8465#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8466#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8483#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8484#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9403#L666-36 assume 1 == ~t8_pc~0; 8674#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8675#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9301#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9302#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8826#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8827#L685-36 assume !(1 == ~t9_pc~0); 8577#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 8578#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9033#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9034#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8966#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8967#L704-36 assume 1 == ~t10_pc~0; 8565#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8566#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8887#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8888#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8593#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8594#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9577#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9460#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9461#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9638#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8893#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8894#L1179-3 assume !(1 == ~T6_E~0); 9552#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8467#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8468#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8837#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8838#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9158#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8338#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8339#L1219-3 assume !(1 == ~E_3~0); 9357#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9358#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9379#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8606#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8607#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9212#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9584#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9361#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9362#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8415#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8875#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 8876#L1584 assume !(0 == start_simulation_~tmp~3#1); 9319#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8620#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8315#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8367#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 8368#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8946#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9201#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9202#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 8447#L1565-2 [2023-11-29 01:35:06,281 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:06,281 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2023-11-29 01:35:06,281 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:06,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386938512] [2023-11-29 01:35:06,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:06,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:06,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:06,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:06,326 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:06,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1386938512] [2023-11-29 01:35:06,326 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1386938512] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:06,326 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:06,326 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:06,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [370300510] [2023-11-29 01:35:06,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:06,327 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:06,328 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:06,328 INFO L85 PathProgramCache]: Analyzing trace with hash -1243014924, now seen corresponding path program 1 times [2023-11-29 01:35:06,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:06,328 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1838671812] [2023-11-29 01:35:06,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:06,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:06,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:06,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:06,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:06,382 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1838671812] [2023-11-29 01:35:06,382 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1838671812] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:06,382 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:06,382 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:06,383 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [460164858] [2023-11-29 01:35:06,383 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:06,383 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:06,383 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:06,384 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:06,384 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:06,384 INFO L87 Difference]: Start difference. First operand 1377 states and 2041 transitions. cyclomatic complexity: 665 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:06,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:06,421 INFO L93 Difference]: Finished difference Result 1377 states and 2040 transitions. [2023-11-29 01:35:06,421 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2040 transitions. [2023-11-29 01:35:06,432 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:06,444 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2040 transitions. [2023-11-29 01:35:06,444 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-29 01:35:06,446 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-29 01:35:06,446 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2040 transitions. [2023-11-29 01:35:06,448 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:06,448 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2023-11-29 01:35:06,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2040 transitions. [2023-11-29 01:35:06,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-29 01:35:06,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4814814814814814) internal successors, (2040), 1376 states have internal predecessors, (2040), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:06,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2040 transitions. [2023-11-29 01:35:06,478 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2023-11-29 01:35:06,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:06,479 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2040 transitions. [2023-11-29 01:35:06,479 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-29 01:35:06,479 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2040 transitions. [2023-11-29 01:35:06,488 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:06,488 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:06,488 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:06,490 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:06,490 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:06,491 INFO L748 eck$LassoCheckResult]: Stem: 11480#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 11481#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 12357#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12358#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12420#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 12361#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12321#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12322#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12350#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11419#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11420#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11525#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11770#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11696#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11421#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11080#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11081#L1036 assume !(0 == ~M_E~0); 11178#L1036-2 assume !(0 == ~T1_E~0); 12083#L1041-1 assume !(0 == ~T2_E~0); 12084#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11455#L1051-1 assume !(0 == ~T4_E~0); 11456#L1056-1 assume !(0 == ~T5_E~0); 12212#L1061-1 assume !(0 == ~T6_E~0); 11350#L1066-1 assume !(0 == ~T7_E~0); 11351#L1071-1 assume !(0 == ~T8_E~0); 12194#L1076-1 assume !(0 == ~T9_E~0); 11240#L1081-1 assume !(0 == ~T10_E~0); 11241#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 11641#L1091-1 assume !(0 == ~E_1~0); 12369#L1096-1 assume !(0 == ~E_2~0); 12370#L1101-1 assume !(0 == ~E_3~0); 11709#L1106-1 assume !(0 == ~E_4~0); 11710#L1111-1 assume !(0 == ~E_5~0); 11874#L1116-1 assume !(0 == ~E_6~0); 11875#L1121-1 assume !(0 == ~E_7~0); 11700#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11701#L1131-1 assume !(0 == ~E_9~0); 11976#L1136-1 assume !(0 == ~E_10~0); 12091#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12240#L514 assume 1 == ~m_pc~0; 12205#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11718#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11719#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12293#L1285 assume !(0 != activate_threads_~tmp~1#1); 12405#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11369#L533 assume !(1 == ~t1_pc~0); 11370#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11889#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11136#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 12112#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12113#L552 assume 1 == ~t2_pc~0; 11590#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11591#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11704#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11705#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 11736#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11737#L571 assume 1 == ~t3_pc~0; 11929#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11930#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11078#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11079#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 11879#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11164#L590 assume !(1 == ~t4_pc~0); 11165#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11938#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11258#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11259#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12140#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11876#L609 assume 1 == ~t5_pc~0; 11877#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12402#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12294#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12295#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 11868#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11869#L628 assume !(1 == ~t6_pc~0); 11801#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11800#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11678#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11679#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 12174#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12175#L647 assume 1 == ~t7_pc~0; 11711#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11712#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12303#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11716#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 11717#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12431#L666 assume !(1 == ~t8_pc~0); 11502#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11503#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11730#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11901#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 11639#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11640#L685 assume 1 == ~t9_pc~0; 12410#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12311#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11764#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11668#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 11669#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12054#L704 assume !(1 == ~t10_pc~0); 11658#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11657#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11919#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11212#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 11213#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11464#L1154 assume !(1 == ~M_E~0); 12162#L1154-2 assume !(1 == ~T1_E~0); 11438#L1159-1 assume !(1 == ~T2_E~0); 11439#L1164-1 assume !(1 == ~T3_E~0); 11898#L1169-1 assume !(1 == ~T4_E~0); 11765#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11569#L1179-1 assume !(1 == ~T6_E~0); 11423#L1184-1 assume !(1 == ~T7_E~0); 11424#L1189-1 assume !(1 == ~T8_E~0); 11500#L1194-1 assume !(1 == ~T9_E~0); 11627#L1199-1 assume !(1 == ~T10_E~0); 11581#L1204-1 assume !(1 == ~E_M~0); 11582#L1209-1 assume !(1 == ~E_1~0); 12135#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12136#L1219-1 assume !(1 == ~E_3~0); 12424#L1224-1 assume !(1 == ~E_4~0); 11923#L1229-1 assume !(1 == ~E_5~0); 11307#L1234-1 assume !(1 == ~E_6~0); 11308#L1239-1 assume !(1 == ~E_7~0); 11365#L1244-1 assume !(1 == ~E_8~0); 11366#L1249-1 assume !(1 == ~E_9~0); 12203#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 11207#L1259-1 assume { :end_inline_reset_delta_events } true; 11208#L1565-2 [2023-11-29 01:35:06,491 INFO L750 eck$LassoCheckResult]: Loop: 11208#L1565-2 assume !false; 12141#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11907#L1011-1 assume !false; 11870#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11646#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11406#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11743#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11435#L866 assume !(0 != eval_~tmp~0#1); 11437#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11940#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11941#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12207#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12386#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12268#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12269#L1051-3 assume !(0 == ~T4_E~0); 12208#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11452#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11453#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11454#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12388#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11199#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11200#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11254#L1091-3 assume !(0 == ~E_1~0); 11255#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12352#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12353#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12385#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12344#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12069#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12070#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12283#L1131-3 assume !(0 == ~E_9~0); 12284#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12436#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12072#L514-36 assume !(1 == ~m_pc~0); 11781#L514-38 is_master_triggered_~__retres1~0#1 := 0; 11616#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11617#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12111#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11509#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11510#L533-36 assume 1 == ~t1_pc~0; 11789#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11883#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12334#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12149#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11946#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11947#L552-36 assume 1 == ~t2_pc~0; 11504#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11505#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12005#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12276#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11476#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11477#L571-36 assume 1 == ~t3_pc~0; 11864#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11567#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11568#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11760#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12267#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11539#L590-36 assume 1 == ~t4_pc~0; 11540#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12163#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11956#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11957#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12246#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12247#L609-36 assume 1 == ~t5_pc~0; 12124#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11949#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11950#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12291#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 12033#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11840#L628-36 assume 1 == ~t6_pc~0; 11688#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11689#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11739#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11740#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12074#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12075#L647-36 assume 1 == ~t7_pc~0; 11998#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11226#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11227#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11244#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11245#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12164#L666-36 assume 1 == ~t8_pc~0; 11432#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11433#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12062#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12063#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11587#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11588#L685-36 assume 1 == ~t9_pc~0; 12049#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11339#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11794#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11795#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11727#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11728#L704-36 assume !(1 == ~t10_pc~0); 11328#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 11327#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11648#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11649#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11354#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11355#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12338#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12221#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12222#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12399#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11654#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11655#L1179-3 assume !(1 == ~T6_E~0); 12313#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11228#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11229#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11598#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11599#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11918#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11096#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11097#L1219-3 assume !(1 == ~E_3~0); 12118#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12119#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12139#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11367#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11368#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11969#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12345#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12122#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12123#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11176#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11636#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 11637#L1584 assume !(0 == start_simulation_~tmp~3#1); 12080#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11381#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11076#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11128#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 11129#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11707#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11962#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 11963#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 11208#L1565-2 [2023-11-29 01:35:06,492 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:06,492 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2023-11-29 01:35:06,492 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:06,492 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1500868884] [2023-11-29 01:35:06,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:06,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:06,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:06,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:06,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:06,557 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1500868884] [2023-11-29 01:35:06,557 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1500868884] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:06,557 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:06,557 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:06,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [450018858] [2023-11-29 01:35:06,557 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:06,558 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:06,558 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:06,558 INFO L85 PathProgramCache]: Analyzing trace with hash 157765683, now seen corresponding path program 1 times [2023-11-29 01:35:06,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:06,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1419754496] [2023-11-29 01:35:06,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:06,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:06,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:06,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:06,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:06,625 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1419754496] [2023-11-29 01:35:06,625 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1419754496] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:06,625 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:06,626 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:06,626 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1398723497] [2023-11-29 01:35:06,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:06,626 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:06,627 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:06,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:06,627 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:06,627 INFO L87 Difference]: Start difference. First operand 1377 states and 2040 transitions. cyclomatic complexity: 664 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:06,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:06,662 INFO L93 Difference]: Finished difference Result 1377 states and 2039 transitions. [2023-11-29 01:35:06,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2039 transitions. [2023-11-29 01:35:06,673 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:06,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2039 transitions. [2023-11-29 01:35:06,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-29 01:35:06,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-29 01:35:06,686 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2039 transitions. [2023-11-29 01:35:06,688 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:06,688 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2039 transitions. [2023-11-29 01:35:06,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2039 transitions. [2023-11-29 01:35:06,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-29 01:35:06,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4807552650689906) internal successors, (2039), 1376 states have internal predecessors, (2039), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:06,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2039 transitions. [2023-11-29 01:35:06,717 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2039 transitions. [2023-11-29 01:35:06,717 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:06,718 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2039 transitions. [2023-11-29 01:35:06,718 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-29 01:35:06,718 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2039 transitions. [2023-11-29 01:35:06,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:06,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:06,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:06,729 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:06,729 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:06,730 INFO L748 eck$LassoCheckResult]: Stem: 14241#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 15118#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15119#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15181#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 15122#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15082#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15083#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15111#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14178#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14179#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14286#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14531#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14457#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14180#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13841#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13842#L1036 assume !(0 == ~M_E~0); 13939#L1036-2 assume !(0 == ~T1_E~0); 14844#L1041-1 assume !(0 == ~T2_E~0); 14845#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14216#L1051-1 assume !(0 == ~T4_E~0); 14217#L1056-1 assume !(0 == ~T5_E~0); 14973#L1061-1 assume !(0 == ~T6_E~0); 14111#L1066-1 assume !(0 == ~T7_E~0); 14112#L1071-1 assume !(0 == ~T8_E~0); 14955#L1076-1 assume !(0 == ~T9_E~0); 14001#L1081-1 assume !(0 == ~T10_E~0); 14002#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14402#L1091-1 assume !(0 == ~E_1~0); 15129#L1096-1 assume !(0 == ~E_2~0); 15130#L1101-1 assume !(0 == ~E_3~0); 14470#L1106-1 assume !(0 == ~E_4~0); 14471#L1111-1 assume !(0 == ~E_5~0); 14635#L1116-1 assume !(0 == ~E_6~0); 14636#L1121-1 assume !(0 == ~E_7~0); 14461#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14462#L1131-1 assume !(0 == ~E_9~0); 14737#L1136-1 assume !(0 == ~E_10~0); 14852#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15001#L514 assume 1 == ~m_pc~0; 14966#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14479#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14480#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15053#L1285 assume !(0 != activate_threads_~tmp~1#1); 15165#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14130#L533 assume !(1 == ~t1_pc~0); 14131#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14650#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13894#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13895#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 14873#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14874#L552 assume 1 == ~t2_pc~0; 14350#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14351#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14465#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14466#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 14492#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14493#L571 assume 1 == ~t3_pc~0; 14688#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14689#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13839#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13840#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 14640#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13925#L590 assume !(1 == ~t4_pc~0); 13926#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14698#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14019#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14020#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14900#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14637#L609 assume 1 == ~t5_pc~0; 14638#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15163#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15055#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15056#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 14629#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14630#L628 assume !(1 == ~t6_pc~0); 14562#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14561#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14438#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14439#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 14935#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14936#L647 assume 1 == ~t7_pc~0; 14472#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14473#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15064#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14475#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 14476#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15192#L666 assume !(1 == ~t8_pc~0); 14263#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14264#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14491#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14661#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 14399#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14400#L685 assume 1 == ~t9_pc~0; 15171#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15072#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14525#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14429#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 14430#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14815#L704 assume !(1 == ~t10_pc~0); 14419#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14418#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14679#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13973#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 13974#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14225#L1154 assume !(1 == ~M_E~0); 14923#L1154-2 assume !(1 == ~T1_E~0); 14199#L1159-1 assume !(1 == ~T2_E~0); 14200#L1164-1 assume !(1 == ~T3_E~0); 14659#L1169-1 assume !(1 == ~T4_E~0); 14526#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14328#L1179-1 assume !(1 == ~T6_E~0); 14184#L1184-1 assume !(1 == ~T7_E~0); 14185#L1189-1 assume !(1 == ~T8_E~0); 14261#L1194-1 assume !(1 == ~T9_E~0); 14386#L1199-1 assume !(1 == ~T10_E~0); 14340#L1204-1 assume !(1 == ~E_M~0); 14341#L1209-1 assume !(1 == ~E_1~0); 14894#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14895#L1219-1 assume !(1 == ~E_3~0); 15185#L1224-1 assume !(1 == ~E_4~0); 14683#L1229-1 assume !(1 == ~E_5~0); 14068#L1234-1 assume !(1 == ~E_6~0); 14069#L1239-1 assume !(1 == ~E_7~0); 14126#L1244-1 assume !(1 == ~E_8~0); 14127#L1249-1 assume !(1 == ~E_9~0); 14964#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13968#L1259-1 assume { :end_inline_reset_delta_events } true; 13969#L1565-2 [2023-11-29 01:35:06,730 INFO L750 eck$LassoCheckResult]: Loop: 13969#L1565-2 assume !false; 14902#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14667#L1011-1 assume !false; 14631#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14404#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14167#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14504#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14191#L866 assume !(0 != eval_~tmp~0#1); 14193#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14700#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14701#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14968#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15147#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15029#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15030#L1051-3 assume !(0 == ~T4_E~0); 14969#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14213#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14214#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14215#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15149#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13960#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13961#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14011#L1091-3 assume !(0 == ~E_1~0); 14012#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15113#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15114#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15146#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15105#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14830#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14831#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15044#L1131-3 assume !(0 == ~E_9~0); 15045#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15197#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14833#L514-36 assume 1 == ~m_pc~0; 14834#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14377#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14378#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14872#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14270#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14271#L533-36 assume 1 == ~t1_pc~0; 14551#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14644#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15095#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14910#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14707#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14708#L552-36 assume 1 == ~t2_pc~0; 14265#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14266#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14766#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15037#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14237#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14238#L571-36 assume 1 == ~t3_pc~0; 14625#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14329#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14330#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14521#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15028#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14300#L590-36 assume 1 == ~t4_pc~0; 14301#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14924#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14717#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14718#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15007#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15008#L609-36 assume 1 == ~t5_pc~0; 14885#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14710#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14711#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15052#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 14794#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14601#L628-36 assume 1 == ~t6_pc~0; 14449#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14450#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14500#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14501#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14835#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14836#L647-36 assume 1 == ~t7_pc~0; 14759#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13987#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13988#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14005#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14006#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14925#L666-36 assume 1 == ~t8_pc~0; 14196#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14197#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14823#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14824#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14348#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14349#L685-36 assume !(1 == ~t9_pc~0); 14099#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 14100#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14555#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14556#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14488#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14489#L704-36 assume 1 == ~t10_pc~0; 14087#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14088#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14409#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14410#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14115#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14116#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15099#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14982#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14983#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15160#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14415#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14416#L1179-3 assume !(1 == ~T6_E~0); 15074#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13989#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13990#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14359#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14360#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14680#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13857#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13858#L1219-3 assume !(1 == ~E_3~0); 14879#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14880#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14901#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14128#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14129#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14734#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15106#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14883#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14884#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13937#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14397#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14398#L1584 assume !(0 == start_simulation_~tmp~3#1); 14841#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14142#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13837#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13889#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 13890#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14468#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14723#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 14724#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 13969#L1565-2 [2023-11-29 01:35:06,731 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:06,731 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2023-11-29 01:35:06,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:06,731 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [823613021] [2023-11-29 01:35:06,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:06,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:06,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:06,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:06,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:06,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [823613021] [2023-11-29 01:35:06,781 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [823613021] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:06,781 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:06,781 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:06,781 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [792003838] [2023-11-29 01:35:06,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:06,782 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:06,782 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:06,783 INFO L85 PathProgramCache]: Analyzing trace with hash -220510030, now seen corresponding path program 1 times [2023-11-29 01:35:06,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:06,783 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082022418] [2023-11-29 01:35:06,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:06,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:06,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:06,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:06,847 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:06,847 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1082022418] [2023-11-29 01:35:06,848 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1082022418] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:06,848 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:06,848 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:06,848 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1383788937] [2023-11-29 01:35:06,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:06,849 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:06,849 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:06,849 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:06,849 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:06,850 INFO L87 Difference]: Start difference. First operand 1377 states and 2039 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:06,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:06,883 INFO L93 Difference]: Finished difference Result 1377 states and 2038 transitions. [2023-11-29 01:35:06,883 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2038 transitions. [2023-11-29 01:35:06,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:06,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2038 transitions. [2023-11-29 01:35:06,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-29 01:35:06,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-29 01:35:06,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2038 transitions. [2023-11-29 01:35:06,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:06,908 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2038 transitions. [2023-11-29 01:35:06,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2038 transitions. [2023-11-29 01:35:06,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-29 01:35:06,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4800290486564995) internal successors, (2038), 1376 states have internal predecessors, (2038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:06,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2038 transitions. [2023-11-29 01:35:06,939 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2038 transitions. [2023-11-29 01:35:06,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:06,940 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2038 transitions. [2023-11-29 01:35:06,940 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-29 01:35:06,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2038 transitions. [2023-11-29 01:35:06,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:06,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:06,948 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:06,950 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:06,950 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:06,951 INFO L748 eck$LassoCheckResult]: Stem: 17002#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 17003#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 17879#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17880#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17942#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 17883#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17843#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17844#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17872#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16939#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16940#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17047#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17292#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17218#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16941#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16602#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16603#L1036 assume !(0 == ~M_E~0); 16700#L1036-2 assume !(0 == ~T1_E~0); 17605#L1041-1 assume !(0 == ~T2_E~0); 17606#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16977#L1051-1 assume !(0 == ~T4_E~0); 16978#L1056-1 assume !(0 == ~T5_E~0); 17734#L1061-1 assume !(0 == ~T6_E~0); 16872#L1066-1 assume !(0 == ~T7_E~0); 16873#L1071-1 assume !(0 == ~T8_E~0); 17716#L1076-1 assume !(0 == ~T9_E~0); 16762#L1081-1 assume !(0 == ~T10_E~0); 16763#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 17163#L1091-1 assume !(0 == ~E_1~0); 17890#L1096-1 assume !(0 == ~E_2~0); 17891#L1101-1 assume !(0 == ~E_3~0); 17231#L1106-1 assume !(0 == ~E_4~0); 17232#L1111-1 assume !(0 == ~E_5~0); 17396#L1116-1 assume !(0 == ~E_6~0); 17397#L1121-1 assume !(0 == ~E_7~0); 17222#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 17223#L1131-1 assume !(0 == ~E_9~0); 17498#L1136-1 assume !(0 == ~E_10~0); 17613#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17762#L514 assume 1 == ~m_pc~0; 17727#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17240#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17241#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17814#L1285 assume !(0 != activate_threads_~tmp~1#1); 17926#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16891#L533 assume !(1 == ~t1_pc~0); 16892#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17411#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16655#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16656#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 17634#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17635#L552 assume 1 == ~t2_pc~0; 17111#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17112#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17226#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17227#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 17253#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17254#L571 assume 1 == ~t3_pc~0; 17449#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17450#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16600#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16601#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 17401#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16686#L590 assume !(1 == ~t4_pc~0); 16687#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17459#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16780#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16781#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17662#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17398#L609 assume 1 == ~t5_pc~0; 17399#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17924#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17816#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17817#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 17390#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17391#L628 assume !(1 == ~t6_pc~0); 17323#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17322#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17199#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17200#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 17696#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17697#L647 assume 1 == ~t7_pc~0; 17233#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17234#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17825#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17236#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 17237#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17953#L666 assume !(1 == ~t8_pc~0); 17024#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17025#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17252#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17422#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 17160#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17161#L685 assume 1 == ~t9_pc~0; 17932#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17833#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17286#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17190#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 17191#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17576#L704 assume !(1 == ~t10_pc~0); 17180#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17179#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17441#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16734#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 16735#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16986#L1154 assume !(1 == ~M_E~0); 17684#L1154-2 assume !(1 == ~T1_E~0); 16960#L1159-1 assume !(1 == ~T2_E~0); 16961#L1164-1 assume !(1 == ~T3_E~0); 17420#L1169-1 assume !(1 == ~T4_E~0); 17287#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17089#L1179-1 assume !(1 == ~T6_E~0); 16945#L1184-1 assume !(1 == ~T7_E~0); 16946#L1189-1 assume !(1 == ~T8_E~0); 17022#L1194-1 assume !(1 == ~T9_E~0); 17147#L1199-1 assume !(1 == ~T10_E~0); 17101#L1204-1 assume !(1 == ~E_M~0); 17102#L1209-1 assume !(1 == ~E_1~0); 17655#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17656#L1219-1 assume !(1 == ~E_3~0); 17946#L1224-1 assume !(1 == ~E_4~0); 17444#L1229-1 assume !(1 == ~E_5~0); 16829#L1234-1 assume !(1 == ~E_6~0); 16830#L1239-1 assume !(1 == ~E_7~0); 16887#L1244-1 assume !(1 == ~E_8~0); 16888#L1249-1 assume !(1 == ~E_9~0); 17725#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16729#L1259-1 assume { :end_inline_reset_delta_events } true; 16730#L1565-2 [2023-11-29 01:35:06,951 INFO L750 eck$LassoCheckResult]: Loop: 16730#L1565-2 assume !false; 17663#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17429#L1011-1 assume !false; 17392#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17165#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16928#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17265#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16952#L866 assume !(0 != eval_~tmp~0#1); 16954#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17461#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17462#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17729#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17908#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17790#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17791#L1051-3 assume !(0 == ~T4_E~0); 17730#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16974#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16975#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16976#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17910#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16721#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16722#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16772#L1091-3 assume !(0 == ~E_1~0); 16773#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17874#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17875#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17907#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17866#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17591#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17592#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17805#L1131-3 assume !(0 == ~E_9~0); 17806#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17958#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17594#L514-36 assume !(1 == ~m_pc~0); 17303#L514-38 is_master_triggered_~__retres1~0#1 := 0; 17138#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17139#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17633#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17031#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17032#L533-36 assume 1 == ~t1_pc~0; 17312#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17405#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17856#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17671#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17468#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17469#L552-36 assume 1 == ~t2_pc~0; 17026#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17027#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17527#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17798#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16998#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16999#L571-36 assume 1 == ~t3_pc~0; 17386#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17090#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17091#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17282#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17789#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17061#L590-36 assume 1 == ~t4_pc~0; 17062#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17685#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17479#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17480#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17768#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17769#L609-36 assume 1 == ~t5_pc~0; 17646#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17471#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17472#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17813#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 17555#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17362#L628-36 assume 1 == ~t6_pc~0; 17210#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17211#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17261#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17262#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17596#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17597#L647-36 assume 1 == ~t7_pc~0; 17520#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16750#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16751#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16766#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16767#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17686#L666-36 assume 1 == ~t8_pc~0; 16957#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16958#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17584#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17585#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17109#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17110#L685-36 assume 1 == ~t9_pc~0; 17570#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16859#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17314#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17315#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17249#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17250#L704-36 assume 1 == ~t10_pc~0; 16848#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16849#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17170#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17171#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16874#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16875#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17860#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17743#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17744#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17921#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17176#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17177#L1179-3 assume !(1 == ~T6_E~0); 17835#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16748#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16749#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17120#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17121#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17440#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16618#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16619#L1219-3 assume !(1 == ~E_3~0); 17640#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17641#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17661#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16889#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16890#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17491#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17867#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17644#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17645#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16698#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17158#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17159#L1584 assume !(0 == start_simulation_~tmp~3#1); 17602#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16903#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16598#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16650#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 16651#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17228#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17484#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 17485#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 16730#L1565-2 [2023-11-29 01:35:06,952 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:06,952 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2023-11-29 01:35:06,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:06,952 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524312321] [2023-11-29 01:35:06,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:06,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:06,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:07,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:07,014 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:07,014 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [524312321] [2023-11-29 01:35:07,014 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [524312321] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:07,014 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:07,015 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:07,015 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [347754776] [2023-11-29 01:35:07,015 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:07,015 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:07,016 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:07,016 INFO L85 PathProgramCache]: Analyzing trace with hash 642940402, now seen corresponding path program 2 times [2023-11-29 01:35:07,016 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:07,016 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1818947817] [2023-11-29 01:35:07,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:07,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:07,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:07,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:07,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:07,077 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1818947817] [2023-11-29 01:35:07,077 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1818947817] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:07,077 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:07,077 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:07,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2005686325] [2023-11-29 01:35:07,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:07,078 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:07,078 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:07,079 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:07,079 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:07,079 INFO L87 Difference]: Start difference. First operand 1377 states and 2038 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:07,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:07,110 INFO L93 Difference]: Finished difference Result 1377 states and 2037 transitions. [2023-11-29 01:35:07,110 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2037 transitions. [2023-11-29 01:35:07,116 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:07,125 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2037 transitions. [2023-11-29 01:35:07,125 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-29 01:35:07,126 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-29 01:35:07,126 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2037 transitions. [2023-11-29 01:35:07,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:07,128 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2037 transitions. [2023-11-29 01:35:07,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2037 transitions. [2023-11-29 01:35:07,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-29 01:35:07,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4793028322440087) internal successors, (2037), 1376 states have internal predecessors, (2037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:07,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2037 transitions. [2023-11-29 01:35:07,154 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2037 transitions. [2023-11-29 01:35:07,154 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:07,155 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2037 transitions. [2023-11-29 01:35:07,155 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-29 01:35:07,156 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2037 transitions. [2023-11-29 01:35:07,161 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:07,161 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:07,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:07,162 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:07,163 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:07,163 INFO L748 eck$LassoCheckResult]: Stem: 19763#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 19764#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 20640#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20641#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20703#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 20644#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20604#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20605#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20633#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19702#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19703#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19808#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20053#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19979#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19704#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19363#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19364#L1036 assume !(0 == ~M_E~0); 19461#L1036-2 assume !(0 == ~T1_E~0); 20366#L1041-1 assume !(0 == ~T2_E~0); 20367#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19738#L1051-1 assume !(0 == ~T4_E~0); 19739#L1056-1 assume !(0 == ~T5_E~0); 20495#L1061-1 assume !(0 == ~T6_E~0); 19633#L1066-1 assume !(0 == ~T7_E~0); 19634#L1071-1 assume !(0 == ~T8_E~0); 20477#L1076-1 assume !(0 == ~T9_E~0); 19523#L1081-1 assume !(0 == ~T10_E~0); 19524#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 19924#L1091-1 assume !(0 == ~E_1~0); 20652#L1096-1 assume !(0 == ~E_2~0); 20653#L1101-1 assume !(0 == ~E_3~0); 19992#L1106-1 assume !(0 == ~E_4~0); 19993#L1111-1 assume !(0 == ~E_5~0); 20157#L1116-1 assume !(0 == ~E_6~0); 20158#L1121-1 assume !(0 == ~E_7~0); 19983#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19984#L1131-1 assume !(0 == ~E_9~0); 20259#L1136-1 assume !(0 == ~E_10~0); 20374#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20523#L514 assume 1 == ~m_pc~0; 20488#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20001#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20002#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20576#L1285 assume !(0 != activate_threads_~tmp~1#1); 20688#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19655#L533 assume !(1 == ~t1_pc~0); 19656#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20172#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19418#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19419#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 20395#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20396#L552 assume 1 == ~t2_pc~0; 19873#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19874#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19987#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19988#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 20019#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20020#L571 assume 1 == ~t3_pc~0; 20212#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20213#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19361#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19362#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 20162#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19447#L590 assume !(1 == ~t4_pc~0); 19448#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20221#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19541#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19542#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20423#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20159#L609 assume 1 == ~t5_pc~0; 20160#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20685#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20577#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20578#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 20151#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20152#L628 assume !(1 == ~t6_pc~0); 20084#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 20083#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19963#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19964#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 20457#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20458#L647 assume 1 == ~t7_pc~0; 19994#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19995#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20586#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19999#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 20000#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20714#L666 assume !(1 == ~t8_pc~0); 19785#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19786#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20013#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20184#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 19922#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19923#L685 assume 1 == ~t9_pc~0; 20693#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20594#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20047#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19951#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 19952#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20337#L704 assume !(1 == ~t10_pc~0); 19941#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19940#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20202#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19495#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 19496#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19747#L1154 assume !(1 == ~M_E~0); 20445#L1154-2 assume !(1 == ~T1_E~0); 19721#L1159-1 assume !(1 == ~T2_E~0); 19722#L1164-1 assume !(1 == ~T3_E~0); 20181#L1169-1 assume !(1 == ~T4_E~0); 20048#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19852#L1179-1 assume !(1 == ~T6_E~0); 19706#L1184-1 assume !(1 == ~T7_E~0); 19707#L1189-1 assume !(1 == ~T8_E~0); 19783#L1194-1 assume !(1 == ~T9_E~0); 19910#L1199-1 assume !(1 == ~T10_E~0); 19864#L1204-1 assume !(1 == ~E_M~0); 19865#L1209-1 assume !(1 == ~E_1~0); 20418#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20419#L1219-1 assume !(1 == ~E_3~0); 20707#L1224-1 assume !(1 == ~E_4~0); 20206#L1229-1 assume !(1 == ~E_5~0); 19590#L1234-1 assume !(1 == ~E_6~0); 19591#L1239-1 assume !(1 == ~E_7~0); 19648#L1244-1 assume !(1 == ~E_8~0); 19649#L1249-1 assume !(1 == ~E_9~0); 20486#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19490#L1259-1 assume { :end_inline_reset_delta_events } true; 19491#L1565-2 [2023-11-29 01:35:07,163 INFO L750 eck$LassoCheckResult]: Loop: 19491#L1565-2 assume !false; 20424#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20190#L1011-1 assume !false; 20153#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19929#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19689#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20026#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19718#L866 assume !(0 != eval_~tmp~0#1); 19720#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20223#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20224#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20490#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20670#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20551#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20552#L1051-3 assume !(0 == ~T4_E~0); 20491#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19735#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19736#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19737#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20671#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19482#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19483#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19537#L1091-3 assume !(0 == ~E_1~0); 19538#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20635#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20636#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20668#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20627#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20352#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20353#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20566#L1131-3 assume !(0 == ~E_9~0); 20567#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20719#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20354#L514-36 assume 1 == ~m_pc~0; 20355#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19899#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19900#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20394#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19792#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19793#L533-36 assume 1 == ~t1_pc~0; 20072#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20166#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20617#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20432#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20229#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20230#L552-36 assume 1 == ~t2_pc~0; 19787#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19788#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20288#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20559#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19759#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19760#L571-36 assume 1 == ~t3_pc~0; 20147#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19850#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19851#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20043#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20550#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19822#L590-36 assume !(1 == ~t4_pc~0); 19824#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 20446#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20239#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20240#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20529#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20530#L609-36 assume 1 == ~t5_pc~0; 20407#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20232#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20233#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20574#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 20316#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20123#L628-36 assume 1 == ~t6_pc~0; 19971#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19972#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20022#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20023#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20357#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20358#L647-36 assume 1 == ~t7_pc~0; 20281#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19509#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19510#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19527#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19528#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20447#L666-36 assume 1 == ~t8_pc~0; 19715#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19716#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20345#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20346#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19870#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19871#L685-36 assume !(1 == ~t9_pc~0); 19621#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 19622#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20077#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20078#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20010#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20011#L704-36 assume 1 == ~t10_pc~0; 19609#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19610#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19931#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19932#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19637#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19638#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20621#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20504#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20505#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20682#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19937#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19938#L1179-3 assume !(1 == ~T6_E~0); 20596#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19511#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19512#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19881#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19882#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20201#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19379#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19380#L1219-3 assume !(1 == ~E_3~0); 20401#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20402#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20422#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19650#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19651#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20252#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20628#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20405#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20406#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19459#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19919#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 19920#L1584 assume !(0 == start_simulation_~tmp~3#1); 20363#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19664#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19359#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19411#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 19412#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19990#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20245#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 20246#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 19491#L1565-2 [2023-11-29 01:35:07,164 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:07,164 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2023-11-29 01:35:07,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:07,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799058547] [2023-11-29 01:35:07,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:07,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:07,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:07,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:07,209 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:07,209 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799058547] [2023-11-29 01:35:07,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [799058547] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:07,210 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:07,210 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:07,210 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [749183748] [2023-11-29 01:35:07,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:07,211 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:07,211 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:07,211 INFO L85 PathProgramCache]: Analyzing trace with hash -2062823821, now seen corresponding path program 1 times [2023-11-29 01:35:07,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:07,212 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1049144443] [2023-11-29 01:35:07,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:07,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:07,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:07,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:07,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:07,268 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1049144443] [2023-11-29 01:35:07,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1049144443] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:07,268 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:07,269 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:07,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674153351] [2023-11-29 01:35:07,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:07,269 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:07,269 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:07,270 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:07,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:07,270 INFO L87 Difference]: Start difference. First operand 1377 states and 2037 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:07,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:07,295 INFO L93 Difference]: Finished difference Result 1377 states and 2036 transitions. [2023-11-29 01:35:07,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2036 transitions. [2023-11-29 01:35:07,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:07,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2036 transitions. [2023-11-29 01:35:07,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-29 01:35:07,309 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-29 01:35:07,310 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2036 transitions. [2023-11-29 01:35:07,311 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:07,311 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2036 transitions. [2023-11-29 01:35:07,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2036 transitions. [2023-11-29 01:35:07,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-29 01:35:07,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.478576615831518) internal successors, (2036), 1376 states have internal predecessors, (2036), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:07,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2036 transitions. [2023-11-29 01:35:07,331 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2036 transitions. [2023-11-29 01:35:07,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:07,332 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2036 transitions. [2023-11-29 01:35:07,332 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-29 01:35:07,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2036 transitions. [2023-11-29 01:35:07,337 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:07,337 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:07,337 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:07,339 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:07,339 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:07,340 INFO L748 eck$LassoCheckResult]: Stem: 22524#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 23401#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23402#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23464#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 23405#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23365#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23366#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23394#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22461#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22462#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22569#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22814#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22740#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22463#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22124#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22125#L1036 assume !(0 == ~M_E~0); 22222#L1036-2 assume !(0 == ~T1_E~0); 23127#L1041-1 assume !(0 == ~T2_E~0); 23128#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22499#L1051-1 assume !(0 == ~T4_E~0); 22500#L1056-1 assume !(0 == ~T5_E~0); 23256#L1061-1 assume !(0 == ~T6_E~0); 22394#L1066-1 assume !(0 == ~T7_E~0); 22395#L1071-1 assume !(0 == ~T8_E~0); 23238#L1076-1 assume !(0 == ~T9_E~0); 22284#L1081-1 assume !(0 == ~T10_E~0); 22285#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 22685#L1091-1 assume !(0 == ~E_1~0); 23412#L1096-1 assume !(0 == ~E_2~0); 23413#L1101-1 assume !(0 == ~E_3~0); 22753#L1106-1 assume !(0 == ~E_4~0); 22754#L1111-1 assume !(0 == ~E_5~0); 22918#L1116-1 assume !(0 == ~E_6~0); 22919#L1121-1 assume !(0 == ~E_7~0); 22744#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 22745#L1131-1 assume !(0 == ~E_9~0); 23020#L1136-1 assume !(0 == ~E_10~0); 23135#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23284#L514 assume 1 == ~m_pc~0; 23249#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22762#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22763#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23336#L1285 assume !(0 != activate_threads_~tmp~1#1); 23448#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22413#L533 assume !(1 == ~t1_pc~0); 22414#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22933#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22177#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22178#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 23156#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23157#L552 assume 1 == ~t2_pc~0; 22633#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22634#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22748#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22749#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 22775#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22776#L571 assume 1 == ~t3_pc~0; 22971#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22972#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22122#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22123#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 22923#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22208#L590 assume !(1 == ~t4_pc~0); 22209#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22981#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22302#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22303#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23183#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22920#L609 assume 1 == ~t5_pc~0; 22921#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23446#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23338#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23339#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 22912#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22913#L628 assume !(1 == ~t6_pc~0); 22845#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22844#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22721#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22722#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 23218#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23219#L647 assume 1 == ~t7_pc~0; 22755#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22756#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23347#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22758#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 22759#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23475#L666 assume !(1 == ~t8_pc~0); 22546#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22547#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22774#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22944#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 22682#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22683#L685 assume 1 == ~t9_pc~0; 23454#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23355#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22808#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22712#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 22713#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23098#L704 assume !(1 == ~t10_pc~0); 22702#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22701#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22962#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22256#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 22257#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22508#L1154 assume !(1 == ~M_E~0); 23206#L1154-2 assume !(1 == ~T1_E~0); 22482#L1159-1 assume !(1 == ~T2_E~0); 22483#L1164-1 assume !(1 == ~T3_E~0); 22942#L1169-1 assume !(1 == ~T4_E~0); 22809#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22611#L1179-1 assume !(1 == ~T6_E~0); 22467#L1184-1 assume !(1 == ~T7_E~0); 22468#L1189-1 assume !(1 == ~T8_E~0); 22544#L1194-1 assume !(1 == ~T9_E~0); 22669#L1199-1 assume !(1 == ~T10_E~0); 22623#L1204-1 assume !(1 == ~E_M~0); 22624#L1209-1 assume !(1 == ~E_1~0); 23177#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 23178#L1219-1 assume !(1 == ~E_3~0); 23468#L1224-1 assume !(1 == ~E_4~0); 22966#L1229-1 assume !(1 == ~E_5~0); 22351#L1234-1 assume !(1 == ~E_6~0); 22352#L1239-1 assume !(1 == ~E_7~0); 22409#L1244-1 assume !(1 == ~E_8~0); 22410#L1249-1 assume !(1 == ~E_9~0); 23247#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22251#L1259-1 assume { :end_inline_reset_delta_events } true; 22252#L1565-2 [2023-11-29 01:35:07,340 INFO L750 eck$LassoCheckResult]: Loop: 22252#L1565-2 assume !false; 23185#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22950#L1011-1 assume !false; 22914#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22687#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22450#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22787#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22474#L866 assume !(0 != eval_~tmp~0#1); 22476#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22983#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22984#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23251#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23430#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23312#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23313#L1051-3 assume !(0 == ~T4_E~0); 23252#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22496#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22497#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22498#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23432#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22243#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22244#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22294#L1091-3 assume !(0 == ~E_1~0); 22295#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23396#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23397#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23429#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23388#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23113#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23114#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23327#L1131-3 assume !(0 == ~E_9~0); 23328#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23480#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23116#L514-36 assume !(1 == ~m_pc~0); 22825#L514-38 is_master_triggered_~__retres1~0#1 := 0; 22660#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22661#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23155#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22553#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22554#L533-36 assume 1 == ~t1_pc~0; 22834#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22927#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23378#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23193#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22990#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22991#L552-36 assume 1 == ~t2_pc~0; 22548#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22549#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23049#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23320#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22520#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22521#L571-36 assume 1 == ~t3_pc~0; 22908#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22612#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22613#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22804#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23311#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22583#L590-36 assume 1 == ~t4_pc~0; 22584#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23207#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23000#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23001#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23290#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23291#L609-36 assume 1 == ~t5_pc~0; 23168#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22993#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22994#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23335#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 23077#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22884#L628-36 assume 1 == ~t6_pc~0; 22732#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22733#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22783#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22784#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23118#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23119#L647-36 assume 1 == ~t7_pc~0; 23042#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22270#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22271#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22288#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22289#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23208#L666-36 assume !(1 == ~t8_pc~0); 22481#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 22480#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23106#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23107#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22631#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22632#L685-36 assume 1 == ~t9_pc~0; 23093#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22383#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22838#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22839#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22771#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22772#L704-36 assume 1 == ~t10_pc~0; 22370#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22371#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22692#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22693#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22398#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22399#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23382#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23265#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23266#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23443#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22698#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22699#L1179-3 assume !(1 == ~T6_E~0); 23357#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22272#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22273#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22642#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22643#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22963#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22140#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22141#L1219-3 assume !(1 == ~E_3~0); 23162#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23163#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23184#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22411#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22412#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23017#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23389#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23166#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23167#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22220#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22680#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 22681#L1584 assume !(0 == start_simulation_~tmp~3#1); 23124#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22425#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22120#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22172#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 22173#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22751#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23006#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 23007#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 22252#L1565-2 [2023-11-29 01:35:07,340 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:07,341 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2023-11-29 01:35:07,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:07,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1443076844] [2023-11-29 01:35:07,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:07,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:07,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:07,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:07,380 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:07,381 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1443076844] [2023-11-29 01:35:07,381 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1443076844] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:07,381 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:07,381 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:07,381 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010708741] [2023-11-29 01:35:07,381 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:07,382 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:07,382 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:07,382 INFO L85 PathProgramCache]: Analyzing trace with hash 369161907, now seen corresponding path program 1 times [2023-11-29 01:35:07,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:07,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296904454] [2023-11-29 01:35:07,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:07,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:07,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:07,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:07,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:07,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [296904454] [2023-11-29 01:35:07,426 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [296904454] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:07,426 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:07,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:07,427 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39018896] [2023-11-29 01:35:07,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:07,427 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:07,427 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:07,427 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:07,428 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:07,428 INFO L87 Difference]: Start difference. First operand 1377 states and 2036 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:07,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:07,453 INFO L93 Difference]: Finished difference Result 1377 states and 2035 transitions. [2023-11-29 01:35:07,453 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2035 transitions. [2023-11-29 01:35:07,459 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:07,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1377 states and 2035 transitions. [2023-11-29 01:35:07,466 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1377 [2023-11-29 01:35:07,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1377 [2023-11-29 01:35:07,468 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 2035 transitions. [2023-11-29 01:35:07,469 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:07,469 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2035 transitions. [2023-11-29 01:35:07,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 2035 transitions. [2023-11-29 01:35:07,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1377. [2023-11-29 01:35:07,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1377 states, 1377 states have (on average 1.4778503994190269) internal successors, (2035), 1376 states have internal predecessors, (2035), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:07,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1377 states to 1377 states and 2035 transitions. [2023-11-29 01:35:07,528 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1377 states and 2035 transitions. [2023-11-29 01:35:07,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:07,529 INFO L428 stractBuchiCegarLoop]: Abstraction has 1377 states and 2035 transitions. [2023-11-29 01:35:07,529 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-29 01:35:07,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1377 states and 2035 transitions. [2023-11-29 01:35:07,535 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1238 [2023-11-29 01:35:07,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:07,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:07,536 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:07,537 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:07,537 INFO L748 eck$LassoCheckResult]: Stem: 25285#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 26162#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26163#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26225#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 26166#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26126#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26127#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26155#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25222#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25223#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25330#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25575#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25501#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25224#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 24885#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24886#L1036 assume !(0 == ~M_E~0); 24983#L1036-2 assume !(0 == ~T1_E~0); 25888#L1041-1 assume !(0 == ~T2_E~0); 25889#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25260#L1051-1 assume !(0 == ~T4_E~0); 25261#L1056-1 assume !(0 == ~T5_E~0); 26017#L1061-1 assume !(0 == ~T6_E~0); 25155#L1066-1 assume !(0 == ~T7_E~0); 25156#L1071-1 assume !(0 == ~T8_E~0); 25999#L1076-1 assume !(0 == ~T9_E~0); 25045#L1081-1 assume !(0 == ~T10_E~0); 25046#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 25446#L1091-1 assume !(0 == ~E_1~0); 26173#L1096-1 assume !(0 == ~E_2~0); 26174#L1101-1 assume !(0 == ~E_3~0); 25514#L1106-1 assume !(0 == ~E_4~0); 25515#L1111-1 assume !(0 == ~E_5~0); 25679#L1116-1 assume !(0 == ~E_6~0); 25680#L1121-1 assume !(0 == ~E_7~0); 25505#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25506#L1131-1 assume !(0 == ~E_9~0); 25781#L1136-1 assume !(0 == ~E_10~0); 25896#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26045#L514 assume 1 == ~m_pc~0; 26010#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25523#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25524#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26097#L1285 assume !(0 != activate_threads_~tmp~1#1); 26209#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25174#L533 assume !(1 == ~t1_pc~0); 25175#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25694#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24938#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24939#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 25917#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25918#L552 assume 1 == ~t2_pc~0; 25394#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25395#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25509#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25510#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 25539#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25540#L571 assume 1 == ~t3_pc~0; 25732#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25733#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24883#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24884#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 25684#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24969#L590 assume !(1 == ~t4_pc~0); 24970#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25742#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25063#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25064#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25945#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25681#L609 assume 1 == ~t5_pc~0; 25682#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26207#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26099#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26100#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 25673#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25674#L628 assume !(1 == ~t6_pc~0); 25606#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25605#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25482#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25483#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 25979#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25980#L647 assume 1 == ~t7_pc~0; 25516#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25517#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26108#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25519#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 25520#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26236#L666 assume !(1 == ~t8_pc~0); 25307#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25308#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25535#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25705#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 25443#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25444#L685 assume 1 == ~t9_pc~0; 26215#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26116#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25569#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25473#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 25474#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25859#L704 assume !(1 == ~t10_pc~0); 25463#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25462#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25724#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25017#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 25018#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25269#L1154 assume !(1 == ~M_E~0); 25967#L1154-2 assume !(1 == ~T1_E~0); 25243#L1159-1 assume !(1 == ~T2_E~0); 25244#L1164-1 assume !(1 == ~T3_E~0); 25703#L1169-1 assume !(1 == ~T4_E~0); 25570#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25372#L1179-1 assume !(1 == ~T6_E~0); 25228#L1184-1 assume !(1 == ~T7_E~0); 25229#L1189-1 assume !(1 == ~T8_E~0); 25305#L1194-1 assume !(1 == ~T9_E~0); 25430#L1199-1 assume !(1 == ~T10_E~0); 25384#L1204-1 assume !(1 == ~E_M~0); 25385#L1209-1 assume !(1 == ~E_1~0); 25940#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25941#L1219-1 assume !(1 == ~E_3~0); 26229#L1224-1 assume !(1 == ~E_4~0); 25727#L1229-1 assume !(1 == ~E_5~0); 25112#L1234-1 assume !(1 == ~E_6~0); 25113#L1239-1 assume !(1 == ~E_7~0); 25170#L1244-1 assume !(1 == ~E_8~0); 25171#L1249-1 assume !(1 == ~E_9~0); 26008#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 25012#L1259-1 assume { :end_inline_reset_delta_events } true; 25013#L1565-2 [2023-11-29 01:35:07,537 INFO L750 eck$LassoCheckResult]: Loop: 25013#L1565-2 assume !false; 25946#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25712#L1011-1 assume !false; 25675#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25448#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 25211#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25548#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25238#L866 assume !(0 != eval_~tmp~0#1); 25240#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25744#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25745#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26012#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26191#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26073#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26074#L1051-3 assume !(0 == ~T4_E~0); 26013#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25257#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25258#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25259#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26193#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25004#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25005#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25055#L1091-3 assume !(0 == ~E_1~0); 25056#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26157#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26158#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26190#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26149#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25874#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25875#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26088#L1131-3 assume !(0 == ~E_9~0); 26089#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26241#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25877#L514-36 assume !(1 == ~m_pc~0); 25586#L514-38 is_master_triggered_~__retres1~0#1 := 0; 25421#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25422#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25916#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25314#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25315#L533-36 assume 1 == ~t1_pc~0; 25595#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25688#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26139#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25954#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25751#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25752#L552-36 assume 1 == ~t2_pc~0; 25309#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25310#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25810#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26081#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25281#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25282#L571-36 assume 1 == ~t3_pc~0; 25669#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25373#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25374#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25565#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26072#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25346#L590-36 assume 1 == ~t4_pc~0; 25347#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25968#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25762#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25763#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26051#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26052#L609-36 assume 1 == ~t5_pc~0; 25929#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25754#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25755#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26096#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 25838#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25645#L628-36 assume 1 == ~t6_pc~0; 25493#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25494#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25544#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25545#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25879#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25880#L647-36 assume 1 == ~t7_pc~0; 25803#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25031#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25032#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25049#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25050#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25969#L666-36 assume 1 == ~t8_pc~0; 25235#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25236#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25867#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25868#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25392#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25393#L685-36 assume !(1 == ~t9_pc~0); 25141#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 25142#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25598#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25599#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25532#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25533#L704-36 assume 1 == ~t10_pc~0; 25131#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25132#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25453#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25454#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25157#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25158#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26143#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26026#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26027#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26204#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25459#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25460#L1179-3 assume !(1 == ~T6_E~0); 26118#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25033#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25034#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25403#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25404#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25723#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24901#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24902#L1219-3 assume !(1 == ~E_3~0); 25923#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25924#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25944#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25172#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25173#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25774#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 26150#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25927#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25928#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24981#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25441#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25442#L1584 assume !(0 == start_simulation_~tmp~3#1); 25885#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25186#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24881#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24933#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 24934#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25511#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25767#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25768#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 25013#L1565-2 [2023-11-29 01:35:07,538 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:07,538 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2023-11-29 01:35:07,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:07,538 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1528415635] [2023-11-29 01:35:07,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:07,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:07,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:07,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:07,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:07,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1528415635] [2023-11-29 01:35:07,605 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1528415635] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:07,606 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:07,606 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:07,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1747613745] [2023-11-29 01:35:07,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:07,606 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:07,607 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:07,607 INFO L85 PathProgramCache]: Analyzing trace with hash -1250501773, now seen corresponding path program 1 times [2023-11-29 01:35:07,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:07,607 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106482669] [2023-11-29 01:35:07,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:07,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:07,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:07,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:07,649 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:07,649 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1106482669] [2023-11-29 01:35:07,649 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1106482669] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:07,649 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:07,649 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:07,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [972741116] [2023-11-29 01:35:07,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:07,650 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:07,650 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:07,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:35:07,651 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:35:07,651 INFO L87 Difference]: Start difference. First operand 1377 states and 2035 transitions. cyclomatic complexity: 659 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:07,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:07,778 INFO L93 Difference]: Finished difference Result 2536 states and 3734 transitions. [2023-11-29 01:35:07,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2536 states and 3734 transitions. [2023-11-29 01:35:07,791 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2375 [2023-11-29 01:35:07,805 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2536 states to 2536 states and 3734 transitions. [2023-11-29 01:35:07,805 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2536 [2023-11-29 01:35:07,808 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2536 [2023-11-29 01:35:07,808 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2536 states and 3734 transitions. [2023-11-29 01:35:07,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:07,811 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2536 states and 3734 transitions. [2023-11-29 01:35:07,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2536 states and 3734 transitions. [2023-11-29 01:35:07,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2536 to 2536. [2023-11-29 01:35:07,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2536 states, 2536 states have (on average 1.472397476340694) internal successors, (3734), 2535 states have internal predecessors, (3734), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:07,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2536 states to 2536 states and 3734 transitions. [2023-11-29 01:35:07,854 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2536 states and 3734 transitions. [2023-11-29 01:35:07,855 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:35:07,855 INFO L428 stractBuchiCegarLoop]: Abstraction has 2536 states and 3734 transitions. [2023-11-29 01:35:07,856 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-29 01:35:07,856 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2536 states and 3734 transitions. [2023-11-29 01:35:07,864 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2375 [2023-11-29 01:35:07,864 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:07,864 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:07,866 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:07,866 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:07,866 INFO L748 eck$LassoCheckResult]: Stem: 29208#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 29209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 30090#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30091#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30162#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 30094#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30054#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30055#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30083#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29145#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29146#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29253#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29499#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29424#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29147#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 28808#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28809#L1036 assume !(0 == ~M_E~0); 28906#L1036-2 assume !(0 == ~T1_E~0); 29813#L1041-1 assume !(0 == ~T2_E~0); 29814#L1046-1 assume !(0 == ~T3_E~0); 29183#L1051-1 assume !(0 == ~T4_E~0); 29184#L1056-1 assume !(0 == ~T5_E~0); 29944#L1061-1 assume !(0 == ~T6_E~0); 29078#L1066-1 assume !(0 == ~T7_E~0); 29079#L1071-1 assume !(0 == ~T8_E~0); 29926#L1076-1 assume !(0 == ~T9_E~0); 28968#L1081-1 assume !(0 == ~T10_E~0); 28969#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 29369#L1091-1 assume !(0 == ~E_1~0); 30101#L1096-1 assume !(0 == ~E_2~0); 30102#L1101-1 assume !(0 == ~E_3~0); 29437#L1106-1 assume !(0 == ~E_4~0); 29438#L1111-1 assume !(0 == ~E_5~0); 29604#L1116-1 assume !(0 == ~E_6~0); 29605#L1121-1 assume !(0 == ~E_7~0); 29428#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 29429#L1131-1 assume !(0 == ~E_9~0); 29706#L1136-1 assume !(0 == ~E_10~0); 29821#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29972#L514 assume 1 == ~m_pc~0; 29937#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29446#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29447#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30024#L1285 assume !(0 != activate_threads_~tmp~1#1); 30141#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29097#L533 assume !(1 == ~t1_pc~0); 29098#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29619#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28861#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28862#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 29842#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29843#L552 assume 1 == ~t2_pc~0; 29317#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29318#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29432#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29433#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 29459#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29460#L571 assume 1 == ~t3_pc~0; 29657#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29658#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28806#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28807#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 29609#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28892#L590 assume !(1 == ~t4_pc~0); 28893#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29667#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28986#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28987#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29869#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29606#L609 assume 1 == ~t5_pc~0; 29607#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30139#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30026#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30027#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 29598#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29599#L628 assume !(1 == ~t6_pc~0); 29531#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29530#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29405#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29406#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 29906#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29907#L647 assume 1 == ~t7_pc~0; 29439#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29440#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30036#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29442#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 29443#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30176#L666 assume !(1 == ~t8_pc~0); 29230#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29231#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29458#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29630#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 29366#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29367#L685 assume 1 == ~t9_pc~0; 30150#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30044#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29493#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29396#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 29397#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29784#L704 assume !(1 == ~t10_pc~0); 29386#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29385#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29648#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28940#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 28941#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29192#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 29893#L1154-2 assume !(1 == ~T1_E~0); 31020#L1159-1 assume !(1 == ~T2_E~0); 31018#L1164-1 assume !(1 == ~T3_E~0); 30184#L1169-1 assume !(1 == ~T4_E~0); 31015#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31013#L1179-1 assume !(1 == ~T6_E~0); 31010#L1184-1 assume !(1 == ~T7_E~0); 31008#L1189-1 assume !(1 == ~T8_E~0); 31006#L1194-1 assume !(1 == ~T9_E~0); 31004#L1199-1 assume !(1 == ~T10_E~0); 30276#L1204-1 assume !(1 == ~E_M~0); 30264#L1209-1 assume !(1 == ~E_1~0); 30262#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30260#L1219-1 assume !(1 == ~E_3~0); 30258#L1224-1 assume !(1 == ~E_4~0); 30256#L1229-1 assume !(1 == ~E_5~0); 30253#L1234-1 assume !(1 == ~E_6~0); 30251#L1239-1 assume !(1 == ~E_7~0); 30249#L1244-1 assume !(1 == ~E_8~0); 30248#L1249-1 assume !(1 == ~E_9~0); 30231#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30222#L1259-1 assume { :end_inline_reset_delta_events } true; 30215#L1565-2 [2023-11-29 01:35:07,866 INFO L750 eck$LassoCheckResult]: Loop: 30215#L1565-2 assume !false; 30211#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30207#L1011-1 assume !false; 30206#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30205#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30194#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30193#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30191#L866 assume !(0 != eval_~tmp~0#1); 30190#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30189#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30188#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30120#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30121#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30000#L1046-3 assume !(0 == ~T3_E~0); 30001#L1051-3 assume !(0 == ~T4_E~0); 29940#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29180#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29181#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29182#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30123#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28927#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28928#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28978#L1091-3 assume !(0 == ~E_1~0); 28979#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31000#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30998#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30996#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30994#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30992#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30989#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30987#L1131-3 assume !(0 == ~E_9~0); 30985#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30983#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30981#L514-36 assume !(1 == ~m_pc~0); 30978#L514-38 is_master_triggered_~__retres1~0#1 := 0; 30975#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30973#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30971#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30969#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30967#L533-36 assume 1 == ~t1_pc~0; 30964#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30961#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30959#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30957#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30955#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30953#L552-36 assume !(1 == ~t2_pc~0); 30950#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 30947#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30945#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30943#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30941#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30939#L571-36 assume 1 == ~t3_pc~0; 30936#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30933#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30931#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30929#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30927#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30925#L590-36 assume !(1 == ~t4_pc~0); 30922#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 30919#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30917#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30915#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30914#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30913#L609-36 assume !(1 == ~t5_pc~0); 30912#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 30910#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30909#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30908#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 30907#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30906#L628-36 assume 1 == ~t6_pc~0; 30904#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30903#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30902#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30901#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30900#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30899#L647-36 assume 1 == ~t7_pc~0; 30897#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30896#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30895#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30894#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30893#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30892#L666-36 assume 1 == ~t8_pc~0; 30889#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30887#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30885#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30883#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30880#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30878#L685-36 assume !(1 == ~t9_pc~0); 30875#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 30873#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30871#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30869#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30866#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30864#L704-36 assume 1 == ~t10_pc~0; 30861#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30859#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30857#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30855#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30852#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30850#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30187#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30847#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30845#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30185#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30841#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30839#L1179-3 assume !(1 == ~T6_E~0); 30837#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30835#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30833#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30831#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30828#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30827#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30826#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30825#L1219-3 assume !(1 == ~E_3~0); 30824#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30823#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30822#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30821#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30820#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30819#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30818#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30817#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30719#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30717#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30715#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30671#L1584 assume !(0 == start_simulation_~tmp~3#1); 30181#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30274#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30263#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30261#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 30259#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30257#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30232#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 30223#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 30215#L1565-2 [2023-11-29 01:35:07,867 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:07,867 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2023-11-29 01:35:07,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:07,867 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1319316010] [2023-11-29 01:35:07,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:07,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:07,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:07,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:07,921 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:07,921 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1319316010] [2023-11-29 01:35:07,921 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1319316010] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:07,922 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:07,922 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:07,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2020517446] [2023-11-29 01:35:07,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:07,922 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:07,922 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:07,923 INFO L85 PathProgramCache]: Analyzing trace with hash -1651803656, now seen corresponding path program 1 times [2023-11-29 01:35:07,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:07,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230732072] [2023-11-29 01:35:07,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:07,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:07,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:07,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:07,964 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:07,964 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230732072] [2023-11-29 01:35:07,964 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1230732072] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:07,964 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:07,964 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:07,965 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1475481116] [2023-11-29 01:35:07,965 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:07,965 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:07,965 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:07,966 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:35:07,966 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:35:07,966 INFO L87 Difference]: Start difference. First operand 2536 states and 3734 transitions. cyclomatic complexity: 1200 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:08,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:08,174 INFO L93 Difference]: Finished difference Result 4684 states and 6883 transitions. [2023-11-29 01:35:08,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4684 states and 6883 transitions. [2023-11-29 01:35:08,191 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4491 [2023-11-29 01:35:08,218 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4684 states to 4684 states and 6883 transitions. [2023-11-29 01:35:08,219 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4684 [2023-11-29 01:35:08,222 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4684 [2023-11-29 01:35:08,223 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4684 states and 6883 transitions. [2023-11-29 01:35:08,227 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:08,227 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4684 states and 6883 transitions. [2023-11-29 01:35:08,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4684 states and 6883 transitions. [2023-11-29 01:35:08,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4684 to 4682. [2023-11-29 01:35:08,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4682 states, 4682 states have (on average 1.4696710807347289) internal successors, (6881), 4681 states have internal predecessors, (6881), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:08,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4682 states to 4682 states and 6881 transitions. [2023-11-29 01:35:08,313 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4682 states and 6881 transitions. [2023-11-29 01:35:08,314 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:35:08,314 INFO L428 stractBuchiCegarLoop]: Abstraction has 4682 states and 6881 transitions. [2023-11-29 01:35:08,314 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-29 01:35:08,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4682 states and 6881 transitions. [2023-11-29 01:35:08,329 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4491 [2023-11-29 01:35:08,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:08,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:08,331 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:08,331 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:08,331 INFO L748 eck$LassoCheckResult]: Stem: 36439#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36440#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 37389#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37390#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37463#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 37393#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37341#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37342#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37381#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36377#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36378#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36485#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36742#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36664#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36379#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36038#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36039#L1036 assume !(0 == ~M_E~0); 36136#L1036-2 assume !(0 == ~T1_E~0); 37070#L1041-1 assume !(0 == ~T2_E~0); 37071#L1046-1 assume !(0 == ~T3_E~0); 36414#L1051-1 assume !(0 == ~T4_E~0); 36415#L1056-1 assume !(0 == ~T5_E~0); 37209#L1061-1 assume !(0 == ~T6_E~0); 36308#L1066-1 assume !(0 == ~T7_E~0); 36309#L1071-1 assume !(0 == ~T8_E~0); 37190#L1076-1 assume !(0 == ~T9_E~0); 36198#L1081-1 assume !(0 == ~T10_E~0); 36199#L1086-1 assume !(0 == ~E_M~0); 36608#L1091-1 assume !(0 == ~E_1~0); 37401#L1096-1 assume !(0 == ~E_2~0); 37402#L1101-1 assume !(0 == ~E_3~0); 36677#L1106-1 assume !(0 == ~E_4~0); 36678#L1111-1 assume !(0 == ~E_5~0); 36854#L1116-1 assume !(0 == ~E_6~0); 36855#L1121-1 assume !(0 == ~E_7~0); 36668#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36669#L1131-1 assume !(0 == ~E_9~0); 36960#L1136-1 assume !(0 == ~E_10~0); 37078#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37245#L514 assume 1 == ~m_pc~0; 37201#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36686#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36687#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37305#L1285 assume !(0 != activate_threads_~tmp~1#1); 37447#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36330#L533 assume !(1 == ~t1_pc~0); 36331#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36869#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36093#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36094#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 37099#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37100#L552 assume 1 == ~t2_pc~0; 36556#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36557#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36672#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36673#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 36706#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36707#L571 assume 1 == ~t3_pc~0; 36913#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36914#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36036#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36037#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 36859#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36122#L590 assume !(1 == ~t4_pc~0); 36123#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36922#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36216#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36217#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37131#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36856#L609 assume 1 == ~t5_pc~0; 36857#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37442#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37306#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37307#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 36848#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36849#L628 assume !(1 == ~t6_pc~0); 36776#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36775#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36648#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36649#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 37168#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37169#L647 assume 1 == ~t7_pc~0; 36679#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36680#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37315#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36684#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 36685#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37484#L666 assume !(1 == ~t8_pc~0); 36462#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36463#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36698#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36883#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 36606#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36607#L685 assume 1 == ~t9_pc~0; 37450#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37330#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36735#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36635#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 36636#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37040#L704 assume !(1 == ~t10_pc~0); 36625#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36624#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36903#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36170#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 36171#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36423#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 37154#L1154-2 assume !(1 == ~T1_E~0); 37470#L1159-1 assume !(1 == ~T2_E~0); 37496#L1164-1 assume !(1 == ~T3_E~0); 36879#L1169-1 assume !(1 == ~T4_E~0); 36880#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36532#L1179-1 assume !(1 == ~T6_E~0); 36533#L1184-1 assume !(1 == ~T7_E~0); 36459#L1189-1 assume !(1 == ~T8_E~0); 36460#L1194-1 assume !(1 == ~T9_E~0); 37507#L1199-1 assume !(1 == ~T10_E~0); 37508#L1204-1 assume !(1 == ~E_M~0); 37580#L1209-1 assume !(1 == ~E_1~0); 37577#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 37575#L1219-1 assume !(1 == ~E_3~0); 37573#L1224-1 assume !(1 == ~E_4~0); 37571#L1229-1 assume !(1 == ~E_5~0); 37569#L1234-1 assume !(1 == ~E_6~0); 37565#L1239-1 assume !(1 == ~E_7~0); 37563#L1244-1 assume !(1 == ~E_8~0); 37561#L1249-1 assume !(1 == ~E_9~0); 37558#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 37548#L1259-1 assume { :end_inline_reset_delta_events } true; 37541#L1565-2 [2023-11-29 01:35:08,331 INFO L750 eck$LassoCheckResult]: Loop: 37541#L1565-2 assume !false; 37535#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37531#L1011-1 assume !false; 37530#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37529#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37518#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37517#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37515#L866 assume !(0 != eval_~tmp~0#1); 37514#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37513#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37512#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37425#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37426#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37495#L1046-3 assume !(0 == ~T3_E~0); 39886#L1051-3 assume !(0 == ~T4_E~0); 37204#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36411#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36412#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36413#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37427#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36157#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36158#L1086-3 assume !(0 == ~E_M~0); 36212#L1091-3 assume !(0 == ~E_1~0); 36213#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37383#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37384#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37423#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37373#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37055#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37056#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37294#L1131-3 assume !(0 == ~E_9~0); 37295#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37492#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37057#L514-36 assume 1 == ~m_pc~0; 37058#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36582#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36583#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37098#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36469#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36470#L533-36 assume 1 == ~t1_pc~0; 36762#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36863#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37357#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37141#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36930#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36931#L552-36 assume 1 == ~t2_pc~0; 36464#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36465#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36989#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37286#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36435#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36436#L571-36 assume 1 == ~t3_pc~0; 36844#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36530#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36531#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36731#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37277#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36499#L590-36 assume 1 == ~t4_pc~0; 36500#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37156#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36940#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36941#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37251#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37252#L609-36 assume !(1 == ~t5_pc~0); 37418#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 39832#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39831#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39830#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 39829#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39828#L628-36 assume 1 == ~t6_pc~0; 36656#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36657#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36709#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36710#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37060#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37061#L647-36 assume 1 == ~t7_pc~0; 36982#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36184#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36185#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36202#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36203#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37157#L666-36 assume 1 == ~t8_pc~0; 36391#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36392#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37048#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37049#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36553#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36554#L685-36 assume !(1 == ~t9_pc~0); 36296#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 36297#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36769#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36770#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38589#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38586#L704-36 assume 1 == ~t10_pc~0; 38579#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38570#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36615#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36616#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38562#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38557#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37361#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37362#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38548#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38544#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38540#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38534#L1179-3 assume !(1 == ~T6_E~0); 38530#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38526#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38522#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36564#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36565#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38506#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38503#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38500#L1219-3 assume !(1 == ~E_3~0); 38497#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38494#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38491#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38485#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38480#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38476#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38472#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 38468#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 38065#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 38052#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 38041#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 38029#L1584 assume !(0 == start_simulation_~tmp~3#1); 37491#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37619#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37607#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37605#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 37603#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37599#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37596#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 37549#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 37541#L1565-2 [2023-11-29 01:35:08,332 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:08,332 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2023-11-29 01:35:08,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:08,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1096987935] [2023-11-29 01:35:08,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:08,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:08,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:08,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:08,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:08,387 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1096987935] [2023-11-29 01:35:08,387 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1096987935] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:08,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:08,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:08,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1041427471] [2023-11-29 01:35:08,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:08,388 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:08,388 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:08,389 INFO L85 PathProgramCache]: Analyzing trace with hash 39360823, now seen corresponding path program 1 times [2023-11-29 01:35:08,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:08,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723845672] [2023-11-29 01:35:08,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:08,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:08,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:08,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:08,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:08,429 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1723845672] [2023-11-29 01:35:08,430 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1723845672] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:08,430 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:08,430 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:08,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [384431282] [2023-11-29 01:35:08,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:08,430 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:08,430 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:08,431 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:35:08,431 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:35:08,431 INFO L87 Difference]: Start difference. First operand 4682 states and 6881 transitions. cyclomatic complexity: 2203 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:08,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:08,609 INFO L93 Difference]: Finished difference Result 8780 states and 12872 transitions. [2023-11-29 01:35:08,609 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8780 states and 12872 transitions. [2023-11-29 01:35:08,669 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8565 [2023-11-29 01:35:08,712 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8780 states to 8780 states and 12872 transitions. [2023-11-29 01:35:08,713 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8780 [2023-11-29 01:35:08,722 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8780 [2023-11-29 01:35:08,722 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8780 states and 12872 transitions. [2023-11-29 01:35:08,734 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:08,734 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8780 states and 12872 transitions. [2023-11-29 01:35:08,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8780 states and 12872 transitions. [2023-11-29 01:35:08,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8780 to 8776. [2023-11-29 01:35:08,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8776 states, 8776 states have (on average 1.466271649954421) internal successors, (12868), 8775 states have internal predecessors, (12868), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:08,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8776 states to 8776 states and 12868 transitions. [2023-11-29 01:35:08,908 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8776 states and 12868 transitions. [2023-11-29 01:35:08,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:35:08,909 INFO L428 stractBuchiCegarLoop]: Abstraction has 8776 states and 12868 transitions. [2023-11-29 01:35:08,910 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-29 01:35:08,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8776 states and 12868 transitions. [2023-11-29 01:35:08,941 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8565 [2023-11-29 01:35:08,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:08,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:08,944 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:08,944 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:08,945 INFO L748 eck$LassoCheckResult]: Stem: 49914#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 49915#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 50857#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50858#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50935#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 50861#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50816#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50817#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50848#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49849#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49850#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49960#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50216#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50137#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49851#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49510#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49511#L1036 assume !(0 == ~M_E~0); 49608#L1036-2 assume !(0 == ~T1_E~0); 50544#L1041-1 assume !(0 == ~T2_E~0); 50545#L1046-1 assume !(0 == ~T3_E~0); 49889#L1051-1 assume !(0 == ~T4_E~0); 49890#L1056-1 assume !(0 == ~T5_E~0); 50691#L1061-1 assume !(0 == ~T6_E~0); 49780#L1066-1 assume !(0 == ~T7_E~0); 49781#L1071-1 assume !(0 == ~T8_E~0); 50673#L1076-1 assume !(0 == ~T9_E~0); 49670#L1081-1 assume !(0 == ~T10_E~0); 49671#L1086-1 assume !(0 == ~E_M~0); 50080#L1091-1 assume !(0 == ~E_1~0); 50869#L1096-1 assume !(0 == ~E_2~0); 50870#L1101-1 assume !(0 == ~E_3~0); 50150#L1106-1 assume !(0 == ~E_4~0); 50151#L1111-1 assume !(0 == ~E_5~0); 50327#L1116-1 assume !(0 == ~E_6~0); 50328#L1121-1 assume !(0 == ~E_7~0); 50141#L1126-1 assume !(0 == ~E_8~0); 50142#L1131-1 assume !(0 == ~E_9~0); 50436#L1136-1 assume !(0 == ~E_10~0); 50553#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50724#L514 assume 1 == ~m_pc~0; 50684#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 50159#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50160#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50780#L1285 assume !(0 != activate_threads_~tmp~1#1); 50911#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49800#L533 assume !(1 == ~t1_pc~0); 49801#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50342#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49563#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49564#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 50576#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50577#L552 assume 1 == ~t2_pc~0; 50026#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50027#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50145#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50146#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 50172#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50173#L571 assume 1 == ~t3_pc~0; 50386#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50387#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49508#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49509#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 50332#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49594#L590 assume !(1 == ~t4_pc~0); 49595#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 50396#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49688#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49689#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50608#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50329#L609 assume 1 == ~t5_pc~0; 50330#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50909#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50784#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50785#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 50321#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50322#L628 assume !(1 == ~t6_pc~0); 50252#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50251#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50118#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50119#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 50650#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50651#L647 assume 1 == ~t7_pc~0; 50152#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50153#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50794#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50155#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 50156#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50952#L666 assume !(1 == ~t8_pc~0); 49937#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49938#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50171#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50355#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 50077#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50078#L685 assume 1 == ~t9_pc~0; 50920#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50804#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50209#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50107#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 50108#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50515#L704 assume !(1 == ~t10_pc~0); 50097#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50096#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50376#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49642#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 49643#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49898#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 50637#L1154-2 assume !(1 == ~T1_E~0); 50938#L1159-1 assume !(1 == ~T2_E~0); 50967#L1164-1 assume !(1 == ~T3_E~0); 50352#L1169-1 assume !(1 == ~T4_E~0); 50353#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50002#L1179-1 assume !(1 == ~T6_E~0); 50003#L1184-1 assume !(1 == ~T7_E~0); 49934#L1189-1 assume !(1 == ~T8_E~0); 49935#L1194-1 assume !(1 == ~T9_E~0); 50981#L1199-1 assume !(1 == ~T10_E~0); 50982#L1204-1 assume !(1 == ~E_M~0); 51061#L1209-1 assume !(1 == ~E_1~0); 51057#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 51054#L1219-1 assume !(1 == ~E_3~0); 51051#L1224-1 assume !(1 == ~E_4~0); 51048#L1229-1 assume !(1 == ~E_5~0); 51045#L1234-1 assume !(1 == ~E_6~0); 51041#L1239-1 assume !(1 == ~E_7~0); 51038#L1244-1 assume !(1 == ~E_8~0); 51034#L1249-1 assume !(1 == ~E_9~0); 51031#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 51022#L1259-1 assume { :end_inline_reset_delta_events } true; 51015#L1565-2 [2023-11-29 01:35:08,945 INFO L750 eck$LassoCheckResult]: Loop: 51015#L1565-2 assume !false; 51009#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51005#L1011-1 assume !false; 51004#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51003#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50992#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50991#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 50989#L866 assume !(0 != eval_~tmp~0#1); 50988#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50987#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50985#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50986#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53502#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53500#L1046-3 assume !(0 == ~T3_E~0); 53498#L1051-3 assume !(0 == ~T4_E~0); 53496#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53494#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53491#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53489#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53487#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53485#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53483#L1086-3 assume !(0 == ~E_M~0); 53481#L1091-3 assume !(0 == ~E_1~0); 53478#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53476#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53474#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53472#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53470#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53468#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53465#L1126-3 assume !(0 == ~E_8~0); 53463#L1131-3 assume !(0 == ~E_9~0); 53461#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53459#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53158#L514-36 assume !(1 == ~m_pc~0); 53154#L514-38 is_master_triggered_~__retres1~0#1 := 0; 53152#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53150#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53148#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53146#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53143#L533-36 assume 1 == ~t1_pc~0; 53139#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53136#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53134#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53132#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53130#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53128#L552-36 assume !(1 == ~t2_pc~0); 53125#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 53124#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53121#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53119#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53117#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53115#L571-36 assume 1 == ~t3_pc~0; 53112#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53110#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53107#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53105#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53103#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53101#L590-36 assume !(1 == ~t4_pc~0); 53098#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 53096#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53095#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53093#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53090#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53089#L609-36 assume 1 == ~t5_pc~0; 53086#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53084#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53082#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52624#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 52620#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52618#L628-36 assume 1 == ~t6_pc~0; 52615#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52614#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52613#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52610#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 52608#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52606#L647-36 assume 1 == ~t7_pc~0; 52604#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52197#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52194#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52192#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52190#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52188#L666-36 assume 1 == ~t8_pc~0; 52185#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52183#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52180#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52178#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52176#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52174#L685-36 assume !(1 == ~t9_pc~0); 52168#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 52166#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52164#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52162#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52160#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52158#L704-36 assume 1 == ~t10_pc~0; 52154#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52152#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52150#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52148#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 52146#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52144#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50978#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52141#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52140#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50971#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52085#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52079#L1179-3 assume !(1 == ~T6_E~0); 52069#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 52063#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52057#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52051#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52045#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 52038#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51436#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51434#L1219-3 assume !(1 == ~E_3~0); 51177#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51175#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51166#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51160#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51155#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 51149#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51145#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51137#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51121#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51118#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51115#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 51112#L1584 assume !(0 == start_simulation_~tmp~3#1); 50962#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51107#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51096#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51093#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 51091#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51089#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51087#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 51023#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 51015#L1565-2 [2023-11-29 01:35:08,945 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:08,945 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2023-11-29 01:35:08,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:08,946 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909661375] [2023-11-29 01:35:08,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:08,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:08,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:08,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:08,999 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:08,999 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909661375] [2023-11-29 01:35:08,999 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909661375] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:08,999 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:08,999 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:35:09,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1627348966] [2023-11-29 01:35:09,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:09,000 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:09,000 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:09,001 INFO L85 PathProgramCache]: Analyzing trace with hash -2145863301, now seen corresponding path program 1 times [2023-11-29 01:35:09,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:09,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774102148] [2023-11-29 01:35:09,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:09,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:09,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:09,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:09,052 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:09,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1774102148] [2023-11-29 01:35:09,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1774102148] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:09,053 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:09,053 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:09,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2013044705] [2023-11-29 01:35:09,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:09,054 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:09,054 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:09,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:09,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:09,055 INFO L87 Difference]: Start difference. First operand 8776 states and 12868 transitions. cyclomatic complexity: 4100 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:09,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:09,253 INFO L93 Difference]: Finished difference Result 17195 states and 25019 transitions. [2023-11-29 01:35:09,254 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17195 states and 25019 transitions. [2023-11-29 01:35:09,347 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16969 [2023-11-29 01:35:09,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17195 states to 17195 states and 25019 transitions. [2023-11-29 01:35:09,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17195 [2023-11-29 01:35:09,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17195 [2023-11-29 01:35:09,440 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17195 states and 25019 transitions. [2023-11-29 01:35:09,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:09,461 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17195 states and 25019 transitions. [2023-11-29 01:35:09,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17195 states and 25019 transitions. [2023-11-29 01:35:09,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17195 to 16587. [2023-11-29 01:35:09,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16587 states, 16587 states have (on average 1.4567432326520768) internal successors, (24163), 16586 states have internal predecessors, (24163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:09,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16587 states to 16587 states and 24163 transitions. [2023-11-29 01:35:09,808 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16587 states and 24163 transitions. [2023-11-29 01:35:09,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:09,809 INFO L428 stractBuchiCegarLoop]: Abstraction has 16587 states and 24163 transitions. [2023-11-29 01:35:09,809 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-29 01:35:09,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16587 states and 24163 transitions. [2023-11-29 01:35:09,905 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16361 [2023-11-29 01:35:09,906 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:09,906 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:09,908 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:09,908 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:09,909 INFO L748 eck$LassoCheckResult]: Stem: 75899#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 75900#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 76948#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76949#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77050#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 76953#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76883#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76884#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76939#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75831#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75832#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75946#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76206#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76128#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75833#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 75488#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75489#L1036 assume !(0 == ~M_E~0); 75586#L1036-2 assume !(0 == ~T1_E~0); 76558#L1041-1 assume !(0 == ~T2_E~0); 76559#L1046-1 assume !(0 == ~T3_E~0); 75873#L1051-1 assume !(0 == ~T4_E~0); 75874#L1056-1 assume !(0 == ~T5_E~0); 76719#L1061-1 assume !(0 == ~T6_E~0); 75759#L1066-1 assume !(0 == ~T7_E~0); 75760#L1071-1 assume !(0 == ~T8_E~0); 76700#L1076-1 assume !(0 == ~T9_E~0); 75647#L1081-1 assume !(0 == ~T10_E~0); 75648#L1086-1 assume !(0 == ~E_M~0); 76073#L1091-1 assume !(0 == ~E_1~0); 76962#L1096-1 assume !(0 == ~E_2~0); 76963#L1101-1 assume !(0 == ~E_3~0); 76141#L1106-1 assume !(0 == ~E_4~0); 76142#L1111-1 assume !(0 == ~E_5~0); 76318#L1116-1 assume !(0 == ~E_6~0); 76319#L1121-1 assume !(0 == ~E_7~0); 76132#L1126-1 assume !(0 == ~E_8~0); 76133#L1131-1 assume !(0 == ~E_9~0); 76428#L1136-1 assume !(0 == ~E_10~0); 76574#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76761#L514 assume !(1 == ~m_pc~0); 76762#L514-2 is_master_triggered_~__retres1~0#1 := 0; 76150#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76151#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76844#L1285 assume !(0 != activate_threads_~tmp~1#1); 77022#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75781#L533 assume !(1 == ~t1_pc~0); 75782#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76333#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75543#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75544#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 76600#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76601#L552 assume 1 == ~t2_pc~0; 76017#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76018#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76136#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76137#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 76170#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76171#L571 assume 1 == ~t3_pc~0; 76378#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76379#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75486#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75487#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 76323#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75572#L590 assume !(1 == ~t4_pc~0); 75573#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76387#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75665#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75666#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76637#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76320#L609 assume 1 == ~t5_pc~0; 76321#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77015#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76845#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76846#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 76312#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76313#L628 assume !(1 == ~t6_pc~0); 76240#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76239#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76112#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76113#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 76678#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76679#L647 assume 1 == ~t7_pc~0; 76143#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76144#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76855#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76148#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 76149#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77076#L666 assume !(1 == ~t8_pc~0); 75923#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75924#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76163#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76346#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 76070#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76071#L685 assume 1 == ~t9_pc~0; 77028#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76866#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76200#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76098#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 76099#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76523#L704 assume !(1 == ~t10_pc~0); 76089#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76088#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76367#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 75619#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 75620#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75881#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 76665#L1154-2 assume !(1 == ~T1_E~0); 75852#L1159-1 assume !(1 == ~T2_E~0); 75853#L1164-1 assume !(1 == ~T3_E~0); 76343#L1169-1 assume !(1 == ~T4_E~0); 76201#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75995#L1179-1 assume !(1 == ~T6_E~0); 75837#L1184-1 assume !(1 == ~T7_E~0); 75838#L1189-1 assume !(1 == ~T8_E~0); 75921#L1194-1 assume !(1 == ~T9_E~0); 76056#L1199-1 assume !(1 == ~T10_E~0); 76008#L1204-1 assume !(1 == ~E_M~0); 76009#L1209-1 assume !(1 == ~E_1~0); 91065#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 91063#L1219-1 assume !(1 == ~E_3~0); 91061#L1224-1 assume !(1 == ~E_4~0); 91059#L1229-1 assume !(1 == ~E_5~0); 75716#L1234-1 assume !(1 == ~E_6~0); 75717#L1239-1 assume !(1 == ~E_7~0); 75774#L1244-1 assume !(1 == ~E_8~0); 75775#L1249-1 assume !(1 == ~E_9~0); 76709#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 75616#L1259-1 assume { :end_inline_reset_delta_events } true; 75617#L1565-2 [2023-11-29 01:35:09,909 INFO L750 eck$LassoCheckResult]: Loop: 75617#L1565-2 assume !false; 76638#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76353#L1011-1 assume !false; 76311#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 76074#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 75817#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 76176#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 75847#L866 assume !(0 != eval_~tmp~0#1); 75849#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76388#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76389#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 76988#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76989#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 91875#L1046-3 assume !(0 == ~T3_E~0); 91874#L1051-3 assume !(0 == ~T4_E~0); 91873#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 91871#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 91869#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 91868#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 91867#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 91866#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 77089#L1086-3 assume !(0 == ~E_M~0); 75657#L1091-3 assume !(0 == ~E_1~0); 75658#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 91858#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 91857#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 91856#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 91855#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 91854#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 91853#L1126-3 assume !(0 == ~E_8~0); 91852#L1131-3 assume !(0 == ~E_9~0); 91851#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 91850#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91849#L514-36 assume !(1 == ~m_pc~0); 91848#L514-38 is_master_triggered_~__retres1~0#1 := 0; 91847#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91829#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 91803#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91802#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91801#L533-36 assume 1 == ~t1_pc~0; 91799#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 91798#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91797#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 91796#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 91795#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 91794#L552-36 assume 1 == ~t2_pc~0; 91793#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 91791#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 91790#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78017#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78016#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78015#L571-36 assume 1 == ~t3_pc~0; 78013#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 78012#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78011#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78010#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78009#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78008#L590-36 assume 1 == ~t4_pc~0; 78007#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 78005#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78004#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78003#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78002#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78001#L609-36 assume !(1 == ~t5_pc~0); 78000#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 77998#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77997#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77996#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 77995#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77994#L628-36 assume !(1 == ~t6_pc~0); 77993#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 77991#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77990#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77989#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 77988#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77987#L647-36 assume 1 == ~t7_pc~0; 77985#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 77984#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77983#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77982#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 77981#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77980#L666-36 assume !(1 == ~t8_pc~0); 77979#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 77977#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77976#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77975#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 77974#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77973#L685-36 assume !(1 == ~t9_pc~0); 77971#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 77970#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77969#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77968#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 77967#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77966#L704-36 assume !(1 == ~t10_pc~0); 77965#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 77963#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77962#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77961#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77960#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77959#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 77958#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77957#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77956#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77941#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77940#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77939#L1179-3 assume !(1 == ~T6_E~0); 77938#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77937#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 77936#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 76026#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 76027#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 77133#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77844#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77841#L1219-3 assume !(1 == ~E_3~0); 77839#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77837#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77835#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77833#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 77831#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77828#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 77826#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 77825#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77811#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77810#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77776#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 76554#L1584 assume !(0 == start_simulation_~tmp~3#1); 76555#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77861#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77851#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77850#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 77849#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77848#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77847#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 77049#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 75617#L1565-2 [2023-11-29 01:35:09,909 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:09,909 INFO L85 PathProgramCache]: Analyzing trace with hash -2098669114, now seen corresponding path program 1 times [2023-11-29 01:35:09,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:09,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252722636] [2023-11-29 01:35:09,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:09,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:09,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:09,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:09,964 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:09,964 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [252722636] [2023-11-29 01:35:09,964 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [252722636] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:09,964 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:09,964 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:35:09,965 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [397690551] [2023-11-29 01:35:09,965 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:09,965 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:09,965 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:09,966 INFO L85 PathProgramCache]: Analyzing trace with hash -1253499843, now seen corresponding path program 1 times [2023-11-29 01:35:09,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:09,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686582470] [2023-11-29 01:35:09,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:09,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:09,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:10,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:10,014 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:10,015 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1686582470] [2023-11-29 01:35:10,015 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1686582470] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:10,015 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:10,015 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:10,015 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708010877] [2023-11-29 01:35:10,015 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:10,016 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:10,016 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:10,016 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:10,016 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:10,016 INFO L87 Difference]: Start difference. First operand 16587 states and 24163 transitions. cyclomatic complexity: 7592 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:10,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:10,222 INFO L93 Difference]: Finished difference Result 31537 states and 45713 transitions. [2023-11-29 01:35:10,222 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31537 states and 45713 transitions. [2023-11-29 01:35:10,359 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31264 [2023-11-29 01:35:10,566 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31537 states to 31537 states and 45713 transitions. [2023-11-29 01:35:10,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31537 [2023-11-29 01:35:10,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31537 [2023-11-29 01:35:10,582 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31537 states and 45713 transitions. [2023-11-29 01:35:10,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:10,602 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31537 states and 45713 transitions. [2023-11-29 01:35:10,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31537 states and 45713 transitions. [2023-11-29 01:35:11,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31537 to 31505. [2023-11-29 01:35:11,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31505 states, 31505 states have (on average 1.4499603237581336) internal successors, (45681), 31504 states have internal predecessors, (45681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:11,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31505 states to 31505 states and 45681 transitions. [2023-11-29 01:35:11,222 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31505 states and 45681 transitions. [2023-11-29 01:35:11,222 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:11,223 INFO L428 stractBuchiCegarLoop]: Abstraction has 31505 states and 45681 transitions. [2023-11-29 01:35:11,223 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-29 01:35:11,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31505 states and 45681 transitions. [2023-11-29 01:35:11,327 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31232 [2023-11-29 01:35:11,327 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:11,327 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:11,330 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:11,330 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:11,330 INFO L748 eck$LassoCheckResult]: Stem: 124025#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 124026#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 125050#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 125051#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 125147#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 125061#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 124983#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 124984#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125043#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 123958#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 123959#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 124070#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 124331#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 124253#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 123960#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 123619#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 123620#L1036 assume !(0 == ~M_E~0); 123716#L1036-2 assume !(0 == ~T1_E~0); 124674#L1041-1 assume !(0 == ~T2_E~0); 124675#L1046-1 assume !(0 == ~T3_E~0); 123999#L1051-1 assume !(0 == ~T4_E~0); 124000#L1056-1 assume !(0 == ~T5_E~0); 124827#L1061-1 assume !(0 == ~T6_E~0); 123889#L1066-1 assume !(0 == ~T7_E~0); 123890#L1071-1 assume !(0 == ~T8_E~0); 124809#L1076-1 assume !(0 == ~T9_E~0); 123778#L1081-1 assume !(0 == ~T10_E~0); 123779#L1086-1 assume !(0 == ~E_M~0); 124195#L1091-1 assume !(0 == ~E_1~0); 125071#L1096-1 assume !(0 == ~E_2~0); 125072#L1101-1 assume !(0 == ~E_3~0); 124266#L1106-1 assume !(0 == ~E_4~0); 124267#L1111-1 assume !(0 == ~E_5~0); 124445#L1116-1 assume !(0 == ~E_6~0); 124446#L1121-1 assume !(0 == ~E_7~0); 124257#L1126-1 assume !(0 == ~E_8~0); 124258#L1131-1 assume !(0 == ~E_9~0); 124556#L1136-1 assume !(0 == ~E_10~0); 124687#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124866#L514 assume !(1 == ~m_pc~0); 124867#L514-2 is_master_triggered_~__retres1~0#1 := 0; 124275#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124276#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 124945#L1285 assume !(0 != activate_threads_~tmp~1#1); 125125#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123909#L533 assume !(1 == ~t1_pc~0); 123910#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 124462#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123671#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 123672#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 124712#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 124713#L552 assume !(1 == ~t2_pc~0); 124405#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 124406#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 124261#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 124262#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 124288#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 124289#L571 assume 1 == ~t3_pc~0; 124504#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 124505#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123617#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123618#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 124450#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123702#L590 assume !(1 == ~t4_pc~0); 123703#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 124514#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123796#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 123797#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124743#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124447#L609 assume 1 == ~t5_pc~0; 124448#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 125123#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124947#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 124948#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 124439#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124440#L628 assume !(1 == ~t6_pc~0); 124365#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 124364#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 124234#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 124235#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 124788#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124789#L647 assume 1 == ~t7_pc~0; 124268#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 124269#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 124958#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 124271#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 124272#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 125178#L666 assume !(1 == ~t8_pc~0); 124047#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 124048#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 124287#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 124474#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 124192#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 124193#L685 assume 1 == ~t9_pc~0; 125133#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 124969#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 124323#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 124224#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 124225#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 124643#L704 assume !(1 == ~t10_pc~0); 124214#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 124213#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 124495#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 123750#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 123751#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124009#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 124770#L1154-2 assume !(1 == ~T1_E~0); 123980#L1159-1 assume !(1 == ~T2_E~0); 123981#L1164-1 assume !(1 == ~T3_E~0); 135335#L1169-1 assume !(1 == ~T4_E~0); 135320#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 135312#L1179-1 assume !(1 == ~T6_E~0); 135309#L1184-1 assume !(1 == ~T7_E~0); 135307#L1189-1 assume !(1 == ~T8_E~0); 135305#L1194-1 assume !(1 == ~T9_E~0); 135303#L1199-1 assume !(1 == ~T10_E~0); 135294#L1204-1 assume !(1 == ~E_M~0); 135292#L1209-1 assume !(1 == ~E_1~0); 135289#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 135287#L1219-1 assume !(1 == ~E_3~0); 135285#L1224-1 assume !(1 == ~E_4~0); 135283#L1229-1 assume !(1 == ~E_5~0); 135281#L1234-1 assume !(1 == ~E_6~0); 133289#L1239-1 assume !(1 == ~E_7~0); 132828#L1244-1 assume !(1 == ~E_8~0); 132823#L1249-1 assume !(1 == ~E_9~0); 132775#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 132762#L1259-1 assume { :end_inline_reset_delta_events } true; 132760#L1565-2 [2023-11-29 01:35:11,331 INFO L750 eck$LassoCheckResult]: Loop: 132760#L1565-2 assume !false; 132758#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 132745#L1011-1 assume !false; 132737#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 132664#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 132648#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 132644#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 132641#L866 assume !(0 != eval_~tmp~0#1); 132642#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 136151#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 136149#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 136147#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 136145#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 136143#L1046-3 assume !(0 == ~T3_E~0); 136141#L1051-3 assume !(0 == ~T4_E~0); 136139#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 136137#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 136135#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 136133#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 136131#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 136129#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 136127#L1086-3 assume !(0 == ~E_M~0); 136125#L1091-3 assume !(0 == ~E_1~0); 136123#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 136121#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 136119#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 136117#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 136115#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 136113#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 136111#L1126-3 assume !(0 == ~E_8~0); 136109#L1131-3 assume !(0 == ~E_9~0); 136107#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 136105#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136103#L514-36 assume !(1 == ~m_pc~0); 136101#L514-38 is_master_triggered_~__retres1~0#1 := 0; 136099#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 136097#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 136095#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 136093#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136091#L533-36 assume 1 == ~t1_pc~0; 136088#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 136086#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136083#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 136081#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 136079#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 136077#L552-36 assume !(1 == ~t2_pc~0); 136075#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 136073#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 136071#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 136069#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 136067#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 136065#L571-36 assume 1 == ~t3_pc~0; 136062#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 136060#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136057#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 136055#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 136053#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 136051#L590-36 assume !(1 == ~t4_pc~0); 136048#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 136046#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 136045#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 136042#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 136040#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 136038#L609-36 assume 1 == ~t5_pc~0; 136035#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 136033#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 136031#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 136028#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 136026#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 136024#L628-36 assume !(1 == ~t6_pc~0); 136022#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 136019#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 136017#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 136014#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 136012#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 136010#L647-36 assume 1 == ~t7_pc~0; 136007#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 136005#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 136003#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 136000#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 135998#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 135996#L666-36 assume !(1 == ~t8_pc~0); 135994#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 135209#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 133199#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 133196#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 133194#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 133192#L685-36 assume 1 == ~t9_pc~0; 133190#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 133187#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 133185#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 133182#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 133180#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 133178#L704-36 assume 1 == ~t10_pc~0; 133175#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 133173#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 133171#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 133168#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 133166#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 133164#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 133160#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 133158#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 133156#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 133151#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 133149#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 133147#L1179-3 assume !(1 == ~T6_E~0); 133145#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 133143#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 133141#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 133138#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 133136#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 133132#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 133130#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 133128#L1219-3 assume !(1 == ~E_3~0); 133126#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 133123#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 133121#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 133119#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 133117#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 133113#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 133112#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 133111#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 133100#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 133099#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 133098#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 133097#L1584 assume !(0 == start_simulation_~tmp~3#1); 133095#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 133093#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 133080#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 133078#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 133076#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 132794#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 132791#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 132763#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 132760#L1565-2 [2023-11-29 01:35:11,331 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:11,331 INFO L85 PathProgramCache]: Analyzing trace with hash 353984391, now seen corresponding path program 1 times [2023-11-29 01:35:11,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:11,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1284562430] [2023-11-29 01:35:11,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:11,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:11,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:11,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:11,477 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:11,477 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1284562430] [2023-11-29 01:35:11,478 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1284562430] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:11,478 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:11,478 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:35:11,478 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [468343058] [2023-11-29 01:35:11,478 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:11,478 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:11,479 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:11,479 INFO L85 PathProgramCache]: Analyzing trace with hash -148556804, now seen corresponding path program 1 times [2023-11-29 01:35:11,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:11,479 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [371461996] [2023-11-29 01:35:11,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:11,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:11,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:11,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:11,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:11,528 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [371461996] [2023-11-29 01:35:11,528 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [371461996] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:11,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:11,528 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:11,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821050043] [2023-11-29 01:35:11,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:11,529 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:11,529 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:11,529 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:11,529 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:11,530 INFO L87 Difference]: Start difference. First operand 31505 states and 45681 transitions. cyclomatic complexity: 14208 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:11,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:11,853 INFO L93 Difference]: Finished difference Result 59948 states and 86522 transitions. [2023-11-29 01:35:11,853 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59948 states and 86522 transitions. [2023-11-29 01:35:12,254 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59580 [2023-11-29 01:35:12,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59948 states to 59948 states and 86522 transitions. [2023-11-29 01:35:12,458 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59948 [2023-11-29 01:35:12,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59948 [2023-11-29 01:35:12,489 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59948 states and 86522 transitions. [2023-11-29 01:35:12,538 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:12,538 INFO L218 hiAutomatonCegarLoop]: Abstraction has 59948 states and 86522 transitions. [2023-11-29 01:35:12,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59948 states and 86522 transitions. [2023-11-29 01:35:13,228 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59948 to 59884. [2023-11-29 01:35:13,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59884 states, 59884 states have (on average 1.4437579320018703) internal successors, (86458), 59883 states have internal predecessors, (86458), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:13,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59884 states to 59884 states and 86458 transitions. [2023-11-29 01:35:13,565 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59884 states and 86458 transitions. [2023-11-29 01:35:13,565 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:13,566 INFO L428 stractBuchiCegarLoop]: Abstraction has 59884 states and 86458 transitions. [2023-11-29 01:35:13,566 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-29 01:35:13,566 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59884 states and 86458 transitions. [2023-11-29 01:35:13,689 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59516 [2023-11-29 01:35:13,690 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:13,690 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:13,692 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:13,692 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:13,693 INFO L748 eck$LassoCheckResult]: Stem: 215482#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 215483#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 216454#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 216455#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 216541#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 216460#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 216403#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 216404#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 216444#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 215416#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 215417#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 215528#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 215781#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 215701#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 215418#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 215079#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 215080#L1036 assume !(0 == ~M_E~0); 215176#L1036-2 assume !(0 == ~T1_E~0); 216115#L1041-1 assume !(0 == ~T2_E~0); 216116#L1046-1 assume !(0 == ~T3_E~0); 215455#L1051-1 assume !(0 == ~T4_E~0); 215456#L1056-1 assume !(0 == ~T5_E~0); 216265#L1061-1 assume !(0 == ~T6_E~0); 215349#L1066-1 assume !(0 == ~T7_E~0); 215350#L1071-1 assume !(0 == ~T8_E~0); 216246#L1076-1 assume !(0 == ~T9_E~0); 215238#L1081-1 assume !(0 == ~T10_E~0); 215239#L1086-1 assume !(0 == ~E_M~0); 215646#L1091-1 assume !(0 == ~E_1~0); 216469#L1096-1 assume !(0 == ~E_2~0); 216470#L1101-1 assume !(0 == ~E_3~0); 215714#L1106-1 assume !(0 == ~E_4~0); 215715#L1111-1 assume !(0 == ~E_5~0); 215895#L1116-1 assume !(0 == ~E_6~0); 215896#L1121-1 assume !(0 == ~E_7~0); 215705#L1126-1 assume !(0 == ~E_8~0); 215706#L1131-1 assume !(0 == ~E_9~0); 216000#L1136-1 assume !(0 == ~E_10~0); 216127#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216299#L514 assume !(1 == ~m_pc~0); 216300#L514-2 is_master_triggered_~__retres1~0#1 := 0; 215723#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 215724#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 216370#L1285 assume !(0 != activate_threads_~tmp~1#1); 216519#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 215369#L533 assume !(1 == ~t1_pc~0); 215370#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 215910#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 215131#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 215132#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 216154#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 216155#L552 assume !(1 == ~t2_pc~0); 215856#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 215857#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 215709#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 215710#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 215736#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 215737#L571 assume !(1 == ~t3_pc~0); 215969#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 216054#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 215077#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 215078#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 215900#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 215162#L590 assume !(1 == ~t4_pc~0); 215163#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 215957#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 215256#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 215257#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 216185#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 215897#L609 assume 1 == ~t5_pc~0; 215898#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 216516#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216372#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 216373#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 215888#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 215889#L628 assume !(1 == ~t6_pc~0); 215815#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 215814#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 215682#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 215683#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 216225#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 216226#L647 assume 1 == ~t7_pc~0; 215716#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 215717#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 216380#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 215719#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 215720#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 216569#L666 assume !(1 == ~t8_pc~0); 215506#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 215507#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 215735#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 215922#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 215643#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 215644#L685 assume 1 == ~t9_pc~0; 216528#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 216389#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 215773#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 215672#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 215673#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 216085#L704 assume !(1 == ~t10_pc~0); 215663#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 215662#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 215941#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 215210#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 215211#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 215464#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 216210#L1154-2 assume !(1 == ~T1_E~0); 215438#L1159-1 assume !(1 == ~T2_E~0); 215439#L1164-1 assume !(1 == ~T3_E~0); 217660#L1169-1 assume !(1 == ~T4_E~0); 217655#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 217650#L1179-1 assume !(1 == ~T6_E~0); 217645#L1184-1 assume !(1 == ~T7_E~0); 217636#L1189-1 assume !(1 == ~T8_E~0); 217629#L1194-1 assume !(1 == ~T9_E~0); 217621#L1199-1 assume !(1 == ~T10_E~0); 217614#L1204-1 assume !(1 == ~E_M~0); 217452#L1209-1 assume !(1 == ~E_1~0); 217450#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 217448#L1219-1 assume !(1 == ~E_3~0); 217446#L1224-1 assume !(1 == ~E_4~0); 217443#L1229-1 assume !(1 == ~E_5~0); 217441#L1234-1 assume !(1 == ~E_6~0); 217304#L1239-1 assume !(1 == ~E_7~0); 217269#L1244-1 assume !(1 == ~E_8~0); 217265#L1249-1 assume !(1 == ~E_9~0); 217253#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 217244#L1259-1 assume { :end_inline_reset_delta_events } true; 217237#L1565-2 [2023-11-29 01:35:13,693 INFO L750 eck$LassoCheckResult]: Loop: 217237#L1565-2 assume !false; 217231#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 217227#L1011-1 assume !false; 217226#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 217225#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 217214#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 217213#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 217211#L866 assume !(0 != eval_~tmp~0#1); 217210#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 217209#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 217206#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 217207#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 220646#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 220644#L1046-3 assume !(0 == ~T3_E~0); 220642#L1051-3 assume !(0 == ~T4_E~0); 220640#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 220638#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 220636#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 220634#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 220632#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 220630#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 220628#L1086-3 assume !(0 == ~E_M~0); 220626#L1091-3 assume !(0 == ~E_1~0); 220624#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 220622#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 220620#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 220618#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 220610#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 220605#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 220600#L1126-3 assume !(0 == ~E_8~0); 220595#L1131-3 assume !(0 == ~E_9~0); 220589#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 220583#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 220577#L514-36 assume !(1 == ~m_pc~0); 220570#L514-38 is_master_triggered_~__retres1~0#1 := 0; 220563#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 220556#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 220549#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 220541#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 220534#L533-36 assume !(1 == ~t1_pc~0); 220526#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 220517#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 220510#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 217134#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 217135#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 220153#L552-36 assume !(1 == ~t2_pc~0); 220151#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 220149#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 220147#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 220145#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 220143#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 220141#L571-36 assume !(1 == ~t3_pc~0); 220140#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 220139#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 220138#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 220137#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 220136#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 220135#L590-36 assume 1 == ~t4_pc~0; 220134#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 220131#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 220129#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 220127#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 220125#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 220122#L609-36 assume 1 == ~t5_pc~0; 220119#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 220117#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 220115#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 220113#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 220111#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 220108#L628-36 assume !(1 == ~t6_pc~0); 220106#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 220103#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 220101#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 220099#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 220097#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 220096#L647-36 assume !(1 == ~t7_pc~0); 220095#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 220093#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 220091#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 220089#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 219679#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 219677#L666-36 assume !(1 == ~t8_pc~0); 219675#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 219672#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 219670#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 219667#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 219665#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 219663#L685-36 assume 1 == ~t9_pc~0; 219661#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 219658#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 219656#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 219654#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 219652#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 219650#L704-36 assume !(1 == ~t10_pc~0); 219648#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 219645#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 219643#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 219641#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 219639#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 219637#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 216989#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 219634#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 219632#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 219627#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 219625#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 219623#L1179-3 assume !(1 == ~T6_E~0); 219621#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 219619#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 219617#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 219614#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 219612#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 219608#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 219606#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 218827#L1219-3 assume !(1 == ~E_3~0); 218825#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 218568#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 218566#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 218538#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 218529#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 218520#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 218128#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 218126#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 218067#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 218058#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 218048#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 218038#L1584 assume !(0 == start_simulation_~tmp~3#1); 218033#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 217802#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 217455#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 217306#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 217270#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 217266#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 217254#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 217245#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 217237#L1565-2 [2023-11-29 01:35:13,693 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:13,694 INFO L85 PathProgramCache]: Analyzing trace with hash -1601336824, now seen corresponding path program 1 times [2023-11-29 01:35:13,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:13,694 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779597286] [2023-11-29 01:35:13,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:13,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:13,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:13,747 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:13,747 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:13,748 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1779597286] [2023-11-29 01:35:13,748 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1779597286] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:13,748 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:13,748 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:35:13,748 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1036918157] [2023-11-29 01:35:13,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:13,748 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:13,749 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:13,749 INFO L85 PathProgramCache]: Analyzing trace with hash -1349972737, now seen corresponding path program 1 times [2023-11-29 01:35:13,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:13,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921316582] [2023-11-29 01:35:13,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:13,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:13,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:13,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:13,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:13,784 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921316582] [2023-11-29 01:35:13,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1921316582] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:13,784 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:13,784 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:13,784 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692390993] [2023-11-29 01:35:13,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:13,785 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:13,785 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:13,785 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 01:35:13,785 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 01:35:13,786 INFO L87 Difference]: Start difference. First operand 59884 states and 86458 transitions. cyclomatic complexity: 26638 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:14,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:14,673 INFO L93 Difference]: Finished difference Result 144384 states and 206761 transitions. [2023-11-29 01:35:14,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144384 states and 206761 transitions. [2023-11-29 01:35:15,217 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 143672 [2023-11-29 01:35:15,564 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144384 states to 144384 states and 206761 transitions. [2023-11-29 01:35:15,565 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144384 [2023-11-29 01:35:15,623 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144384 [2023-11-29 01:35:15,623 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144384 states and 206761 transitions. [2023-11-29 01:35:15,698 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:15,698 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144384 states and 206761 transitions. [2023-11-29 01:35:15,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144384 states and 206761 transitions. [2023-11-29 01:35:16,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144384 to 61735. [2023-11-29 01:35:16,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61735 states, 61735 states have (on average 1.4304527415566535) internal successors, (88309), 61734 states have internal predecessors, (88309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:16,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61735 states to 61735 states and 88309 transitions. [2023-11-29 01:35:16,636 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61735 states and 88309 transitions. [2023-11-29 01:35:16,636 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 01:35:16,637 INFO L428 stractBuchiCegarLoop]: Abstraction has 61735 states and 88309 transitions. [2023-11-29 01:35:16,637 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-29 01:35:16,637 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61735 states and 88309 transitions. [2023-11-29 01:35:16,783 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 61364 [2023-11-29 01:35:16,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:16,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:16,785 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:16,785 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:16,785 INFO L748 eck$LassoCheckResult]: Stem: 419770#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 419771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 420839#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 420840#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 420951#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 420847#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 420768#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 420769#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 420829#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 419700#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 419701#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 419820#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 420073#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 419997#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 419702#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 419360#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 419361#L1036 assume !(0 == ~M_E~0); 419459#L1036-2 assume !(0 == ~T1_E~0); 420427#L1041-1 assume !(0 == ~T2_E~0); 420428#L1046-1 assume !(0 == ~T3_E~0); 419742#L1051-1 assume !(0 == ~T4_E~0); 419743#L1056-1 assume !(0 == ~T5_E~0); 420600#L1061-1 assume !(0 == ~T6_E~0); 419631#L1066-1 assume !(0 == ~T7_E~0); 419632#L1071-1 assume !(0 == ~T8_E~0); 420578#L1076-1 assume !(0 == ~T9_E~0); 419521#L1081-1 assume !(0 == ~T10_E~0); 419522#L1086-1 assume !(0 == ~E_M~0); 419940#L1091-1 assume !(0 == ~E_1~0); 420858#L1096-1 assume !(0 == ~E_2~0); 420859#L1101-1 assume !(0 == ~E_3~0); 420010#L1106-1 assume !(0 == ~E_4~0); 420011#L1111-1 assume !(0 == ~E_5~0); 420189#L1116-1 assume !(0 == ~E_6~0); 420190#L1121-1 assume !(0 == ~E_7~0); 420001#L1126-1 assume !(0 == ~E_8~0); 420002#L1131-1 assume !(0 == ~E_9~0); 420302#L1136-1 assume !(0 == ~E_10~0); 420441#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 420639#L514 assume !(1 == ~m_pc~0); 420640#L514-2 is_master_triggered_~__retres1~0#1 := 0; 420019#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 420020#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 420727#L1285 assume !(0 != activate_threads_~tmp~1#1); 420918#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 419650#L533 assume !(1 == ~t1_pc~0); 419651#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 420206#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 419413#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 419414#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 420471#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 420472#L552 assume !(1 == ~t2_pc~0); 420148#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 420149#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 420005#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 420006#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 420033#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 420034#L571 assume !(1 == ~t3_pc~0); 420267#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 420359#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 419358#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 419359#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 420195#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 419445#L590 assume !(1 == ~t4_pc~0); 419446#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 420266#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 421018#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 420924#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 420505#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 420191#L609 assume 1 == ~t5_pc~0; 420192#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 420915#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 420730#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 420731#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 420182#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 420183#L628 assume !(1 == ~t6_pc~0); 420108#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 420107#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 419977#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 419978#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 420553#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 420554#L647 assume 1 == ~t7_pc~0; 420012#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 420013#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 420744#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 420015#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 420016#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 420980#L666 assume !(1 == ~t8_pc~0); 419797#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 419798#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 420032#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 420218#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 419935#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 419936#L685 assume 1 == ~t9_pc~0; 420934#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 420755#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 420067#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 419967#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 419968#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 420394#L704 assume !(1 == ~t10_pc~0); 419958#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 419957#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 420237#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 419493#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 419494#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 419752#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 420537#L1154-2 assume !(1 == ~T1_E~0); 420961#L1159-1 assume !(1 == ~T2_E~0); 421024#L1164-1 assume !(1 == ~T3_E~0); 420216#L1169-1 assume !(1 == ~T4_E~0); 420068#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 419865#L1179-1 assume !(1 == ~T6_E~0); 419708#L1184-1 assume !(1 == ~T7_E~0); 419709#L1189-1 assume !(1 == ~T8_E~0); 419795#L1194-1 assume !(1 == ~T9_E~0); 419921#L1199-1 assume !(1 == ~T10_E~0); 419877#L1204-1 assume !(1 == ~E_M~0); 419878#L1209-1 assume !(1 == ~E_1~0); 420499#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 420500#L1219-1 assume !(1 == ~E_3~0); 420963#L1224-1 assume !(1 == ~E_4~0); 420241#L1229-1 assume !(1 == ~E_5~0); 419588#L1234-1 assume !(1 == ~E_6~0); 419589#L1239-1 assume !(1 == ~E_7~0); 419646#L1244-1 assume !(1 == ~E_8~0); 419647#L1249-1 assume !(1 == ~E_9~0); 420682#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 430620#L1259-1 assume { :end_inline_reset_delta_events } true; 430613#L1565-2 [2023-11-29 01:35:16,786 INFO L750 eck$LassoCheckResult]: Loop: 430613#L1565-2 assume !false; 430607#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 430603#L1011-1 assume !false; 430602#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 430601#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 430590#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 430589#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 430587#L866 assume !(0 != eval_~tmp~0#1); 430588#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 465362#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 465361#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 465360#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 465359#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 465358#L1046-3 assume !(0 == ~T3_E~0); 465357#L1051-3 assume !(0 == ~T4_E~0); 465356#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 465355#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 465354#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 465353#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 465352#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 465351#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 465350#L1086-3 assume !(0 == ~E_M~0); 465349#L1091-3 assume !(0 == ~E_1~0); 465348#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 465347#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 465346#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 465345#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 465344#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 465343#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 465342#L1126-3 assume !(0 == ~E_8~0); 465341#L1131-3 assume !(0 == ~E_9~0); 465340#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 465339#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 465338#L514-36 assume !(1 == ~m_pc~0); 465337#L514-38 is_master_triggered_~__retres1~0#1 := 0; 465336#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 465335#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 465334#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 465333#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 465332#L533-36 assume !(1 == ~t1_pc~0); 465331#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 465329#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 465328#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 465327#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 465326#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 465325#L552-36 assume !(1 == ~t2_pc~0); 465324#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 465323#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 465322#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 465321#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 465320#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 465319#L571-36 assume !(1 == ~t3_pc~0); 465318#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 465317#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 465316#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 465315#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 465314#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 465313#L590-36 assume !(1 == ~t4_pc~0); 465312#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 465310#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 465308#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 465306#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 465303#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 465300#L609-36 assume !(1 == ~t5_pc~0); 465298#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 465295#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 465293#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 465291#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 465289#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 465286#L628-36 assume !(1 == ~t6_pc~0); 465284#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 465281#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 465279#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 465277#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 465275#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 465272#L647-36 assume !(1 == ~t7_pc~0); 465270#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 465267#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 465265#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 465263#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 465261#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 465258#L666-36 assume 1 == ~t8_pc~0; 465255#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 465253#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 465251#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 465249#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 465247#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 465244#L685-36 assume 1 == ~t9_pc~0; 465242#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 465239#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 465237#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 465235#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 465233#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 465219#L704-36 assume !(1 == ~t10_pc~0); 465216#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 465211#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 465203#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 465200#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 419635#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 419636#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 420805#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 420612#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 420613#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 420910#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 419954#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 419955#L1179-3 assume !(1 == ~T6_E~0); 420757#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 419509#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 419510#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 419894#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 419895#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 420238#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 419376#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 419377#L1219-3 assume !(1 == ~E_3~0); 420479#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 420480#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 420506#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 419648#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 419649#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 420299#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 430738#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 430736#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 430703#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 430693#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 430686#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 430677#L1584 assume !(0 == start_simulation_~tmp~3#1); 430671#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 430665#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 430654#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 430652#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 430651#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 430648#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 430629#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 430621#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 430613#L1565-2 [2023-11-29 01:35:16,786 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:16,786 INFO L85 PathProgramCache]: Analyzing trace with hash 360237834, now seen corresponding path program 1 times [2023-11-29 01:35:16,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:16,786 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [228574198] [2023-11-29 01:35:16,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:16,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:16,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:16,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:16,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:16,830 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [228574198] [2023-11-29 01:35:16,830 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [228574198] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:16,830 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:16,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:35:16,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562389428] [2023-11-29 01:35:16,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:16,831 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:16,831 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:16,831 INFO L85 PathProgramCache]: Analyzing trace with hash 1805062786, now seen corresponding path program 1 times [2023-11-29 01:35:16,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:16,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1578152489] [2023-11-29 01:35:16,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:16,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:16,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:16,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:16,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:16,866 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1578152489] [2023-11-29 01:35:16,866 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1578152489] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:16,866 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:16,866 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:16,866 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [892994087] [2023-11-29 01:35:16,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:16,867 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:16,867 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:16,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:16,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:16,867 INFO L87 Difference]: Start difference. First operand 61735 states and 88309 transitions. cyclomatic complexity: 26638 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:17,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:17,407 INFO L93 Difference]: Finished difference Result 117490 states and 167414 transitions. [2023-11-29 01:35:17,407 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117490 states and 167414 transitions. [2023-11-29 01:35:18,021 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 116832 [2023-11-29 01:35:18,296 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117490 states to 117490 states and 167414 transitions. [2023-11-29 01:35:18,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117490 [2023-11-29 01:35:18,353 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117490 [2023-11-29 01:35:18,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117490 states and 167414 transitions. [2023-11-29 01:35:18,407 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:18,408 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117490 states and 167414 transitions. [2023-11-29 01:35:18,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117490 states and 167414 transitions. [2023-11-29 01:35:19,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117490 to 117362. [2023-11-29 01:35:19,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117362 states, 117362 states have (on average 1.4253847071454133) internal successors, (167286), 117361 states have internal predecessors, (167286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:19,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117362 states to 117362 states and 167286 transitions. [2023-11-29 01:35:19,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117362 states and 167286 transitions. [2023-11-29 01:35:19,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:19,766 INFO L428 stractBuchiCegarLoop]: Abstraction has 117362 states and 167286 transitions. [2023-11-29 01:35:19,766 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-29 01:35:19,766 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117362 states and 167286 transitions. [2023-11-29 01:35:20,044 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 116704 [2023-11-29 01:35:20,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:20,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:20,046 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:20,046 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:20,046 INFO L748 eck$LassoCheckResult]: Stem: 598996#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 598997#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 599974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 599975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 600074#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 599979#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 599926#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 599927#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 599963#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 598932#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 598933#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 599041#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 599295#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 599217#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 598934#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 598592#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 598593#L1036 assume !(0 == ~M_E~0); 598688#L1036-2 assume !(0 == ~T1_E~0); 599635#L1041-1 assume !(0 == ~T2_E~0); 599636#L1046-1 assume !(0 == ~T3_E~0); 598972#L1051-1 assume !(0 == ~T4_E~0); 598973#L1056-1 assume !(0 == ~T5_E~0); 599782#L1061-1 assume !(0 == ~T6_E~0); 598861#L1066-1 assume !(0 == ~T7_E~0); 598862#L1071-1 assume !(0 == ~T8_E~0); 599761#L1076-1 assume !(0 == ~T9_E~0); 598751#L1081-1 assume !(0 == ~T10_E~0); 598752#L1086-1 assume !(0 == ~E_M~0); 599161#L1091-1 assume !(0 == ~E_1~0); 599989#L1096-1 assume !(0 == ~E_2~0); 599990#L1101-1 assume !(0 == ~E_3~0); 599232#L1106-1 assume !(0 == ~E_4~0); 599233#L1111-1 assume !(0 == ~E_5~0); 599412#L1116-1 assume !(0 == ~E_6~0); 599413#L1121-1 assume !(0 == ~E_7~0); 599221#L1126-1 assume !(0 == ~E_8~0); 599222#L1131-1 assume !(0 == ~E_9~0); 599519#L1136-1 assume !(0 == ~E_10~0); 599644#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 599820#L514 assume !(1 == ~m_pc~0); 599821#L514-2 is_master_triggered_~__retres1~0#1 := 0; 599241#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 599242#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 599886#L1285 assume !(0 != activate_threads_~tmp~1#1); 600048#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 598884#L533 assume !(1 == ~t1_pc~0); 598885#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 599428#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 598647#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 598648#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 599668#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 599669#L552 assume !(1 == ~t2_pc~0); 599369#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 599370#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 599225#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 599226#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 599260#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 599261#L571 assume !(1 == ~t3_pc~0); 599489#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 599573#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 598590#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 598591#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 599416#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 598674#L590 assume !(1 == ~t4_pc~0); 598675#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 599487#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 600132#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 600051#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 599700#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 599414#L609 assume !(1 == ~t5_pc~0); 599415#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 600043#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 599887#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 599888#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 599407#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 599408#L628 assume !(1 == ~t6_pc~0); 599326#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 599325#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 599201#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 599202#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 599737#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 599738#L647 assume 1 == ~t7_pc~0; 599234#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 599235#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 599899#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 599239#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 599240#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 600091#L666 assume !(1 == ~t8_pc~0); 599018#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 599019#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 599253#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 599441#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 599158#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 599159#L685 assume 1 == ~t9_pc~0; 600056#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 599911#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 599288#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 599186#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 599187#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 599605#L704 assume !(1 == ~t10_pc~0); 599177#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 599176#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 599461#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 598723#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 598724#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 598980#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 599723#L1154-2 assume !(1 == ~T1_E~0); 598951#L1159-1 assume !(1 == ~T2_E~0); 598952#L1164-1 assume !(1 == ~T3_E~0); 599437#L1169-1 assume !(1 == ~T4_E~0); 599290#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 599084#L1179-1 assume !(1 == ~T6_E~0); 598936#L1184-1 assume !(1 == ~T7_E~0); 598937#L1189-1 assume !(1 == ~T8_E~0); 599016#L1194-1 assume !(1 == ~T9_E~0); 599144#L1199-1 assume !(1 == ~T10_E~0); 599097#L1204-1 assume !(1 == ~E_M~0); 599098#L1209-1 assume !(1 == ~E_1~0); 600090#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 603588#L1219-1 assume !(1 == ~E_3~0); 603586#L1224-1 assume !(1 == ~E_4~0); 603583#L1229-1 assume !(1 == ~E_5~0); 603581#L1234-1 assume !(1 == ~E_6~0); 603579#L1239-1 assume !(1 == ~E_7~0); 603001#L1244-1 assume !(1 == ~E_8~0); 602270#L1249-1 assume !(1 == ~E_9~0); 602268#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 602000#L1259-1 assume { :end_inline_reset_delta_events } true; 601998#L1565-2 [2023-11-29 01:35:20,047 INFO L750 eck$LassoCheckResult]: Loop: 601998#L1565-2 assume !false; 601996#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 601991#L1011-1 assume !false; 601988#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 601703#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 601691#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 601689#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 601686#L866 assume !(0 != eval_~tmp~0#1); 601687#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 604081#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 604079#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 604077#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 604075#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 604073#L1046-3 assume !(0 == ~T3_E~0); 604071#L1051-3 assume !(0 == ~T4_E~0); 604069#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 604067#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 604065#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 604063#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 604061#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 604059#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 604057#L1086-3 assume !(0 == ~E_M~0); 604055#L1091-3 assume !(0 == ~E_1~0); 604053#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 604051#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 604049#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 604047#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 604045#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 604043#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 604041#L1126-3 assume !(0 == ~E_8~0); 604039#L1131-3 assume !(0 == ~E_9~0); 604037#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 604035#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 604033#L514-36 assume !(1 == ~m_pc~0); 604031#L514-38 is_master_triggered_~__retres1~0#1 := 0; 604029#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 604027#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 604025#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 604023#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 604021#L533-36 assume 1 == ~t1_pc~0; 604017#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 604015#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 604013#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 604011#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 604009#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 604007#L552-36 assume !(1 == ~t2_pc~0); 604005#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 604003#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 604001#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 603999#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 603997#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 603995#L571-36 assume !(1 == ~t3_pc~0); 603993#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 603991#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 603989#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 603987#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 603985#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 603981#L590-36 assume !(1 == ~t4_pc~0); 603977#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 603975#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 603973#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 603970#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 603967#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 603965#L609-36 assume !(1 == ~t5_pc~0); 603963#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 603961#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 603959#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 603957#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 603955#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 603953#L628-36 assume 1 == ~t6_pc~0; 603949#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 603947#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 603945#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 603943#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 603941#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 603939#L647-36 assume 1 == ~t7_pc~0; 603935#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 603933#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 603931#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 603929#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 603927#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 603925#L666-36 assume 1 == ~t8_pc~0; 603921#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 603919#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 603917#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 603915#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 603913#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 603911#L685-36 assume !(1 == ~t9_pc~0); 603907#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 603905#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 603903#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 603901#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 603899#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 603897#L704-36 assume 1 == ~t10_pc~0; 603893#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 603891#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 603889#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 603887#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 603885#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 603883#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 603879#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 603877#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 603876#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 603873#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 603872#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 603871#L1179-3 assume !(1 == ~T6_E~0); 603870#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 603869#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 603868#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 603867#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 603855#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 603851#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 603849#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 603847#L1219-3 assume !(1 == ~E_3~0); 603845#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 603843#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 603841#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 603839#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 603834#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 603831#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 603830#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 603829#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 603616#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 603072#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 603070#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 602409#L1584 assume !(0 == start_simulation_~tmp~3#1); 602406#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 602023#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 602011#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 602009#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 602007#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 602005#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 602003#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 602001#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 601998#L1565-2 [2023-11-29 01:35:20,047 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:20,047 INFO L85 PathProgramCache]: Analyzing trace with hash -671092981, now seen corresponding path program 1 times [2023-11-29 01:35:20,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:20,047 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1075956030] [2023-11-29 01:35:20,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:20,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:20,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:20,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:20,313 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:20,313 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1075956030] [2023-11-29 01:35:20,313 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1075956030] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:20,314 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:20,314 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:20,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1108834312] [2023-11-29 01:35:20,314 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:20,314 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:20,315 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:20,315 INFO L85 PathProgramCache]: Analyzing trace with hash 1177559807, now seen corresponding path program 1 times [2023-11-29 01:35:20,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:20,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239626110] [2023-11-29 01:35:20,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:20,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:20,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:20,361 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:20,361 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:20,361 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239626110] [2023-11-29 01:35:20,361 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [239626110] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:20,361 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:20,361 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:20,361 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [64587714] [2023-11-29 01:35:20,361 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:20,362 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:20,362 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:20,362 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:35:20,362 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:35:20,363 INFO L87 Difference]: Start difference. First operand 117362 states and 167286 transitions. cyclomatic complexity: 50052 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:21,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:21,501 INFO L93 Difference]: Finished difference Result 282357 states and 399839 transitions. [2023-11-29 01:35:21,501 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 282357 states and 399839 transitions. [2023-11-29 01:35:22,867 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 280612 [2023-11-29 01:35:23,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 282357 states to 282357 states and 399839 transitions. [2023-11-29 01:35:23,359 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 282357 [2023-11-29 01:35:23,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 282357 [2023-11-29 01:35:23,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 282357 states and 399839 transitions. [2023-11-29 01:35:23,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:23,547 INFO L218 hiAutomatonCegarLoop]: Abstraction has 282357 states and 399839 transitions. [2023-11-29 01:35:23,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282357 states and 399839 transitions. [2023-11-29 01:35:25,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282357 to 227905. [2023-11-29 01:35:25,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 227905 states, 227905 states have (on average 1.4191307781751168) internal successors, (323427), 227904 states have internal predecessors, (323427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:26,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227905 states to 227905 states and 323427 transitions. [2023-11-29 01:35:26,502 INFO L240 hiAutomatonCegarLoop]: Abstraction has 227905 states and 323427 transitions. [2023-11-29 01:35:26,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:35:26,503 INFO L428 stractBuchiCegarLoop]: Abstraction has 227905 states and 323427 transitions. [2023-11-29 01:35:26,503 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-29 01:35:26,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 227905 states and 323427 transitions. [2023-11-29 01:35:27,180 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 226800 [2023-11-29 01:35:27,180 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:27,180 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:27,183 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:27,183 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:27,184 INFO L748 eck$LassoCheckResult]: Stem: 998721#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 998722#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 999686#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 999687#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 999766#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 999692#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 999635#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 999636#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 999676#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 998654#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 998655#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 998767#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 999016#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 998937#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 998653#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 998321#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 998322#L1036 assume !(0 == ~M_E~0); 998418#L1036-2 assume !(0 == ~T1_E~0); 999344#L1041-1 assume !(0 == ~T2_E~0); 999345#L1046-1 assume !(0 == ~T3_E~0); 998696#L1051-1 assume !(0 == ~T4_E~0); 998697#L1056-1 assume !(0 == ~T5_E~0); 999494#L1061-1 assume !(0 == ~T6_E~0); 998587#L1066-1 assume !(0 == ~T7_E~0); 998588#L1071-1 assume !(0 == ~T8_E~0); 999474#L1076-1 assume !(0 == ~T9_E~0); 998479#L1081-1 assume !(0 == ~T10_E~0); 998480#L1086-1 assume !(0 == ~E_M~0); 998882#L1091-1 assume !(0 == ~E_1~0); 999699#L1096-1 assume !(0 == ~E_2~0); 999700#L1101-1 assume !(0 == ~E_3~0); 998951#L1106-1 assume !(0 == ~E_4~0); 998952#L1111-1 assume !(0 == ~E_5~0); 999127#L1116-1 assume !(0 == ~E_6~0); 999128#L1121-1 assume !(0 == ~E_7~0); 998941#L1126-1 assume !(0 == ~E_8~0); 998942#L1131-1 assume !(0 == ~E_9~0); 999229#L1136-1 assume !(0 == ~E_10~0); 999353#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 999524#L514 assume !(1 == ~m_pc~0); 999525#L514-2 is_master_triggered_~__retres1~0#1 := 0; 998957#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 998958#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 999594#L1285 assume !(0 != activate_threads_~tmp~1#1); 999741#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 998606#L533 assume !(1 == ~t1_pc~0); 998607#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 999142#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 998374#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 998375#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 999375#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 999376#L552 assume !(1 == ~t2_pc~0); 999086#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 999087#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 998945#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 998946#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 998970#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 998971#L571 assume !(1 == ~t3_pc~0); 999200#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 999284#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 998319#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 998320#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 999131#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 998404#L590 assume !(1 == ~t4_pc~0); 998405#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 999199#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 999831#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 999747#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 999407#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 999129#L609 assume !(1 == ~t5_pc~0); 999130#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 999739#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 999596#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 999597#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 999121#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 999122#L628 assume !(1 == ~t6_pc~0); 999047#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 999046#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 998918#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 998919#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 999450#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 999451#L647 assume !(1 == ~t7_pc~0); 999577#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 999613#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 999614#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 998953#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 998954#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 999786#L666 assume !(1 == ~t8_pc~0); 998744#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 998745#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 998969#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 999154#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 998879#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 998880#L685 assume 1 == ~t9_pc~0; 999751#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 999623#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 999008#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 998908#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 998909#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 999314#L704 assume !(1 == ~t10_pc~0); 998900#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 998899#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 999173#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 998452#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 998453#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 998705#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 999435#L1154-2 assume !(1 == ~T1_E~0); 999770#L1159-1 assume !(1 == ~T2_E~0); 999817#L1164-1 assume !(1 == ~T3_E~0); 999818#L1169-1 assume !(1 == ~T4_E~0); 999009#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 999010#L1179-1 assume !(1 == ~T6_E~0); 998661#L1184-1 assume !(1 == ~T7_E~0); 998662#L1189-1 assume !(1 == ~T8_E~0); 998864#L1194-1 assume !(1 == ~T9_E~0); 998865#L1199-1 assume !(1 == ~T10_E~0); 998821#L1204-1 assume !(1 == ~E_M~0); 998822#L1209-1 assume !(1 == ~E_1~0); 999401#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 999402#L1219-1 assume !(1 == ~E_3~0); 999773#L1224-1 assume !(1 == ~E_4~0); 999177#L1229-1 assume !(1 == ~E_5~0); 998546#L1234-1 assume !(1 == ~E_6~0); 998547#L1239-1 assume !(1 == ~E_7~0); 998602#L1244-1 assume !(1 == ~E_8~0); 998603#L1249-1 assume !(1 == ~E_9~0); 999557#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 998447#L1259-1 assume { :end_inline_reset_delta_events } true; 998448#L1565-2 [2023-11-29 01:35:27,184 INFO L750 eck$LassoCheckResult]: Loop: 998448#L1565-2 assume !false; 1047929#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1047907#L1011-1 assume !false; 1047906#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1047464#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1047451#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1047449#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1047446#L866 assume !(0 != eval_~tmp~0#1); 1047447#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1050295#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1050290#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1050284#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1050278#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1050273#L1046-3 assume !(0 == ~T3_E~0); 1050268#L1051-3 assume !(0 == ~T4_E~0); 1050263#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1050257#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1050253#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1050250#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1050248#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1050191#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1050190#L1086-3 assume !(0 == ~E_M~0); 1050189#L1091-3 assume !(0 == ~E_1~0); 1050188#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1050118#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1050112#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1050106#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1050100#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1050092#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1050084#L1126-3 assume !(0 == ~E_8~0); 1050075#L1131-3 assume !(0 == ~E_9~0); 1050067#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1050061#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1050056#L514-36 assume !(1 == ~m_pc~0); 1050050#L514-38 is_master_triggered_~__retres1~0#1 := 0; 1050043#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1050036#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1050030#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1050025#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1050020#L533-36 assume 1 == ~t1_pc~0; 1050013#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1050007#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1050001#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1049995#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1049989#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1049424#L552-36 assume !(1 == ~t2_pc~0); 1049141#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1048251#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1048248#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1048246#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1048244#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1048242#L571-36 assume !(1 == ~t3_pc~0); 1048240#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1048238#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1048236#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1048234#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1048232#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1048230#L590-36 assume 1 == ~t4_pc~0; 1048228#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1048229#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1048278#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1048219#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1048217#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1048215#L609-36 assume !(1 == ~t5_pc~0); 1048213#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1048209#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1048207#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1048205#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 1048203#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1048200#L628-36 assume !(1 == ~t6_pc~0); 1048191#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1048188#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1048186#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1048184#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1048181#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1048179#L647-36 assume !(1 == ~t7_pc~0); 1018204#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1048176#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1048174#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1048172#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1048170#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1048168#L666-36 assume !(1 == ~t8_pc~0); 1048166#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1048162#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1048160#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1048158#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1048156#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1048154#L685-36 assume 1 == ~t9_pc~0; 1048152#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1048150#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1048148#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1048146#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1048144#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1048142#L704-36 assume !(1 == ~t10_pc~0); 1048140#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1048136#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1048134#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1048132#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1048130#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1048128#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1030995#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1048122#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1048120#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1048116#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1048114#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1048112#L1179-3 assume !(1 == ~T6_E~0); 1048110#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1048107#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1048105#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1048103#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1048101#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1031580#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1048098#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1048096#L1219-3 assume !(1 == ~E_3~0); 1048094#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1048092#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1048090#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1048088#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1048086#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1037402#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1048083#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1048081#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1048058#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1048057#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1048056#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1048054#L1584 assume !(0 == start_simulation_~tmp~3#1); 1048051#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1047955#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1047943#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1047941#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1047939#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1047937#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1047935#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1047933#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 998448#L1565-2 [2023-11-29 01:35:27,185 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:27,185 INFO L85 PathProgramCache]: Analyzing trace with hash 1730432140, now seen corresponding path program 1 times [2023-11-29 01:35:27,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:27,185 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267503695] [2023-11-29 01:35:27,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:27,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:27,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:27,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:27,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:27,253 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267503695] [2023-11-29 01:35:27,253 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [267503695] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:27,253 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:27,253 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:35:27,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [815507859] [2023-11-29 01:35:27,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:27,254 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:27,254 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:27,255 INFO L85 PathProgramCache]: Analyzing trace with hash 1116749823, now seen corresponding path program 1 times [2023-11-29 01:35:27,255 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:27,255 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792730953] [2023-11-29 01:35:27,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:27,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:27,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:27,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:27,310 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:27,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [792730953] [2023-11-29 01:35:27,311 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [792730953] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:27,311 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:27,311 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:27,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126197680] [2023-11-29 01:35:27,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:27,312 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:27,312 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:27,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:27,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:27,313 INFO L87 Difference]: Start difference. First operand 227905 states and 323427 transitions. cyclomatic complexity: 95650 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:28,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:28,924 INFO L93 Difference]: Finished difference Result 432976 states and 612432 transitions. [2023-11-29 01:35:28,924 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 432976 states and 612432 transitions. [2023-11-29 01:35:31,164 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 430464 [2023-11-29 01:35:31,978 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 432976 states to 432976 states and 612432 transitions. [2023-11-29 01:35:31,978 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 432976 [2023-11-29 01:35:32,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 432976 [2023-11-29 01:35:32,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 432976 states and 612432 transitions. [2023-11-29 01:35:32,613 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:32,613 INFO L218 hiAutomatonCegarLoop]: Abstraction has 432976 states and 612432 transitions. [2023-11-29 01:35:32,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 432976 states and 612432 transitions. [2023-11-29 01:35:35,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 432976 to 432464. [2023-11-29 01:35:36,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 432464 states, 432464 states have (on average 1.414961707795331) internal successors, (611920), 432463 states have internal predecessors, (611920), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:37,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432464 states to 432464 states and 611920 transitions. [2023-11-29 01:35:37,481 INFO L240 hiAutomatonCegarLoop]: Abstraction has 432464 states and 611920 transitions. [2023-11-29 01:35:37,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:37,481 INFO L428 stractBuchiCegarLoop]: Abstraction has 432464 states and 611920 transitions. [2023-11-29 01:35:37,481 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-29 01:35:37,481 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 432464 states and 611920 transitions. [2023-11-29 01:35:38,956 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 429952 [2023-11-29 01:35:38,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:38,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:38,958 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:38,958 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:38,959 INFO L748 eck$LassoCheckResult]: Stem: 1659609#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1659610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1660626#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1660627#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1660730#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 1660632#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1660567#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1660568#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1660613#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1659541#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1659542#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1659655#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1659909#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1659832#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1659543#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1659209#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1659210#L1036 assume !(0 == ~M_E~0); 1659306#L1036-2 assume !(0 == ~T1_E~0); 1660253#L1041-1 assume !(0 == ~T2_E~0); 1660254#L1046-1 assume !(0 == ~T3_E~0); 1659583#L1051-1 assume !(0 == ~T4_E~0); 1659584#L1056-1 assume !(0 == ~T5_E~0); 1660408#L1061-1 assume !(0 == ~T6_E~0); 1659475#L1066-1 assume !(0 == ~T7_E~0); 1659476#L1071-1 assume !(0 == ~T8_E~0); 1660390#L1076-1 assume !(0 == ~T9_E~0); 1659366#L1081-1 assume !(0 == ~T10_E~0); 1659367#L1086-1 assume !(0 == ~E_M~0); 1659775#L1091-1 assume !(0 == ~E_1~0); 1660642#L1096-1 assume !(0 == ~E_2~0); 1660643#L1101-1 assume !(0 == ~E_3~0); 1659846#L1106-1 assume !(0 == ~E_4~0); 1659847#L1111-1 assume !(0 == ~E_5~0); 1660022#L1116-1 assume !(0 == ~E_6~0); 1660023#L1121-1 assume !(0 == ~E_7~0); 1659836#L1126-1 assume !(0 == ~E_8~0); 1659837#L1131-1 assume !(0 == ~E_9~0); 1660131#L1136-1 assume !(0 == ~E_10~0); 1660262#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1660442#L514 assume !(1 == ~m_pc~0); 1660443#L514-2 is_master_triggered_~__retres1~0#1 := 0; 1659852#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1659853#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1660521#L1285 assume !(0 != activate_threads_~tmp~1#1); 1660697#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1659494#L533 assume !(1 == ~t1_pc~0); 1659495#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1660040#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1659262#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1659263#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 1660286#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1660287#L552 assume !(1 == ~t2_pc~0); 1659982#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1659983#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1659840#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1659841#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 1659867#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1659868#L571 assume !(1 == ~t3_pc~0); 1660102#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1660186#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1659207#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1659208#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 1660027#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1659292#L590 assume !(1 == ~t4_pc~0); 1659293#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1660101#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1660826#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1660703#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 1660319#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1660024#L609 assume !(1 == ~t5_pc~0); 1660025#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1660695#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1660523#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1660524#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 1660016#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1660017#L628 assume !(1 == ~t6_pc~0); 1659941#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1659940#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1659813#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1659814#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 1660364#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1660365#L647 assume !(1 == ~t7_pc~0); 1660496#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1660539#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1660540#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1659848#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 1659849#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1660762#L666 assume !(1 == ~t8_pc~0); 1659633#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1659634#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1659866#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1660052#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 1659772#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1659773#L685 assume !(1 == ~t9_pc~0); 1660714#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1660553#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1659903#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1659802#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 1659803#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1660221#L704 assume !(1 == ~t10_pc~0); 1659794#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1659793#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1660071#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1659339#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 1659340#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1659593#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 1660345#L1154-2 assume !(1 == ~T1_E~0); 1659562#L1159-1 assume !(1 == ~T2_E~0); 1659563#L1164-1 assume !(1 == ~T3_E~0); 1660050#L1169-1 assume !(1 == ~T4_E~0); 1659904#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1659699#L1179-1 assume !(1 == ~T6_E~0); 1659547#L1184-1 assume !(1 == ~T7_E~0); 1659548#L1189-1 assume !(1 == ~T8_E~0); 1659631#L1194-1 assume !(1 == ~T9_E~0); 1659758#L1199-1 assume !(1 == ~T10_E~0); 1659713#L1204-1 assume !(1 == ~E_M~0); 1659714#L1209-1 assume !(1 == ~E_1~0); 1660312#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1660313#L1219-1 assume !(1 == ~E_3~0); 1660740#L1224-1 assume !(1 == ~E_4~0); 1660077#L1229-1 assume !(1 == ~E_5~0); 1659434#L1234-1 assume !(1 == ~E_6~0); 1659435#L1239-1 assume !(1 == ~E_7~0); 1659490#L1244-1 assume !(1 == ~E_8~0); 1659491#L1249-1 assume !(1 == ~E_9~0); 1678056#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1676098#L1259-1 assume { :end_inline_reset_delta_events } true; 1676096#L1565-2 [2023-11-29 01:35:38,959 INFO L750 eck$LassoCheckResult]: Loop: 1676096#L1565-2 assume !false; 1676094#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1676089#L1011-1 assume !false; 1676087#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1676085#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1676073#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1676071#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1676068#L866 assume !(0 != eval_~tmp~0#1); 1676069#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1682221#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1682219#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1682217#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1682215#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1682213#L1046-3 assume !(0 == ~T3_E~0); 1682211#L1051-3 assume !(0 == ~T4_E~0); 1682209#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1682207#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1682205#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1682203#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1682201#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1682199#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1682197#L1086-3 assume !(0 == ~E_M~0); 1682195#L1091-3 assume !(0 == ~E_1~0); 1682193#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1682191#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1682189#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1682187#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1682184#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1682181#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1682178#L1126-3 assume !(0 == ~E_8~0); 1682175#L1131-3 assume !(0 == ~E_9~0); 1682173#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1682171#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1682168#L514-36 assume !(1 == ~m_pc~0); 1682166#L514-38 is_master_triggered_~__retres1~0#1 := 0; 1682164#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1682162#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1682160#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1682158#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1682155#L533-36 assume !(1 == ~t1_pc~0); 1682153#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1682150#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1682148#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1682146#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1682145#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1682144#L552-36 assume !(1 == ~t2_pc~0); 1682142#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1682140#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1682138#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1682136#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1682134#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1682132#L571-36 assume !(1 == ~t3_pc~0); 1682130#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1682127#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1682125#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1682123#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1682121#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1682119#L590-36 assume !(1 == ~t4_pc~0); 1682117#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1682114#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1682111#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1682108#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 1682105#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1682103#L609-36 assume !(1 == ~t5_pc~0); 1682101#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1682099#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1682097#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1682095#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 1682093#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1682091#L628-36 assume !(1 == ~t6_pc~0); 1682089#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1682085#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1682082#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1682079#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1682076#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1676257#L647-36 assume !(1 == ~t7_pc~0); 1676255#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1676253#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1676251#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1676249#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1676247#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1676245#L666-36 assume !(1 == ~t8_pc~0); 1676243#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1676240#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1676237#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1676235#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1676233#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1676231#L685-36 assume !(1 == ~t9_pc~0); 1676229#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1676225#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1676223#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1676221#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1676219#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1676217#L704-36 assume !(1 == ~t10_pc~0); 1676215#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1676212#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1676209#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1676207#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1676205#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1676203#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1666156#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1676198#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1676196#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1676192#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1676190#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1676188#L1179-3 assume !(1 == ~T6_E~0); 1676186#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1676184#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1676181#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1676179#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1676177#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1676173#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1676171#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1676169#L1219-3 assume !(1 == ~E_3~0); 1676167#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1676165#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1676163#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1676161#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1676159#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1666109#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1676156#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1676154#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1676132#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1676130#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1676128#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1676127#L1584 assume !(0 == start_simulation_~tmp~3#1); 1676125#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1676121#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1676110#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1676108#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1676106#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1676104#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1676102#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1676099#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 1676096#L1565-2 [2023-11-29 01:35:38,960 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:38,960 INFO L85 PathProgramCache]: Analyzing trace with hash -1513086067, now seen corresponding path program 1 times [2023-11-29 01:35:38,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:38,960 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1839663705] [2023-11-29 01:35:38,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:38,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:38,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:39,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:39,041 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:39,042 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1839663705] [2023-11-29 01:35:39,042 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1839663705] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:39,042 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:39,042 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:35:39,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1553691148] [2023-11-29 01:35:39,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:39,043 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:39,043 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:39,043 INFO L85 PathProgramCache]: Analyzing trace with hash -362157884, now seen corresponding path program 1 times [2023-11-29 01:35:39,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:39,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [6526152] [2023-11-29 01:35:39,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:39,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:39,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:39,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:39,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:39,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [6526152] [2023-11-29 01:35:39,100 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [6526152] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:39,100 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:39,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:39,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1326128459] [2023-11-29 01:35:39,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:39,101 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:39,101 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:39,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:39,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:39,102 INFO L87 Difference]: Start difference. First operand 432464 states and 611920 transitions. cyclomatic complexity: 179712 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:40,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:40,782 INFO L93 Difference]: Finished difference Result 490877 states and 694473 transitions. [2023-11-29 01:35:40,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 490877 states and 694473 transitions. [2023-11-29 01:35:43,018 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 488096 [2023-11-29 01:35:44,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 490877 states to 490877 states and 694473 transitions. [2023-11-29 01:35:44,293 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 490877 [2023-11-29 01:35:44,450 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 490877 [2023-11-29 01:35:44,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 490877 states and 694473 transitions. [2023-11-29 01:35:44,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:44,583 INFO L218 hiAutomatonCegarLoop]: Abstraction has 490877 states and 694473 transitions. [2023-11-29 01:35:44,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 490877 states and 694473 transitions. [2023-11-29 01:35:46,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 490877 to 122056. [2023-11-29 01:35:46,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122056 states, 122056 states have (on average 1.4194631972209477) internal successors, (173254), 122055 states have internal predecessors, (173254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:47,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122056 states to 122056 states and 173254 transitions. [2023-11-29 01:35:47,159 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122056 states and 173254 transitions. [2023-11-29 01:35:47,159 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:47,159 INFO L428 stractBuchiCegarLoop]: Abstraction has 122056 states and 173254 transitions. [2023-11-29 01:35:47,160 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-29 01:35:47,160 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122056 states and 173254 transitions. [2023-11-29 01:35:47,793 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 121344 [2023-11-29 01:35:47,793 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:47,793 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:47,796 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:47,796 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:47,796 INFO L748 eck$LassoCheckResult]: Stem: 2582959#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 2582960#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 2583988#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2583989#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2584095#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 2583995#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2583915#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2583916#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2583976#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2582893#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2582894#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2583005#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2583256#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2583179#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2582892#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2582557#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2582558#L1036 assume !(0 == ~M_E~0); 2582653#L1036-2 assume !(0 == ~T1_E~0); 2583595#L1041-1 assume !(0 == ~T2_E~0); 2583596#L1046-1 assume !(0 == ~T3_E~0); 2582933#L1051-1 assume !(0 == ~T4_E~0); 2582934#L1056-1 assume !(0 == ~T5_E~0); 2583753#L1061-1 assume !(0 == ~T6_E~0); 2582823#L1066-1 assume !(0 == ~T7_E~0); 2582824#L1071-1 assume !(0 == ~T8_E~0); 2583734#L1076-1 assume !(0 == ~T9_E~0); 2582714#L1081-1 assume !(0 == ~T10_E~0); 2582715#L1086-1 assume !(0 == ~E_M~0); 2583122#L1091-1 assume !(0 == ~E_1~0); 2584004#L1096-1 assume !(0 == ~E_2~0); 2584005#L1101-1 assume !(0 == ~E_3~0); 2583193#L1106-1 assume !(0 == ~E_4~0); 2583194#L1111-1 assume !(0 == ~E_5~0); 2583370#L1116-1 assume !(0 == ~E_6~0); 2583371#L1121-1 assume !(0 == ~E_7~0); 2583183#L1126-1 assume !(0 == ~E_8~0); 2583184#L1131-1 assume !(0 == ~E_9~0); 2583475#L1136-1 assume !(0 == ~E_10~0); 2583609#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2583797#L514 assume !(1 == ~m_pc~0); 2583798#L514-2 is_master_triggered_~__retres1~0#1 := 0; 2583199#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2583200#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2583877#L1285 assume !(0 != activate_threads_~tmp~1#1); 2584059#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2582845#L533 assume !(1 == ~t1_pc~0); 2582846#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2583384#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2582612#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2582613#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 2583631#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2583632#L552 assume !(1 == ~t2_pc~0); 2583333#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2583334#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2583187#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2583188#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 2583221#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2583222#L571 assume !(1 == ~t3_pc~0); 2583445#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2583530#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2582555#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2582556#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 2583374#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2582639#L590 assume !(1 == ~t4_pc~0); 2582640#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2583443#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2582732#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2582733#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 2583669#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2583372#L609 assume !(1 == ~t5_pc~0); 2583373#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2584054#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2583878#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2583879#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 2583364#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2583365#L628 assume !(1 == ~t6_pc~0); 2583289#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2583288#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2583163#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2583164#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 2583706#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2583707#L647 assume !(1 == ~t7_pc~0); 2583856#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2583889#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2583890#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2583197#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 2583198#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2584115#L666 assume !(1 == ~t8_pc~0); 2582982#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2582983#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2583212#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2583399#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 2583119#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2583120#L685 assume !(1 == ~t9_pc~0); 2584070#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2583903#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2583249#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2583149#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 2583150#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2583562#L704 assume !(1 == ~t10_pc~0); 2583140#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2583139#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2583418#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2582687#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 2582688#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2582941#L1154 assume !(1 == ~M_E~0); 2583692#L1154-2 assume !(1 == ~T1_E~0); 2582912#L1159-1 assume !(1 == ~T2_E~0); 2582913#L1164-1 assume !(1 == ~T3_E~0); 2583394#L1169-1 assume !(1 == ~T4_E~0); 2583251#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2583050#L1179-1 assume !(1 == ~T6_E~0); 2582896#L1184-1 assume !(1 == ~T7_E~0); 2582897#L1189-1 assume !(1 == ~T8_E~0); 2582980#L1194-1 assume !(1 == ~T9_E~0); 2583106#L1199-1 assume !(1 == ~T10_E~0); 2583062#L1204-1 assume !(1 == ~E_M~0); 2583063#L1209-1 assume !(1 == ~E_1~0); 2583660#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2583661#L1219-1 assume !(1 == ~E_3~0); 2584103#L1224-1 assume !(1 == ~E_4~0); 2583423#L1229-1 assume !(1 == ~E_5~0); 2582782#L1234-1 assume !(1 == ~E_6~0); 2582783#L1239-1 assume !(1 == ~E_7~0); 2582838#L1244-1 assume !(1 == ~E_8~0); 2582839#L1249-1 assume !(1 == ~E_9~0); 2583745#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2582684#L1259-1 assume { :end_inline_reset_delta_events } true; 2582685#L1565-2 [2023-11-29 01:35:47,796 INFO L750 eck$LassoCheckResult]: Loop: 2582685#L1565-2 assume !false; 2624242#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2624236#L1011-1 assume !false; 2624235#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2624192#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2624179#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2624177#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2624174#L866 assume !(0 != eval_~tmp~0#1); 2624175#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2641584#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2641581#L1036-3 assume !(0 == ~M_E~0); 2641577#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2641573#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2641569#L1046-3 assume !(0 == ~T3_E~0); 2641565#L1051-3 assume !(0 == ~T4_E~0); 2641562#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2641559#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2641555#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2641552#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2641549#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2641546#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2641543#L1086-3 assume !(0 == ~E_M~0); 2641540#L1091-3 assume !(0 == ~E_1~0); 2641536#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2641533#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2641530#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2641528#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2641527#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2641525#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2641521#L1126-3 assume !(0 == ~E_8~0); 2641518#L1131-3 assume !(0 == ~E_9~0); 2641515#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2641513#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2641512#L514-36 assume !(1 == ~m_pc~0); 2641510#L514-38 is_master_triggered_~__retres1~0#1 := 0; 2641507#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2641503#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2641500#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2641497#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2641494#L533-36 assume 1 == ~t1_pc~0; 2641490#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2641486#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2641482#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2641479#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2641476#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2641473#L552-36 assume !(1 == ~t2_pc~0); 2641470#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2641466#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2641462#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2641459#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2641456#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2641453#L571-36 assume !(1 == ~t3_pc~0); 2641450#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2641446#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2641442#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2641439#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2641436#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2641433#L590-36 assume 1 == ~t4_pc~0; 2641429#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2641424#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2641418#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2641412#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2641407#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2641403#L609-36 assume !(1 == ~t5_pc~0); 2641400#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2641396#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2641391#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2641387#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 2641383#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2641379#L628-36 assume 1 == ~t6_pc~0; 2641374#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2641368#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2641294#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2641283#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2641278#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2615351#L647-36 assume !(1 == ~t7_pc~0); 2615349#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2615347#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2615345#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2615343#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2615341#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2615339#L666-36 assume !(1 == ~t8_pc~0); 2615337#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 2615335#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2615332#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2615330#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2615328#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2615326#L685-36 assume !(1 == ~t9_pc~0); 2615324#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 2615322#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2615321#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2615319#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2615317#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2615315#L704-36 assume !(1 == ~t10_pc~0); 2615313#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2615310#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2615308#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2615306#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2615304#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2615302#L1154-3 assume !(1 == ~M_E~0); 2594579#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2615299#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2615297#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2615295#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2615293#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2615291#L1179-3 assume !(1 == ~T6_E~0); 2615289#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2615287#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2615285#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2615283#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2615281#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2615279#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2615264#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2615259#L1219-3 assume !(1 == ~E_3~0); 2615254#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2615250#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2615247#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2615243#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2615239#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2615235#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2615233#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2615231#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2615089#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2615088#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2615075#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2594778#L1584 assume !(0 == start_simulation_~tmp~3#1); 2594779#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2624267#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2624256#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2624254#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2624253#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2624250#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2624249#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2624246#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 2582685#L1565-2 [2023-11-29 01:35:47,797 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:47,797 INFO L85 PathProgramCache]: Analyzing trace with hash 976442895, now seen corresponding path program 1 times [2023-11-29 01:35:47,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:47,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266831101] [2023-11-29 01:35:47,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:47,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:47,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:47,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:47,846 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:47,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266831101] [2023-11-29 01:35:47,846 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1266831101] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:47,846 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:47,846 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:47,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1388740264] [2023-11-29 01:35:47,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:47,847 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:47,847 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:47,847 INFO L85 PathProgramCache]: Analyzing trace with hash -1051302785, now seen corresponding path program 1 times [2023-11-29 01:35:47,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:47,847 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914076615] [2023-11-29 01:35:47,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:47,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:47,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:47,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:47,879 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:47,879 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [914076615] [2023-11-29 01:35:47,879 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [914076615] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:47,879 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:47,879 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:47,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [115613248] [2023-11-29 01:35:47,880 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:47,880 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:47,880 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:47,880 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:35:47,880 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:35:47,881 INFO L87 Difference]: Start difference. First operand 122056 states and 173254 transitions. cyclomatic complexity: 51230 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:48,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:48,290 INFO L93 Difference]: Finished difference Result 191994 states and 272143 transitions. [2023-11-29 01:35:48,291 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191994 states and 272143 transitions. [2023-11-29 01:35:49,336 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 190880 [2023-11-29 01:35:49,608 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191994 states to 191994 states and 272143 transitions. [2023-11-29 01:35:49,608 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191994 [2023-11-29 01:35:49,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191994 [2023-11-29 01:35:49,667 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191994 states and 272143 transitions. [2023-11-29 01:35:49,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:49,720 INFO L218 hiAutomatonCegarLoop]: Abstraction has 191994 states and 272143 transitions. [2023-11-29 01:35:49,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191994 states and 272143 transitions. [2023-11-29 01:35:50,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191994 to 134953. [2023-11-29 01:35:50,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134953 states, 134953 states have (on average 1.4218728001600558) internal successors, (191886), 134952 states have internal predecessors, (191886), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:51,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134953 states to 134953 states and 191886 transitions. [2023-11-29 01:35:51,108 INFO L240 hiAutomatonCegarLoop]: Abstraction has 134953 states and 191886 transitions. [2023-11-29 01:35:51,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:35:51,108 INFO L428 stractBuchiCegarLoop]: Abstraction has 134953 states and 191886 transitions. [2023-11-29 01:35:51,108 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-29 01:35:51,109 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134953 states and 191886 transitions. [2023-11-29 01:35:51,427 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 134144 [2023-11-29 01:35:51,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:51,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:51,430 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:51,430 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:51,430 INFO L748 eck$LassoCheckResult]: Stem: 2897015#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 2897016#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 2898018#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2898019#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2898129#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 2898024#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2897960#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2897961#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2898006#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2896951#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2896952#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2897060#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2897306#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2897229#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2896950#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2896617#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2896618#L1036 assume !(0 == ~M_E~0); 2896713#L1036-2 assume !(0 == ~T1_E~0); 2897653#L1041-1 assume !(0 == ~T2_E~0); 2897654#L1046-1 assume !(0 == ~T3_E~0); 2896988#L1051-1 assume !(0 == ~T4_E~0); 2896989#L1056-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2897806#L1061-1 assume !(0 == ~T6_E~0); 2896882#L1066-1 assume !(0 == ~T7_E~0); 2896883#L1071-1 assume !(0 == ~T8_E~0); 2897787#L1076-1 assume !(0 == ~T9_E~0); 2897788#L1081-1 assume !(0 == ~T10_E~0); 2897173#L1086-1 assume !(0 == ~E_M~0); 2897174#L1091-1 assume !(0 == ~E_1~0); 2898036#L1096-1 assume !(0 == ~E_2~0); 2898037#L1101-1 assume !(0 == ~E_3~0); 2897244#L1106-1 assume !(0 == ~E_4~0); 2897245#L1111-1 assume !(0 == ~E_5~0); 2897424#L1116-1 assume !(0 == ~E_6~0); 2897425#L1121-1 assume !(0 == ~E_7~0); 2897233#L1126-1 assume !(0 == ~E_8~0); 2897234#L1131-1 assume !(0 == ~E_9~0); 2897661#L1136-1 assume !(0 == ~E_10~0); 2897662#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2897842#L514 assume !(1 == ~m_pc~0); 2897843#L514-2 is_master_triggered_~__retres1~0#1 := 0; 2897250#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2897251#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2898097#L1285 assume !(0 != activate_threads_~tmp~1#1); 2898098#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2896901#L533 assume !(1 == ~t1_pc~0); 2896902#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2898249#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2896672#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2896673#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 2897685#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2897686#L552 assume !(1 == ~t2_pc~0); 2897384#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2897385#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2897237#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2897238#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 2897267#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2897268#L571 assume !(1 == ~t3_pc~0); 2897503#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2897733#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2897734#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2897695#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 2897696#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2896699#L590 assume !(1 == ~t4_pc~0); 2896700#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2897502#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2898241#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2898242#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 2897722#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2897723#L609 assume !(1 == ~t5_pc~0); 2898236#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2898237#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2897919#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2897920#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 2897417#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2897418#L628 assume !(1 == ~t6_pc~0); 2897339#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2897338#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2897213#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2897214#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 2897762#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2897763#L647 assume !(1 == ~t7_pc~0); 2898131#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2898132#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2898201#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2898202#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 2898173#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2898174#L666 assume !(1 == ~t8_pc~0); 2897037#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2897038#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2897844#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2897845#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 2897171#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2897172#L685 assume !(1 == ~t9_pc~0); 2898233#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2898234#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2897298#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2897299#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 2898245#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2897621#L704 assume !(1 == ~t10_pc~0); 2897622#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2898044#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2898045#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2896746#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 2896747#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2897747#L1154 assume !(1 == ~M_E~0); 2897748#L1154-2 assume !(1 == ~T1_E~0); 2896969#L1159-1 assume !(1 == ~T2_E~0); 2896970#L1164-1 assume !(1 == ~T3_E~0); 2897452#L1169-1 assume !(1 == ~T4_E~0); 2897453#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2897103#L1179-1 assume !(1 == ~T6_E~0); 2896954#L1184-1 assume !(1 == ~T7_E~0); 2896955#L1189-1 assume !(1 == ~T8_E~0); 2897035#L1194-1 assume !(1 == ~T9_E~0); 2897158#L1199-1 assume !(1 == ~T10_E~0); 2897115#L1204-1 assume !(1 == ~E_M~0); 2897116#L1209-1 assume !(1 == ~E_1~0); 2897713#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2897714#L1219-1 assume !(1 == ~E_3~0); 2898145#L1224-1 assume !(1 == ~E_4~0); 2897480#L1229-1 assume !(1 == ~E_5~0); 2896841#L1234-1 assume !(1 == ~E_6~0); 2896842#L1239-1 assume !(1 == ~E_7~0); 2896897#L1244-1 assume !(1 == ~E_8~0); 2896898#L1249-1 assume !(1 == ~E_9~0); 2897797#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2896741#L1259-1 assume { :end_inline_reset_delta_events } true; 2896742#L1565-2 [2023-11-29 01:35:51,430 INFO L750 eck$LassoCheckResult]: Loop: 2896742#L1565-2 assume !false; 2939082#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2939075#L1011-1 assume !false; 2939073#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2939071#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2939060#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2939057#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2939055#L866 assume !(0 != eval_~tmp~0#1); 2939056#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2942510#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2942508#L1036-3 assume !(0 == ~M_E~0); 2942506#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2942504#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2942501#L1046-3 assume !(0 == ~T3_E~0); 2942499#L1051-3 assume !(0 == ~T4_E~0); 2942496#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2942495#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2942494#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2942493#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2942492#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2942491#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2942490#L1086-3 assume !(0 == ~E_M~0); 2942489#L1091-3 assume !(0 == ~E_1~0); 2942488#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2942487#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2942486#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2942485#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2942484#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2942483#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2942482#L1126-3 assume !(0 == ~E_8~0); 2942481#L1131-3 assume !(0 == ~E_9~0); 2942480#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2942479#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2942478#L514-36 assume !(1 == ~m_pc~0); 2942477#L514-38 is_master_triggered_~__retres1~0#1 := 0; 2942476#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2942475#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2942474#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2942473#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2942472#L533-36 assume 1 == ~t1_pc~0; 2942470#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2942469#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2942468#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2942467#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2942466#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2936934#L552-36 assume !(1 == ~t2_pc~0); 2936935#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2936928#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2936929#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2936922#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2936923#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2936916#L571-36 assume !(1 == ~t3_pc~0); 2936917#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2936910#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2936911#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2936904#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2936905#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2936897#L590-36 assume 1 == ~t4_pc~0; 2936898#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2936987#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2936988#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2936882#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2936883#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2936878#L609-36 assume !(1 == ~t5_pc~0); 2936879#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2936874#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2936875#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2936870#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 2936871#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2936865#L628-36 assume 1 == ~t6_pc~0; 2936866#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2936860#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2936861#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2936845#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2936846#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2936840#L647-36 assume !(1 == ~t7_pc~0); 2936839#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2936838#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2936837#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2936836#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2936835#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2936834#L666-36 assume 1 == ~t8_pc~0; 2936832#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2936831#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2936830#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2936829#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2936828#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2936827#L685-36 assume !(1 == ~t9_pc~0); 2936826#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 2936825#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2936824#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2936823#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2936822#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2936821#L704-36 assume !(1 == ~t10_pc~0); 2936820#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2936818#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2936817#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2936816#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2936815#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2936814#L1154-3 assume !(1 == ~M_E~0); 2908966#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2936813#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2936812#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2936811#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2936809#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2936807#L1179-3 assume !(1 == ~T6_E~0); 2936805#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2936803#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2936801#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2936799#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2936797#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2936795#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2936793#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2936791#L1219-3 assume !(1 == ~E_3~0); 2936789#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2936787#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2936785#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2936783#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2936781#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2936779#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2936777#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2936775#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2936764#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2936763#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2936762#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2936760#L1584 assume !(0 == start_simulation_~tmp~3#1); 2936761#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2939107#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2939096#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2939094#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2939092#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2939089#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2939087#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2939085#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 2896742#L1565-2 [2023-11-29 01:35:51,431 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:51,431 INFO L85 PathProgramCache]: Analyzing trace with hash -1176663923, now seen corresponding path program 1 times [2023-11-29 01:35:51,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:51,431 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772143486] [2023-11-29 01:35:51,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:51,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:51,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:51,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:51,486 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:51,486 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1772143486] [2023-11-29 01:35:51,486 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1772143486] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:51,486 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:51,487 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:51,487 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974121411] [2023-11-29 01:35:51,487 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:51,487 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:51,488 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:51,488 INFO L85 PathProgramCache]: Analyzing trace with hash -777524290, now seen corresponding path program 1 times [2023-11-29 01:35:51,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:51,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227255776] [2023-11-29 01:35:51,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:51,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:51,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:51,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:51,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:51,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [227255776] [2023-11-29 01:35:51,531 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [227255776] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:51,532 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:51,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:51,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [939300357] [2023-11-29 01:35:51,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:51,532 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:51,533 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:51,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:35:51,533 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:35:51,533 INFO L87 Difference]: Start difference. First operand 134953 states and 191886 transitions. cyclomatic complexity: 56965 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:52,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:52,441 INFO L93 Difference]: Finished difference Result 179080 states and 253028 transitions. [2023-11-29 01:35:52,441 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179080 states and 253028 transitions. [2023-11-29 01:35:53,044 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 178080 [2023-11-29 01:35:53,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179080 states to 179080 states and 253028 transitions. [2023-11-29 01:35:53,344 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179080 [2023-11-29 01:35:53,406 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179080 [2023-11-29 01:35:53,407 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179080 states and 253028 transitions. [2023-11-29 01:35:53,458 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:53,458 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179080 states and 253028 transitions. [2023-11-29 01:35:53,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179080 states and 253028 transitions. [2023-11-29 01:35:54,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179080 to 122056. [2023-11-29 01:35:54,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122056 states, 122056 states have (on average 1.416300714426165) internal successors, (172868), 122055 states have internal predecessors, (172868), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:55,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122056 states to 122056 states and 172868 transitions. [2023-11-29 01:35:55,233 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122056 states and 172868 transitions. [2023-11-29 01:35:55,233 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:35:55,234 INFO L428 stractBuchiCegarLoop]: Abstraction has 122056 states and 172868 transitions. [2023-11-29 01:35:55,234 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-29 01:35:55,234 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122056 states and 172868 transitions. [2023-11-29 01:35:55,551 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 121344 [2023-11-29 01:35:55,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:55,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:55,553 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:55,553 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:55,553 INFO L748 eck$LassoCheckResult]: Stem: 3211067#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3211068#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3212047#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3212048#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3212147#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 3212052#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3211990#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3211991#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3212036#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3210999#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3211000#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3211115#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3211361#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3211283#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3210998#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3210660#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3210661#L1036 assume !(0 == ~M_E~0); 3210757#L1036-2 assume !(0 == ~T1_E~0); 3211694#L1041-1 assume !(0 == ~T2_E~0); 3211695#L1046-1 assume !(0 == ~T3_E~0); 3211041#L1051-1 assume !(0 == ~T4_E~0); 3211042#L1056-1 assume !(0 == ~T5_E~0); 3211843#L1061-1 assume !(0 == ~T6_E~0); 3210929#L1066-1 assume !(0 == ~T7_E~0); 3210930#L1071-1 assume !(0 == ~T8_E~0); 3211824#L1076-1 assume !(0 == ~T9_E~0); 3210818#L1081-1 assume !(0 == ~T10_E~0); 3210819#L1086-1 assume !(0 == ~E_M~0); 3211230#L1091-1 assume !(0 == ~E_1~0); 3212063#L1096-1 assume !(0 == ~E_2~0); 3212064#L1101-1 assume !(0 == ~E_3~0); 3211298#L1106-1 assume !(0 == ~E_4~0); 3211299#L1111-1 assume !(0 == ~E_5~0); 3211477#L1116-1 assume !(0 == ~E_6~0); 3211478#L1121-1 assume !(0 == ~E_7~0); 3211287#L1126-1 assume !(0 == ~E_8~0); 3211288#L1131-1 assume !(0 == ~E_9~0); 3211578#L1136-1 assume !(0 == ~E_10~0); 3211704#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3211883#L514 assume !(1 == ~m_pc~0); 3211884#L514-2 is_master_triggered_~__retres1~0#1 := 0; 3211304#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3211305#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3211955#L1285 assume !(0 != activate_threads_~tmp~1#1); 3212122#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3210951#L533 assume !(1 == ~t1_pc~0); 3210952#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3211491#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3210715#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3210716#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3211725#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3211726#L552 assume !(1 == ~t2_pc~0); 3211438#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3211439#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3211291#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3211292#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3211324#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3211325#L571 assume !(1 == ~t3_pc~0); 3211549#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3211630#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3210658#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3210659#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3211481#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3210743#L590 assume !(1 == ~t4_pc~0); 3210744#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3211547#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3212237#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3212125#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 3211761#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3211479#L609 assume !(1 == ~t5_pc~0); 3211480#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3212116#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3211956#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3211957#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3211471#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3211472#L628 assume !(1 == ~t6_pc~0); 3211394#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3211393#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3211267#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3211268#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3211798#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3211799#L647 assume !(1 == ~t7_pc~0); 3211936#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3211966#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3211967#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3211302#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3211303#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3212175#L666 assume !(1 == ~t8_pc~0); 3211092#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3211093#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3211317#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3211504#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3211227#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3211228#L685 assume !(1 == ~t9_pc~0); 3212133#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3211977#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3211355#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3211254#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3211255#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3211664#L704 assume !(1 == ~t10_pc~0); 3211246#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3211245#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3211522#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3210791#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 3210792#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3211049#L1154 assume !(1 == ~M_E~0); 3211785#L1154-2 assume !(1 == ~T1_E~0); 3211020#L1159-1 assume !(1 == ~T2_E~0); 3211021#L1164-1 assume !(1 == ~T3_E~0); 3211500#L1169-1 assume !(1 == ~T4_E~0); 3211356#L1174-1 assume !(1 == ~T5_E~0); 3211160#L1179-1 assume !(1 == ~T6_E~0); 3211004#L1184-1 assume !(1 == ~T7_E~0); 3211005#L1189-1 assume !(1 == ~T8_E~0); 3211090#L1194-1 assume !(1 == ~T9_E~0); 3211215#L1199-1 assume !(1 == ~T10_E~0); 3211172#L1204-1 assume !(1 == ~E_M~0); 3211173#L1209-1 assume !(1 == ~E_1~0); 3211752#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3211753#L1219-1 assume !(1 == ~E_3~0); 3212160#L1224-1 assume !(1 == ~E_4~0); 3211527#L1229-1 assume !(1 == ~E_5~0); 3210887#L1234-1 assume !(1 == ~E_6~0); 3210888#L1239-1 assume !(1 == ~E_7~0); 3210944#L1244-1 assume !(1 == ~E_8~0); 3210945#L1249-1 assume !(1 == ~E_9~0); 3211835#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3210788#L1259-1 assume { :end_inline_reset_delta_events } true; 3210789#L1565-2 [2023-11-29 01:35:55,554 INFO L750 eck$LassoCheckResult]: Loop: 3210789#L1565-2 assume !false; 3248451#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3248447#L1011-1 assume !false; 3248445#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3248443#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3248431#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3248429#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3248426#L866 assume !(0 != eval_~tmp~0#1); 3248427#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3308844#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3308842#L1036-3 assume !(0 == ~M_E~0); 3308840#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3308837#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3308835#L1046-3 assume !(0 == ~T3_E~0); 3308833#L1051-3 assume !(0 == ~T4_E~0); 3308831#L1056-3 assume !(0 == ~T5_E~0); 3308829#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3308827#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3308824#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3308822#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3308820#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3308818#L1086-3 assume !(0 == ~E_M~0); 3308816#L1091-3 assume !(0 == ~E_1~0); 3308815#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3308814#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3308810#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3308808#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3308806#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3308805#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3308802#L1126-3 assume !(0 == ~E_8~0); 3308801#L1131-3 assume !(0 == ~E_9~0); 3308800#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3308799#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3308798#L514-36 assume !(1 == ~m_pc~0); 3308797#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3308796#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3308795#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3308794#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3308793#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3308792#L533-36 assume !(1 == ~t1_pc~0); 3308790#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 3308788#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3308787#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3308786#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3308785#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3308784#L552-36 assume !(1 == ~t2_pc~0); 3308782#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3308781#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3308780#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3308779#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3308778#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3308777#L571-36 assume !(1 == ~t3_pc~0); 3308775#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3308772#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3308770#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3308768#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3308766#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3308764#L590-36 assume 1 == ~t4_pc~0; 3308762#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3308763#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3308783#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3308752#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3308750#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3308748#L609-36 assume !(1 == ~t5_pc~0); 3308746#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3308744#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3308742#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3308740#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 3308738#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3308736#L628-36 assume !(1 == ~t6_pc~0); 3308734#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 3308730#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3308728#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3308726#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3308724#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3308722#L647-36 assume !(1 == ~t7_pc~0); 3242175#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3308717#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3308715#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3308713#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3308710#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3308708#L666-36 assume !(1 == ~t8_pc~0); 3308706#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 3308702#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3308700#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3308698#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3308696#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3308694#L685-36 assume !(1 == ~t9_pc~0); 3308692#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3308689#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3308687#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3308685#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3308683#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3308681#L704-36 assume 1 == ~t10_pc~0; 3308678#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3308677#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3308674#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3308672#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3308670#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3308668#L1154-3 assume !(1 == ~M_E~0); 3232532#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3308665#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3308662#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3308660#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3308658#L1174-3 assume !(1 == ~T5_E~0); 3308656#L1179-3 assume !(1 == ~T6_E~0); 3308654#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3308652#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3308649#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3308647#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3308645#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3308643#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3308641#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3308639#L1219-3 assume !(1 == ~E_3~0); 3308636#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3308634#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3308632#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3308630#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3308628#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3308627#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3308626#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3289344#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3268863#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3268861#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3268859#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3234312#L1584 assume !(0 == start_simulation_~tmp~3#1); 3234313#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3249094#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3249081#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3249077#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3249072#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3249066#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3249060#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3249054#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 3210789#L1565-2 [2023-11-29 01:35:55,554 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:55,554 INFO L85 PathProgramCache]: Analyzing trace with hash -1017701811, now seen corresponding path program 1 times [2023-11-29 01:35:55,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:55,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [346392865] [2023-11-29 01:35:55,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:55,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:55,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:55,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:55,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:55,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [346392865] [2023-11-29 01:35:55,621 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [346392865] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:55,621 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:55,621 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:35:55,622 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1212154429] [2023-11-29 01:35:55,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:55,622 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:55,623 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:55,623 INFO L85 PathProgramCache]: Analyzing trace with hash -1575101760, now seen corresponding path program 1 times [2023-11-29 01:35:55,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:55,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1838117238] [2023-11-29 01:35:55,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:55,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:55,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:55,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:55,670 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:55,670 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1838117238] [2023-11-29 01:35:55,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1838117238] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:55,671 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:55,671 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:55,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [188312540] [2023-11-29 01:35:55,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:55,672 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:55,672 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:55,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:35:55,672 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:35:55,672 INFO L87 Difference]: Start difference. First operand 122056 states and 172868 transitions. cyclomatic complexity: 50844 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:56,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:56,038 INFO L93 Difference]: Finished difference Result 122056 states and 171906 transitions. [2023-11-29 01:35:56,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122056 states and 171906 transitions. [2023-11-29 01:35:56,778 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 121344 [2023-11-29 01:35:57,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122056 states to 122056 states and 171906 transitions. [2023-11-29 01:35:57,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122056 [2023-11-29 01:35:57,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122056 [2023-11-29 01:35:57,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122056 states and 171906 transitions. [2023-11-29 01:35:57,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:35:57,132 INFO L218 hiAutomatonCegarLoop]: Abstraction has 122056 states and 171906 transitions. [2023-11-29 01:35:57,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122056 states and 171906 transitions. [2023-11-29 01:35:57,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122056 to 122056. [2023-11-29 01:35:57,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122056 states, 122056 states have (on average 1.408419086321033) internal successors, (171906), 122055 states have internal predecessors, (171906), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:58,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122056 states to 122056 states and 171906 transitions. [2023-11-29 01:35:58,657 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122056 states and 171906 transitions. [2023-11-29 01:35:58,657 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:35:58,657 INFO L428 stractBuchiCegarLoop]: Abstraction has 122056 states and 171906 transitions. [2023-11-29 01:35:58,657 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-29 01:35:58,658 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122056 states and 171906 transitions. [2023-11-29 01:35:58,946 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 121344 [2023-11-29 01:35:58,947 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:35:58,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:35:58,948 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:58,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:35:58,949 INFO L748 eck$LassoCheckResult]: Stem: 3455179#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3455180#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3456178#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3456179#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3456289#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 3456184#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3456121#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3456122#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3456165#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3455114#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3455115#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3455225#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3455479#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3455403#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3455116#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3454779#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3454780#L1036 assume !(0 == ~M_E~0); 3454875#L1036-2 assume !(0 == ~T1_E~0); 3455817#L1041-1 assume !(0 == ~T2_E~0); 3455818#L1046-1 assume !(0 == ~T3_E~0); 3455155#L1051-1 assume !(0 == ~T4_E~0); 3455156#L1056-1 assume !(0 == ~T5_E~0); 3455970#L1061-1 assume !(0 == ~T6_E~0); 3455046#L1066-1 assume !(0 == ~T7_E~0); 3455047#L1071-1 assume !(0 == ~T8_E~0); 3455951#L1076-1 assume !(0 == ~T9_E~0); 3454935#L1081-1 assume !(0 == ~T10_E~0); 3454936#L1086-1 assume !(0 == ~E_M~0); 3455345#L1091-1 assume !(0 == ~E_1~0); 3456194#L1096-1 assume !(0 == ~E_2~0); 3456195#L1101-1 assume !(0 == ~E_3~0); 3455417#L1106-1 assume !(0 == ~E_4~0); 3455418#L1111-1 assume !(0 == ~E_5~0); 3455595#L1116-1 assume !(0 == ~E_6~0); 3455596#L1121-1 assume !(0 == ~E_7~0); 3455407#L1126-1 assume !(0 == ~E_8~0); 3455408#L1131-1 assume !(0 == ~E_9~0); 3455702#L1136-1 assume !(0 == ~E_10~0); 3455831#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3456012#L514 assume !(1 == ~m_pc~0); 3456013#L514-2 is_master_triggered_~__retres1~0#1 := 0; 3455423#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3455424#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3456084#L1285 assume !(0 != activate_threads_~tmp~1#1); 3456253#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3455067#L533 assume !(1 == ~t1_pc~0); 3455068#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3455610#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3454833#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3454834#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3455856#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3455857#L552 assume !(1 == ~t2_pc~0); 3455551#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3455552#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3455411#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3455412#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3455444#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3455445#L571 assume !(1 == ~t3_pc~0); 3455670#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3455755#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3454777#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3454778#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3455599#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3454861#L590 assume !(1 == ~t4_pc~0); 3454862#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3455668#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3456367#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3456254#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 3455889#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3455597#L609 assume !(1 == ~t5_pc~0); 3455598#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3456247#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3456085#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3456086#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3455589#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3455590#L628 assume !(1 == ~t6_pc~0); 3455511#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3455510#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3455387#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3455388#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3455932#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3455933#L647 assume !(1 == ~t7_pc~0); 3456065#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3456096#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3456097#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3455421#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3455422#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3456318#L666 assume !(1 == ~t8_pc~0); 3455203#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3455204#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3455436#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3455624#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3455342#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3455343#L685 assume !(1 == ~t9_pc~0); 3456266#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3456110#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3455473#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3455372#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3455373#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3455787#L704 assume !(1 == ~t10_pc~0); 3455364#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3455363#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3455642#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3454908#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 3454909#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3455163#L1154 assume !(1 == ~M_E~0); 3455918#L1154-2 assume !(1 == ~T1_E~0); 3455133#L1159-1 assume !(1 == ~T2_E~0); 3455134#L1164-1 assume !(1 == ~T3_E~0); 3455620#L1169-1 assume !(1 == ~T4_E~0); 3455474#L1174-1 assume !(1 == ~T5_E~0); 3455270#L1179-1 assume !(1 == ~T6_E~0); 3455118#L1184-1 assume !(1 == ~T7_E~0); 3455119#L1189-1 assume !(1 == ~T8_E~0); 3455201#L1194-1 assume !(1 == ~T9_E~0); 3455329#L1199-1 assume !(1 == ~T10_E~0); 3455284#L1204-1 assume !(1 == ~E_M~0); 3455285#L1209-1 assume !(1 == ~E_1~0); 3455883#L1214-1 assume !(1 == ~E_2~0); 3455884#L1219-1 assume !(1 == ~E_3~0); 3456300#L1224-1 assume !(1 == ~E_4~0); 3455647#L1229-1 assume !(1 == ~E_5~0); 3455004#L1234-1 assume !(1 == ~E_6~0); 3455005#L1239-1 assume !(1 == ~E_7~0); 3455061#L1244-1 assume !(1 == ~E_8~0); 3455062#L1249-1 assume !(1 == ~E_9~0); 3455963#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3454904#L1259-1 assume { :end_inline_reset_delta_events } true; 3454905#L1565-2 [2023-11-29 01:35:58,949 INFO L750 eck$LassoCheckResult]: Loop: 3454905#L1565-2 assume !false; 3479409#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3479404#L1011-1 assume !false; 3479402#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3479400#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3479387#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3479385#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3479382#L866 assume !(0 != eval_~tmp~0#1); 3479383#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3479692#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3479690#L1036-3 assume !(0 == ~M_E~0); 3479688#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3479686#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3479684#L1046-3 assume !(0 == ~T3_E~0); 3479681#L1051-3 assume !(0 == ~T4_E~0); 3479679#L1056-3 assume !(0 == ~T5_E~0); 3479677#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3479675#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3479673#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3479671#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3479670#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3479668#L1086-3 assume !(0 == ~E_M~0); 3479666#L1091-3 assume !(0 == ~E_1~0); 3479664#L1096-3 assume !(0 == ~E_2~0); 3479662#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3479660#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3479657#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3479655#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3479653#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3479651#L1126-3 assume !(0 == ~E_8~0); 3479649#L1131-3 assume !(0 == ~E_9~0); 3479647#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3479645#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3479643#L514-36 assume !(1 == ~m_pc~0); 3479641#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3479639#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3479637#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3479635#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3479632#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3479630#L533-36 assume !(1 == ~t1_pc~0); 3479628#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 3479625#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3479623#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3479619#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3479617#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3479615#L552-36 assume !(1 == ~t2_pc~0); 3479614#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3479611#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3479610#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3479609#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3479606#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3479602#L571-36 assume !(1 == ~t3_pc~0); 3479601#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3479600#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3479599#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3479598#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3479597#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3479596#L590-36 assume 1 == ~t4_pc~0; 3479595#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3479593#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3479591#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3479588#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3479587#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3479586#L609-36 assume !(1 == ~t5_pc~0); 3479585#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3479584#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3479582#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3479580#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 3479578#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3479576#L628-36 assume 1 == ~t6_pc~0; 3479573#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3479571#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3479569#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3479567#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3479565#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3479563#L647-36 assume !(1 == ~t7_pc~0); 3477817#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3479560#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3479558#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3479556#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3479554#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3479552#L666-36 assume 1 == ~t8_pc~0; 3479549#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3479547#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3479545#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3479543#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3479542#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3479541#L685-36 assume !(1 == ~t9_pc~0); 3479539#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3479538#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3479537#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3479536#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3479535#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3479533#L704-36 assume !(1 == ~t10_pc~0); 3479531#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3479528#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3479526#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3479524#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3479522#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3479520#L1154-3 assume !(1 == ~M_E~0); 3471535#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3479516#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3479514#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3479512#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3479510#L1174-3 assume !(1 == ~T5_E~0); 3479508#L1179-3 assume !(1 == ~T6_E~0); 3479506#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3479504#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3479502#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3479500#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3479498#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3479496#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3479494#L1214-3 assume !(1 == ~E_2~0); 3479492#L1219-3 assume !(1 == ~E_3~0); 3479490#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3479488#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3479486#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3479485#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3479481#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3479479#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3479477#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3479475#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3479450#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3479448#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3479446#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3479444#L1584 assume !(0 == start_simulation_~tmp~3#1); 3479442#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3479433#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3479422#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3479420#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3479418#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3479416#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3479414#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3479412#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 3454905#L1565-2 [2023-11-29 01:35:58,950 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:58,950 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728821, now seen corresponding path program 1 times [2023-11-29 01:35:58,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:58,950 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [360962806] [2023-11-29 01:35:58,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:58,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:58,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:59,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:59,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:59,011 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [360962806] [2023-11-29 01:35:59,011 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [360962806] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:59,011 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:59,011 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:59,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1813018385] [2023-11-29 01:35:59,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:59,012 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:35:59,012 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:35:59,012 INFO L85 PathProgramCache]: Analyzing trace with hash 702318271, now seen corresponding path program 1 times [2023-11-29 01:35:59,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:35:59,012 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329710457] [2023-11-29 01:35:59,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:35:59,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:35:59,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:35:59,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:35:59,042 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:35:59,042 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [329710457] [2023-11-29 01:35:59,042 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [329710457] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:35:59,042 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:35:59,042 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:35:59,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [321707484] [2023-11-29 01:35:59,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:35:59,043 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:35:59,043 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:35:59,043 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:35:59,043 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:35:59,043 INFO L87 Difference]: Start difference. First operand 122056 states and 171906 transitions. cyclomatic complexity: 49882 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:35:59,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:35:59,500 INFO L93 Difference]: Finished difference Result 189877 states and 265576 transitions. [2023-11-29 01:35:59,500 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 189877 states and 265576 transitions. [2023-11-29 01:36:00,384 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 188720 [2023-11-29 01:36:00,665 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 189877 states to 189877 states and 265576 transitions. [2023-11-29 01:36:00,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 189877 [2023-11-29 01:36:00,722 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 189877 [2023-11-29 01:36:00,722 INFO L73 IsDeterministic]: Start isDeterministic. Operand 189877 states and 265576 transitions. [2023-11-29 01:36:00,773 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:36:00,773 INFO L218 hiAutomatonCegarLoop]: Abstraction has 189877 states and 265576 transitions. [2023-11-29 01:36:00,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189877 states and 265576 transitions. [2023-11-29 01:36:01,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189877 to 134953. [2023-11-29 01:36:02,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134953 states, 134953 states have (on average 1.4028661830415032) internal successors, (189321), 134952 states have internal predecessors, (189321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:02,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134953 states to 134953 states and 189321 transitions. [2023-11-29 01:36:02,246 INFO L240 hiAutomatonCegarLoop]: Abstraction has 134953 states and 189321 transitions. [2023-11-29 01:36:02,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:36:02,247 INFO L428 stractBuchiCegarLoop]: Abstraction has 134953 states and 189321 transitions. [2023-11-29 01:36:02,247 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-29 01:36:02,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134953 states and 189321 transitions. [2023-11-29 01:36:02,565 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 134144 [2023-11-29 01:36:02,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:36:02,565 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:36:02,567 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:02,567 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:02,568 INFO L748 eck$LassoCheckResult]: Stem: 3767116#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3767117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3768124#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3768125#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3768232#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 3768132#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3768063#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3768064#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3768114#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3767053#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3767054#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3767161#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3767410#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3767333#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3767055#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3766722#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3766723#L1036 assume !(0 == ~M_E~0); 3766818#L1036-2 assume !(0 == ~T1_E~0); 3767751#L1041-1 assume !(0 == ~T2_E~0); 3767752#L1046-1 assume !(0 == ~T3_E~0); 3767093#L1051-1 assume !(0 == ~T4_E~0); 3767094#L1056-1 assume !(0 == ~T5_E~0); 3767906#L1061-1 assume !(0 == ~T6_E~0); 3766986#L1066-1 assume !(0 == ~T7_E~0); 3766987#L1071-1 assume !(0 == ~T8_E~0); 3767886#L1076-1 assume !(0 == ~T9_E~0); 3766878#L1081-1 assume !(0 == ~T10_E~0); 3766879#L1086-1 assume !(0 == ~E_M~0); 3767280#L1091-1 assume !(0 == ~E_1~0); 3768141#L1096-1 assume !(0 == ~E_2~0); 3768142#L1101-1 assume !(0 == ~E_3~0); 3767347#L1106-1 assume !(0 == ~E_4~0); 3767348#L1111-1 assume !(0 == ~E_5~0); 3767519#L1116-1 assume !(0 == ~E_6~0); 3767520#L1121-1 assume !(0 == ~E_7~0); 3767337#L1126-1 assume !(0 == ~E_8~0); 3767338#L1131-1 assume !(0 == ~E_9~0); 3767627#L1136-1 assume 0 == ~E_10~0;~E_10~0 := 1; 3767761#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3767941#L514 assume !(1 == ~m_pc~0); 3767942#L514-2 is_master_triggered_~__retres1~0#1 := 0; 3767353#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3767354#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3768022#L1285 assume !(0 != activate_threads_~tmp~1#1); 3768203#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3768402#L533 assume !(1 == ~t1_pc~0); 3767535#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3767534#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3767577#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3768400#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3768399#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3768398#L552 assume !(1 == ~t2_pc~0); 3768397#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3768396#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3767341#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3767342#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3767372#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3767373#L571 assume !(1 == ~t3_pc~0); 3767596#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3767683#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3766720#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3766721#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3767523#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3766804#L590 assume !(1 == ~t4_pc~0); 3766805#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3768287#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3766896#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3766897#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 3768204#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3768382#L609 assume !(1 == ~t5_pc~0); 3768381#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3768380#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3768379#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3768319#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3767514#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3767515#L628 assume !(1 == ~t6_pc~0); 3767442#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3767441#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3767317#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3767318#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3767859#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3767860#L647 assume !(1 == ~t7_pc~0); 3768002#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3768035#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3768036#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3767351#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3767352#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3768256#L666 assume !(1 == ~t8_pc~0); 3767138#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3767139#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3767366#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3767548#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3767277#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3767278#L685 assume !(1 == ~t9_pc~0); 3768353#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3768352#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3768351#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3768350#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3768349#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3768348#L704 assume !(1 == ~t10_pc~0); 3768346#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3768345#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3768344#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3768343#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 3768342#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3768341#L1154 assume !(1 == ~M_E~0); 3768340#L1154-2 assume !(1 == ~T1_E~0); 3768339#L1159-1 assume !(1 == ~T2_E~0); 3768338#L1164-1 assume !(1 == ~T3_E~0); 3768337#L1169-1 assume !(1 == ~T4_E~0); 3768336#L1174-1 assume !(1 == ~T5_E~0); 3768335#L1179-1 assume !(1 == ~T6_E~0); 3768334#L1184-1 assume !(1 == ~T7_E~0); 3768333#L1189-1 assume !(1 == ~T8_E~0); 3768332#L1194-1 assume !(1 == ~T9_E~0); 3768331#L1199-1 assume !(1 == ~T10_E~0); 3768330#L1204-1 assume !(1 == ~E_M~0); 3768329#L1209-1 assume !(1 == ~E_1~0); 3768328#L1214-1 assume !(1 == ~E_2~0); 3768327#L1219-1 assume !(1 == ~E_3~0); 3768326#L1224-1 assume !(1 == ~E_4~0); 3768325#L1229-1 assume !(1 == ~E_5~0); 3768324#L1234-1 assume !(1 == ~E_6~0); 3768323#L1239-1 assume !(1 == ~E_7~0); 3768322#L1244-1 assume !(1 == ~E_8~0); 3768321#L1249-1 assume !(1 == ~E_9~0); 3768320#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3766848#L1259-1 assume { :end_inline_reset_delta_events } true; 3766849#L1565-2 [2023-11-29 01:36:02,568 INFO L750 eck$LassoCheckResult]: Loop: 3766849#L1565-2 assume !false; 3799874#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3799870#L1011-1 assume !false; 3799869#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3799868#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3799857#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3799856#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3799853#L866 assume !(0 != eval_~tmp~0#1); 3799854#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3830744#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3830738#L1036-3 assume !(0 == ~M_E~0); 3830732#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3830726#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3830719#L1046-3 assume !(0 == ~T3_E~0); 3830712#L1051-3 assume !(0 == ~T4_E~0); 3830705#L1056-3 assume !(0 == ~T5_E~0); 3830699#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3830691#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3830684#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3830679#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3830673#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3830668#L1086-3 assume !(0 == ~E_M~0); 3830659#L1091-3 assume !(0 == ~E_1~0); 3830653#L1096-3 assume !(0 == ~E_2~0); 3830648#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3830639#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3830581#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3830573#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3830566#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3830558#L1126-3 assume !(0 == ~E_8~0); 3830144#L1131-3 assume !(0 == ~E_9~0); 3824117#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3824118#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3824099#L514-36 assume !(1 == ~m_pc~0); 3824100#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3824080#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3824081#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3824066#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3824067#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3824027#L533-36 assume 1 == ~t1_pc~0; 3824028#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3824013#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3824014#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3823998#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3823999#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3823961#L552-36 assume !(1 == ~t2_pc~0); 3823962#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3823611#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3823612#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3823607#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3823608#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3823603#L571-36 assume !(1 == ~t3_pc~0); 3823604#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3823558#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3823559#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3823541#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3823542#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3823524#L590-36 assume !(1 == ~t4_pc~0); 3823526#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3823510#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3823511#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3823494#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 3823493#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3823478#L609-36 assume !(1 == ~t5_pc~0); 3823479#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3823463#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3823464#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3823448#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 3823449#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3823431#L628-36 assume 1 == ~t6_pc~0; 3823432#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3823414#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3823415#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3823402#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3823403#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3822544#L647-36 assume !(1 == ~t7_pc~0); 3822541#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3822538#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3822535#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3822532#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3822528#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3822526#L666-36 assume 1 == ~t8_pc~0; 3822522#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3822519#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3822516#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3822513#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3822511#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3822507#L685-36 assume !(1 == ~t9_pc~0); 3822504#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3822501#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3822498#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3822495#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3822491#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3822487#L704-36 assume 1 == ~t10_pc~0; 3822483#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3822480#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3822477#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3822476#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3822475#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3822473#L1154-3 assume !(1 == ~M_E~0); 3788939#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3822468#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3822465#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3822462#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3822459#L1174-3 assume !(1 == ~T5_E~0); 3822456#L1179-3 assume !(1 == ~T6_E~0); 3822453#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3822450#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3822447#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3822444#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3822441#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3822438#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3822435#L1214-3 assume !(1 == ~E_2~0); 3822432#L1219-3 assume !(1 == ~E_3~0); 3822429#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3822426#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3822423#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3822420#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3822417#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3817005#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3817003#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3817001#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3816977#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3816976#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3816972#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3788752#L1584 assume !(0 == start_simulation_~tmp~3#1); 3788753#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3799905#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3799892#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3799888#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3799887#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3799886#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3799882#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3799878#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 3766849#L1565-2 [2023-11-29 01:36:02,568 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:02,568 INFO L85 PathProgramCache]: Analyzing trace with hash 529853193, now seen corresponding path program 1 times [2023-11-29 01:36:02,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:02,569 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359137265] [2023-11-29 01:36:02,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:02,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:02,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:36:02,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:36:02,620 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:36:02,620 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359137265] [2023-11-29 01:36:02,621 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359137265] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:36:02,621 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:36:02,621 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:36:02,621 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [200977930] [2023-11-29 01:36:02,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:36:02,621 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:36:02,622 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:02,622 INFO L85 PathProgramCache]: Analyzing trace with hash 1856180416, now seen corresponding path program 1 times [2023-11-29 01:36:02,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:02,622 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130473655] [2023-11-29 01:36:02,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:02,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:02,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:36:02,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:36:02,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:36:02,653 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1130473655] [2023-11-29 01:36:02,653 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1130473655] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:36:02,653 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:36:02,654 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:36:02,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778972162] [2023-11-29 01:36:02,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:36:02,654 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:36:02,654 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:36:02,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:36:02,655 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:36:02,655 INFO L87 Difference]: Start difference. First operand 134953 states and 189321 transitions. cyclomatic complexity: 54400 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:03,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:36:03,453 INFO L93 Difference]: Finished difference Result 176568 states and 246063 transitions. [2023-11-29 01:36:03,454 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176568 states and 246063 transitions. [2023-11-29 01:36:03,990 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 175536 [2023-11-29 01:36:04,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176568 states to 176568 states and 246063 transitions. [2023-11-29 01:36:04,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176568 [2023-11-29 01:36:04,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176568 [2023-11-29 01:36:04,409 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176568 states and 246063 transitions. [2023-11-29 01:36:04,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:36:04,472 INFO L218 hiAutomatonCegarLoop]: Abstraction has 176568 states and 246063 transitions. [2023-11-29 01:36:04,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176568 states and 246063 transitions. [2023-11-29 01:36:05,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176568 to 122056. [2023-11-29 01:36:05,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122056 states, 122056 states have (on average 1.3958101199449433) internal successors, (170367), 122055 states have internal predecessors, (170367), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:06,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122056 states to 122056 states and 170367 transitions. [2023-11-29 01:36:06,144 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122056 states and 170367 transitions. [2023-11-29 01:36:06,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:36:06,145 INFO L428 stractBuchiCegarLoop]: Abstraction has 122056 states and 170367 transitions. [2023-11-29 01:36:06,145 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-29 01:36:06,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122056 states and 170367 transitions. [2023-11-29 01:36:06,768 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 121344 [2023-11-29 01:36:06,768 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:36:06,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:36:06,770 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:06,770 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:06,770 INFO L748 eck$LassoCheckResult]: Stem: 4078651#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 4078652#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4079603#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4079604#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4079693#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4079609#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4079554#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4079555#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4079594#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4078585#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4078586#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4078695#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4078943#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4078867#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4078584#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4078253#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4078254#L1036 assume !(0 == ~M_E~0); 4078349#L1036-2 assume !(0 == ~T1_E~0); 4079267#L1041-1 assume !(0 == ~T2_E~0); 4079268#L1046-1 assume !(0 == ~T3_E~0); 4078627#L1051-1 assume !(0 == ~T4_E~0); 4078628#L1056-1 assume !(0 == ~T5_E~0); 4079413#L1061-1 assume !(0 == ~T6_E~0); 4078517#L1066-1 assume !(0 == ~T7_E~0); 4078518#L1071-1 assume !(0 == ~T8_E~0); 4079395#L1076-1 assume !(0 == ~T9_E~0); 4078410#L1081-1 assume !(0 == ~T10_E~0); 4078411#L1086-1 assume !(0 == ~E_M~0); 4078812#L1091-1 assume !(0 == ~E_1~0); 4079619#L1096-1 assume !(0 == ~E_2~0); 4079620#L1101-1 assume !(0 == ~E_3~0); 4078881#L1106-1 assume !(0 == ~E_4~0); 4078882#L1111-1 assume !(0 == ~E_5~0); 4079054#L1116-1 assume !(0 == ~E_6~0); 4079055#L1121-1 assume !(0 == ~E_7~0); 4078871#L1126-1 assume !(0 == ~E_8~0); 4078872#L1131-1 assume !(0 == ~E_9~0); 4079156#L1136-1 assume !(0 == ~E_10~0); 4079277#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4079448#L514 assume !(1 == ~m_pc~0); 4079449#L514-2 is_master_triggered_~__retres1~0#1 := 0; 4078887#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4078888#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4079517#L1285 assume !(0 != activate_threads_~tmp~1#1); 4079672#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4078538#L533 assume !(1 == ~t1_pc~0); 4078539#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4079069#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4078307#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4078308#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 4079300#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4079301#L552 assume !(1 == ~t2_pc~0); 4079018#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4079019#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4078875#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4078876#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 4078908#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4078909#L571 assume !(1 == ~t3_pc~0); 4079127#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4079209#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4078251#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4078252#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 4079059#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4078335#L590 assume !(1 == ~t4_pc~0); 4078336#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4079125#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4079750#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4079674#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 4079333#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4079056#L609 assume !(1 == ~t5_pc~0); 4079057#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4079667#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4079519#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4079520#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 4079049#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4079050#L628 assume !(1 == ~t6_pc~0); 4078976#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4078975#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4078851#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4078852#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 4079367#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4079368#L647 assume !(1 == ~t7_pc~0); 4079501#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4079530#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4079531#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4078885#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 4078886#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4079708#L666 assume !(1 == ~t8_pc~0); 4078673#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4078674#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4078900#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4079082#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 4078809#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4078810#L685 assume !(1 == ~t9_pc~0); 4079679#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4079542#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4078937#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4078838#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 4078839#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4079240#L704 assume !(1 == ~t10_pc~0); 4078830#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4079627#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4079100#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4078383#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 4078384#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4078634#L1154 assume !(1 == ~M_E~0); 4079354#L1154-2 assume !(1 == ~T1_E~0); 4078606#L1159-1 assume !(1 == ~T2_E~0); 4078607#L1164-1 assume !(1 == ~T3_E~0); 4079079#L1169-1 assume !(1 == ~T4_E~0); 4078938#L1174-1 assume !(1 == ~T5_E~0); 4078738#L1179-1 assume !(1 == ~T6_E~0); 4078590#L1184-1 assume !(1 == ~T7_E~0); 4078591#L1189-1 assume !(1 == ~T8_E~0); 4078671#L1194-1 assume !(1 == ~T9_E~0); 4078796#L1199-1 assume !(1 == ~T10_E~0); 4078752#L1204-1 assume !(1 == ~E_M~0); 4078753#L1209-1 assume !(1 == ~E_1~0); 4079326#L1214-1 assume !(1 == ~E_2~0); 4079327#L1219-1 assume !(1 == ~E_3~0); 4079699#L1224-1 assume !(1 == ~E_4~0); 4079104#L1229-1 assume !(1 == ~E_5~0); 4078477#L1234-1 assume !(1 == ~E_6~0); 4078478#L1239-1 assume !(1 == ~E_7~0); 4078531#L1244-1 assume !(1 == ~E_8~0); 4078532#L1249-1 assume !(1 == ~E_9~0); 4079406#L1254-1 assume !(1 == ~E_10~0); 4078380#L1259-1 assume { :end_inline_reset_delta_events } true; 4078381#L1565-2 [2023-11-29 01:36:06,770 INFO L750 eck$LassoCheckResult]: Loop: 4078381#L1565-2 assume !false; 4115690#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4115687#L1011-1 assume !false; 4115686#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4115685#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4115674#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4115673#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4115671#L866 assume !(0 != eval_~tmp~0#1); 4115672#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4136998#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4136996#L1036-3 assume !(0 == ~M_E~0); 4136994#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4136992#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4136990#L1046-3 assume !(0 == ~T3_E~0); 4136988#L1051-3 assume !(0 == ~T4_E~0); 4136986#L1056-3 assume !(0 == ~T5_E~0); 4136984#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4136982#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4136979#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4136977#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4136975#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4136973#L1086-3 assume !(0 == ~E_M~0); 4136971#L1091-3 assume !(0 == ~E_1~0); 4136969#L1096-3 assume !(0 == ~E_2~0); 4136967#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4136965#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4136963#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4136961#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4136959#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4136957#L1126-3 assume !(0 == ~E_8~0); 4136954#L1131-3 assume !(0 == ~E_9~0); 4136952#L1136-3 assume !(0 == ~E_10~0); 4136950#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4136948#L514-36 assume !(1 == ~m_pc~0); 4136946#L514-38 is_master_triggered_~__retres1~0#1 := 0; 4136942#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4136940#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4136938#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4136936#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4136935#L533-36 assume !(1 == ~t1_pc~0); 4136934#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 4136930#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4136928#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4136926#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4136923#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4136921#L552-36 assume !(1 == ~t2_pc~0); 4136919#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 4136917#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4136915#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4136913#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4136910#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4136908#L571-36 assume !(1 == ~t3_pc~0); 4136906#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 4136904#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4136902#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4136900#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4136897#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4136895#L590-36 assume !(1 == ~t4_pc~0); 4136893#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 4137130#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4137122#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4136883#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 4136880#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4136878#L609-36 assume !(1 == ~t5_pc~0); 4136875#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4136873#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4136871#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4136869#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 4136867#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4136863#L628-36 assume !(1 == ~t6_pc~0); 4136860#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 4136857#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4136854#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4136852#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4136832#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4135725#L647-36 assume !(1 == ~t7_pc~0); 4135720#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 4135716#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4135712#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4135708#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4135704#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4135700#L666-36 assume 1 == ~t8_pc~0; 4135695#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4135691#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4135687#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4135681#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4135677#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4135673#L685-36 assume !(1 == ~t9_pc~0); 4135669#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 4135665#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4135661#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4135657#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4135653#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4135649#L704-36 assume !(1 == ~t10_pc~0); 4135644#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 4135639#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4135634#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4135629#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4135626#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4135623#L1154-3 assume !(1 == ~M_E~0); 4088416#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4135617#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4135613#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4135610#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4135606#L1174-3 assume !(1 == ~T5_E~0); 4135602#L1179-3 assume !(1 == ~T6_E~0); 4135598#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4135594#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4135589#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4135585#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4135581#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4135577#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4135573#L1214-3 assume !(1 == ~E_2~0); 4135569#L1219-3 assume !(1 == ~E_3~0); 4135565#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4135563#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4135562#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4135561#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4135560#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4135559#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4135557#L1254-3 assume !(1 == ~E_10~0); 4135556#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4135517#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4135513#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4131326#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4088562#L1584 assume !(0 == start_simulation_~tmp~3#1); 4088563#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4115713#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4115700#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4115698#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 4115696#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4115695#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4115692#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4115691#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 4078381#L1565-2 [2023-11-29 01:36:06,771 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:06,771 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 1 times [2023-11-29 01:36:06,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:06,771 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481414793] [2023-11-29 01:36:06,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:06,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:06,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:06,780 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:36:06,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:06,844 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:36:06,844 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:06,845 INFO L85 PathProgramCache]: Analyzing trace with hash -1422939261, now seen corresponding path program 1 times [2023-11-29 01:36:06,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:06,845 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254559260] [2023-11-29 01:36:06,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:06,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:06,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:36:06,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:36:06,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:36:06,882 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254559260] [2023-11-29 01:36:06,882 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [254559260] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:36:06,882 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:36:06,882 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:36:06,883 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1565107216] [2023-11-29 01:36:06,883 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:36:06,883 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:36:06,883 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:36:06,884 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:36:06,884 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:36:06,884 INFO L87 Difference]: Start difference. First operand 122056 states and 170367 transitions. cyclomatic complexity: 48343 Second operand has 3 states, 3 states have (on average 44.666666666666664) internal successors, (134), 3 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:07,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:36:07,167 INFO L93 Difference]: Finished difference Result 134953 states and 188547 transitions. [2023-11-29 01:36:07,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 134953 states and 188547 transitions. [2023-11-29 01:36:07,599 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 134144 [2023-11-29 01:36:07,861 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 134953 states to 134953 states and 188547 transitions. [2023-11-29 01:36:07,861 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134953 [2023-11-29 01:36:07,921 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134953 [2023-11-29 01:36:07,921 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134953 states and 188547 transitions. [2023-11-29 01:36:07,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:36:07,974 INFO L218 hiAutomatonCegarLoop]: Abstraction has 134953 states and 188547 transitions. [2023-11-29 01:36:08,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134953 states and 188547 transitions. [2023-11-29 01:36:09,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134953 to 134953. [2023-11-29 01:36:09,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134953 states, 134953 states have (on average 1.3971308529636244) internal successors, (188547), 134952 states have internal predecessors, (188547), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:09,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134953 states to 134953 states and 188547 transitions. [2023-11-29 01:36:09,434 INFO L240 hiAutomatonCegarLoop]: Abstraction has 134953 states and 188547 transitions. [2023-11-29 01:36:09,435 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:36:09,435 INFO L428 stractBuchiCegarLoop]: Abstraction has 134953 states and 188547 transitions. [2023-11-29 01:36:09,435 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-29 01:36:09,435 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134953 states and 188547 transitions. [2023-11-29 01:36:10,078 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 134144 [2023-11-29 01:36:10,078 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:36:10,078 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:36:10,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:10,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:10,080 INFO L748 eck$LassoCheckResult]: Stem: 4335665#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 4335666#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4336676#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4336677#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4336785#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4336682#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4336619#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4336620#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4336665#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4335596#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4335597#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4335709#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4335961#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4335884#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4335598#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4335268#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4335269#L1036 assume !(0 == ~M_E~0); 4335362#L1036-2 assume !(0 == ~T1_E~0); 4336300#L1041-1 assume !(0 == ~T2_E~0); 4336301#L1046-1 assume !(0 == ~T3_E~0); 4335641#L1051-1 assume !(0 == ~T4_E~0); 4335642#L1056-1 assume !(0 == ~T5_E~0); 4336461#L1061-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4335531#L1066-1 assume !(0 == ~T7_E~0); 4335532#L1071-1 assume !(0 == ~T8_E~0); 4336442#L1076-1 assume !(0 == ~T9_E~0); 4336443#L1081-1 assume !(0 == ~T10_E~0); 4335825#L1086-1 assume !(0 == ~E_M~0); 4335826#L1091-1 assume !(0 == ~E_1~0); 4336690#L1096-1 assume !(0 == ~E_2~0); 4336691#L1101-1 assume !(0 == ~E_3~0); 4335898#L1106-1 assume !(0 == ~E_4~0); 4335899#L1111-1 assume !(0 == ~E_5~0); 4336919#L1116-1 assume !(0 == ~E_6~0); 4336737#L1121-1 assume !(0 == ~E_7~0); 4336738#L1126-1 assume !(0 == ~E_8~0); 4336181#L1131-1 assume !(0 == ~E_9~0); 4336182#L1136-1 assume !(0 == ~E_10~0); 4336918#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4336917#L514 assume !(1 == ~m_pc~0); 4336851#L514-2 is_master_triggered_~__retres1~0#1 := 0; 4336852#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4336916#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4336748#L1285 assume !(0 != activate_threads_~tmp~1#1); 4336749#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4335549#L533 assume !(1 == ~t1_pc~0); 4335550#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4336915#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4335319#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4335320#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 4336607#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4336913#L552 assume !(1 == ~t2_pc~0); 4336912#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4336911#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4335892#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4335893#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 4336650#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4336909#L571 assume !(1 == ~t3_pc~0); 4336238#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4336239#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4335266#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4335267#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 4336908#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4336907#L590 assume !(1 == ~t4_pc~0); 4336139#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4336905#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4336891#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4336892#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 4336371#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4336075#L609 assume !(1 == ~t5_pc~0); 4336076#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4336871#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4336900#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4336899#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 4336898#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4336840#L628 assume !(1 == ~t6_pc~0); 4335994#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4335993#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4335864#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4335865#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 4336895#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4336894#L647 assume !(1 == ~t7_pc~0); 4336787#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4336594#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4336595#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4336890#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 4336824#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4336825#L666 assume !(1 == ~t8_pc~0); 4336888#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4336887#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4336886#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4336885#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 4335822#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4335823#L685 assume !(1 == ~t9_pc~0); 4336884#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4336883#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4336882#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4335853#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 4335854#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4336674#L704 assume !(1 == ~t10_pc~0); 4336735#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4336736#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4336879#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4335396#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 4335397#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4335650#L1154 assume !(1 == ~M_E~0); 4336400#L1154-2 assume !(1 == ~T1_E~0); 4336876#L1159-1 assume !(1 == ~T2_E~0); 4336854#L1164-1 assume !(1 == ~T3_E~0); 4336098#L1169-1 assume !(1 == ~T4_E~0); 4335955#L1174-1 assume !(1 == ~T5_E~0); 4335753#L1179-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4335604#L1184-1 assume !(1 == ~T7_E~0); 4335605#L1189-1 assume !(1 == ~T8_E~0); 4335685#L1194-1 assume !(1 == ~T9_E~0); 4335808#L1199-1 assume !(1 == ~T10_E~0); 4335765#L1204-1 assume !(1 == ~E_M~0); 4335766#L1209-1 assume !(1 == ~E_1~0); 4336365#L1214-1 assume !(1 == ~E_2~0); 4336366#L1219-1 assume !(1 == ~E_3~0); 4336802#L1224-1 assume !(1 == ~E_4~0); 4336126#L1229-1 assume !(1 == ~E_5~0); 4335491#L1234-1 assume !(1 == ~E_6~0); 4335492#L1239-1 assume !(1 == ~E_7~0); 4335545#L1244-1 assume !(1 == ~E_8~0); 4335546#L1249-1 assume !(1 == ~E_9~0); 4336453#L1254-1 assume !(1 == ~E_10~0); 4335390#L1259-1 assume { :end_inline_reset_delta_events } true; 4335391#L1565-2 [2023-11-29 01:36:10,081 INFO L750 eck$LassoCheckResult]: Loop: 4335391#L1565-2 assume !false; 4347021#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4347016#L1011-1 assume !false; 4347014#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4347011#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4346999#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4346997#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4346994#L866 assume !(0 != eval_~tmp~0#1); 4346995#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4347326#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4347324#L1036-3 assume !(0 == ~M_E~0); 4347322#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4347320#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4347317#L1046-3 assume !(0 == ~T3_E~0); 4347315#L1051-3 assume !(0 == ~T4_E~0); 4347313#L1056-3 assume !(0 == ~T5_E~0); 4347310#L1061-3 assume !(0 == ~T6_E~0); 4347311#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4347943#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4347941#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4347939#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4347937#L1086-3 assume !(0 == ~E_M~0); 4347933#L1091-3 assume !(0 == ~E_1~0); 4347931#L1096-3 assume !(0 == ~E_2~0); 4347929#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4347928#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4347925#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4347924#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4347923#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4347920#L1126-3 assume !(0 == ~E_8~0); 4347916#L1131-3 assume !(0 == ~E_9~0); 4347915#L1136-3 assume !(0 == ~E_10~0); 4347914#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4347913#L514-36 assume !(1 == ~m_pc~0); 4347912#L514-38 is_master_triggered_~__retres1~0#1 := 0; 4347911#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4347910#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4347909#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4347908#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4347907#L533-36 assume !(1 == ~t1_pc~0); 4347906#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 4347904#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4347903#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4347902#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4347900#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4347898#L552-36 assume !(1 == ~t2_pc~0); 4347897#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 4347896#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4347895#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4347894#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4347893#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4347891#L571-36 assume !(1 == ~t3_pc~0); 4347890#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 4347889#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4347888#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4347886#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4347884#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4347882#L590-36 assume !(1 == ~t4_pc~0); 4347878#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 4347876#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4347874#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4347872#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 4347868#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4347866#L609-36 assume !(1 == ~t5_pc~0); 4347864#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4347862#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4347860#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4347858#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 4347856#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4347854#L628-36 assume 1 == ~t6_pc~0; 4347851#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4347849#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4347847#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4347845#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4347843#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4347841#L647-36 assume !(1 == ~t7_pc~0); 4346670#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 4347838#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4347836#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4347834#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4347831#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4347829#L666-36 assume 1 == ~t8_pc~0; 4347826#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4347823#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4347821#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4347819#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4347817#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4347815#L685-36 assume !(1 == ~t9_pc~0); 4347813#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 4347811#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4347809#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4347807#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4347804#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4347802#L704-36 assume !(1 == ~t10_pc~0); 4347799#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 4347797#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4347795#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4347793#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4347792#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4347790#L1154-3 assume !(1 == ~M_E~0); 4347335#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4347787#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4347785#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4347783#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4347780#L1174-3 assume !(1 == ~T5_E~0); 4347119#L1179-3 assume !(1 == ~T6_E~0); 4347116#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4347114#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4347112#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4347110#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4347108#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4347106#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4347103#L1214-3 assume !(1 == ~E_2~0); 4347101#L1219-3 assume !(1 == ~E_3~0); 4347099#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4347097#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4347095#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4347093#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4347091#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4347089#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4347087#L1254-3 assume !(1 == ~E_10~0); 4347085#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4347063#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4347061#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4347060#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4347057#L1584 assume !(0 == start_simulation_~tmp~3#1); 4347054#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4347045#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4347034#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4347032#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 4347030#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4347028#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4347026#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4347024#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 4335391#L1565-2 [2023-11-29 01:36:10,081 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:10,081 INFO L85 PathProgramCache]: Analyzing trace with hash 800900745, now seen corresponding path program 1 times [2023-11-29 01:36:10,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:10,081 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1058075506] [2023-11-29 01:36:10,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:10,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:10,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:36:10,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:36:10,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:36:10,136 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1058075506] [2023-11-29 01:36:10,137 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1058075506] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:36:10,137 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:36:10,137 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:36:10,137 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901575136] [2023-11-29 01:36:10,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:36:10,137 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:36:10,138 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:10,138 INFO L85 PathProgramCache]: Analyzing trace with hash 651909504, now seen corresponding path program 1 times [2023-11-29 01:36:10,138 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:10,138 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415156549] [2023-11-29 01:36:10,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:10,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:10,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:36:10,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:36:10,178 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:36:10,179 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415156549] [2023-11-29 01:36:10,179 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1415156549] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:36:10,179 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:36:10,179 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:36:10,179 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [722740761] [2023-11-29 01:36:10,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:36:10,179 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:36:10,180 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:36:10,180 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:36:10,180 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:36:10,180 INFO L87 Difference]: Start difference. First operand 134953 states and 188547 transitions. cyclomatic complexity: 53626 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:10,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:36:10,561 INFO L93 Difference]: Finished difference Result 179096 states and 249291 transitions. [2023-11-29 01:36:10,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179096 states and 249291 transitions. [2023-11-29 01:36:11,125 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 178080 [2023-11-29 01:36:11,911 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179096 states to 179096 states and 249291 transitions. [2023-11-29 01:36:11,911 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179096 [2023-11-29 01:36:11,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179096 [2023-11-29 01:36:11,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179096 states and 249291 transitions. [2023-11-29 01:36:12,053 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:36:12,053 INFO L218 hiAutomatonCegarLoop]: Abstraction has 179096 states and 249291 transitions. [2023-11-29 01:36:12,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179096 states and 249291 transitions. [2023-11-29 01:36:12,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179096 to 122056. [2023-11-29 01:36:12,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122056 states, 122056 states have (on average 1.3947532280264796) internal successors, (170238), 122055 states have internal predecessors, (170238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:13,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122056 states to 122056 states and 170238 transitions. [2023-11-29 01:36:13,518 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122056 states and 170238 transitions. [2023-11-29 01:36:13,518 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:36:13,519 INFO L428 stractBuchiCegarLoop]: Abstraction has 122056 states and 170238 transitions. [2023-11-29 01:36:13,519 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-29 01:36:13,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122056 states and 170238 transitions. [2023-11-29 01:36:13,776 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 121344 [2023-11-29 01:36:13,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:36:13,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:36:13,778 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:13,778 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:13,778 INFO L748 eck$LassoCheckResult]: Stem: 4649720#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 4649721#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4650705#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4650706#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4650795#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4650711#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4650649#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4650650#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4650695#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4649654#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4649655#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4649765#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4650013#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4649935#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4649656#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4649327#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4649328#L1036 assume !(0 == ~M_E~0); 4649422#L1036-2 assume !(0 == ~T1_E~0); 4650351#L1041-1 assume !(0 == ~T2_E~0); 4650352#L1046-1 assume !(0 == ~T3_E~0); 4649694#L1051-1 assume !(0 == ~T4_E~0); 4649695#L1056-1 assume !(0 == ~T5_E~0); 4650501#L1061-1 assume !(0 == ~T6_E~0); 4649590#L1066-1 assume !(0 == ~T7_E~0); 4649591#L1071-1 assume !(0 == ~T8_E~0); 4650485#L1076-1 assume !(0 == ~T9_E~0); 4649483#L1081-1 assume !(0 == ~T10_E~0); 4649484#L1086-1 assume !(0 == ~E_M~0); 4649881#L1091-1 assume !(0 == ~E_1~0); 4650722#L1096-1 assume !(0 == ~E_2~0); 4650723#L1101-1 assume !(0 == ~E_3~0); 4649949#L1106-1 assume !(0 == ~E_4~0); 4649950#L1111-1 assume !(0 == ~E_5~0); 4650133#L1116-1 assume !(0 == ~E_6~0); 4650134#L1121-1 assume !(0 == ~E_7~0); 4649939#L1126-1 assume !(0 == ~E_8~0); 4649940#L1131-1 assume !(0 == ~E_9~0); 4650234#L1136-1 assume !(0 == ~E_10~0); 4650361#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4650537#L514 assume !(1 == ~m_pc~0); 4650538#L514-2 is_master_triggered_~__retres1~0#1 := 0; 4649955#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4649956#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4650611#L1285 assume !(0 != activate_threads_~tmp~1#1); 4650771#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4649608#L533 assume !(1 == ~t1_pc~0); 4649609#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4650148#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4649378#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4649379#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 4650387#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4650388#L552 assume !(1 == ~t2_pc~0); 4650087#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4650088#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4649943#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4649944#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 4649969#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4649970#L571 assume !(1 == ~t3_pc~0); 4650204#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4650290#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4649325#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4649326#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 4650137#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4649408#L590 assume !(1 == ~t4_pc~0); 4649409#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4650203#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4649501#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4649502#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 4650417#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4650135#L609 assume !(1 == ~t5_pc~0); 4650136#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4650769#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4650614#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4650615#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 4650127#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4650128#L628 assume !(1 == ~t6_pc~0); 4650046#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4650045#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4649916#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4649917#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 4650460#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4650461#L647 assume !(1 == ~t7_pc~0); 4650594#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4650626#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4650627#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4649951#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 4649952#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4650825#L666 assume !(1 == ~t8_pc~0); 4649743#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4649744#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4649968#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4650159#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 4649878#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4649879#L685 assume !(1 == ~t9_pc~0); 4650780#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4650637#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4650007#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4649906#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 4649907#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4650320#L704 assume !(1 == ~t10_pc~0); 4649898#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4650729#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4650177#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4649456#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 4649457#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4649703#L1154 assume !(1 == ~M_E~0); 4650447#L1154-2 assume !(1 == ~T1_E~0); 4649675#L1159-1 assume !(1 == ~T2_E~0); 4649676#L1164-1 assume !(1 == ~T3_E~0); 4650157#L1169-1 assume !(1 == ~T4_E~0); 4650008#L1174-1 assume !(1 == ~T5_E~0); 4649805#L1179-1 assume !(1 == ~T6_E~0); 4649660#L1184-1 assume !(1 == ~T7_E~0); 4649661#L1189-1 assume !(1 == ~T8_E~0); 4649741#L1194-1 assume !(1 == ~T9_E~0); 4649863#L1199-1 assume !(1 == ~T10_E~0); 4649817#L1204-1 assume !(1 == ~E_M~0); 4649818#L1209-1 assume !(1 == ~E_1~0); 4650411#L1214-1 assume !(1 == ~E_2~0); 4650412#L1219-1 assume !(1 == ~E_3~0); 4650808#L1224-1 assume !(1 == ~E_4~0); 4650181#L1229-1 assume !(1 == ~E_5~0); 4649550#L1234-1 assume !(1 == ~E_6~0); 4649551#L1239-1 assume !(1 == ~E_7~0); 4649604#L1244-1 assume !(1 == ~E_8~0); 4649605#L1249-1 assume !(1 == ~E_9~0); 4650494#L1254-1 assume !(1 == ~E_10~0); 4649450#L1259-1 assume { :end_inline_reset_delta_events } true; 4649451#L1565-2 [2023-11-29 01:36:13,778 INFO L750 eck$LassoCheckResult]: Loop: 4649451#L1565-2 assume !false; 4748992#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4748988#L1011-1 assume !false; 4748984#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4748982#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4748970#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4748968#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4748964#L866 assume !(0 != eval_~tmp~0#1); 4748965#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4771138#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4771135#L1036-3 assume !(0 == ~M_E~0); 4771133#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4771131#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4771129#L1046-3 assume !(0 == ~T3_E~0); 4771127#L1051-3 assume !(0 == ~T4_E~0); 4771125#L1056-3 assume !(0 == ~T5_E~0); 4770557#L1061-3 assume !(0 == ~T6_E~0); 4770556#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4769216#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4769215#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4769214#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4769213#L1086-3 assume !(0 == ~E_M~0); 4769212#L1091-3 assume !(0 == ~E_1~0); 4769210#L1096-3 assume !(0 == ~E_2~0); 4769209#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4769208#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4769206#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4769205#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4769204#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4769203#L1126-3 assume !(0 == ~E_8~0); 4769202#L1131-3 assume !(0 == ~E_9~0); 4769201#L1136-3 assume !(0 == ~E_10~0); 4769200#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4769198#L514-36 assume !(1 == ~m_pc~0); 4769196#L514-38 is_master_triggered_~__retres1~0#1 := 0; 4769194#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4769192#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4769190#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4769188#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4769186#L533-36 assume 1 == ~t1_pc~0; 4769183#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4769181#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4769178#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4769176#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4769174#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4769172#L552-36 assume !(1 == ~t2_pc~0); 4769170#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 4769168#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4769167#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4769165#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4769163#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4769161#L571-36 assume !(1 == ~t3_pc~0); 4769159#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 4769157#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4769155#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4769153#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4769151#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4769149#L590-36 assume !(1 == ~t4_pc~0); 4769145#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 4769141#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4769139#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4769137#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 4769134#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4769131#L609-36 assume !(1 == ~t5_pc~0); 4769129#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4769127#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4769125#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4769123#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 4769121#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4769119#L628-36 assume 1 == ~t6_pc~0; 4769116#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4769114#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4769111#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4769109#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4769107#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4727175#L647-36 assume !(1 == ~t7_pc~0); 4727173#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 4727171#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4727169#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4727167#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4727166#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4727163#L666-36 assume 1 == ~t8_pc~0; 4727160#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4727158#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4727156#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4727154#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4727152#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4727150#L685-36 assume !(1 == ~t9_pc~0); 4727148#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 4727146#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4727144#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4727142#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4727140#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4727136#L704-36 assume !(1 == ~t10_pc~0); 4727133#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 4727131#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4727129#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4727126#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4727124#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4727122#L1154-3 assume !(1 == ~M_E~0); 4677640#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4727118#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4727116#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4727114#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4727112#L1174-3 assume !(1 == ~T5_E~0); 4727110#L1179-3 assume !(1 == ~T6_E~0); 4727107#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4727105#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4727103#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4727101#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4727099#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4727097#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4727096#L1214-3 assume !(1 == ~E_2~0); 4727094#L1219-3 assume !(1 == ~E_3~0); 4727092#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4727090#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4727088#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4727086#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4727083#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4727081#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4727079#L1254-3 assume !(1 == ~E_10~0); 4727077#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4727053#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4727051#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4727050#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4677809#L1584 assume !(0 == start_simulation_~tmp~3#1); 4677810#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4749017#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4749006#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4749004#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 4749002#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4749000#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4748997#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4748995#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 4649451#L1565-2 [2023-11-29 01:36:13,779 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:13,779 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 2 times [2023-11-29 01:36:13,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:13,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1262854603] [2023-11-29 01:36:13,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:13,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:13,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:13,788 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:36:13,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:13,828 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:36:13,829 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:13,829 INFO L85 PathProgramCache]: Analyzing trace with hash 778985983, now seen corresponding path program 1 times [2023-11-29 01:36:13,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:13,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428070963] [2023-11-29 01:36:13,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:13,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:13,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:36:13,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:36:13,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:36:13,870 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1428070963] [2023-11-29 01:36:13,870 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1428070963] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:36:13,870 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:36:13,870 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:36:13,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [460980573] [2023-11-29 01:36:13,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:36:13,871 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:36:13,871 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:36:13,871 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:36:13,872 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:36:13,872 INFO L87 Difference]: Start difference. First operand 122056 states and 170238 transitions. cyclomatic complexity: 48214 Second operand has 3 states, 3 states have (on average 44.666666666666664) internal successors, (134), 3 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:14,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:36:14,335 INFO L93 Difference]: Finished difference Result 185945 states and 258099 transitions. [2023-11-29 01:36:14,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 185945 states and 258099 transitions. [2023-11-29 01:36:15,256 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 184880 [2023-11-29 01:36:15,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 185945 states to 185945 states and 258099 transitions. [2023-11-29 01:36:15,565 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 185945 [2023-11-29 01:36:15,628 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 185945 [2023-11-29 01:36:15,629 INFO L73 IsDeterministic]: Start isDeterministic. Operand 185945 states and 258099 transitions. [2023-11-29 01:36:15,688 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:36:15,688 INFO L218 hiAutomatonCegarLoop]: Abstraction has 185945 states and 258099 transitions. [2023-11-29 01:36:15,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 185945 states and 258099 transitions. [2023-11-29 01:36:17,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 185945 to 185913. [2023-11-29 01:36:17,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 185913 states, 185913 states have (on average 1.3881062647582472) internal successors, (258067), 185912 states have internal predecessors, (258067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:17,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185913 states to 185913 states and 258067 transitions. [2023-11-29 01:36:17,395 INFO L240 hiAutomatonCegarLoop]: Abstraction has 185913 states and 258067 transitions. [2023-11-29 01:36:17,396 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:36:17,396 INFO L428 stractBuchiCegarLoop]: Abstraction has 185913 states and 258067 transitions. [2023-11-29 01:36:17,396 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-29 01:36:17,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 185913 states and 258067 transitions. [2023-11-29 01:36:18,203 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 184848 [2023-11-29 01:36:18,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:36:18,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:36:18,205 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:18,205 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:18,206 INFO L748 eck$LassoCheckResult]: Stem: 4957729#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 4957730#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4958733#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4958734#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4958849#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4958741#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4958675#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4958676#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4958718#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4957668#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4957669#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4957771#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4958019#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4957942#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4957667#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4957334#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4957335#L1036 assume !(0 == ~M_E~0); 4957431#L1036-2 assume !(0 == ~T1_E~0); 4958369#L1041-1 assume !(0 == ~T2_E~0); 4958370#L1046-1 assume !(0 == ~T3_E~0); 4957705#L1051-1 assume !(0 == ~T4_E~0); 4957706#L1056-1 assume !(0 == ~T5_E~0); 4958523#L1061-1 assume !(0 == ~T6_E~0); 4957601#L1066-1 assume !(0 == ~T7_E~0); 4957602#L1071-1 assume !(0 == ~T8_E~0); 4958504#L1076-1 assume !(0 == ~T9_E~0); 4957491#L1081-1 assume !(0 == ~T10_E~0); 4957492#L1086-1 assume !(0 == ~E_M~0); 4957887#L1091-1 assume !(0 == ~E_1~0); 4958751#L1096-1 assume !(0 == ~E_2~0); 4958752#L1101-1 assume 0 == ~E_3~0;~E_3~0 := 1; 4958909#L1106-1 assume !(0 == ~E_4~0); 4958282#L1111-1 assume !(0 == ~E_5~0); 4958137#L1116-1 assume !(0 == ~E_6~0); 4958138#L1121-1 assume !(0 == ~E_7~0); 4957946#L1126-1 assume !(0 == ~E_8~0); 4957947#L1131-1 assume !(0 == ~E_9~0); 4958378#L1136-1 assume !(0 == ~E_10~0); 4958379#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4958558#L514 assume !(1 == ~m_pc~0); 4958559#L514-2 is_master_triggered_~__retres1~0#1 := 0; 4957962#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4957963#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4958635#L1285 assume !(0 != activate_threads_~tmp~1#1); 4958865#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4958866#L533 assume !(1 == ~t1_pc~0); 4958155#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4958154#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4958197#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4959005#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 4958407#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4958408#L552 assume !(1 == ~t2_pc~0); 4958091#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4958092#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4958677#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4959001#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 4959000#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4958999#L571 assume !(1 == ~t3_pc~0); 4958305#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4958306#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4958451#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4958417#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 4958141#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4958142#L590 assume !(1 == ~t4_pc~0); 4958204#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4958995#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4958981#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4958982#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 4958437#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4958139#L609 assume !(1 == ~t5_pc~0); 4958140#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4958957#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4958991#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4958990#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 4958989#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4958913#L628 assume !(1 == ~t6_pc~0); 4958051#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4958050#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4957921#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4957922#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 4958985#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4958984#L647 assume !(1 == ~t7_pc~0); 4958851#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4958650#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4958651#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4957958#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 4957959#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4958882#L666 assume !(1 == ~t8_pc~0); 4957750#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4957751#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4957974#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4958166#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 4958167#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4958830#L685 assume !(1 == ~t9_pc~0); 4958831#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4958663#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4958011#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4958012#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 4958972#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4958340#L704 assume !(1 == ~t10_pc~0); 4957903#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4958759#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4958185#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4958186#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 4958969#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4958968#L1154 assume !(1 == ~M_E~0); 4958858#L1154-2 assume !(1 == ~T1_E~0); 4957688#L1159-1 assume !(1 == ~T2_E~0); 4957689#L1164-1 assume !(1 == ~T3_E~0); 4958966#L1169-1 assume !(1 == ~T4_E~0); 4958965#L1174-1 assume !(1 == ~T5_E~0); 4958963#L1179-1 assume !(1 == ~T6_E~0); 4958962#L1184-1 assume !(1 == ~T7_E~0); 4958961#L1189-1 assume !(1 == ~T8_E~0); 4957869#L1194-1 assume !(1 == ~T9_E~0); 4957870#L1199-1 assume !(1 == ~T10_E~0); 4958950#L1204-1 assume !(1 == ~E_M~0); 4958878#L1209-1 assume !(1 == ~E_1~0); 4958431#L1214-1 assume !(1 == ~E_2~0); 4958432#L1219-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4958862#L1224-1 assume !(1 == ~E_4~0); 4958190#L1229-1 assume !(1 == ~E_5~0); 4957560#L1234-1 assume !(1 == ~E_6~0); 4957561#L1239-1 assume !(1 == ~E_7~0); 4957615#L1244-1 assume !(1 == ~E_8~0); 4957616#L1249-1 assume !(1 == ~E_9~0); 4958515#L1254-1 assume !(1 == ~E_10~0); 4957459#L1259-1 assume { :end_inline_reset_delta_events } true; 4957460#L1565-2 [2023-11-29 01:36:18,206 INFO L750 eck$LassoCheckResult]: Loop: 4957460#L1565-2 assume !false; 4982010#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4982006#L1011-1 assume !false; 4982004#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4982001#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4981989#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4981987#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4981984#L866 assume !(0 != eval_~tmp~0#1); 4981985#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5048326#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5048322#L1036-3 assume !(0 == ~M_E~0); 5048318#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5048313#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5048309#L1046-3 assume !(0 == ~T3_E~0); 5048305#L1051-3 assume !(0 == ~T4_E~0); 5048301#L1056-3 assume !(0 == ~T5_E~0); 5048297#L1061-3 assume !(0 == ~T6_E~0); 5048293#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5048288#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5048284#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5048280#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5048276#L1086-3 assume !(0 == ~E_M~0); 5048274#L1091-3 assume !(0 == ~E_1~0); 5048271#L1096-3 assume !(0 == ~E_2~0); 5048267#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5048268#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5048272#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5048269#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5048265#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5048262#L1126-3 assume !(0 == ~E_8~0); 5048259#L1131-3 assume !(0 == ~E_9~0); 5048256#L1136-3 assume !(0 == ~E_10~0); 5048253#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5048250#L514-36 assume !(1 == ~m_pc~0); 5048247#L514-38 is_master_triggered_~__retres1~0#1 := 0; 5048244#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5048241#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5048238#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5048235#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5048232#L533-36 assume !(1 == ~t1_pc~0); 5048228#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 5048224#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5048221#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5048218#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5048214#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5048211#L552-36 assume !(1 == ~t2_pc~0); 5048208#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5048205#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5048202#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5048199#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5048196#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5048193#L571-36 assume !(1 == ~t3_pc~0); 5048189#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 5048186#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5048183#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5048180#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5048177#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5048174#L590-36 assume 1 == ~t4_pc~0; 5048169#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5048164#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5048159#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5048154#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5048150#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5048146#L609-36 assume !(1 == ~t5_pc~0); 5048142#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 5048138#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5048135#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5048132#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 5048129#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5048126#L628-36 assume 1 == ~t6_pc~0; 5048121#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5048118#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5048115#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5048112#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5042784#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4982181#L647-36 assume !(1 == ~t7_pc~0); 4982179#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 4982177#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4982175#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4982173#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4982171#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4982169#L666-36 assume 1 == ~t8_pc~0; 4982166#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4982164#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4982162#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4982160#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4982157#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4982155#L685-36 assume !(1 == ~t9_pc~0); 4982153#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 4982151#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4982149#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4982147#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4982143#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4982141#L704-36 assume !(1 == ~t10_pc~0); 4982138#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 4982136#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4982134#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4982132#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4982130#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4982128#L1154-3 assume !(1 == ~M_E~0); 4982124#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4982122#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4982120#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4982118#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4982116#L1174-3 assume !(1 == ~T5_E~0); 4982114#L1179-3 assume !(1 == ~T6_E~0); 4982113#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4982112#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4982110#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4982108#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4982106#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4982104#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4982102#L1214-3 assume !(1 == ~E_2~0); 4982100#L1219-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4982097#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4982094#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4982092#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4982090#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4982088#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4982086#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4982084#L1254-3 assume !(1 == ~E_10~0); 4982082#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4982052#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4982050#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4982048#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4982045#L1584 assume !(0 == start_simulation_~tmp~3#1); 4982042#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4982033#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4982022#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4982020#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 4982018#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4982016#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4982015#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4982013#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 4957460#L1565-2 [2023-11-29 01:36:18,207 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:18,207 INFO L85 PathProgramCache]: Analyzing trace with hash -184383863, now seen corresponding path program 1 times [2023-11-29 01:36:18,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:18,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187886812] [2023-11-29 01:36:18,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:18,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:18,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:36:18,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:36:18,274 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:36:18,274 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1187886812] [2023-11-29 01:36:18,274 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1187886812] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:36:18,274 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:36:18,274 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:36:18,275 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1722949919] [2023-11-29 01:36:18,275 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:36:18,275 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:36:18,275 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:18,276 INFO L85 PathProgramCache]: Analyzing trace with hash -312403269, now seen corresponding path program 1 times [2023-11-29 01:36:18,276 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:18,276 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487957614] [2023-11-29 01:36:18,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:18,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:18,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:36:18,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:36:18,350 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:36:18,350 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487957614] [2023-11-29 01:36:18,350 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487957614] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:36:18,351 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:36:18,351 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:36:18,351 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869650732] [2023-11-29 01:36:18,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:36:18,351 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:36:18,352 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:36:18,352 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:36:18,352 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:36:18,352 INFO L87 Difference]: Start difference. First operand 185913 states and 258067 transitions. cyclomatic complexity: 72186 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:18,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:36:18,961 INFO L93 Difference]: Finished difference Result 261328 states and 361787 transitions. [2023-11-29 01:36:18,961 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 261328 states and 361787 transitions. [2023-11-29 01:36:20,193 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 256144 [2023-11-29 01:36:20,677 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 261328 states to 261328 states and 361787 transitions. [2023-11-29 01:36:20,677 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 261328 [2023-11-29 01:36:20,792 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 261328 [2023-11-29 01:36:20,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 261328 states and 361787 transitions. [2023-11-29 01:36:20,881 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:36:20,881 INFO L218 hiAutomatonCegarLoop]: Abstraction has 261328 states and 361787 transitions. [2023-11-29 01:36:21,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 261328 states and 361787 transitions. [2023-11-29 01:36:22,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 261328 to 179448. [2023-11-29 01:36:22,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179448 states, 179448 states have (on average 1.386546520440462) internal successors, (248813), 179447 states have internal predecessors, (248813), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:22,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179448 states to 179448 states and 248813 transitions. [2023-11-29 01:36:22,749 INFO L240 hiAutomatonCegarLoop]: Abstraction has 179448 states and 248813 transitions. [2023-11-29 01:36:22,749 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:36:22,750 INFO L428 stractBuchiCegarLoop]: Abstraction has 179448 states and 248813 transitions. [2023-11-29 01:36:22,750 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-29 01:36:22,750 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179448 states and 248813 transitions. [2023-11-29 01:36:23,454 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 178480 [2023-11-29 01:36:23,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:36:23,454 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:36:23,455 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:23,456 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:23,456 INFO L748 eck$LassoCheckResult]: Stem: 5404983#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5404984#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 5405973#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5405974#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5406074#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 5405979#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5405914#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5405915#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5405961#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5404921#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5404922#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5405027#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5405279#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5405198#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5404920#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 5404587#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5404588#L1036 assume !(0 == ~M_E~0); 5404682#L1036-2 assume !(0 == ~T1_E~0); 5405612#L1041-1 assume !(0 == ~T2_E~0); 5405613#L1046-1 assume !(0 == ~T3_E~0); 5404961#L1051-1 assume !(0 == ~T4_E~0); 5404962#L1056-1 assume !(0 == ~T5_E~0); 5405769#L1061-1 assume !(0 == ~T6_E~0); 5404853#L1066-1 assume !(0 == ~T7_E~0); 5404854#L1071-1 assume !(0 == ~T8_E~0); 5405748#L1076-1 assume !(0 == ~T9_E~0); 5404744#L1081-1 assume !(0 == ~T10_E~0); 5404745#L1086-1 assume !(0 == ~E_M~0); 5405142#L1091-1 assume !(0 == ~E_1~0); 5405989#L1096-1 assume !(0 == ~E_2~0); 5405990#L1101-1 assume !(0 == ~E_3~0); 5405211#L1106-1 assume !(0 == ~E_4~0); 5405212#L1111-1 assume !(0 == ~E_5~0); 5405392#L1116-1 assume !(0 == ~E_6~0); 5405393#L1121-1 assume !(0 == ~E_7~0); 5405202#L1126-1 assume !(0 == ~E_8~0); 5405203#L1131-1 assume !(0 == ~E_9~0); 5405498#L1136-1 assume !(0 == ~E_10~0); 5405621#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5405807#L514 assume !(1 == ~m_pc~0); 5405808#L514-2 is_master_triggered_~__retres1~0#1 := 0; 5405217#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5405218#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5405875#L1285 assume !(0 != activate_threads_~tmp~1#1); 5406046#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5404874#L533 assume !(1 == ~t1_pc~0); 5404875#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5405406#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5404640#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5404641#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 5405644#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5405645#L552 assume !(1 == ~t2_pc~0); 5405354#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5405355#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5405206#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5405207#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 5405239#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5405240#L571 assume !(1 == ~t3_pc~0); 5405465#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5405550#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5404585#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5404586#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 5405396#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5404667#L590 assume !(1 == ~t4_pc~0); 5404668#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5405463#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5406153#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5406049#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 5405682#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5405394#L609 assume !(1 == ~t5_pc~0); 5405395#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5406041#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5405877#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5405878#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 5405387#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5405388#L628 assume !(1 == ~t6_pc~0); 5405312#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5405311#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5405182#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5405183#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 5405723#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5405724#L647 assume !(1 == ~t7_pc~0); 5405859#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5405889#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5405890#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5405215#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 5405216#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5406097#L666 assume !(1 == ~t8_pc~0); 5405005#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5405006#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5405229#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5405419#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 5405139#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5405140#L685 assume !(1 == ~t9_pc~0); 5406056#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5405902#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5405272#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5405166#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 5405167#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5405582#L704 assume !(1 == ~t10_pc~0); 5405158#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 5405996#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5405439#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5404717#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 5404718#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5404968#L1154 assume !(1 == ~M_E~0); 5405708#L1154-2 assume !(1 == ~T1_E~0); 5404940#L1159-1 assume !(1 == ~T2_E~0); 5404941#L1164-1 assume !(1 == ~T3_E~0); 5405416#L1169-1 assume !(1 == ~T4_E~0); 5405274#L1174-1 assume !(1 == ~T5_E~0); 5405069#L1179-1 assume !(1 == ~T6_E~0); 5404925#L1184-1 assume !(1 == ~T7_E~0); 5404926#L1189-1 assume !(1 == ~T8_E~0); 5405003#L1194-1 assume !(1 == ~T9_E~0); 5405125#L1199-1 assume !(1 == ~T10_E~0); 5405081#L1204-1 assume !(1 == ~E_M~0); 5405082#L1209-1 assume !(1 == ~E_1~0); 5405673#L1214-1 assume !(1 == ~E_2~0); 5405674#L1219-1 assume !(1 == ~E_3~0); 5406086#L1224-1 assume !(1 == ~E_4~0); 5405443#L1229-1 assume !(1 == ~E_5~0); 5404813#L1234-1 assume !(1 == ~E_6~0); 5404814#L1239-1 assume !(1 == ~E_7~0); 5404867#L1244-1 assume !(1 == ~E_8~0); 5404868#L1249-1 assume !(1 == ~E_9~0); 5405760#L1254-1 assume !(1 == ~E_10~0); 5404713#L1259-1 assume { :end_inline_reset_delta_events } true; 5404714#L1565-2 [2023-11-29 01:36:23,456 INFO L750 eck$LassoCheckResult]: Loop: 5404714#L1565-2 assume !false; 5454420#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5454414#L1011-1 assume !false; 5454412#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5454410#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5454398#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5454396#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5454393#L866 assume !(0 != eval_~tmp~0#1); 5454391#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5454389#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5454387#L1036-3 assume !(0 == ~M_E~0); 5454385#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5454383#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5454380#L1046-3 assume !(0 == ~T3_E~0); 5454378#L1051-3 assume !(0 == ~T4_E~0); 5454376#L1056-3 assume !(0 == ~T5_E~0); 5454374#L1061-3 assume !(0 == ~T6_E~0); 5454372#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5454370#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5454368#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5454367#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5454364#L1086-3 assume !(0 == ~E_M~0); 5454360#L1091-3 assume !(0 == ~E_1~0); 5454356#L1096-3 assume !(0 == ~E_2~0); 5454353#L1101-3 assume !(0 == ~E_3~0); 5454350#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5454349#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5454348#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5454347#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5454346#L1126-3 assume !(0 == ~E_8~0); 5454345#L1131-3 assume !(0 == ~E_9~0); 5454344#L1136-3 assume !(0 == ~E_10~0); 5454343#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5454342#L514-36 assume !(1 == ~m_pc~0); 5454341#L514-38 is_master_triggered_~__retres1~0#1 := 0; 5454340#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5454339#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5454337#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5454335#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5454334#L533-36 assume !(1 == ~t1_pc~0); 5454333#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 5454331#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5454330#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5454329#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5454327#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5454326#L552-36 assume !(1 == ~t2_pc~0); 5454325#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5454324#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5454323#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5454322#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5454320#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5454317#L571-36 assume !(1 == ~t3_pc~0); 5454315#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 5454313#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5454311#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5454309#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5454307#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5454304#L590-36 assume 1 == ~t4_pc~0; 5454302#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5454303#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5454328#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5454293#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5454291#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5454288#L609-36 assume !(1 == ~t5_pc~0); 5454286#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 5454284#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5454282#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5454280#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 5454278#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5454277#L628-36 assume !(1 == ~t6_pc~0); 5454274#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 5454271#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5454269#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5454267#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5454265#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5454263#L647-36 assume !(1 == ~t7_pc~0); 5452740#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 5454259#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5454257#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5454254#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5454252#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5454250#L666-36 assume !(1 == ~t8_pc~0); 5454247#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 5454244#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5454242#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5454240#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5454238#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5454236#L685-36 assume !(1 == ~t9_pc~0); 5454233#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 5454231#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5454229#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5454227#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5454225#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5454223#L704-36 assume !(1 == ~t10_pc~0); 5454221#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 5454219#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5454217#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5454215#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5454213#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5454211#L1154-3 assume !(1 == ~M_E~0); 5426710#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5454207#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5454205#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5454203#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5454201#L1174-3 assume !(1 == ~T5_E~0); 5454199#L1179-3 assume !(1 == ~T6_E~0); 5454197#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5454195#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5454193#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5454191#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5454189#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5454186#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5454184#L1214-3 assume !(1 == ~E_2~0); 5454182#L1219-3 assume !(1 == ~E_3~0); 5454180#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5454178#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5454176#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5454172#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5454170#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5454168#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5454167#L1254-3 assume !(1 == ~E_10~0); 5454164#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5453816#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5453812#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5453809#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 5426858#L1584 assume !(0 == start_simulation_~tmp~3#1); 5426859#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5454443#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5454433#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5454431#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 5454429#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5454427#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5454425#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 5454423#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 5404714#L1565-2 [2023-11-29 01:36:23,456 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:23,456 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 3 times [2023-11-29 01:36:23,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:23,457 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416823589] [2023-11-29 01:36:23,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:23,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:23,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:23,469 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:36:23,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:23,509 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:36:23,509 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:23,510 INFO L85 PathProgramCache]: Analyzing trace with hash -1917187843, now seen corresponding path program 1 times [2023-11-29 01:36:23,510 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:23,510 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2026939702] [2023-11-29 01:36:23,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:23,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:23,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:36:23,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:36:23,554 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:36:23,554 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2026939702] [2023-11-29 01:36:23,554 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2026939702] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:36:23,554 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:36:23,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:36:23,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [750006901] [2023-11-29 01:36:23,554 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:36:23,555 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:36:23,555 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:36:23,555 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 01:36:23,555 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 01:36:23,555 INFO L87 Difference]: Start difference. First operand 179448 states and 248813 transitions. cyclomatic complexity: 69397 Second operand has 5 states, 5 states have (on average 26.8) internal successors, (134), 5 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:24,383 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:36:24,383 INFO L93 Difference]: Finished difference Result 333448 states and 458525 transitions. [2023-11-29 01:36:24,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 333448 states and 458525 transitions. [2023-11-29 01:36:25,927 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 331648 [2023-11-29 01:36:26,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 333448 states to 333448 states and 458525 transitions. [2023-11-29 01:36:26,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 333448 [2023-11-29 01:36:27,063 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 333448 [2023-11-29 01:36:27,063 INFO L73 IsDeterministic]: Start isDeterministic. Operand 333448 states and 458525 transitions. [2023-11-29 01:36:27,138 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:36:27,139 INFO L218 hiAutomatonCegarLoop]: Abstraction has 333448 states and 458525 transitions. [2023-11-29 01:36:27,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 333448 states and 458525 transitions. [2023-11-29 01:36:28,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 333448 to 180024. [2023-11-29 01:36:28,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 180024 states, 180024 states have (on average 1.3853097364795806) internal successors, (249389), 180023 states have internal predecessors, (249389), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:29,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180024 states to 180024 states and 249389 transitions. [2023-11-29 01:36:29,190 INFO L240 hiAutomatonCegarLoop]: Abstraction has 180024 states and 249389 transitions. [2023-11-29 01:36:29,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-29 01:36:29,191 INFO L428 stractBuchiCegarLoop]: Abstraction has 180024 states and 249389 transitions. [2023-11-29 01:36:29,191 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2023-11-29 01:36:29,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 180024 states and 249389 transitions. [2023-11-29 01:36:29,612 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 179056 [2023-11-29 01:36:29,613 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:36:29,613 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:36:29,614 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:29,614 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:29,615 INFO L748 eck$LassoCheckResult]: Stem: 5917894#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5917895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 5918865#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5918866#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5918964#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 5918870#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5918811#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5918812#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5918853#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5917832#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5917833#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5917936#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5918184#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5918104#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5917831#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 5917500#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5917501#L1036 assume !(0 == ~M_E~0); 5917596#L1036-2 assume !(0 == ~T1_E~0); 5918519#L1041-1 assume !(0 == ~T2_E~0); 5918520#L1046-1 assume !(0 == ~T3_E~0); 5917871#L1051-1 assume !(0 == ~T4_E~0); 5917872#L1056-1 assume !(0 == ~T5_E~0); 5918673#L1061-1 assume !(0 == ~T6_E~0); 5917764#L1066-1 assume !(0 == ~T7_E~0); 5917765#L1071-1 assume !(0 == ~T8_E~0); 5918655#L1076-1 assume !(0 == ~T9_E~0); 5917656#L1081-1 assume !(0 == ~T10_E~0); 5917657#L1086-1 assume !(0 == ~E_M~0); 5918050#L1091-1 assume !(0 == ~E_1~0); 5918879#L1096-1 assume !(0 == ~E_2~0); 5918880#L1101-1 assume !(0 == ~E_3~0); 5918118#L1106-1 assume !(0 == ~E_4~0); 5918119#L1111-1 assume !(0 == ~E_5~0); 5918300#L1116-1 assume !(0 == ~E_6~0); 5918301#L1121-1 assume !(0 == ~E_7~0); 5918108#L1126-1 assume !(0 == ~E_8~0); 5918109#L1131-1 assume !(0 == ~E_9~0); 5918406#L1136-1 assume !(0 == ~E_10~0); 5918529#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5918710#L514 assume !(1 == ~m_pc~0); 5918711#L514-2 is_master_triggered_~__retres1~0#1 := 0; 5918124#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5918125#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5918777#L1285 assume !(0 != activate_threads_~tmp~1#1); 5918935#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5917785#L533 assume !(1 == ~t1_pc~0); 5917786#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5918315#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5917554#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5917555#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 5918553#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5918554#L552 assume !(1 == ~t2_pc~0); 5918261#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5918262#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5918112#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5918113#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 5918146#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5918147#L571 assume !(1 == ~t3_pc~0); 5918374#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5918460#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5917498#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5917499#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 5918304#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5917582#L590 assume !(1 == ~t4_pc~0); 5917583#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5918372#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5919032#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5918936#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 5918587#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5918302#L609 assume !(1 == ~t5_pc~0); 5918303#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5918930#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5918779#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5918780#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 5918295#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5918296#L628 assume !(1 == ~t6_pc~0); 5918217#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5918216#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5918088#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5918089#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 5918627#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5918628#L647 assume !(1 == ~t7_pc~0); 5918759#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5918790#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5918791#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5918122#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 5918123#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5918984#L666 assume !(1 == ~t8_pc~0); 5917915#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5917916#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5918136#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5918327#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 5918047#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5918048#L685 assume !(1 == ~t9_pc~0); 5918941#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5918801#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5918178#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5918074#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 5918075#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5918491#L704 assume !(1 == ~t10_pc~0); 5918065#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 5918886#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5918346#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5917629#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 5917630#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5917879#L1154 assume !(1 == ~M_E~0); 5918612#L1154-2 assume !(1 == ~T1_E~0); 5917850#L1159-1 assume !(1 == ~T2_E~0); 5917851#L1164-1 assume !(1 == ~T3_E~0); 5918324#L1169-1 assume !(1 == ~T4_E~0); 5918179#L1174-1 assume !(1 == ~T5_E~0); 5917977#L1179-1 assume !(1 == ~T6_E~0); 5917836#L1184-1 assume !(1 == ~T7_E~0); 5917837#L1189-1 assume !(1 == ~T8_E~0); 5917913#L1194-1 assume !(1 == ~T9_E~0); 5918034#L1199-1 assume !(1 == ~T10_E~0); 5917990#L1204-1 assume !(1 == ~E_M~0); 5917991#L1209-1 assume !(1 == ~E_1~0); 5918578#L1214-1 assume !(1 == ~E_2~0); 5918579#L1219-1 assume !(1 == ~E_3~0); 5918973#L1224-1 assume !(1 == ~E_4~0); 5918350#L1229-1 assume !(1 == ~E_5~0); 5917724#L1234-1 assume !(1 == ~E_6~0); 5917725#L1239-1 assume !(1 == ~E_7~0); 5917778#L1244-1 assume !(1 == ~E_8~0); 5917779#L1249-1 assume !(1 == ~E_9~0); 5918665#L1254-1 assume !(1 == ~E_10~0); 5917626#L1259-1 assume { :end_inline_reset_delta_events } true; 5917627#L1565-2 [2023-11-29 01:36:29,615 INFO L750 eck$LassoCheckResult]: Loop: 5917627#L1565-2 assume !false; 5945117#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5944682#L1011-1 assume !false; 5944680#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5944678#L794 assume !(0 == ~m_st~0); 5944672#L798 assume !(0 == ~t1_st~0); 5944673#L802 assume !(0 == ~t2_st~0); 5944676#L806 assume !(0 == ~t3_st~0); 5944670#L810 assume !(0 == ~t4_st~0); 5944671#L814 assume !(0 == ~t5_st~0); 5944675#L818 assume !(0 == ~t6_st~0); 5944668#L822 assume !(0 == ~t7_st~0); 5944669#L826 assume !(0 == ~t8_st~0); 5944674#L830 assume !(0 == ~t9_st~0); 5944677#L834 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 5944679#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5928903#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5928904#L866 assume !(0 != eval_~tmp~0#1); 5944665#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5944664#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5944663#L1036-3 assume !(0 == ~M_E~0); 5944662#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5944661#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5944660#L1046-3 assume !(0 == ~T3_E~0); 5944659#L1051-3 assume !(0 == ~T4_E~0); 5944658#L1056-3 assume !(0 == ~T5_E~0); 5944657#L1061-3 assume !(0 == ~T6_E~0); 5944656#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5944655#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5944654#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5944653#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5944652#L1086-3 assume !(0 == ~E_M~0); 5944651#L1091-3 assume !(0 == ~E_1~0); 5944650#L1096-3 assume !(0 == ~E_2~0); 5944649#L1101-3 assume !(0 == ~E_3~0); 5944648#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5944647#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5944646#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5944645#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5944644#L1126-3 assume !(0 == ~E_8~0); 5944643#L1131-3 assume !(0 == ~E_9~0); 5944642#L1136-3 assume !(0 == ~E_10~0); 5944641#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5944640#L514-36 assume !(1 == ~m_pc~0); 5944639#L514-38 is_master_triggered_~__retres1~0#1 := 0; 5944638#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5944637#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5944636#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5944635#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5944634#L533-36 assume 1 == ~t1_pc~0; 5944632#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5944631#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5944630#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5944629#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5944628#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5944627#L552-36 assume !(1 == ~t2_pc~0); 5944626#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5944625#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5944624#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5944623#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5944622#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5944621#L571-36 assume !(1 == ~t3_pc~0); 5944620#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 5944619#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5944618#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5944617#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5944616#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5944615#L590-36 assume !(1 == ~t4_pc~0); 5944614#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 5944612#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5944610#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5944608#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 5944606#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5944605#L609-36 assume !(1 == ~t5_pc~0); 5944604#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 5944603#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5944602#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5944601#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 5944600#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5944599#L628-36 assume !(1 == ~t6_pc~0); 5944598#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 5944596#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5944595#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5944594#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5944593#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5944592#L647-36 assume !(1 == ~t7_pc~0); 5930337#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 5944591#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5944590#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5944589#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5944588#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5944587#L666-36 assume !(1 == ~t8_pc~0); 5944586#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 5944584#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5944583#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5944582#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5944581#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5944580#L685-36 assume !(1 == ~t9_pc~0); 5944579#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 5944578#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5944577#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5944576#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5944575#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5944574#L704-36 assume !(1 == ~t10_pc~0); 5944572#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 5944571#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5944570#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5944569#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5944568#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5944567#L1154-3 assume !(1 == ~M_E~0); 5944125#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5944566#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5944565#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5944564#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5944563#L1174-3 assume !(1 == ~T5_E~0); 5944562#L1179-3 assume !(1 == ~T6_E~0); 5944561#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5944560#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5944559#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5944558#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5944557#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5944556#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5944555#L1214-3 assume !(1 == ~E_2~0); 5944554#L1219-3 assume !(1 == ~E_3~0); 5944553#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5944552#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5944551#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5944550#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5944549#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5944548#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5944547#L1254-3 assume !(1 == ~E_10~0); 5944546#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5944535#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5944534#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5944533#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 5944531#L1584 assume !(0 == start_simulation_~tmp~3#1); 5944532#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5945159#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5945147#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5945144#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 5945139#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5945136#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5945131#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 5945127#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 5917627#L1565-2 [2023-11-29 01:36:29,615 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:29,616 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 4 times [2023-11-29 01:36:29,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:29,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004522344] [2023-11-29 01:36:29,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:29,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:29,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:29,625 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:36:29,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:29,651 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:36:29,652 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:29,652 INFO L85 PathProgramCache]: Analyzing trace with hash -1988541308, now seen corresponding path program 1 times [2023-11-29 01:36:29,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:29,652 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223989822] [2023-11-29 01:36:29,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:29,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:29,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:36:29,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:36:29,730 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:36:29,730 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [223989822] [2023-11-29 01:36:29,730 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [223989822] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:36:29,730 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:36:29,730 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:36:29,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1798634319] [2023-11-29 01:36:29,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:36:29,731 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:36:29,731 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:36:29,731 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 01:36:29,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 01:36:29,732 INFO L87 Difference]: Start difference. First operand 180024 states and 249389 transitions. cyclomatic complexity: 69397 Second operand has 5 states, 5 states have (on average 28.8) internal successors, (144), 5 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:31,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:36:31,155 INFO L93 Difference]: Finished difference Result 340440 states and 465884 transitions. [2023-11-29 01:36:31,155 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 340440 states and 465884 transitions. [2023-11-29 01:36:32,913 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 339152 [2023-11-29 01:36:33,475 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 340440 states to 340440 states and 465884 transitions. [2023-11-29 01:36:33,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 340440 [2023-11-29 01:36:33,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 340440 [2023-11-29 01:36:33,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 340440 states and 465884 transitions. [2023-11-29 01:36:33,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:36:33,676 INFO L218 hiAutomatonCegarLoop]: Abstraction has 340440 states and 465884 transitions. [2023-11-29 01:36:33,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340440 states and 465884 transitions. [2023-11-29 01:36:35,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340440 to 182856. [2023-11-29 01:36:35,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 182856 states, 182856 states have (on average 1.3746992168701055) internal successors, (251372), 182855 states have internal predecessors, (251372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:36,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182856 states to 182856 states and 251372 transitions. [2023-11-29 01:36:36,177 INFO L240 hiAutomatonCegarLoop]: Abstraction has 182856 states and 251372 transitions. [2023-11-29 01:36:36,177 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 01:36:36,178 INFO L428 stractBuchiCegarLoop]: Abstraction has 182856 states and 251372 transitions. [2023-11-29 01:36:36,178 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2023-11-29 01:36:36,178 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 182856 states and 251372 transitions. [2023-11-29 01:36:36,547 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 181888 [2023-11-29 01:36:36,547 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:36:36,547 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:36:36,549 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:36,549 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:36,549 INFO L748 eck$LassoCheckResult]: Stem: 6438376#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 6438377#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6439414#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6439415#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6439543#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 6439423#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6439350#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6439351#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6439403#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6438311#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6438312#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 6438418#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 6438679#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 6438597#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6438310#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 6437976#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6437977#L1036 assume !(0 == ~M_E~0); 6438072#L1036-2 assume !(0 == ~T1_E~0); 6439021#L1041-1 assume !(0 == ~T2_E~0); 6439022#L1046-1 assume !(0 == ~T3_E~0); 6438352#L1051-1 assume !(0 == ~T4_E~0); 6438353#L1056-1 assume !(0 == ~T5_E~0); 6439188#L1061-1 assume !(0 == ~T6_E~0); 6438242#L1066-1 assume !(0 == ~T7_E~0); 6438243#L1071-1 assume !(0 == ~T8_E~0); 6439167#L1076-1 assume !(0 == ~T9_E~0); 6438133#L1081-1 assume !(0 == ~T10_E~0); 6438134#L1086-1 assume !(0 == ~E_M~0); 6438541#L1091-1 assume !(0 == ~E_1~0); 6439435#L1096-1 assume !(0 == ~E_2~0); 6439436#L1101-1 assume !(0 == ~E_3~0); 6438611#L1106-1 assume !(0 == ~E_4~0); 6438612#L1111-1 assume !(0 == ~E_5~0); 6438794#L1116-1 assume !(0 == ~E_6~0); 6438795#L1121-1 assume !(0 == ~E_7~0); 6438601#L1126-1 assume !(0 == ~E_8~0); 6438602#L1131-1 assume !(0 == ~E_9~0); 6438899#L1136-1 assume !(0 == ~E_10~0); 6439035#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6439228#L514 assume !(1 == ~m_pc~0); 6439229#L514-2 is_master_triggered_~__retres1~0#1 := 0; 6438617#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6438618#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6439306#L1285 assume !(0 != activate_threads_~tmp~1#1); 6439506#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6438263#L533 assume !(1 == ~t1_pc~0); 6438264#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6438809#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6438029#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6438030#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 6439062#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6439063#L552 assume !(1 == ~t2_pc~0); 6438757#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6438758#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6438605#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6438606#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 6438639#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6438640#L571 assume !(1 == ~t3_pc~0); 6438869#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6438954#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6437974#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6437975#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 6438798#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6438058#L590 assume !(1 == ~t4_pc~0); 6438059#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6438867#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6439663#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6439511#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 6439101#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6438796#L609 assume !(1 == ~t5_pc~0); 6438797#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6439500#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6439308#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6439309#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 6438789#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6438790#L628 assume !(1 == ~t6_pc~0); 6438714#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6438713#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6438581#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6438582#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 6439142#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6439143#L647 assume !(1 == ~t7_pc~0); 6439286#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6439320#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6439321#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6438615#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 6438616#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6439573#L666 assume !(1 == ~t8_pc~0); 6438397#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6438398#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6438629#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6438821#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 6438537#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6438538#L685 assume !(1 == ~t9_pc~0); 6439522#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6439337#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6438670#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6438564#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 6438565#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6438986#L704 assume !(1 == ~t10_pc~0); 6438556#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6439441#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6438841#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6438106#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 6438107#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6438359#L1154 assume !(1 == ~M_E~0); 6439127#L1154-2 assume !(1 == ~T1_E~0); 6438330#L1159-1 assume !(1 == ~T2_E~0); 6438331#L1164-1 assume !(1 == ~T3_E~0); 6438818#L1169-1 assume !(1 == ~T4_E~0); 6438673#L1174-1 assume !(1 == ~T5_E~0); 6438462#L1179-1 assume !(1 == ~T6_E~0); 6438315#L1184-1 assume !(1 == ~T7_E~0); 6438316#L1189-1 assume !(1 == ~T8_E~0); 6438395#L1194-1 assume !(1 == ~T9_E~0); 6438522#L1199-1 assume !(1 == ~T10_E~0); 6438476#L1204-1 assume !(1 == ~E_M~0); 6438477#L1209-1 assume !(1 == ~E_1~0); 6439092#L1214-1 assume !(1 == ~E_2~0); 6439093#L1219-1 assume !(1 == ~E_3~0); 6439554#L1224-1 assume !(1 == ~E_4~0); 6438845#L1229-1 assume !(1 == ~E_5~0); 6438202#L1234-1 assume !(1 == ~E_6~0); 6438203#L1239-1 assume !(1 == ~E_7~0); 6438256#L1244-1 assume !(1 == ~E_8~0); 6438257#L1249-1 assume !(1 == ~E_9~0); 6439178#L1254-1 assume !(1 == ~E_10~0); 6438102#L1259-1 assume { :end_inline_reset_delta_events } true; 6438103#L1565-2 [2023-11-29 01:36:36,549 INFO L750 eck$LassoCheckResult]: Loop: 6438103#L1565-2 assume !false; 6466118#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6466115#L1011-1 assume !false; 6466114#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6466113#L794 assume !(0 == ~m_st~0); 6466108#L798 assume !(0 == ~t1_st~0); 6466109#L802 assume !(0 == ~t2_st~0); 6466112#L806 assume !(0 == ~t3_st~0); 6466106#L810 assume !(0 == ~t4_st~0); 6466107#L814 assume !(0 == ~t5_st~0); 6466111#L818 assume !(0 == ~t6_st~0); 6466102#L822 assume !(0 == ~t7_st~0); 6466103#L826 assume !(0 == ~t8_st~0); 6466110#L830 assume !(0 == ~t9_st~0); 6466104#L834 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 6466105#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6467171#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6467170#L866 assume !(0 != eval_~tmp~0#1); 6467169#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6467168#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6467167#L1036-3 assume !(0 == ~M_E~0); 6467165#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6467163#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6467161#L1046-3 assume !(0 == ~T3_E~0); 6467159#L1051-3 assume !(0 == ~T4_E~0); 6467157#L1056-3 assume !(0 == ~T5_E~0); 6467155#L1061-3 assume !(0 == ~T6_E~0); 6467153#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6467150#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6467148#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6467146#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6467144#L1086-3 assume !(0 == ~E_M~0); 6467142#L1091-3 assume !(0 == ~E_1~0); 6467140#L1096-3 assume !(0 == ~E_2~0); 6467138#L1101-3 assume !(0 == ~E_3~0); 6467136#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6467134#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6467132#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6467130#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6467128#L1126-3 assume !(0 == ~E_8~0); 6467126#L1131-3 assume !(0 == ~E_9~0); 6467124#L1136-3 assume !(0 == ~E_10~0); 6467122#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6467120#L514-36 assume !(1 == ~m_pc~0); 6467118#L514-38 is_master_triggered_~__retres1~0#1 := 0; 6467114#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6467112#is_master_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6467110#L1285-36 assume !(0 != activate_threads_~tmp~1#1); 6467108#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6467107#L533-36 assume !(1 == ~t1_pc~0); 6467106#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 6467102#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6467100#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6467098#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6467096#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6467094#L552-36 assume !(1 == ~t2_pc~0); 6467092#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 6467090#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6467088#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6467086#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6467083#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6467081#L571-36 assume !(1 == ~t3_pc~0); 6467079#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 6467077#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6467075#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6467073#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6467072#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6467069#L590-36 assume 1 == ~t4_pc~0; 6467066#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6467064#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6467062#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6467021#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6467018#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6467016#L609-36 assume !(1 == ~t5_pc~0); 6467014#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 6467012#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6467010#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6466978#L1325-36 assume !(0 != activate_threads_~tmp___4~0#1); 6466972#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6466967#L628-36 assume 1 == ~t6_pc~0; 6466960#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6466953#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6466949#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6466946#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6466465#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6466311#L647-36 assume !(1 == ~t7_pc~0); 6466309#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 6466306#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6466303#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6466300#L1341-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6466297#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6466294#L666-36 assume 1 == ~t8_pc~0; 6466290#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6466286#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6466282#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6466279#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6466276#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6466273#L685-36 assume !(1 == ~t9_pc~0); 6466270#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 6466267#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6466264#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6466261#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6466258#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6466255#L704-36 assume !(1 == ~t10_pc~0); 6466250#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 6466246#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6466243#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6466240#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6466237#L1365-38 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6466234#L1154-3 assume !(1 == ~M_E~0); 6466230#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6466227#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6466225#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6466223#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6466221#L1174-3 assume !(1 == ~T5_E~0); 6466218#L1179-3 assume !(1 == ~T6_E~0); 6466215#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6466212#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6466209#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6466206#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6466203#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6466200#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6466196#L1214-3 assume !(1 == ~E_2~0); 6466193#L1219-3 assume !(1 == ~E_3~0); 6466190#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6466187#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6466184#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6466181#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6466178#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6466176#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6466175#L1254-3 assume !(1 == ~E_10~0); 6466174#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6466161#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 6466158#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6466155#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6466150#L1584 assume !(0 == start_simulation_~tmp~3#1); 6466148#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6466145#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 6466134#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6466132#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 6466130#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6466128#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6466124#stop_simulation_returnLabel#1 start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6466122#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 6438103#L1565-2 [2023-11-29 01:36:36,549 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:36,549 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 5 times [2023-11-29 01:36:36,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:36,550 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1754489796] [2023-11-29 01:36:36,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:36,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:36,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:36,564 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:36:36,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:36,604 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:36:36,604 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:36,605 INFO L85 PathProgramCache]: Analyzing trace with hash -1160021950, now seen corresponding path program 1 times [2023-11-29 01:36:36,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:36,605 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [99617990] [2023-11-29 01:36:36,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:36,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:36,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:36:36,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:36:36,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:36:36,651 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [99617990] [2023-11-29 01:36:36,651 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [99617990] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:36:36,651 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:36:36,652 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:36:36,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1863272495] [2023-11-29 01:36:36,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:36:36,652 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:36:36,652 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:36:36,653 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:36:36,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:36:36,653 INFO L87 Difference]: Start difference. First operand 182856 states and 251372 transitions. cyclomatic complexity: 68548 Second operand has 3 states, 3 states have (on average 48.0) internal successors, (144), 3 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:37,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:36:37,756 INFO L93 Difference]: Finished difference Result 304318 states and 414718 transitions. [2023-11-29 01:36:37,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 304318 states and 414718 transitions. [2023-11-29 01:36:38,716 INFO L131 ngComponentsAnalysis]: Automaton has 52 accepting balls. 302964 [2023-11-29 01:36:39,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 304318 states to 304318 states and 414718 transitions. [2023-11-29 01:36:39,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 304318 [2023-11-29 01:36:39,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 304318 [2023-11-29 01:36:39,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 304318 states and 414718 transitions. [2023-11-29 01:36:39,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:36:39,944 INFO L218 hiAutomatonCegarLoop]: Abstraction has 304318 states and 414718 transitions. [2023-11-29 01:36:40,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304318 states and 414718 transitions. [2023-11-29 01:36:41,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304318 to 297342. [2023-11-29 01:36:42,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 297342 states, 297342 states have (on average 1.3637024032931775) internal successors, (405486), 297341 states have internal predecessors, (405486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:43,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 297342 states to 297342 states and 405486 transitions. [2023-11-29 01:36:43,044 INFO L240 hiAutomatonCegarLoop]: Abstraction has 297342 states and 405486 transitions. [2023-11-29 01:36:43,044 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:36:43,045 INFO L428 stractBuchiCegarLoop]: Abstraction has 297342 states and 405486 transitions. [2023-11-29 01:36:43,045 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2023-11-29 01:36:43,045 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 297342 states and 405486 transitions. [2023-11-29 01:36:43,688 INFO L131 ngComponentsAnalysis]: Automaton has 52 accepting balls. 295988 [2023-11-29 01:36:43,688 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:36:43,688 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:36:43,689 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:43,689 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:43,689 INFO L748 eck$LassoCheckResult]: Stem: 6925547#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 6925548#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6926580#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6926581#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6926695#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 6926587#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6926515#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6926516#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6926566#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6925489#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6925490#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 6925591#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 6925844#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 6925765#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6925488#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 6925156#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6925157#L1036 assume !(0 == ~M_E~0); 6925253#L1036-2 assume !(0 == ~T1_E~0); 6926183#L1041-1 assume !(0 == ~T2_E~0); 6926184#L1046-1 assume !(0 == ~T3_E~0); 6925525#L1051-1 assume !(0 == ~T4_E~0); 6925526#L1056-1 assume !(0 == ~T5_E~0); 6926342#L1061-1 assume !(0 == ~T6_E~0); 6925421#L1066-1 assume !(0 == ~T7_E~0); 6925422#L1071-1 assume !(0 == ~T8_E~0); 6926323#L1076-1 assume !(0 == ~T9_E~0); 6925313#L1081-1 assume !(0 == ~T10_E~0); 6925314#L1086-1 assume !(0 == ~E_M~0); 6925710#L1091-1 assume !(0 == ~E_1~0); 6926599#L1096-1 assume !(0 == ~E_2~0); 6926600#L1101-1 assume !(0 == ~E_3~0); 6925779#L1106-1 assume !(0 == ~E_4~0); 6925780#L1111-1 assume !(0 == ~E_5~0); 6925958#L1116-1 assume !(0 == ~E_6~0); 6925959#L1121-1 assume !(0 == ~E_7~0); 6925769#L1126-1 assume !(0 == ~E_8~0); 6925770#L1131-1 assume !(0 == ~E_9~0); 6926066#L1136-1 assume !(0 == ~E_10~0); 6926193#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6926384#L514 assume !(1 == ~m_pc~0); 6926385#L514-2 is_master_triggered_~__retres1~0#1 := 0; 6925785#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6925786#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6926470#L1285 assume !(0 != activate_threads_~tmp~1#1); 6926660#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6925441#L533 assume !(1 == ~t1_pc~0); 6925442#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6925975#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6925210#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6925211#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 6926219#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6926220#L552 assume !(1 == ~t2_pc~0); 6925919#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6925920#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6925773#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6925774#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 6925806#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6925807#L571 assume !(1 == ~t3_pc~0); 6926036#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6926118#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6925154#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6925155#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 6925962#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6925239#L590 assume !(1 == ~t4_pc~0); 6925240#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6926034#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6926800#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6926665#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 6926255#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6925960#L609 assume !(1 == ~t5_pc~0); 6925961#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6926654#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6926473#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6926474#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 6925953#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6925954#L628 assume !(1 == ~t6_pc~0); 6925876#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6925875#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6925748#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6925749#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 6926299#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6926300#L647 assume !(1 == ~t7_pc~0); 6926445#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6926485#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6926486#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6925783#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 6925784#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6926733#L666 assume !(1 == ~t8_pc~0); 6925568#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6925569#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6925799#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6925987#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 6925707#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6925708#L685 assume !(1 == ~t9_pc~0); 6926676#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6926499#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6925837#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6925735#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 6925736#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6926150#L704 assume !(1 == ~t10_pc~0); 6925726#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6926606#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6926006#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6925286#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 6925287#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6925532#L1154 assume !(1 == ~M_E~0); 6926282#L1154-2 assume !(1 == ~T1_E~0); 6925506#L1159-1 assume !(1 == ~T2_E~0); 6925507#L1164-1 assume !(1 == ~T3_E~0); 6925984#L1169-1 assume !(1 == ~T4_E~0); 6925839#L1174-1 assume !(1 == ~T5_E~0); 6925632#L1179-1 assume !(1 == ~T6_E~0); 6925492#L1184-1 assume !(1 == ~T7_E~0); 6925493#L1189-1 assume !(1 == ~T8_E~0); 6925566#L1194-1 assume !(1 == ~T9_E~0); 6925693#L1199-1 assume !(1 == ~T10_E~0); 6925647#L1204-1 assume !(1 == ~E_M~0); 6925648#L1209-1 assume !(1 == ~E_1~0); 6926246#L1214-1 assume !(1 == ~E_2~0); 6926247#L1219-1 assume !(1 == ~E_3~0); 6926711#L1224-1 assume !(1 == ~E_4~0); 6926011#L1229-1 assume !(1 == ~E_5~0); 6925381#L1234-1 assume !(1 == ~E_6~0); 6925382#L1239-1 assume !(1 == ~E_7~0); 6925435#L1244-1 assume !(1 == ~E_8~0); 6925436#L1249-1 assume !(1 == ~E_9~0); 6926333#L1254-1 assume !(1 == ~E_10~0); 6925283#L1259-1 assume { :end_inline_reset_delta_events } true; 6925284#L1565-2 assume !false; 6948421#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6948414#L1011-1 [2023-11-29 01:36:43,689 INFO L750 eck$LassoCheckResult]: Loop: 6948414#L1011-1 assume !false; 6948407#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6948188#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 6948185#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6948183#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6948181#L866 assume 0 != eval_~tmp~0#1; 6948178#L866-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 6948175#L874 assume !(0 != eval_~tmp_ndt_1~0#1); 6948173#L874-2 havoc eval_~tmp_ndt_1~0#1; 6948168#L871-1 assume !(0 == ~t1_st~0); 6948165#L885-1 assume !(0 == ~t2_st~0); 6948150#L899-1 assume !(0 == ~t3_st~0); 6948142#L913-1 assume !(0 == ~t4_st~0); 6948137#L927-1 assume !(0 == ~t5_st~0); 6948134#L941-1 assume !(0 == ~t6_st~0); 6948130#L955-1 assume !(0 == ~t7_st~0); 6948123#L969-1 assume !(0 == ~t8_st~0); 6948117#L983-1 assume !(0 == ~t9_st~0); 6948118#L997-1 assume !(0 == ~t10_st~0); 6948414#L1011-1 [2023-11-29 01:36:43,690 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:43,690 INFO L85 PathProgramCache]: Analyzing trace with hash 1499347499, now seen corresponding path program 1 times [2023-11-29 01:36:43,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:43,690 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39725237] [2023-11-29 01:36:43,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:43,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:43,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:43,702 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:36:43,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:43,744 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:36:43,744 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:43,744 INFO L85 PathProgramCache]: Analyzing trace with hash 2001393697, now seen corresponding path program 1 times [2023-11-29 01:36:43,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:43,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975738] [2023-11-29 01:36:43,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:43,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:43,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:43,748 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:36:43,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:43,753 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:36:43,753 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:43,753 INFO L85 PathProgramCache]: Analyzing trace with hash -531920457, now seen corresponding path program 1 times [2023-11-29 01:36:43,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:43,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [682280026] [2023-11-29 01:36:43,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:43,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:43,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:36:43,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:36:43,799 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:36:43,800 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [682280026] [2023-11-29 01:36:43,800 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [682280026] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:36:43,800 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:36:43,800 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:36:43,800 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395173956] [2023-11-29 01:36:43,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:36:43,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:36:43,938 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:36:43,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:36:43,939 INFO L87 Difference]: Start difference. First operand 297342 states and 405486 transitions. cyclomatic complexity: 108196 Second operand has 3 states, 3 states have (on average 49.666666666666664) internal successors, (149), 3 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:45,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:36:45,580 INFO L93 Difference]: Finished difference Result 575430 states and 780373 transitions. [2023-11-29 01:36:45,580 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 575430 states and 780373 transitions. [2023-11-29 01:36:47,887 INFO L131 ngComponentsAnalysis]: Automaton has 52 accepting balls. 572728 [2023-11-29 01:36:49,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 575430 states to 575430 states and 780373 transitions. [2023-11-29 01:36:49,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 575430 [2023-11-29 01:36:49,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 575430 [2023-11-29 01:36:49,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 575430 states and 780373 transitions. [2023-11-29 01:36:49,594 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:36:49,594 INFO L218 hiAutomatonCegarLoop]: Abstraction has 575430 states and 780373 transitions. [2023-11-29 01:36:49,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 575430 states and 780373 transitions. [2023-11-29 01:36:53,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 575430 to 552694. [2023-11-29 01:36:53,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552694 states, 552694 states have (on average 1.3580407965347914) internal successors, (750581), 552693 states have internal predecessors, (750581), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:55,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552694 states to 552694 states and 750581 transitions. [2023-11-29 01:36:55,385 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552694 states and 750581 transitions. [2023-11-29 01:36:55,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:36:55,386 INFO L428 stractBuchiCegarLoop]: Abstraction has 552694 states and 750581 transitions. [2023-11-29 01:36:55,386 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2023-11-29 01:36:55,386 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552694 states and 750581 transitions. [2023-11-29 01:36:57,063 INFO L131 ngComponentsAnalysis]: Automaton has 52 accepting balls. 549992 [2023-11-29 01:36:57,063 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:36:57,063 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:36:57,064 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:57,064 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:36:57,065 INFO L748 eck$LassoCheckResult]: Stem: 7798331#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 7798332#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 7799413#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7799414#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7799547#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 7799426#L731-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 7799346#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7799347#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7799401#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7798268#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7798269#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7798377#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 7798634#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 7798553#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7798267#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 7797936#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7797937#L1036 assume !(0 == ~M_E~0); 7798030#L1036-2 assume !(0 == ~T1_E~0); 7798985#L1041-1 assume !(0 == ~T2_E~0); 7798986#L1046-1 assume !(0 == ~T3_E~0); 7798307#L1051-1 assume !(0 == ~T4_E~0); 7798308#L1056-1 assume !(0 == ~T5_E~0); 7799154#L1061-1 assume !(0 == ~T6_E~0); 7798201#L1066-1 assume !(0 == ~T7_E~0); 7798202#L1071-1 assume !(0 == ~T8_E~0); 7799131#L1076-1 assume !(0 == ~T9_E~0); 7798091#L1081-1 assume !(0 == ~T10_E~0); 7798092#L1086-1 assume !(0 == ~E_M~0); 7798498#L1091-1 assume !(0 == ~E_1~0); 7799437#L1096-1 assume !(0 == ~E_2~0); 7799438#L1101-1 assume !(0 == ~E_3~0); 7798567#L1106-1 assume !(0 == ~E_4~0); 7798568#L1111-1 assume !(0 == ~E_5~0); 7798750#L1116-1 assume !(0 == ~E_6~0); 7798751#L1121-1 assume !(0 == ~E_7~0); 7798557#L1126-1 assume !(0 == ~E_8~0); 7798558#L1131-1 assume !(0 == ~E_9~0); 7798861#L1136-1 assume !(0 == ~E_10~0); 7798996#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7799200#L514 assume !(1 == ~m_pc~0); 7799201#L514-2 is_master_triggered_~__retres1~0#1 := 0; 7798573#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7798574#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7799292#L1285 assume !(0 != activate_threads_~tmp~1#1); 7799515#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7798221#L533 assume !(1 == ~t1_pc~0); 7798222#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7798765#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7797989#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7797990#L1293 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7799328#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7807102#L552 assume !(1 == ~t2_pc~0); 7807101#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7807100#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7807099#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7807098#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 7807097#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7807096#L571 assume !(1 == ~t3_pc~0); 7807095#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7807094#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7807093#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7807092#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 7807091#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7807090#L590 assume !(1 == ~t4_pc~0); 7807087#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7807086#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7807085#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7807083#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 7807082#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7807081#L609 assume !(1 == ~t5_pc~0); 7807080#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7807079#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7807078#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7807077#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 7807076#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7807075#L628 assume !(1 == ~t6_pc~0); 7807074#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7807072#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7807071#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7807070#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 7807069#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7807068#L647 assume !(1 == ~t7_pc~0); 7807067#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 7807066#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7807065#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7807064#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 7807063#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7807062#L666 assume !(1 == ~t8_pc~0); 7807060#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7807059#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7807058#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7807057#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 7807056#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7807055#L685 assume !(1 == ~t9_pc~0); 7807054#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 7807053#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7807052#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7807051#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 7807050#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7807048#L704 assume !(1 == ~t10_pc~0); 7807047#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7807046#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7807045#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7807044#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 7807043#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7807042#L1154 assume !(1 == ~M_E~0); 7807041#L1154-2 assume !(1 == ~T1_E~0); 7807040#L1159-1 assume !(1 == ~T2_E~0); 7807039#L1164-1 assume !(1 == ~T3_E~0); 7807038#L1169-1 assume !(1 == ~T4_E~0); 7807037#L1174-1 assume !(1 == ~T5_E~0); 7807036#L1179-1 assume !(1 == ~T6_E~0); 7807035#L1184-1 assume !(1 == ~T7_E~0); 7807034#L1189-1 assume !(1 == ~T8_E~0); 7807033#L1194-1 assume !(1 == ~T9_E~0); 7807032#L1199-1 assume !(1 == ~T10_E~0); 7807031#L1204-1 assume !(1 == ~E_M~0); 7807030#L1209-1 assume !(1 == ~E_1~0); 7807029#L1214-1 assume !(1 == ~E_2~0); 7807028#L1219-1 assume !(1 == ~E_3~0); 7807027#L1224-1 assume !(1 == ~E_4~0); 7807026#L1229-1 assume !(1 == ~E_5~0); 7807025#L1234-1 assume !(1 == ~E_6~0); 7807024#L1239-1 assume !(1 == ~E_7~0); 7807023#L1244-1 assume !(1 == ~E_8~0); 7807022#L1249-1 assume !(1 == ~E_9~0); 7807021#L1254-1 assume !(1 == ~E_10~0); 7798060#L1259-1 assume { :end_inline_reset_delta_events } true; 7798061#L1565-2 assume !false; 7815496#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7815491#L1011-1 [2023-11-29 01:36:57,065 INFO L750 eck$LassoCheckResult]: Loop: 7815491#L1011-1 assume !false; 7815489#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 7815486#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7815483#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 7815481#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7815479#L866 assume 0 != eval_~tmp~0#1; 7815476#L866-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 7815473#L874 assume !(0 != eval_~tmp_ndt_1~0#1); 7815471#L874-2 havoc eval_~tmp_ndt_1~0#1; 7815470#L871-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 7806989#L888 assume !(0 != eval_~tmp_ndt_2~0#1); 7815464#L888-2 havoc eval_~tmp_ndt_2~0#1; 7815461#L885-1 assume !(0 == ~t2_st~0); 7815456#L899-1 assume !(0 == ~t3_st~0); 7815453#L913-1 assume !(0 == ~t4_st~0); 7815448#L927-1 assume !(0 == ~t5_st~0); 7815445#L941-1 assume !(0 == ~t6_st~0); 7815442#L955-1 assume !(0 == ~t7_st~0); 7815443#L969-1 assume !(0 == ~t8_st~0); 7815501#L983-1 assume !(0 == ~t9_st~0); 7815494#L997-1 assume !(0 == ~t10_st~0); 7815491#L1011-1 [2023-11-29 01:36:57,065 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:57,065 INFO L85 PathProgramCache]: Analyzing trace with hash 1850588971, now seen corresponding path program 1 times [2023-11-29 01:36:57,065 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:57,065 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447707653] [2023-11-29 01:36:57,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:57,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:57,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:36:57,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:36:57,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:36:57,101 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [447707653] [2023-11-29 01:36:57,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [447707653] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:36:57,101 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:36:57,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:36:57,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1909659698] [2023-11-29 01:36:57,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:36:57,102 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:36:57,102 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:36:57,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1357006180, now seen corresponding path program 1 times [2023-11-29 01:36:57,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:36:57,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2004813654] [2023-11-29 01:36:57,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:36:57,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:36:57,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:57,107 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:36:57,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:36:57,111 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:36:57,234 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:36:57,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:36:57,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:36:57,235 INFO L87 Difference]: Start difference. First operand 552694 states and 750581 transitions. cyclomatic complexity: 197939 Second operand has 3 states, 3 states have (on average 43.333333333333336) internal successors, (130), 3 states have internal predecessors, (130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:36:58,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:36:58,856 INFO L93 Difference]: Finished difference Result 552562 states and 750397 transitions. [2023-11-29 01:36:58,856 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552562 states and 750397 transitions. [2023-11-29 01:37:01,390 INFO L131 ngComponentsAnalysis]: Automaton has 52 accepting balls. 549992 [2023-11-29 01:37:02,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552562 states to 552562 states and 750397 transitions. [2023-11-29 01:37:02,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552562 [2023-11-29 01:37:03,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552562 [2023-11-29 01:37:03,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552562 states and 750397 transitions. [2023-11-29 01:37:03,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:37:03,310 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552562 states and 750397 transitions. [2023-11-29 01:37:03,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552562 states and 750397 transitions. [2023-11-29 01:37:07,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552562 to 552562. [2023-11-29 01:37:07,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552562 states, 552562 states have (on average 1.3580322208186593) internal successors, (750397), 552561 states have internal predecessors, (750397), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:37:09,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552562 states to 552562 states and 750397 transitions. [2023-11-29 01:37:09,717 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552562 states and 750397 transitions. [2023-11-29 01:37:09,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:37:09,718 INFO L428 stractBuchiCegarLoop]: Abstraction has 552562 states and 750397 transitions. [2023-11-29 01:37:09,718 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2023-11-29 01:37:09,718 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552562 states and 750397 transitions. [2023-11-29 01:37:10,875 INFO L131 ngComponentsAnalysis]: Automaton has 52 accepting balls. 549992 [2023-11-29 01:37:10,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:37:10,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:37:10,876 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:37:10,876 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:37:10,876 INFO L748 eck$LassoCheckResult]: Stem: 8903591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 8903592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8904636#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8904637#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8904759#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 8904643#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8904568#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8904569#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8904622#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8903530#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8903531#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8903637#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 8903894#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 8903813#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8903529#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 8903198#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8903199#L1036 assume !(0 == ~M_E~0); 8903293#L1036-2 assume !(0 == ~T1_E~0); 8904237#L1041-1 assume !(0 == ~T2_E~0); 8904238#L1046-1 assume !(0 == ~T3_E~0); 8903569#L1051-1 assume !(0 == ~T4_E~0); 8903570#L1056-1 assume !(0 == ~T5_E~0); 8904407#L1061-1 assume !(0 == ~T6_E~0); 8903463#L1066-1 assume !(0 == ~T7_E~0); 8903464#L1071-1 assume !(0 == ~T8_E~0); 8904384#L1076-1 assume !(0 == ~T9_E~0); 8903354#L1081-1 assume !(0 == ~T10_E~0); 8903355#L1086-1 assume !(0 == ~E_M~0); 8903759#L1091-1 assume !(0 == ~E_1~0); 8904654#L1096-1 assume !(0 == ~E_2~0); 8904655#L1101-1 assume !(0 == ~E_3~0); 8903827#L1106-1 assume !(0 == ~E_4~0); 8903828#L1111-1 assume !(0 == ~E_5~0); 8904014#L1116-1 assume !(0 == ~E_6~0); 8904015#L1121-1 assume !(0 == ~E_7~0); 8903817#L1126-1 assume !(0 == ~E_8~0); 8903818#L1131-1 assume !(0 == ~E_9~0); 8904119#L1136-1 assume !(0 == ~E_10~0); 8904245#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8904450#L514 assume !(1 == ~m_pc~0); 8904451#L514-2 is_master_triggered_~__retres1~0#1 := 0; 8903833#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8903834#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8904529#L1285 assume !(0 != activate_threads_~tmp~1#1); 8904722#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8903483#L533 assume !(1 == ~t1_pc~0); 8903484#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8904028#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8903252#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8903253#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 8904274#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8904275#L552 assume !(1 == ~t2_pc~0); 8903971#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8903972#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8903821#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8903822#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 8903856#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8903857#L571 assume !(1 == ~t3_pc~0); 8904089#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8904170#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8903196#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8903197#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 8904018#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8903279#L590 assume !(1 == ~t4_pc~0); 8903280#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8904087#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8904868#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8904728#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 8904311#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8904016#L609 assume !(1 == ~t5_pc~0); 8904017#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8904717#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8904531#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8904532#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 8904008#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8904009#L628 assume !(1 == ~t6_pc~0); 8903929#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8903928#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8903797#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8903798#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 8904358#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8904359#L647 assume !(1 == ~t7_pc~0); 8904510#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8904541#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8904542#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8903831#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 8903832#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8904797#L666 assume !(1 == ~t8_pc~0); 8903614#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8903615#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8903847#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8904041#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 8903756#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8903757#L685 assume !(1 == ~t9_pc~0); 8904740#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 8904553#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8903887#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8903784#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 8903785#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8904203#L704 assume !(1 == ~t10_pc~0); 8903776#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8904663#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8904061#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8903327#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 8903328#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8903576#L1154 assume !(1 == ~M_E~0); 8904341#L1154-2 assume !(1 == ~T1_E~0); 8903548#L1159-1 assume !(1 == ~T2_E~0); 8903549#L1164-1 assume !(1 == ~T3_E~0); 8904037#L1169-1 assume !(1 == ~T4_E~0); 8903889#L1174-1 assume !(1 == ~T5_E~0); 8903682#L1179-1 assume !(1 == ~T6_E~0); 8903533#L1184-1 assume !(1 == ~T7_E~0); 8903534#L1189-1 assume !(1 == ~T8_E~0); 8903612#L1194-1 assume !(1 == ~T9_E~0); 8903742#L1199-1 assume !(1 == ~T10_E~0); 8903696#L1204-1 assume !(1 == ~E_M~0); 8903697#L1209-1 assume !(1 == ~E_1~0); 8904303#L1214-1 assume !(1 == ~E_2~0); 8904304#L1219-1 assume !(1 == ~E_3~0); 8904774#L1224-1 assume !(1 == ~E_4~0); 8904066#L1229-1 assume !(1 == ~E_5~0); 8903422#L1234-1 assume !(1 == ~E_6~0); 8903423#L1239-1 assume !(1 == ~E_7~0); 8903477#L1244-1 assume !(1 == ~E_8~0); 8903478#L1249-1 assume !(1 == ~E_9~0); 8904396#L1254-1 assume !(1 == ~E_10~0); 8903324#L1259-1 assume { :end_inline_reset_delta_events } true; 8903325#L1565-2 assume !false; 8931973#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8931966#L1011-1 [2023-11-29 01:37:10,876 INFO L750 eck$LassoCheckResult]: Loop: 8931966#L1011-1 assume !false; 8931961#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8931956#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8931952#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8931946#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8931939#L866 assume 0 != eval_~tmp~0#1; 8931930#L866-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 8931921#L874 assume !(0 != eval_~tmp_ndt_1~0#1); 8931723#L874-2 havoc eval_~tmp_ndt_1~0#1; 8912014#L871-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 8912012#L888 assume !(0 != eval_~tmp_ndt_2~0#1); 8912010#L888-2 havoc eval_~tmp_ndt_2~0#1; 8912008#L885-1 assume !(0 == ~t2_st~0); 8912005#L899-1 assume !(0 == ~t3_st~0); 8911999#L913-1 assume !(0 == ~t4_st~0); 8911993#L927-1 assume !(0 == ~t5_st~0); 8911987#L941-1 assume !(0 == ~t6_st~0); 8911981#L955-1 assume !(0 == ~t7_st~0); 8911982#L969-1 assume !(0 == ~t8_st~0); 8915004#L983-1 assume !(0 == ~t9_st~0); 8915005#L997-1 assume !(0 == ~t10_st~0); 8931966#L1011-1 [2023-11-29 01:37:10,877 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:37:10,877 INFO L85 PathProgramCache]: Analyzing trace with hash 1499347499, now seen corresponding path program 2 times [2023-11-29 01:37:10,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:37:10,877 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445389664] [2023-11-29 01:37:10,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:37:10,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:37:10,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:37:10,886 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:37:10,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:37:10,915 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:37:10,916 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:37:10,916 INFO L85 PathProgramCache]: Analyzing trace with hash 1357006180, now seen corresponding path program 2 times [2023-11-29 01:37:10,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:37:10,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1595579127] [2023-11-29 01:37:10,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:37:10,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:37:10,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:37:10,919 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:37:10,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:37:10,923 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:37:10,924 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:37:10,924 INFO L85 PathProgramCache]: Analyzing trace with hash 2088561018, now seen corresponding path program 1 times [2023-11-29 01:37:10,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:37:10,924 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187379217] [2023-11-29 01:37:10,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:37:10,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:37:10,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:37:10,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:37:10,980 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:37:10,980 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1187379217] [2023-11-29 01:37:10,981 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1187379217] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:37:10,981 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:37:10,981 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:37:10,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128435834] [2023-11-29 01:37:10,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:37:11,116 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:37:11,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:37:11,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:37:11,117 INFO L87 Difference]: Start difference. First operand 552562 states and 750397 transitions. cyclomatic complexity: 197887 Second operand has 3 states, 3 states have (on average 50.333333333333336) internal successors, (151), 3 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:37:13,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:37:13,459 INFO L93 Difference]: Finished difference Result 682042 states and 921565 transitions. [2023-11-29 01:37:13,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 682042 states and 921565 transitions. [2023-11-29 01:37:16,019 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 679216 [2023-11-29 01:37:17,498 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 682042 states to 682042 states and 921565 transitions. [2023-11-29 01:37:17,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 682042 [2023-11-29 01:37:17,692 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 682042 [2023-11-29 01:37:17,692 INFO L73 IsDeterministic]: Start isDeterministic. Operand 682042 states and 921565 transitions. [2023-11-29 01:37:17,888 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:37:17,889 INFO L218 hiAutomatonCegarLoop]: Abstraction has 682042 states and 921565 transitions. [2023-11-29 01:37:18,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 682042 states and 921565 transitions. [2023-11-29 01:37:22,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 682042 to 668378. [2023-11-29 01:37:22,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 668378 states, 668378 states have (on average 1.3521644937445578) internal successors, (903757), 668377 states have internal predecessors, (903757), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:37:24,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 668378 states to 668378 states and 903757 transitions. [2023-11-29 01:37:24,935 INFO L240 hiAutomatonCegarLoop]: Abstraction has 668378 states and 903757 transitions. [2023-11-29 01:37:24,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:37:24,936 INFO L428 stractBuchiCegarLoop]: Abstraction has 668378 states and 903757 transitions. [2023-11-29 01:37:24,936 INFO L335 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2023-11-29 01:37:24,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 668378 states and 903757 transitions. [2023-11-29 01:37:26,474 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 665552 [2023-11-29 01:37:26,474 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:37:26,475 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:37:26,475 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:37:26,475 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:37:26,476 INFO L748 eck$LassoCheckResult]: Stem: 10138207#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 10138208#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 10139273#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10139274#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10139390#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 10139282#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10139197#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10139198#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10139260#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10138145#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10138146#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10138250#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 10138505#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 10138426#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10138144#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 10137810#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10137811#L1036 assume !(0 == ~M_E~0); 10137907#L1036-2 assume !(0 == ~T1_E~0); 10138857#L1041-1 assume !(0 == ~T2_E~0); 10138858#L1046-1 assume !(0 == ~T3_E~0); 10138183#L1051-1 assume !(0 == ~T4_E~0); 10138184#L1056-1 assume !(0 == ~T5_E~0); 10139023#L1061-1 assume !(0 == ~T6_E~0); 10138079#L1066-1 assume !(0 == ~T7_E~0); 10138080#L1071-1 assume !(0 == ~T8_E~0); 10139003#L1076-1 assume !(0 == ~T9_E~0); 10137969#L1081-1 assume !(0 == ~T10_E~0); 10137970#L1086-1 assume !(0 == ~E_M~0); 10138369#L1091-1 assume !(0 == ~E_1~0); 10139293#L1096-1 assume !(0 == ~E_2~0); 10139294#L1101-1 assume !(0 == ~E_3~0); 10138440#L1106-1 assume !(0 == ~E_4~0); 10138441#L1111-1 assume !(0 == ~E_5~0); 10138624#L1116-1 assume !(0 == ~E_6~0); 10138625#L1121-1 assume !(0 == ~E_7~0); 10138430#L1126-1 assume !(0 == ~E_8~0); 10138431#L1131-1 assume !(0 == ~E_9~0); 10138732#L1136-1 assume !(0 == ~E_10~0); 10138868#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10139063#L514 assume !(1 == ~m_pc~0); 10139064#L514-2 is_master_triggered_~__retres1~0#1 := 0; 10138446#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10138447#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10139149#L1285 assume !(0 != activate_threads_~tmp~1#1); 10139353#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10138097#L533 assume !(1 == ~t1_pc~0); 10138098#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10138640#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10137861#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10137862#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 10138896#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10138897#L552 assume !(1 == ~t2_pc~0); 10138581#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10138582#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10138434#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10138435#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 10138460#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10138461#L571 assume !(1 == ~t3_pc~0); 10138701#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10138787#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10137808#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10137809#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 10138629#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10137893#L590 assume !(1 == ~t4_pc~0); 10137894#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10138700#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10139509#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10139360#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 10138929#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10138626#L609 assume !(1 == ~t5_pc~0); 10138627#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10139351#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10139153#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10139154#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 10138618#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10138619#L628 assume !(1 == ~t6_pc~0); 10138538#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10138537#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10138405#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10138406#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 10138977#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10138978#L647 assume !(1 == ~t7_pc~0); 10139127#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10139167#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10139168#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10138442#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 10138443#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10139426#L666 assume !(1 == ~t8_pc~0); 10138228#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10138229#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10138459#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10138652#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 10138366#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10138367#L685 assume !(1 == ~t9_pc~0); 10139370#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 10139183#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10138499#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10138394#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 10138395#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10138822#L704 assume !(1 == ~t10_pc~0); 10138386#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10139302#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10138672#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10137942#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 10137943#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10138192#L1154 assume !(1 == ~M_E~0); 10138962#L1154-2 assume !(1 == ~T1_E~0); 10138166#L1159-1 assume !(1 == ~T2_E~0); 10138167#L1164-1 assume !(1 == ~T3_E~0); 10138650#L1169-1 assume !(1 == ~T4_E~0); 10138500#L1174-1 assume !(1 == ~T5_E~0); 10138293#L1179-1 assume !(1 == ~T6_E~0); 10138150#L1184-1 assume !(1 == ~T7_E~0); 10138151#L1189-1 assume !(1 == ~T8_E~0); 10138226#L1194-1 assume !(1 == ~T9_E~0); 10138351#L1199-1 assume !(1 == ~T10_E~0); 10138305#L1204-1 assume !(1 == ~E_M~0); 10138306#L1209-1 assume !(1 == ~E_1~0); 10138922#L1214-1 assume !(1 == ~E_2~0); 10138923#L1219-1 assume !(1 == ~E_3~0); 10139409#L1224-1 assume !(1 == ~E_4~0); 10138677#L1229-1 assume !(1 == ~E_5~0); 10138038#L1234-1 assume !(1 == ~E_6~0); 10138039#L1239-1 assume !(1 == ~E_7~0); 10138093#L1244-1 assume !(1 == ~E_8~0); 10138094#L1249-1 assume !(1 == ~E_9~0); 10139015#L1254-1 assume !(1 == ~E_10~0); 10137936#L1259-1 assume { :end_inline_reset_delta_events } true; 10137937#L1565-2 assume !false; 10253327#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10253322#L1011-1 [2023-11-29 01:37:26,476 INFO L750 eck$LassoCheckResult]: Loop: 10253322#L1011-1 assume !false; 10253320#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 10253317#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10253315#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10253313#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10253311#L866 assume 0 != eval_~tmp~0#1; 10253307#L866-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 10253304#L874 assume !(0 != eval_~tmp_ndt_1~0#1); 10253302#L874-2 havoc eval_~tmp_ndt_1~0#1; 10251237#L871-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 10251234#L888 assume !(0 != eval_~tmp_ndt_2~0#1); 10251231#L888-2 havoc eval_~tmp_ndt_2~0#1; 10251229#L885-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 10251226#L902 assume !(0 != eval_~tmp_ndt_3~0#1); 10251224#L902-2 havoc eval_~tmp_ndt_3~0#1; 10251221#L899-1 assume !(0 == ~t3_st~0); 10251222#L913-1 assume !(0 == ~t4_st~0); 10251604#L927-1 assume !(0 == ~t5_st~0); 10251600#L941-1 assume !(0 == ~t6_st~0); 10251596#L955-1 assume !(0 == ~t7_st~0); 10251597#L969-1 assume !(0 == ~t8_st~0); 10253333#L983-1 assume !(0 == ~t9_st~0); 10253325#L997-1 assume !(0 == ~t10_st~0); 10253322#L1011-1 [2023-11-29 01:37:26,476 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:37:26,476 INFO L85 PathProgramCache]: Analyzing trace with hash 1499347499, now seen corresponding path program 3 times [2023-11-29 01:37:26,476 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:37:26,476 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052039149] [2023-11-29 01:37:26,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:37:26,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:37:26,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:37:26,484 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:37:26,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:37:26,509 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:37:26,509 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:37:26,509 INFO L85 PathProgramCache]: Analyzing trace with hash -270285215, now seen corresponding path program 1 times [2023-11-29 01:37:26,509 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:37:26,509 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [43451487] [2023-11-29 01:37:26,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:37:26,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:37:26,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:37:26,512 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:37:26,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:37:26,516 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:37:26,517 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:37:26,517 INFO L85 PathProgramCache]: Analyzing trace with hash -1620722441, now seen corresponding path program 1 times [2023-11-29 01:37:26,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:37:26,517 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589814915] [2023-11-29 01:37:26,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:37:26,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:37:26,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:37:26,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:37:26,548 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:37:26,548 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [589814915] [2023-11-29 01:37:26,548 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [589814915] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:37:26,548 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:37:26,548 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:37:26,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [318774941] [2023-11-29 01:37:26,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:37:26,757 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:37:26,757 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:37:26,757 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:37:26,757 INFO L87 Difference]: Start difference. First operand 668378 states and 903757 transitions. cyclomatic complexity: 235439 Second operand has 3 states, 3 states have (on average 51.0) internal successors, (153), 3 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:37:29,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:37:29,263 INFO L93 Difference]: Finished difference Result 1004434 states and 1354981 transitions. [2023-11-29 01:37:29,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1004434 states and 1354981 transitions. [2023-11-29 01:37:33,803 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 1000296 [2023-11-29 01:37:36,259 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1004434 states to 1004434 states and 1354981 transitions. [2023-11-29 01:37:36,259 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1004434 [2023-11-29 01:37:36,669 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1004434 [2023-11-29 01:37:36,669 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1004434 states and 1354981 transitions. [2023-11-29 01:37:37,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:37:37,431 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1004434 states and 1354981 transitions. [2023-11-29 01:37:37,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1004434 states and 1354981 transitions. [2023-11-29 01:37:44,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1004434 to 973042. [2023-11-29 01:37:45,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 973042 states, 973042 states have (on average 1.3501955722363475) internal successors, (1313797), 973041 states have internal predecessors, (1313797), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:37:47,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 973042 states to 973042 states and 1313797 transitions. [2023-11-29 01:37:47,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 973042 states and 1313797 transitions. [2023-11-29 01:37:47,765 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:37:47,766 INFO L428 stractBuchiCegarLoop]: Abstraction has 973042 states and 1313797 transitions. [2023-11-29 01:37:47,766 INFO L335 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2023-11-29 01:37:47,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 973042 states and 1313797 transitions. [2023-11-29 01:37:51,281 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 968904 [2023-11-29 01:37:51,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:37:51,282 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:37:51,282 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:37:51,282 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:37:51,283 INFO L748 eck$LassoCheckResult]: Stem: 11811030#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 11811031#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 11812114#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11812115#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11812251#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 11812123#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11812046#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11812047#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11812101#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11810962#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11810963#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11811075#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11811333#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 11811253#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11810964#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 11810630#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11810631#L1036 assume !(0 == ~M_E~0); 11810727#L1036-2 assume !(0 == ~T1_E~0); 11811685#L1041-1 assume !(0 == ~T2_E~0); 11811686#L1046-1 assume !(0 == ~T3_E~0); 11811006#L1051-1 assume !(0 == ~T4_E~0); 11811007#L1056-1 assume !(0 == ~T5_E~0); 11811858#L1061-1 assume !(0 == ~T6_E~0); 11810896#L1066-1 assume !(0 == ~T7_E~0); 11810897#L1071-1 assume !(0 == ~T8_E~0); 11811839#L1076-1 assume !(0 == ~T9_E~0); 11810787#L1081-1 assume !(0 == ~T10_E~0); 11810788#L1086-1 assume !(0 == ~E_M~0); 11811197#L1091-1 assume !(0 == ~E_1~0); 11812137#L1096-1 assume !(0 == ~E_2~0); 11812138#L1101-1 assume !(0 == ~E_3~0); 11811267#L1106-1 assume !(0 == ~E_4~0); 11811268#L1111-1 assume !(0 == ~E_5~0); 11811452#L1116-1 assume !(0 == ~E_6~0); 11811453#L1121-1 assume !(0 == ~E_7~0); 11811257#L1126-1 assume !(0 == ~E_8~0); 11811258#L1131-1 assume !(0 == ~E_9~0); 11811562#L1136-1 assume !(0 == ~E_10~0); 11811695#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11811904#L514 assume !(1 == ~m_pc~0); 11811905#L514-2 is_master_triggered_~__retres1~0#1 := 0; 11811273#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11811274#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11811993#L1285 assume !(0 != activate_threads_~tmp~1#1); 11812209#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11810914#L533 assume !(1 == ~t1_pc~0); 11810915#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11811467#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11810682#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11810683#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 11811725#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11811726#L552 assume !(1 == ~t2_pc~0); 11811408#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11811409#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11811261#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11811262#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 11811286#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11811287#L571 assume !(1 == ~t3_pc~0); 11811526#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11811619#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11810628#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11810629#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 11811457#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11810712#L590 assume !(1 == ~t4_pc~0); 11810713#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11811525#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11812368#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11812219#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 11811759#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11811454#L609 assume !(1 == ~t5_pc~0); 11811455#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11812206#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11811999#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11812000#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 11811446#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11811447#L628 assume !(1 == ~t6_pc~0); 11811365#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11811364#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11811234#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11811235#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 11811811#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11811812#L647 assume !(1 == ~t7_pc~0); 11811973#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11812012#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11812013#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11811269#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 11811270#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11812286#L666 assume !(1 == ~t8_pc~0); 11811052#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11811053#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11811285#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11811479#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 11811194#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11811195#L685 assume !(1 == ~t9_pc~0); 11812232#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11812028#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11811326#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11811225#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 11811226#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11811649#L704 assume !(1 == ~t10_pc~0); 11811217#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11812146#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11811497#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11810760#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 11810761#L1365-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11811015#L1154 assume !(1 == ~M_E~0); 11811794#L1154-2 assume !(1 == ~T1_E~0); 11810987#L1159-1 assume !(1 == ~T2_E~0); 11810988#L1164-1 assume !(1 == ~T3_E~0); 11811477#L1169-1 assume !(1 == ~T4_E~0); 11811327#L1174-1 assume !(1 == ~T5_E~0); 11811116#L1179-1 assume !(1 == ~T6_E~0); 11810971#L1184-1 assume !(1 == ~T7_E~0); 11810972#L1189-1 assume !(1 == ~T8_E~0); 11811050#L1194-1 assume !(1 == ~T9_E~0); 11811177#L1199-1 assume !(1 == ~T10_E~0); 11811131#L1204-1 assume !(1 == ~E_M~0); 11811132#L1209-1 assume !(1 == ~E_1~0); 11811753#L1214-1 assume !(1 == ~E_2~0); 11811754#L1219-1 assume !(1 == ~E_3~0); 11812265#L1224-1 assume !(1 == ~E_4~0); 11811501#L1229-1 assume !(1 == ~E_5~0); 11810856#L1234-1 assume !(1 == ~E_6~0); 11810857#L1239-1 assume !(1 == ~E_7~0); 11810910#L1244-1 assume !(1 == ~E_8~0); 11810911#L1249-1 assume !(1 == ~E_9~0); 11811850#L1254-1 assume !(1 == ~E_10~0); 11810755#L1259-1 assume { :end_inline_reset_delta_events } true; 11810756#L1565-2 assume !false; 11960855#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11960850#L1011-1 [2023-11-29 01:37:51,283 INFO L750 eck$LassoCheckResult]: Loop: 11960850#L1011-1 assume !false; 11960848#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11960845#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11960843#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11960841#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11960839#L866 assume 0 != eval_~tmp~0#1; 11960836#L866-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 11960833#L874 assume !(0 != eval_~tmp_ndt_1~0#1); 11960831#L874-2 havoc eval_~tmp_ndt_1~0#1; 11960829#L871-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 11960813#L888 assume !(0 != eval_~tmp_ndt_2~0#1); 11960827#L888-2 havoc eval_~tmp_ndt_2~0#1; 11989309#L885-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 11989306#L902 assume !(0 != eval_~tmp_ndt_3~0#1); 11989304#L902-2 havoc eval_~tmp_ndt_3~0#1; 11989303#L899-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 11989300#L916 assume !(0 != eval_~tmp_ndt_4~0#1); 11989301#L916-2 havoc eval_~tmp_ndt_4~0#1; 12009338#L913-1 assume !(0 == ~t4_st~0); 12009334#L927-1 assume !(0 == ~t5_st~0); 12009328#L941-1 assume !(0 == ~t6_st~0); 12009322#L955-1 assume !(0 == ~t7_st~0); 12009323#L969-1 assume !(0 == ~t8_st~0); 12024295#L983-1 assume !(0 == ~t9_st~0); 11960853#L997-1 assume !(0 == ~t10_st~0); 11960850#L1011-1 [2023-11-29 01:37:51,284 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:37:51,284 INFO L85 PathProgramCache]: Analyzing trace with hash 1499347499, now seen corresponding path program 4 times [2023-11-29 01:37:51,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:37:51,284 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [823904936] [2023-11-29 01:37:51,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:37:51,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:37:51,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:37:51,293 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:37:51,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:37:51,331 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:37:51,332 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:37:51,332 INFO L85 PathProgramCache]: Analyzing trace with hash -340874140, now seen corresponding path program 1 times [2023-11-29 01:37:51,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:37:51,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184758139] [2023-11-29 01:37:51,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:37:51,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:37:51,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:37:51,336 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:37:51,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:37:51,340 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:37:51,341 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:37:51,341 INFO L85 PathProgramCache]: Analyzing trace with hash -1030924934, now seen corresponding path program 1 times [2023-11-29 01:37:51,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:37:51,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641319] [2023-11-29 01:37:51,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:37:51,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:37:51,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:37:51,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:37:51,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:37:51,387 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641319] [2023-11-29 01:37:51,387 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [641319] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:37:51,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:37:51,388 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:37:51,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [731045896] [2023-11-29 01:37:51,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:37:51,523 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:37:51,523 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:37:51,524 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:37:51,524 INFO L87 Difference]: Start difference. First operand 973042 states and 1313797 transitions. cyclomatic complexity: 340815 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:37:57,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:37:57,071 INFO L93 Difference]: Finished difference Result 1873018 states and 2527533 transitions. [2023-11-29 01:37:57,071 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1873018 states and 2527533 transitions. [2023-11-29 01:38:05,814 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 1864880 [2023-11-29 01:38:11,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1873018 states to 1873018 states and 2527533 transitions. [2023-11-29 01:38:11,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1873018 [2023-11-29 01:38:12,674 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1873018 [2023-11-29 01:38:12,674 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1873018 states and 2527533 transitions. [2023-11-29 01:38:13,189 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:38:13,190 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1873018 states and 2527533 transitions. [2023-11-29 01:38:14,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1873018 states and 2527533 transitions. [2023-11-29 01:38:28,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1873018 to 1813210. [2023-11-29 01:38:29,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1813210 states, 1813210 states have (on average 1.3505931469603631) internal successors, (2448909), 1813209 states have internal predecessors, (2448909), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)