./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.10.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.10.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-29 05:59:17,241 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-29 05:59:17,312 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-29 05:59:17,318 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-29 05:59:17,319 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-29 05:59:17,345 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-29 05:59:17,346 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-29 05:59:17,346 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-29 05:59:17,347 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-29 05:59:17,348 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-29 05:59:17,349 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-29 05:59:17,349 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-29 05:59:17,350 INFO L153 SettingsManager]: * Use SBE=true [2023-11-29 05:59:17,350 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-29 05:59:17,351 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-29 05:59:17,351 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-29 05:59:17,352 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-29 05:59:17,352 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-29 05:59:17,353 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-29 05:59:17,353 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-29 05:59:17,354 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-29 05:59:17,355 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-29 05:59:17,355 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-29 05:59:17,356 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-29 05:59:17,356 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-29 05:59:17,357 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-29 05:59:17,357 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-29 05:59:17,357 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-29 05:59:17,358 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-29 05:59:17,358 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-29 05:59:17,359 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-29 05:59:17,359 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-29 05:59:17,359 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-29 05:59:17,360 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-29 05:59:17,360 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-29 05:59:17,361 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-29 05:59:17,361 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-29 05:59:17,361 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-29 05:59:17,362 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6ba9401cadb8fecd59a1a331c94e3215cc972a92f03516bfd6c95164e3ec98a9 [2023-11-29 05:59:17,586 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-29 05:59:17,607 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-29 05:59:17,610 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-29 05:59:17,611 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-29 05:59:17,612 INFO L274 PluginConnector]: CDTParser initialized [2023-11-29 05:59:17,613 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2023-11-29 05:59:20,377 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-29 05:59:20,565 INFO L384 CDTParser]: Found 1 translation units. [2023-11-29 05:59:20,566 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/sv-benchmarks/c/systemc/token_ring.10.cil-2.c [2023-11-29 05:59:20,578 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya/data/f3f4ae1bb/71880f3e96214d70b5a35c70dee81f80/FLAG943aedf50 [2023-11-29 05:59:20,591 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya/data/f3f4ae1bb/71880f3e96214d70b5a35c70dee81f80 [2023-11-29 05:59:20,594 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-29 05:59:20,595 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-29 05:59:20,596 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-29 05:59:20,597 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-29 05:59:20,601 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-29 05:59:20,601 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 05:59:20" (1/1) ... [2023-11-29 05:59:20,602 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@f170f7a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20, skipping insertion in model container [2023-11-29 05:59:20,603 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 05:59:20" (1/1) ... [2023-11-29 05:59:20,656 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-29 05:59:20,884 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 05:59:20,902 INFO L202 MainTranslator]: Completed pre-run [2023-11-29 05:59:20,974 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 05:59:20,998 INFO L206 MainTranslator]: Completed translation [2023-11-29 05:59:20,998 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20 WrapperNode [2023-11-29 05:59:20,998 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-29 05:59:20,999 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-29 05:59:21,000 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-29 05:59:21,000 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-29 05:59:21,005 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20" (1/1) ... [2023-11-29 05:59:21,018 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20" (1/1) ... [2023-11-29 05:59:21,094 INFO L138 Inliner]: procedures = 48, calls = 62, calls flagged for inlining = 57, calls inlined = 210, statements flattened = 3209 [2023-11-29 05:59:21,095 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-29 05:59:21,095 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-29 05:59:21,096 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-29 05:59:21,096 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-29 05:59:21,107 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20" (1/1) ... [2023-11-29 05:59:21,108 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20" (1/1) ... [2023-11-29 05:59:21,120 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20" (1/1) ... [2023-11-29 05:59:21,155 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-29 05:59:21,156 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20" (1/1) ... [2023-11-29 05:59:21,156 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20" (1/1) ... [2023-11-29 05:59:21,192 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20" (1/1) ... [2023-11-29 05:59:21,222 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20" (1/1) ... [2023-11-29 05:59:21,228 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20" (1/1) ... [2023-11-29 05:59:21,239 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20" (1/1) ... [2023-11-29 05:59:21,251 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-29 05:59:21,252 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-29 05:59:21,252 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-29 05:59:21,252 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-29 05:59:21,253 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20" (1/1) ... [2023-11-29 05:59:21,259 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 05:59:21,270 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 05:59:21,282 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 05:59:21,288 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_08751238-2fe1-47a8-91bc-7e2db3b8f79a/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-29 05:59:21,354 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-29 05:59:21,354 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-29 05:59:21,354 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-29 05:59:21,354 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-29 05:59:21,486 INFO L241 CfgBuilder]: Building ICFG [2023-11-29 05:59:21,487 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-29 05:59:23,080 INFO L282 CfgBuilder]: Performing block encoding [2023-11-29 05:59:23,109 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-29 05:59:23,110 INFO L309 CfgBuilder]: Removed 13 assume(true) statements. [2023-11-29 05:59:23,112 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 05:59:23 BoogieIcfgContainer [2023-11-29 05:59:23,112 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-29 05:59:23,113 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-29 05:59:23,113 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-29 05:59:23,117 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-29 05:59:23,117 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 05:59:23,118 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.11 05:59:20" (1/3) ... [2023-11-29 05:59:23,118 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@62f9e3d6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 05:59:23, skipping insertion in model container [2023-11-29 05:59:23,119 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 05:59:23,119 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 05:59:20" (2/3) ... [2023-11-29 05:59:23,119 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@62f9e3d6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 05:59:23, skipping insertion in model container [2023-11-29 05:59:23,119 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 05:59:23,119 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 05:59:23" (3/3) ... [2023-11-29 05:59:23,121 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-2.c [2023-11-29 05:59:23,200 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-29 05:59:23,200 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-29 05:59:23,200 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-29 05:59:23,200 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-29 05:59:23,200 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-29 05:59:23,200 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-29 05:59:23,200 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-29 05:59:23,200 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-29 05:59:23,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1379 states, 1378 states have (on average 1.5014513788098693) internal successors, (2069), 1378 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:23,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1236 [2023-11-29 05:59:23,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:23,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:23,276 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:23,276 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:23,276 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-29 05:59:23,280 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1379 states, 1378 states have (on average 1.5014513788098693) internal successors, (2069), 1378 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:23,297 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1236 [2023-11-29 05:59:23,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:23,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:23,302 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:23,303 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:23,313 INFO L748 eck$LassoCheckResult]: Stem: 188#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1260#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 998#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1256#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 589#L719true assume !(1 == ~m_i~0);~m_st~0 := 2; 358#L719-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 563#L724-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 730#L729-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1246#L734-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 477#L739-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 848#L744-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 392#L749-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 683#L754-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 869#L759-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 639#L764-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 571#L769-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 857#L1024true assume !(0 == ~M_E~0); 960#L1024-2true assume !(0 == ~T1_E~0); 186#L1029-1true assume !(0 == ~T2_E~0); 245#L1034-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1328#L1039-1true assume !(0 == ~T4_E~0); 1035#L1044-1true assume !(0 == ~T5_E~0); 407#L1049-1true assume !(0 == ~T6_E~0); 1342#L1054-1true assume !(0 == ~T7_E~0); 588#L1059-1true assume !(0 == ~T8_E~0); 214#L1064-1true assume !(0 == ~T9_E~0); 822#L1069-1true assume !(0 == ~T10_E~0); 1239#L1074-1true assume 0 == ~E_M~0;~E_M~0 := 1; 899#L1079-1true assume !(0 == ~E_1~0); 860#L1084-1true assume !(0 == ~E_2~0); 1059#L1089-1true assume !(0 == ~E_3~0); 933#L1094-1true assume !(0 == ~E_4~0); 469#L1099-1true assume !(0 == ~E_5~0); 1074#L1104-1true assume !(0 == ~E_6~0); 702#L1109-1true assume !(0 == ~E_7~0); 320#L1114-1true assume 0 == ~E_8~0;~E_8~0 := 1; 1291#L1119-1true assume !(0 == ~E_9~0); 365#L1124-1true assume !(0 == ~E_10~0); 39#L1129-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 721#L502true assume 1 == ~m_pc~0; 586#L503true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 100#L513true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 851#is_master_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 636#L1273true assume !(0 != activate_threads_~tmp~1#1); 1378#L1273-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1143#L521true assume !(1 == ~t1_pc~0); 1070#L521-2true is_transmit1_triggered_~__retres1~1#1 := 0; 63#L532true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 652#L1281true assume !(0 != activate_threads_~tmp___0~0#1); 56#L1281-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 875#L540true assume 1 == ~t2_pc~0; 1125#L541true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 879#L551true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 318#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1240#L1289true assume !(0 != activate_threads_~tmp___1~0#1); 968#L1289-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 203#L559true assume 1 == ~t3_pc~0; 1044#L560true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 377#L570true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 665#L1297true assume !(0 != activate_threads_~tmp___2~0#1); 108#L1297-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1267#L578true assume !(1 == ~t4_pc~0); 828#L578-2true is_transmit4_triggered_~__retres1~4#1 := 0; 854#L589true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1111#L1305true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 619#L1305-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1179#L597true assume 1 == ~t5_pc~0; 1347#L598true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 73#L608true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 855#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1366#L1313true assume !(0 != activate_threads_~tmp___4~0#1); 572#L1313-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 633#L616true assume !(1 == ~t6_pc~0); 1191#L616-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1087#L627true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 304#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 509#L1321true assume !(0 != activate_threads_~tmp___5~0#1); 462#L1321-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 697#L635true assume 1 == ~t7_pc~0; 622#L636true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 255#L646true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1276#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 928#L1329true assume !(0 != activate_threads_~tmp___6~0#1); 567#L1329-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 816#L654true assume !(1 == ~t8_pc~0); 426#L654-2true is_transmit8_triggered_~__retres1~8#1 := 0; 969#L665true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 764#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 819#L1337true assume !(0 != activate_threads_~tmp___7~0#1); 1021#L1337-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 185#L673true assume 1 == ~t9_pc~0; 1038#L674true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1215#L684true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 355#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 768#L1345true assume !(0 != activate_threads_~tmp___8~0#1); 715#L1345-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 888#L692true assume !(1 == ~t10_pc~0); 701#L692-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1028#L703true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 464#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 472#L1353true assume !(0 != activate_threads_~tmp___9~0#1); 792#L1353-2true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1325#L1142true assume !(1 == ~M_E~0); 138#L1142-2true assume !(1 == ~T1_E~0); 769#L1147-1true assume !(1 == ~T2_E~0); 1324#L1152-1true assume !(1 == ~T3_E~0); 382#L1157-1true assume !(1 == ~T4_E~0); 868#L1162-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 491#L1167-1true assume !(1 == ~T6_E~0); 952#L1172-1true assume !(1 == ~T7_E~0); 982#L1177-1true assume !(1 == ~T8_E~0); 604#L1182-1true assume !(1 == ~T9_E~0); 708#L1187-1true assume !(1 == ~T10_E~0); 758#L1192-1true assume !(1 == ~E_M~0); 288#L1197-1true assume !(1 == ~E_1~0); 773#L1202-1true assume 1 == ~E_2~0;~E_2~0 := 2; 555#L1207-1true assume !(1 == ~E_3~0); 539#L1212-1true assume !(1 == ~E_4~0); 66#L1217-1true assume !(1 == ~E_5~0); 1380#L1222-1true assume !(1 == ~E_6~0); 536#L1227-1true assume !(1 == ~E_7~0); 601#L1232-1true assume !(1 == ~E_8~0); 7#L1237-1true assume !(1 == ~E_9~0); 1079#L1242-1true assume 1 == ~E_10~0;~E_10~0 := 2; 587#L1247-1true assume { :end_inline_reset_delta_events } true; 88#L1553-2true [2023-11-29 05:59:23,317 INFO L750 eck$LassoCheckResult]: Loop: 88#L1553-2true assume !false; 755#L1554true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 235#L999-1true assume false; 779#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 481#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1305#L1024-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1025#L1024-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 459#L1029-3true assume !(0 == ~T2_E~0); 435#L1034-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 735#L1039-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 788#L1044-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 183#L1049-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 664#L1054-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 64#L1059-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1350#L1064-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 415#L1069-3true assume !(0 == ~T10_E~0); 710#L1074-3true assume 0 == ~E_M~0;~E_M~0 := 1; 1001#L1079-3true assume 0 == ~E_1~0;~E_1~0 := 1; 595#L1084-3true assume 0 == ~E_2~0;~E_2~0 := 1; 504#L1089-3true assume 0 == ~E_3~0;~E_3~0 := 1; 662#L1094-3true assume 0 == ~E_4~0;~E_4~0 := 1; 448#L1099-3true assume 0 == ~E_5~0;~E_5~0 := 1; 733#L1104-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1085#L1109-3true assume !(0 == ~E_7~0); 719#L1114-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1204#L1119-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1344#L1124-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1237#L1129-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1118#L502-36true assume 1 == ~m_pc~0; 736#L503-12true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2#L513-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1003#is_master_triggered_returnLabel#13true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 215#L1273-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 703#L1273-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 394#L521-36true assume !(1 == ~t1_pc~0); 1098#L521-38true is_transmit1_triggered_~__retres1~1#1 := 0; 528#L532-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 999#is_transmit1_triggered_returnLabel#13true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1209#L1281-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 826#L1281-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1128#L540-36true assume !(1 == ~t2_pc~0); 42#L540-38true is_transmit2_triggered_~__retres1~2#1 := 0; 258#L551-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 827#is_transmit2_triggered_returnLabel#13true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1351#L1289-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 488#L1289-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6#L559-36true assume 1 == ~t3_pc~0; 726#L560-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 756#L570-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 353#is_transmit3_triggered_returnLabel#13true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 606#L1297-36true assume !(0 != activate_threads_~tmp___2~0#1); 894#L1297-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1250#L578-36true assume 1 == ~t4_pc~0; 579#L579-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1259#L589-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 496#is_transmit4_triggered_returnLabel#13true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1323#L1305-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 419#L1305-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 594#L597-36true assume !(1 == ~t5_pc~0); 1141#L597-38true is_transmit5_triggered_~__retres1~5#1 := 0; 1078#L608-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 967#is_transmit5_triggered_returnLabel#13true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 556#L1313-36true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 289#L1313-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1130#L616-36true assume 1 == ~t6_pc~0; 1349#L617-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37#L627-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 338#is_transmit6_triggered_returnLabel#13true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 456#L1321-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 754#L1321-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1362#L635-36true assume 1 == ~t7_pc~0; 1030#L636-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 838#L646-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 932#is_transmit7_triggered_returnLabel#13true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1284#L1329-36true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 446#L1329-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1297#L654-36true assume 1 == ~t8_pc~0; 1218#L655-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1346#L665-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 576#is_transmit8_triggered_returnLabel#13true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1190#L1337-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1145#L1337-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 231#L673-36true assume !(1 == ~t9_pc~0); 740#L673-38true is_transmit9_triggered_~__retres1~9#1 := 0; 478#L684-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 380#is_transmit9_triggered_returnLabel#13true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1050#L1345-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10#L1345-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1201#L692-36true assume !(1 == ~t10_pc~0); 112#L692-38true is_transmit10_triggered_~__retres1~10#1 := 0; 455#L703-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 278#is_transmit10_triggered_returnLabel#13true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 212#L1353-36true assume !(0 != activate_threads_~tmp___9~0#1); 454#L1353-38true havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 573#L1142-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1185#L1142-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1034#L1147-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1090#L1152-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 513#L1157-3true assume !(1 == ~T4_E~0); 834#L1162-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1088#L1167-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1011#L1172-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 444#L1177-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 374#L1182-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 867#L1187-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 384#L1192-3true assume 1 == ~E_M~0;~E_M~0 := 2; 266#L1197-3true assume !(1 == ~E_1~0); 433#L1202-3true assume 1 == ~E_2~0;~E_2~0 := 2; 522#L1207-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1126#L1212-3true assume 1 == ~E_4~0;~E_4~0 := 2; 731#L1217-3true assume 1 == ~E_5~0;~E_5~0 := 2; 207#L1222-3true assume 1 == ~E_6~0;~E_6~0 := 2; 48#L1227-3true assume 1 == ~E_7~0;~E_7~0 := 2; 900#L1232-3true assume 1 == ~E_8~0;~E_8~0 := 2; 870#L1237-3true assume !(1 == ~E_9~0); 1310#L1242-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1264#L1247-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 945#L782-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 120#L839-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 271#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 580#L1572true assume !(0 == start_simulation_~tmp~3#1); 395#L1572-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1231#L782-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1103#L839-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 43#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1301#L1527true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4#L1534true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 499#stop_simulation_returnLabel#1true start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1371#L1585true assume !(0 != start_simulation_~tmp___0~1#1); 88#L1553-2true [2023-11-29 05:59:23,324 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:23,324 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2023-11-29 05:59:23,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:23,335 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1069628670] [2023-11-29 05:59:23,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:23,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:23,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:23,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:23,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:23,654 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1069628670] [2023-11-29 05:59:23,655 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1069628670] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:23,655 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:23,656 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:23,657 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1246862469] [2023-11-29 05:59:23,658 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:23,662 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:23,663 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:23,664 INFO L85 PathProgramCache]: Analyzing trace with hash 1194100893, now seen corresponding path program 1 times [2023-11-29 05:59:23,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:23,664 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [648415783] [2023-11-29 05:59:23,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:23,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:23,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:23,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:23,736 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:23,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [648415783] [2023-11-29 05:59:23,737 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [648415783] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:23,737 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:23,737 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 05:59:23,737 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [343293258] [2023-11-29 05:59:23,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:23,739 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:23,740 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:23,773 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:23,774 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:23,779 INFO L87 Difference]: Start difference. First operand has 1379 states, 1378 states have (on average 1.5014513788098693) internal successors, (2069), 1378 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:23,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:23,864 INFO L93 Difference]: Finished difference Result 1377 states and 2039 transitions. [2023-11-29 05:59:23,866 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1377 states and 2039 transitions. [2023-11-29 05:59:23,881 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:23,900 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1377 states to 1372 states and 2034 transitions. [2023-11-29 05:59:23,901 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-29 05:59:23,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-29 05:59:23,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2034 transitions. [2023-11-29 05:59:23,912 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:23,912 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2034 transitions. [2023-11-29 05:59:23,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2034 transitions. [2023-11-29 05:59:23,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-29 05:59:23,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4825072886297377) internal successors, (2034), 1371 states have internal predecessors, (2034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:23,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2034 transitions. [2023-11-29 05:59:24,000 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2034 transitions. [2023-11-29 05:59:24,001 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 05:59:24,005 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2034 transitions. [2023-11-29 05:59:24,005 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-29 05:59:24,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2034 transitions. [2023-11-29 05:59:24,016 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:24,016 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:24,016 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:24,020 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:24,020 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:24,021 INFO L748 eck$LassoCheckResult]: Stem: 3147#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3148#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4050#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3729#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3418#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3419#L724-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3699#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3869#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3587#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3588#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3469#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3470#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3823#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3783#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3707#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3708#L1024 assume !(0 == ~M_E~0); 3963#L1024-2 assume !(0 == ~T1_E~0); 3143#L1029-1 assume !(0 == ~T2_E~0); 3144#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3246#L1039-1 assume !(0 == ~T4_E~0); 4073#L1044-1 assume !(0 == ~T5_E~0); 3491#L1049-1 assume !(0 == ~T6_E~0); 3492#L1054-1 assume !(0 == ~T7_E~0); 3728#L1059-1 assume !(0 == ~T8_E~0); 3193#L1064-1 assume !(0 == ~T9_E~0); 3194#L1069-1 assume !(0 == ~T10_E~0); 3932#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3992#L1079-1 assume !(0 == ~E_1~0); 3965#L1084-1 assume !(0 == ~E_2~0); 3966#L1089-1 assume !(0 == ~E_3~0); 4010#L1094-1 assume !(0 == ~E_4~0); 3577#L1099-1 assume !(0 == ~E_5~0); 3578#L1104-1 assume !(0 == ~E_6~0); 3841#L1109-1 assume !(0 == ~E_7~0); 3360#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3361#L1119-1 assume !(0 == ~E_9~0); 3431#L1124-1 assume !(0 == ~E_10~0); 2847#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2848#L502 assume 1 == ~m_pc~0; 3726#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2973#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2974#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3779#L1273 assume !(0 != activate_threads_~tmp~1#1); 3780#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4103#L521 assume !(1 == ~t1_pc~0); 4038#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2898#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2863#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2864#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 2884#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2885#L540 assume 1 == ~t2_pc~0; 3976#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3688#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3356#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3357#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 4034#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3171#L559 assume 1 == ~t3_pc~0; 3172#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3449#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2800#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2801#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 2991#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2992#L578 assume !(1 == ~t4_pc~0); 3115#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3114#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2931#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2932#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3760#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3761#L597 assume 1 == ~t5_pc~0; 4119#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2918#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2919#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3961#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3709#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3710#L616 assume !(1 == ~t6_pc~0); 3725#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3724#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3332#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3333#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3567#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3568#L635 assume 1 == ~t7_pc~0; 3764#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2887#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3264#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4006#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3701#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3702#L654 assume !(1 == ~t8_pc~0); 3518#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3519#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3894#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3895#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3930#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3141#L673 assume 1 == ~t9_pc~0; 3142#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2838#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3413#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3414#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3853#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3854#L692 assume !(1 == ~t10_pc~0); 3798#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3797#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3569#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3570#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3581#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3909#L1142 assume !(1 == ~M_E~0); 3052#L1142-2 assume !(1 == ~T1_E~0); 3053#L1147-1 assume !(1 == ~T2_E~0); 3898#L1152-1 assume !(1 == ~T3_E~0); 3455#L1157-1 assume !(1 == ~T4_E~0); 3456#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3605#L1167-1 assume !(1 == ~T6_E~0); 3606#L1172-1 assume !(1 == ~T7_E~0); 4028#L1177-1 assume !(1 == ~T8_E~0); 3746#L1182-1 assume !(1 == ~T9_E~0); 3747#L1187-1 assume !(1 == ~T10_E~0); 3846#L1192-1 assume !(1 == ~E_M~0); 3312#L1197-1 assume !(1 == ~E_1~0); 3313#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3691#L1207-1 assume !(1 == ~E_3~0); 3666#L1212-1 assume !(1 == ~E_4~0); 2903#L1217-1 assume !(1 == ~E_5~0); 2904#L1222-1 assume !(1 == ~E_6~0); 3663#L1227-1 assume !(1 == ~E_7~0); 3664#L1232-1 assume !(1 == ~E_8~0); 2777#L1237-1 assume !(1 == ~E_9~0); 2778#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3727#L1247-1 assume { :end_inline_reset_delta_events } true; 2948#L1553-2 [2023-11-29 05:59:24,022 INFO L750 eck$LassoCheckResult]: Loop: 2948#L1553-2 assume !false; 2949#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3088#L999-1 assume !false; 3229#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3036#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2921#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3393#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3394#L854 assume !(0 != eval_~tmp~0#1); 3803#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3590#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3591#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4063#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3563#L1029-3 assume !(0 == ~T2_E~0); 3531#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3532#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3874#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3137#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3138#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2899#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2900#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3501#L1069-3 assume !(0 == ~T10_E~0); 3502#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3848#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3739#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3624#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3625#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3550#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3551#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3872#L1109-3 assume !(0 == ~E_7~0); 3860#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3861#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4124#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4131#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4097#L502-36 assume !(1 == ~m_pc~0); 3280#L502-38 is_master_triggered_~__retres1~0#1 := 0; 2765#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2766#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3195#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3196#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3474#L521-36 assume 1 == ~t1_pc~0; 3475#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3485#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3655#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4051#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3934#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3935#L540-36 assume !(1 == ~t2_pc~0); 2849#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2850#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3267#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3936#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3600#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2771#L559-36 assume !(1 == ~t3_pc~0); 2772#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3230#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3408#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3409#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 3748#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3988#L578-36 assume 1 == ~t4_pc~0; 3717#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3673#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3611#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3612#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3507#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3508#L597-36 assume !(1 == ~t5_pc~0); 3736#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4089#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4033#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3690#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3310#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3311#L616-36 assume 1 == ~t6_pc~0; 4100#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2843#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2844#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3388#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3560#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3889#L635-36 assume 1 == ~t7_pc~0; 4064#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3946#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3947#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4009#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3546#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3547#L654-36 assume !(1 == ~t8_pc~0); 4069#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 4070#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3713#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3714#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4104#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3221#L673-36 assume 1 == ~t9_pc~0; 3222#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3586#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3451#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3452#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2784#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2785#L692-36 assume !(1 == ~t10_pc~0); 2999#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3000#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3294#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3188#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 3189#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3557#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3706#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4071#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4072#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3637#L1157-3 assume !(1 == ~T4_E~0); 3638#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3942#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4055#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3545#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3443#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3444#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3458#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3277#L1197-3 assume !(1 == ~E_1~0); 3278#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3528#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3646#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3870#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3181#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2868#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2869#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3971#L1237-3 assume !(1 == ~E_9~0); 3972#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4134#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4020#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3019#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3020#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3284#L1572 assume !(0 == start_simulation_~tmp~3#1); 3315#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3477#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2798#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2856#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 2857#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2769#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2770#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3617#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 2948#L1553-2 [2023-11-29 05:59:24,023 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:24,023 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2023-11-29 05:59:24,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:24,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405716396] [2023-11-29 05:59:24,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:24,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:24,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:24,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:24,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:24,118 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1405716396] [2023-11-29 05:59:24,119 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1405716396] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:24,119 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:24,119 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:24,119 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [748477666] [2023-11-29 05:59:24,119 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:24,120 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:24,121 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:24,121 INFO L85 PathProgramCache]: Analyzing trace with hash 1542473243, now seen corresponding path program 1 times [2023-11-29 05:59:24,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:24,121 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052429196] [2023-11-29 05:59:24,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:24,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:24,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:24,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:24,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:24,224 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052429196] [2023-11-29 05:59:24,224 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2052429196] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:24,225 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:24,225 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:24,225 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [148461586] [2023-11-29 05:59:24,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:24,226 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:24,226 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:24,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:24,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:24,227 INFO L87 Difference]: Start difference. First operand 1372 states and 2034 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:24,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:24,265 INFO L93 Difference]: Finished difference Result 1372 states and 2033 transitions. [2023-11-29 05:59:24,265 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2033 transitions. [2023-11-29 05:59:24,277 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:24,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2033 transitions. [2023-11-29 05:59:24,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-29 05:59:24,290 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-29 05:59:24,291 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2033 transitions. [2023-11-29 05:59:24,293 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:24,293 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2033 transitions. [2023-11-29 05:59:24,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2033 transitions. [2023-11-29 05:59:24,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-29 05:59:24,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4817784256559767) internal successors, (2033), 1371 states have internal predecessors, (2033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:24,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2033 transitions. [2023-11-29 05:59:24,325 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2033 transitions. [2023-11-29 05:59:24,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 05:59:24,326 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2033 transitions. [2023-11-29 05:59:24,326 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-29 05:59:24,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2033 transitions. [2023-11-29 05:59:24,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:24,335 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:24,335 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:24,337 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:24,338 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:24,338 INFO L748 eck$LassoCheckResult]: Stem: 5898#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5899#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6800#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6801#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6480#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 6168#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6169#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6450#L729-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6620#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6337#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6338#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6220#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6221#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6574#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6534#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6457#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6458#L1024 assume !(0 == ~M_E~0); 6714#L1024-2 assume !(0 == ~T1_E~0); 5894#L1029-1 assume !(0 == ~T2_E~0); 5895#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5997#L1039-1 assume !(0 == ~T4_E~0); 6824#L1044-1 assume !(0 == ~T5_E~0); 6240#L1049-1 assume !(0 == ~T6_E~0); 6241#L1054-1 assume !(0 == ~T7_E~0); 6479#L1059-1 assume !(0 == ~T8_E~0); 5944#L1064-1 assume !(0 == ~T9_E~0); 5945#L1069-1 assume !(0 == ~T10_E~0); 6683#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6743#L1079-1 assume !(0 == ~E_1~0); 6716#L1084-1 assume !(0 == ~E_2~0); 6717#L1089-1 assume !(0 == ~E_3~0); 6761#L1094-1 assume !(0 == ~E_4~0); 6328#L1099-1 assume !(0 == ~E_5~0); 6329#L1104-1 assume !(0 == ~E_6~0); 6592#L1109-1 assume !(0 == ~E_7~0); 6111#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 6112#L1119-1 assume !(0 == ~E_9~0); 6178#L1124-1 assume !(0 == ~E_10~0); 5598#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5599#L502 assume 1 == ~m_pc~0; 6477#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5724#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5725#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6528#L1273 assume !(0 != activate_threads_~tmp~1#1); 6529#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6854#L521 assume !(1 == ~t1_pc~0); 6789#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5649#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5614#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5615#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 5635#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5636#L540 assume 1 == ~t2_pc~0; 6727#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6439#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6107#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6108#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 6785#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5922#L559 assume 1 == ~t3_pc~0; 5923#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6199#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5551#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5552#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 5742#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5743#L578 assume !(1 == ~t4_pc~0); 5861#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5860#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5681#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5682#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6509#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6510#L597 assume 1 == ~t5_pc~0; 6869#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5669#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5670#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6712#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 6459#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6460#L616 assume !(1 == ~t6_pc~0); 6474#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6473#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6083#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6084#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 6317#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6318#L635 assume 1 == ~t7_pc~0; 6514#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5638#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6013#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6757#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 6452#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6453#L654 assume !(1 == ~t8_pc~0); 6269#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6270#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6642#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6643#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 6681#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5892#L673 assume 1 == ~t9_pc~0; 5893#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5589#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6162#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6163#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 6604#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6605#L692 assume !(1 == ~t10_pc~0); 6549#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6548#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6320#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6321#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 6332#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6660#L1142 assume !(1 == ~M_E~0); 5803#L1142-2 assume !(1 == ~T1_E~0); 5804#L1147-1 assume !(1 == ~T2_E~0); 6649#L1152-1 assume !(1 == ~T3_E~0); 6206#L1157-1 assume !(1 == ~T4_E~0); 6207#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6356#L1167-1 assume !(1 == ~T6_E~0); 6357#L1172-1 assume !(1 == ~T7_E~0); 6778#L1177-1 assume !(1 == ~T8_E~0); 6497#L1182-1 assume !(1 == ~T9_E~0); 6498#L1187-1 assume !(1 == ~T10_E~0); 6597#L1192-1 assume !(1 == ~E_M~0); 6061#L1197-1 assume !(1 == ~E_1~0); 6062#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6441#L1207-1 assume !(1 == ~E_3~0); 6417#L1212-1 assume !(1 == ~E_4~0); 5654#L1217-1 assume !(1 == ~E_5~0); 5655#L1222-1 assume !(1 == ~E_6~0); 6414#L1227-1 assume !(1 == ~E_7~0); 6415#L1232-1 assume !(1 == ~E_8~0); 5528#L1237-1 assume !(1 == ~E_9~0); 5529#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 6478#L1247-1 assume { :end_inline_reset_delta_events } true; 5699#L1553-2 [2023-11-29 05:59:24,339 INFO L750 eck$LassoCheckResult]: Loop: 5699#L1553-2 assume !false; 5700#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5839#L999-1 assume !false; 5980#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5787#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5672#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6144#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6145#L854 assume !(0 != eval_~tmp~0#1); 6554#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6341#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6342#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6814#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6314#L1029-3 assume !(0 == ~T2_E~0); 6282#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6283#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6625#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5888#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5889#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5650#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5651#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6252#L1069-3 assume !(0 == ~T10_E~0); 6253#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6599#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6489#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6375#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6376#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6301#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6302#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6623#L1109-3 assume !(0 == ~E_7~0); 6611#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6612#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6875#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6882#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6848#L502-36 assume 1 == ~m_pc~0; 6626#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5516#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5517#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5946#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5947#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6225#L521-36 assume 1 == ~t1_pc~0; 6226#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6236#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6406#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6802#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6685#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6686#L540-36 assume 1 == ~t2_pc~0; 6850#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5606#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6018#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6687#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6351#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5525#L559-36 assume !(1 == ~t3_pc~0); 5526#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 5984#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6159#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6160#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 6499#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6739#L578-36 assume 1 == ~t4_pc~0; 6468#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6427#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6363#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6364#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6260#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6261#L597-36 assume !(1 == ~t5_pc~0); 6487#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 6840#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6784#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6442#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6063#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6064#L616-36 assume 1 == ~t6_pc~0; 6851#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5594#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5595#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6139#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6311#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6640#L635-36 assume !(1 == ~t7_pc~0); 6816#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 6697#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6698#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6760#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6297#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6298#L654-36 assume !(1 == ~t8_pc~0); 6820#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 6821#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6464#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6465#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6855#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5972#L673-36 assume 1 == ~t9_pc~0; 5973#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6339#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6202#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6203#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5535#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5536#L692-36 assume !(1 == ~t10_pc~0); 5750#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 5751#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6045#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5939#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 5940#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6310#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6461#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6822#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6823#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6388#L1157-3 assume !(1 == ~T4_E~0); 6389#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6693#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6806#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6296#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6194#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6195#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6209#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6028#L1197-3 assume !(1 == ~E_1~0); 6029#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6279#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6397#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6621#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5932#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5619#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5620#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6722#L1237-3 assume !(1 == ~E_9~0); 6723#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6885#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6771#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5770#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5771#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 6035#L1572 assume !(0 == start_simulation_~tmp~3#1); 6066#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6228#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5549#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5607#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 5608#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5520#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5521#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6368#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 5699#L1553-2 [2023-11-29 05:59:24,339 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:24,340 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2023-11-29 05:59:24,340 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:24,340 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364393773] [2023-11-29 05:59:24,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:24,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:24,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:24,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:24,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:24,412 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364393773] [2023-11-29 05:59:24,412 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364393773] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:24,413 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:24,413 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:24,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1402754576] [2023-11-29 05:59:24,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:24,414 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:24,414 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:24,414 INFO L85 PathProgramCache]: Analyzing trace with hash -1367151846, now seen corresponding path program 1 times [2023-11-29 05:59:24,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:24,415 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [35340727] [2023-11-29 05:59:24,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:24,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:24,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:24,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:24,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:24,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [35340727] [2023-11-29 05:59:24,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [35340727] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:24,474 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:24,474 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:24,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473869513] [2023-11-29 05:59:24,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:24,475 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:24,475 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:24,476 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:24,476 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:24,476 INFO L87 Difference]: Start difference. First operand 1372 states and 2033 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:24,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:24,501 INFO L93 Difference]: Finished difference Result 1372 states and 2032 transitions. [2023-11-29 05:59:24,502 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2032 transitions. [2023-11-29 05:59:24,508 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:24,516 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2032 transitions. [2023-11-29 05:59:24,516 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-29 05:59:24,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-29 05:59:24,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2032 transitions. [2023-11-29 05:59:24,518 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:24,518 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2032 transitions. [2023-11-29 05:59:24,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2032 transitions. [2023-11-29 05:59:24,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-29 05:59:24,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4810495626822158) internal successors, (2032), 1371 states have internal predecessors, (2032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:24,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2032 transitions. [2023-11-29 05:59:24,539 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2032 transitions. [2023-11-29 05:59:24,540 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 05:59:24,540 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2032 transitions. [2023-11-29 05:59:24,541 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-29 05:59:24,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2032 transitions. [2023-11-29 05:59:24,546 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:24,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:24,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:24,548 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:24,548 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:24,548 INFO L748 eck$LassoCheckResult]: Stem: 8649#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 8650#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9551#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9552#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9231#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 8919#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8920#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9201#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9371#L734-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9088#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9089#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8971#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8972#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9325#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9285#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9208#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9209#L1024 assume !(0 == ~M_E~0); 9465#L1024-2 assume !(0 == ~T1_E~0); 8645#L1029-1 assume !(0 == ~T2_E~0); 8646#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8748#L1039-1 assume !(0 == ~T4_E~0); 9575#L1044-1 assume !(0 == ~T5_E~0); 8991#L1049-1 assume !(0 == ~T6_E~0); 8992#L1054-1 assume !(0 == ~T7_E~0); 9230#L1059-1 assume !(0 == ~T8_E~0); 8695#L1064-1 assume !(0 == ~T9_E~0); 8696#L1069-1 assume !(0 == ~T10_E~0); 9434#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 9494#L1079-1 assume !(0 == ~E_1~0); 9467#L1084-1 assume !(0 == ~E_2~0); 9468#L1089-1 assume !(0 == ~E_3~0); 9512#L1094-1 assume !(0 == ~E_4~0); 9079#L1099-1 assume !(0 == ~E_5~0); 9080#L1104-1 assume !(0 == ~E_6~0); 9343#L1109-1 assume !(0 == ~E_7~0); 8862#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8863#L1119-1 assume !(0 == ~E_9~0); 8929#L1124-1 assume !(0 == ~E_10~0); 8349#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8350#L502 assume 1 == ~m_pc~0; 9228#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8475#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8476#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9279#L1273 assume !(0 != activate_threads_~tmp~1#1); 9280#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9605#L521 assume !(1 == ~t1_pc~0); 9540#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8400#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8365#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8366#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 8386#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8387#L540 assume 1 == ~t2_pc~0; 9478#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9190#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8858#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8859#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 9536#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8673#L559 assume 1 == ~t3_pc~0; 8674#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8950#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8302#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8303#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 8493#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8494#L578 assume !(1 == ~t4_pc~0); 8614#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8613#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8433#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8434#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9262#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9263#L597 assume 1 == ~t5_pc~0; 9620#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8420#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8421#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9463#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 9210#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9211#L616 assume !(1 == ~t6_pc~0); 9225#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9224#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8834#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8835#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 9068#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9069#L635 assume 1 == ~t7_pc~0; 9265#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8389#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8764#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9508#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 9203#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9204#L654 assume !(1 == ~t8_pc~0); 9020#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9021#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9395#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9396#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 9432#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8643#L673 assume 1 == ~t9_pc~0; 8644#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8340#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8915#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8916#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 9355#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9356#L692 assume !(1 == ~t10_pc~0); 9300#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9299#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9071#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9072#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 9083#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9411#L1142 assume !(1 == ~M_E~0); 8554#L1142-2 assume !(1 == ~T1_E~0); 8555#L1147-1 assume !(1 == ~T2_E~0); 9400#L1152-1 assume !(1 == ~T3_E~0); 8957#L1157-1 assume !(1 == ~T4_E~0); 8958#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9107#L1167-1 assume !(1 == ~T6_E~0); 9108#L1172-1 assume !(1 == ~T7_E~0); 9529#L1177-1 assume !(1 == ~T8_E~0); 9248#L1182-1 assume !(1 == ~T9_E~0); 9249#L1187-1 assume !(1 == ~T10_E~0); 9348#L1192-1 assume !(1 == ~E_M~0); 8812#L1197-1 assume !(1 == ~E_1~0); 8813#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9192#L1207-1 assume !(1 == ~E_3~0); 9168#L1212-1 assume !(1 == ~E_4~0); 8405#L1217-1 assume !(1 == ~E_5~0); 8406#L1222-1 assume !(1 == ~E_6~0); 9165#L1227-1 assume !(1 == ~E_7~0); 9166#L1232-1 assume !(1 == ~E_8~0); 8279#L1237-1 assume !(1 == ~E_9~0); 8280#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 9229#L1247-1 assume { :end_inline_reset_delta_events } true; 8450#L1553-2 [2023-11-29 05:59:24,549 INFO L750 eck$LassoCheckResult]: Loop: 8450#L1553-2 assume !false; 8451#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8590#L999-1 assume !false; 8731#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8538#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8423#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8895#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8896#L854 assume !(0 != eval_~tmp~0#1); 9305#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9092#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9093#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9565#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9065#L1029-3 assume !(0 == ~T2_E~0); 9033#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9034#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9376#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8639#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8640#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8401#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8402#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9003#L1069-3 assume !(0 == ~T10_E~0); 9004#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9350#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9240#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9126#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9127#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9052#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9053#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9374#L1109-3 assume !(0 == ~E_7~0); 9362#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9363#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9626#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9633#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9599#L502-36 assume 1 == ~m_pc~0; 9377#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8267#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8268#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8697#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8698#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8976#L521-36 assume 1 == ~t1_pc~0; 8977#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8987#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9157#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9553#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9436#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9437#L540-36 assume 1 == ~t2_pc~0; 9601#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8357#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8769#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9438#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9102#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8276#L559-36 assume !(1 == ~t3_pc~0); 8277#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 8735#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8910#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8911#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 9250#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9490#L578-36 assume 1 == ~t4_pc~0; 9219#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9178#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9114#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9115#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9011#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9012#L597-36 assume !(1 == ~t5_pc~0); 9238#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 9591#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9535#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9193#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8814#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8815#L616-36 assume 1 == ~t6_pc~0; 9602#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8345#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8346#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8890#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9062#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9391#L635-36 assume 1 == ~t7_pc~0; 9566#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9448#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9449#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9511#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9048#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9049#L654-36 assume !(1 == ~t8_pc~0); 9571#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 9572#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9215#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9216#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9606#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8723#L673-36 assume 1 == ~t9_pc~0; 8724#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9090#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8953#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8954#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8286#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8287#L692-36 assume !(1 == ~t10_pc~0); 8501#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 8502#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8796#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8690#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 8691#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9061#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9212#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9573#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9574#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9139#L1157-3 assume !(1 == ~T4_E~0); 9140#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9444#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9557#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9047#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8947#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8948#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8960#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8779#L1197-3 assume !(1 == ~E_1~0); 8780#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9030#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9148#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9372#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8683#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8370#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8371#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9473#L1237-3 assume !(1 == ~E_9~0); 9474#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9636#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9522#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8521#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8522#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8786#L1572 assume !(0 == start_simulation_~tmp~3#1); 8817#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8979#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8300#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8358#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 8359#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8271#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8272#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9119#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 8450#L1553-2 [2023-11-29 05:59:24,550 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:24,550 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2023-11-29 05:59:24,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:24,550 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2147055365] [2023-11-29 05:59:24,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:24,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:24,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:24,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:24,593 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:24,594 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2147055365] [2023-11-29 05:59:24,594 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2147055365] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:24,594 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:24,594 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:24,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1065582555] [2023-11-29 05:59:24,594 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:24,595 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:24,595 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:24,595 INFO L85 PathProgramCache]: Analyzing trace with hash -335821031, now seen corresponding path program 1 times [2023-11-29 05:59:24,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:24,596 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075727300] [2023-11-29 05:59:24,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:24,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:24,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:24,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:24,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:24,668 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075727300] [2023-11-29 05:59:24,669 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2075727300] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:24,669 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:24,669 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:24,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320913891] [2023-11-29 05:59:24,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:24,670 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:24,670 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:24,670 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:24,670 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:24,671 INFO L87 Difference]: Start difference. First operand 1372 states and 2032 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:24,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:24,704 INFO L93 Difference]: Finished difference Result 1372 states and 2031 transitions. [2023-11-29 05:59:24,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2031 transitions. [2023-11-29 05:59:24,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:24,725 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2031 transitions. [2023-11-29 05:59:24,725 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-29 05:59:24,726 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-29 05:59:24,726 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2031 transitions. [2023-11-29 05:59:24,728 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:24,728 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2031 transitions. [2023-11-29 05:59:24,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2031 transitions. [2023-11-29 05:59:24,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-29 05:59:24,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4803206997084548) internal successors, (2031), 1371 states have internal predecessors, (2031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:24,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2031 transitions. [2023-11-29 05:59:24,759 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2031 transitions. [2023-11-29 05:59:24,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 05:59:24,760 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2031 transitions. [2023-11-29 05:59:24,760 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-29 05:59:24,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2031 transitions. [2023-11-29 05:59:24,768 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:24,768 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:24,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:24,771 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:24,771 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:24,771 INFO L748 eck$LassoCheckResult]: Stem: 11400#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 11401#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 12303#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12304#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11982#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 11671#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11672#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11952#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12122#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11840#L739-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11841#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11722#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11723#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12076#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12036#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11960#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11961#L1024 assume !(0 == ~M_E~0); 12216#L1024-2 assume !(0 == ~T1_E~0); 11396#L1029-1 assume !(0 == ~T2_E~0); 11397#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11499#L1039-1 assume !(0 == ~T4_E~0); 12326#L1044-1 assume !(0 == ~T5_E~0); 11744#L1049-1 assume !(0 == ~T6_E~0); 11745#L1054-1 assume !(0 == ~T7_E~0); 11981#L1059-1 assume !(0 == ~T8_E~0); 11446#L1064-1 assume !(0 == ~T9_E~0); 11447#L1069-1 assume !(0 == ~T10_E~0); 12185#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 12245#L1079-1 assume !(0 == ~E_1~0); 12218#L1084-1 assume !(0 == ~E_2~0); 12219#L1089-1 assume !(0 == ~E_3~0); 12263#L1094-1 assume !(0 == ~E_4~0); 11830#L1099-1 assume !(0 == ~E_5~0); 11831#L1104-1 assume !(0 == ~E_6~0); 12094#L1109-1 assume !(0 == ~E_7~0); 11613#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11614#L1119-1 assume !(0 == ~E_9~0); 11684#L1124-1 assume !(0 == ~E_10~0); 11100#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11101#L502 assume 1 == ~m_pc~0; 11979#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11226#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11227#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12032#L1273 assume !(0 != activate_threads_~tmp~1#1); 12033#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12356#L521 assume !(1 == ~t1_pc~0); 12291#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11151#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11116#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11117#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 11137#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11138#L540 assume 1 == ~t2_pc~0; 12229#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11941#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11609#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11610#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 12287#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11424#L559 assume 1 == ~t3_pc~0; 11425#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11702#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11053#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11054#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 11244#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11245#L578 assume !(1 == ~t4_pc~0); 11368#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11367#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11184#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11185#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12013#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12014#L597 assume 1 == ~t5_pc~0; 12372#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11171#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11172#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12214#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 11962#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11963#L616 assume !(1 == ~t6_pc~0); 11978#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11977#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11585#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11586#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 11820#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11821#L635 assume 1 == ~t7_pc~0; 12017#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11140#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11517#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12259#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 11954#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11955#L654 assume !(1 == ~t8_pc~0); 11771#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11772#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12147#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12148#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 12183#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11394#L673 assume 1 == ~t9_pc~0; 11395#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11091#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11666#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11667#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 12106#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12107#L692 assume !(1 == ~t10_pc~0); 12051#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12050#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11822#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11823#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 11834#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12162#L1142 assume !(1 == ~M_E~0); 11305#L1142-2 assume !(1 == ~T1_E~0); 11306#L1147-1 assume !(1 == ~T2_E~0); 12151#L1152-1 assume !(1 == ~T3_E~0); 11708#L1157-1 assume !(1 == ~T4_E~0); 11709#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11858#L1167-1 assume !(1 == ~T6_E~0); 11859#L1172-1 assume !(1 == ~T7_E~0); 12281#L1177-1 assume !(1 == ~T8_E~0); 11999#L1182-1 assume !(1 == ~T9_E~0); 12000#L1187-1 assume !(1 == ~T10_E~0); 12099#L1192-1 assume !(1 == ~E_M~0); 11565#L1197-1 assume !(1 == ~E_1~0); 11566#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 11944#L1207-1 assume !(1 == ~E_3~0); 11919#L1212-1 assume !(1 == ~E_4~0); 11156#L1217-1 assume !(1 == ~E_5~0); 11157#L1222-1 assume !(1 == ~E_6~0); 11916#L1227-1 assume !(1 == ~E_7~0); 11917#L1232-1 assume !(1 == ~E_8~0); 11030#L1237-1 assume !(1 == ~E_9~0); 11031#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 11980#L1247-1 assume { :end_inline_reset_delta_events } true; 11201#L1553-2 [2023-11-29 05:59:24,771 INFO L750 eck$LassoCheckResult]: Loop: 11201#L1553-2 assume !false; 11202#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11341#L999-1 assume !false; 11482#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11289#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11174#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11646#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11647#L854 assume !(0 != eval_~tmp~0#1); 12056#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11843#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11844#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12316#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11816#L1029-3 assume !(0 == ~T2_E~0); 11784#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11785#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12127#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11390#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11391#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11152#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11153#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11754#L1069-3 assume !(0 == ~T10_E~0); 11755#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12101#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11992#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11877#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11878#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11803#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11804#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12125#L1109-3 assume !(0 == ~E_7~0); 12113#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12114#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12377#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12384#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12350#L502-36 assume 1 == ~m_pc~0; 12128#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11018#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11019#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11448#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11449#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11727#L521-36 assume 1 == ~t1_pc~0; 11728#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11738#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11908#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12302#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12187#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12188#L540-36 assume 1 == ~t2_pc~0; 12352#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11103#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11520#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12189#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11853#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11024#L559-36 assume !(1 == ~t3_pc~0); 11025#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 11483#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11661#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11662#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 12001#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12241#L578-36 assume 1 == ~t4_pc~0; 11970#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11927#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11865#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11866#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11762#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11763#L597-36 assume !(1 == ~t5_pc~0); 11989#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 12342#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12286#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11943#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11563#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11564#L616-36 assume 1 == ~t6_pc~0; 12353#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11096#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11097#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11641#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11813#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12142#L635-36 assume 1 == ~t7_pc~0; 12317#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12199#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12200#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12262#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11799#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11800#L654-36 assume !(1 == ~t8_pc~0); 12322#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 12323#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11966#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11967#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12357#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11474#L673-36 assume 1 == ~t9_pc~0; 11475#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11839#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11704#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11705#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11037#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11038#L692-36 assume !(1 == ~t10_pc~0); 11252#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 11253#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11547#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11441#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 11442#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11810#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11959#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12324#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12325#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11890#L1157-3 assume !(1 == ~T4_E~0); 11891#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12195#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12308#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11798#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11696#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11697#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11711#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11530#L1197-3 assume !(1 == ~E_1~0); 11531#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11781#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11899#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12123#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11434#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11121#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11122#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12224#L1237-3 assume !(1 == ~E_9~0); 12225#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12387#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12273#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11272#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11273#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 11537#L1572 assume !(0 == start_simulation_~tmp~3#1); 11568#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11730#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11051#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11109#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 11110#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11022#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11023#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 11870#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 11201#L1553-2 [2023-11-29 05:59:24,772 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:24,772 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2023-11-29 05:59:24,772 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:24,772 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446590905] [2023-11-29 05:59:24,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:24,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:24,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:24,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:24,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:24,823 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446590905] [2023-11-29 05:59:24,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1446590905] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:24,823 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:24,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:24,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732279671] [2023-11-29 05:59:24,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:24,824 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:24,824 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:24,824 INFO L85 PathProgramCache]: Analyzing trace with hash -335821031, now seen corresponding path program 2 times [2023-11-29 05:59:24,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:24,825 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [950153419] [2023-11-29 05:59:24,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:24,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:24,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:24,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:24,916 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:24,916 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [950153419] [2023-11-29 05:59:24,916 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [950153419] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:24,917 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:24,917 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:24,917 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126397505] [2023-11-29 05:59:24,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:24,917 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:24,918 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:24,918 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:24,918 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:24,918 INFO L87 Difference]: Start difference. First operand 1372 states and 2031 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:24,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:24,953 INFO L93 Difference]: Finished difference Result 1372 states and 2030 transitions. [2023-11-29 05:59:24,953 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2030 transitions. [2023-11-29 05:59:24,963 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:24,974 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2030 transitions. [2023-11-29 05:59:24,974 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-29 05:59:24,975 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-29 05:59:24,976 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2030 transitions. [2023-11-29 05:59:24,978 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:24,978 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2030 transitions. [2023-11-29 05:59:24,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2030 transitions. [2023-11-29 05:59:25,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-29 05:59:25,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4795918367346939) internal successors, (2030), 1371 states have internal predecessors, (2030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:25,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2030 transitions. [2023-11-29 05:59:25,009 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2030 transitions. [2023-11-29 05:59:25,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 05:59:25,010 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2030 transitions. [2023-11-29 05:59:25,010 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-29 05:59:25,010 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2030 transitions. [2023-11-29 05:59:25,018 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:25,018 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:25,018 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:25,020 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:25,021 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:25,021 INFO L748 eck$LassoCheckResult]: Stem: 14151#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14152#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 15053#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15054#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14733#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 14421#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14422#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14703#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14873#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14590#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14591#L744-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14473#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14474#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14827#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14787#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14710#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14711#L1024 assume !(0 == ~M_E~0); 14967#L1024-2 assume !(0 == ~T1_E~0); 14147#L1029-1 assume !(0 == ~T2_E~0); 14148#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14250#L1039-1 assume !(0 == ~T4_E~0); 15077#L1044-1 assume !(0 == ~T5_E~0); 14493#L1049-1 assume !(0 == ~T6_E~0); 14494#L1054-1 assume !(0 == ~T7_E~0); 14732#L1059-1 assume !(0 == ~T8_E~0); 14197#L1064-1 assume !(0 == ~T9_E~0); 14198#L1069-1 assume !(0 == ~T10_E~0); 14936#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14996#L1079-1 assume !(0 == ~E_1~0); 14969#L1084-1 assume !(0 == ~E_2~0); 14970#L1089-1 assume !(0 == ~E_3~0); 15014#L1094-1 assume !(0 == ~E_4~0); 14581#L1099-1 assume !(0 == ~E_5~0); 14582#L1104-1 assume !(0 == ~E_6~0); 14845#L1109-1 assume !(0 == ~E_7~0); 14364#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14365#L1119-1 assume !(0 == ~E_9~0); 14431#L1124-1 assume !(0 == ~E_10~0); 13851#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13852#L502 assume 1 == ~m_pc~0; 14730#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13977#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13978#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14781#L1273 assume !(0 != activate_threads_~tmp~1#1); 14782#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15107#L521 assume !(1 == ~t1_pc~0); 15042#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13902#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13867#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13868#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 13888#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13889#L540 assume 1 == ~t2_pc~0; 14980#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14692#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14360#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14361#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 15038#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14175#L559 assume 1 == ~t3_pc~0; 14176#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14452#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13804#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13805#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 13995#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13996#L578 assume !(1 == ~t4_pc~0); 14114#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14113#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13934#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13935#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14762#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14763#L597 assume 1 == ~t5_pc~0; 15122#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13922#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13923#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14965#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 14712#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14713#L616 assume !(1 == ~t6_pc~0); 14727#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14726#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14336#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14337#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 14570#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14571#L635 assume 1 == ~t7_pc~0; 14767#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13891#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14266#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15010#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 14705#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14706#L654 assume !(1 == ~t8_pc~0); 14522#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14523#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14895#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14896#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 14934#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14145#L673 assume 1 == ~t9_pc~0; 14146#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13842#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14415#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14416#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 14857#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14858#L692 assume !(1 == ~t10_pc~0); 14802#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14801#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14573#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14574#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 14585#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14913#L1142 assume !(1 == ~M_E~0); 14056#L1142-2 assume !(1 == ~T1_E~0); 14057#L1147-1 assume !(1 == ~T2_E~0); 14902#L1152-1 assume !(1 == ~T3_E~0); 14459#L1157-1 assume !(1 == ~T4_E~0); 14460#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14609#L1167-1 assume !(1 == ~T6_E~0); 14610#L1172-1 assume !(1 == ~T7_E~0); 15031#L1177-1 assume !(1 == ~T8_E~0); 14750#L1182-1 assume !(1 == ~T9_E~0); 14751#L1187-1 assume !(1 == ~T10_E~0); 14850#L1192-1 assume !(1 == ~E_M~0); 14314#L1197-1 assume !(1 == ~E_1~0); 14315#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14694#L1207-1 assume !(1 == ~E_3~0); 14670#L1212-1 assume !(1 == ~E_4~0); 13907#L1217-1 assume !(1 == ~E_5~0); 13908#L1222-1 assume !(1 == ~E_6~0); 14667#L1227-1 assume !(1 == ~E_7~0); 14668#L1232-1 assume !(1 == ~E_8~0); 13781#L1237-1 assume !(1 == ~E_9~0); 13782#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14731#L1247-1 assume { :end_inline_reset_delta_events } true; 13952#L1553-2 [2023-11-29 05:59:25,021 INFO L750 eck$LassoCheckResult]: Loop: 13952#L1553-2 assume !false; 13953#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14092#L999-1 assume !false; 14233#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14040#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13925#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14397#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14398#L854 assume !(0 != eval_~tmp~0#1); 14807#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14594#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14595#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15067#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14567#L1029-3 assume !(0 == ~T2_E~0); 14535#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14536#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14878#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14141#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14142#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13903#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13904#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14505#L1069-3 assume !(0 == ~T10_E~0); 14506#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14852#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14742#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14628#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14629#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14554#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14555#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14876#L1109-3 assume !(0 == ~E_7~0); 14864#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14865#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15128#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15135#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15101#L502-36 assume !(1 == ~m_pc~0); 14284#L502-38 is_master_triggered_~__retres1~0#1 := 0; 13769#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13770#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14199#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14200#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14478#L521-36 assume !(1 == ~t1_pc~0); 14480#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 14489#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14659#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15055#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14938#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14939#L540-36 assume !(1 == ~t2_pc~0); 13858#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 13859#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14271#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14940#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14604#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13778#L559-36 assume !(1 == ~t3_pc~0); 13779#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 14237#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14412#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14413#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 14752#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14992#L578-36 assume 1 == ~t4_pc~0; 14721#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14680#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14616#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14617#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14513#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14514#L597-36 assume !(1 == ~t5_pc~0); 14740#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 15093#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15037#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14695#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14316#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14317#L616-36 assume 1 == ~t6_pc~0; 15104#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13847#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13848#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14392#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14564#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14893#L635-36 assume 1 == ~t7_pc~0; 15068#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14950#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14951#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15013#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14550#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14551#L654-36 assume !(1 == ~t8_pc~0); 15073#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 15074#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14717#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14718#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15108#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14225#L673-36 assume 1 == ~t9_pc~0; 14226#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14592#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14455#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14456#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13788#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13789#L692-36 assume !(1 == ~t10_pc~0); 14003#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 14004#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14298#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14192#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 14193#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14563#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14714#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15075#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15076#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14641#L1157-3 assume !(1 == ~T4_E~0); 14642#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14946#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15059#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14549#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14447#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14448#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14462#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14281#L1197-3 assume !(1 == ~E_1~0); 14282#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14532#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14650#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14874#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14185#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13872#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13873#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14975#L1237-3 assume !(1 == ~E_9~0); 14976#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15138#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 15024#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14023#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14024#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 14288#L1572 assume !(0 == start_simulation_~tmp~3#1); 14319#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14481#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13802#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13860#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 13861#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13773#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13774#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14621#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 13952#L1553-2 [2023-11-29 05:59:25,022 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:25,022 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2023-11-29 05:59:25,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:25,022 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658229695] [2023-11-29 05:59:25,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:25,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:25,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:25,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:25,071 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:25,072 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658229695] [2023-11-29 05:59:25,072 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1658229695] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:25,072 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:25,072 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:25,072 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [765364629] [2023-11-29 05:59:25,072 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:25,073 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:25,073 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:25,073 INFO L85 PathProgramCache]: Analyzing trace with hash 1415396764, now seen corresponding path program 1 times [2023-11-29 05:59:25,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:25,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638237300] [2023-11-29 05:59:25,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:25,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:25,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:25,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:25,138 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:25,138 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1638237300] [2023-11-29 05:59:25,139 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1638237300] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:25,139 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:25,139 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:25,139 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1188360624] [2023-11-29 05:59:25,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:25,140 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:25,140 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:25,140 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:25,140 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:25,140 INFO L87 Difference]: Start difference. First operand 1372 states and 2030 transitions. cyclomatic complexity: 659 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:25,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:25,175 INFO L93 Difference]: Finished difference Result 1372 states and 2029 transitions. [2023-11-29 05:59:25,175 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2029 transitions. [2023-11-29 05:59:25,185 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:25,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2029 transitions. [2023-11-29 05:59:25,197 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-29 05:59:25,198 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-29 05:59:25,198 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2029 transitions. [2023-11-29 05:59:25,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:25,200 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2029 transitions. [2023-11-29 05:59:25,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2029 transitions. [2023-11-29 05:59:25,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-29 05:59:25,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.478862973760933) internal successors, (2029), 1371 states have internal predecessors, (2029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:25,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2029 transitions. [2023-11-29 05:59:25,232 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2029 transitions. [2023-11-29 05:59:25,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 05:59:25,233 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2029 transitions. [2023-11-29 05:59:25,233 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-29 05:59:25,233 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2029 transitions. [2023-11-29 05:59:25,240 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:25,240 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:25,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:25,243 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:25,243 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:25,243 INFO L748 eck$LassoCheckResult]: Stem: 16902#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 16903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 17804#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17805#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17484#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 17172#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17173#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17454#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17624#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17341#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17342#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17224#L749-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17225#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17578#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17538#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17461#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17462#L1024 assume !(0 == ~M_E~0); 17718#L1024-2 assume !(0 == ~T1_E~0); 16898#L1029-1 assume !(0 == ~T2_E~0); 16899#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17001#L1039-1 assume !(0 == ~T4_E~0); 17828#L1044-1 assume !(0 == ~T5_E~0); 17244#L1049-1 assume !(0 == ~T6_E~0); 17245#L1054-1 assume !(0 == ~T7_E~0); 17483#L1059-1 assume !(0 == ~T8_E~0); 16948#L1064-1 assume !(0 == ~T9_E~0); 16949#L1069-1 assume !(0 == ~T10_E~0); 17687#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 17747#L1079-1 assume !(0 == ~E_1~0); 17720#L1084-1 assume !(0 == ~E_2~0); 17721#L1089-1 assume !(0 == ~E_3~0); 17765#L1094-1 assume !(0 == ~E_4~0); 17332#L1099-1 assume !(0 == ~E_5~0); 17333#L1104-1 assume !(0 == ~E_6~0); 17596#L1109-1 assume !(0 == ~E_7~0); 17115#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 17116#L1119-1 assume !(0 == ~E_9~0); 17182#L1124-1 assume !(0 == ~E_10~0); 16602#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16603#L502 assume 1 == ~m_pc~0; 17481#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16728#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16729#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17532#L1273 assume !(0 != activate_threads_~tmp~1#1); 17533#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17858#L521 assume !(1 == ~t1_pc~0); 17793#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16653#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16618#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16619#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 16639#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16640#L540 assume 1 == ~t2_pc~0; 17731#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17443#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17111#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17112#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 17789#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16926#L559 assume 1 == ~t3_pc~0; 16927#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17203#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16555#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16556#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 16746#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16747#L578 assume !(1 == ~t4_pc~0); 16868#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16867#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16686#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16687#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17515#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17516#L597 assume 1 == ~t5_pc~0; 17873#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16673#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16674#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17716#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 17463#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17464#L616 assume !(1 == ~t6_pc~0); 17478#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17477#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17087#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17088#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 17321#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17322#L635 assume 1 == ~t7_pc~0; 17518#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16642#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17017#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17761#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 17456#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17457#L654 assume !(1 == ~t8_pc~0); 17273#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17274#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17648#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17649#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 17685#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16896#L673 assume 1 == ~t9_pc~0; 16897#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16593#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17168#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17169#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 17608#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17609#L692 assume !(1 == ~t10_pc~0); 17553#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17552#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17324#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17325#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 17336#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17664#L1142 assume !(1 == ~M_E~0); 16807#L1142-2 assume !(1 == ~T1_E~0); 16808#L1147-1 assume !(1 == ~T2_E~0); 17653#L1152-1 assume !(1 == ~T3_E~0); 17210#L1157-1 assume !(1 == ~T4_E~0); 17211#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17360#L1167-1 assume !(1 == ~T6_E~0); 17361#L1172-1 assume !(1 == ~T7_E~0); 17782#L1177-1 assume !(1 == ~T8_E~0); 17501#L1182-1 assume !(1 == ~T9_E~0); 17502#L1187-1 assume !(1 == ~T10_E~0); 17601#L1192-1 assume !(1 == ~E_M~0); 17065#L1197-1 assume !(1 == ~E_1~0); 17066#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17445#L1207-1 assume !(1 == ~E_3~0); 17421#L1212-1 assume !(1 == ~E_4~0); 16658#L1217-1 assume !(1 == ~E_5~0); 16659#L1222-1 assume !(1 == ~E_6~0); 17418#L1227-1 assume !(1 == ~E_7~0); 17419#L1232-1 assume !(1 == ~E_8~0); 16532#L1237-1 assume !(1 == ~E_9~0); 16533#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 17482#L1247-1 assume { :end_inline_reset_delta_events } true; 16703#L1553-2 [2023-11-29 05:59:25,244 INFO L750 eck$LassoCheckResult]: Loop: 16703#L1553-2 assume !false; 16704#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16843#L999-1 assume !false; 16984#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16791#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16676#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17148#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17149#L854 assume !(0 != eval_~tmp~0#1); 17558#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17345#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17346#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17818#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17318#L1029-3 assume !(0 == ~T2_E~0); 17286#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17287#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17629#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16892#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16893#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16654#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16655#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17256#L1069-3 assume !(0 == ~T10_E~0); 17257#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17603#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17493#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17379#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17380#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17305#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17306#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17627#L1109-3 assume !(0 == ~E_7~0); 17615#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17616#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17879#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17886#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17852#L502-36 assume !(1 == ~m_pc~0); 17035#L502-38 is_master_triggered_~__retres1~0#1 := 0; 16520#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16521#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16950#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16951#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17229#L521-36 assume 1 == ~t1_pc~0; 17230#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17240#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17410#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17806#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17689#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17690#L540-36 assume !(1 == ~t2_pc~0); 16609#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 16610#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17022#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17691#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17355#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16529#L559-36 assume !(1 == ~t3_pc~0); 16530#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 16988#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17163#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17164#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 17503#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17743#L578-36 assume 1 == ~t4_pc~0; 17473#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17431#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17367#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17368#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17264#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17265#L597-36 assume !(1 == ~t5_pc~0); 17491#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 17844#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17788#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17446#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17067#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17068#L616-36 assume !(1 == ~t6_pc~0); 17814#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 16598#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16599#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17143#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17315#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17644#L635-36 assume 1 == ~t7_pc~0; 17819#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17701#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17702#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17764#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17301#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17302#L654-36 assume !(1 == ~t8_pc~0); 17824#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 17825#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17468#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17469#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17859#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16976#L673-36 assume 1 == ~t9_pc~0; 16977#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17343#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17206#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17207#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16539#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16540#L692-36 assume !(1 == ~t10_pc~0); 16754#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 16755#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17049#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16943#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 16944#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17314#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17465#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17826#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17827#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17392#L1157-3 assume !(1 == ~T4_E~0); 17393#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17697#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17811#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17300#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17200#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17201#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17213#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17032#L1197-3 assume !(1 == ~E_1~0); 17033#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17283#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17401#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17626#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16936#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16623#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16624#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17726#L1237-3 assume !(1 == ~E_9~0); 17727#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17889#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17775#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16774#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16775#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 17039#L1572 assume !(0 == start_simulation_~tmp~3#1); 17070#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17232#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16553#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16611#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 16612#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16524#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16525#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17372#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 16703#L1553-2 [2023-11-29 05:59:25,244 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:25,244 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2023-11-29 05:59:25,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:25,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094240923] [2023-11-29 05:59:25,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:25,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:25,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:25,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:25,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:25,295 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2094240923] [2023-11-29 05:59:25,295 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2094240923] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:25,295 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:25,295 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:25,295 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879119114] [2023-11-29 05:59:25,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:25,296 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:25,296 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:25,297 INFO L85 PathProgramCache]: Analyzing trace with hash 1920116060, now seen corresponding path program 1 times [2023-11-29 05:59:25,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:25,297 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355516826] [2023-11-29 05:59:25,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:25,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:25,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:25,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:25,363 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:25,363 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355516826] [2023-11-29 05:59:25,363 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355516826] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:25,363 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:25,364 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:25,364 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [290054496] [2023-11-29 05:59:25,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:25,364 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:25,364 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:25,365 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:25,365 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:25,365 INFO L87 Difference]: Start difference. First operand 1372 states and 2029 transitions. cyclomatic complexity: 658 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:25,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:25,399 INFO L93 Difference]: Finished difference Result 1372 states and 2028 transitions. [2023-11-29 05:59:25,399 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2028 transitions. [2023-11-29 05:59:25,407 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:25,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2028 transitions. [2023-11-29 05:59:25,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-29 05:59:25,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-29 05:59:25,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2028 transitions. [2023-11-29 05:59:25,421 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:25,421 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2028 transitions. [2023-11-29 05:59:25,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2028 transitions. [2023-11-29 05:59:25,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-29 05:59:25,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.478134110787172) internal successors, (2028), 1371 states have internal predecessors, (2028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:25,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2028 transitions. [2023-11-29 05:59:25,491 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2028 transitions. [2023-11-29 05:59:25,492 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 05:59:25,493 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2028 transitions. [2023-11-29 05:59:25,493 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-29 05:59:25,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2028 transitions. [2023-11-29 05:59:25,498 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:25,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:25,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:25,501 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:25,501 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:25,501 INFO L748 eck$LassoCheckResult]: Stem: 19653#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 19654#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 20556#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20557#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20235#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 19924#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19925#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20206#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20375#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20093#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20094#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19978#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19979#L754-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20329#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20289#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20213#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20214#L1024 assume !(0 == ~M_E~0); 20469#L1024-2 assume !(0 == ~T1_E~0); 19649#L1029-1 assume !(0 == ~T2_E~0); 19650#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19752#L1039-1 assume !(0 == ~T4_E~0); 20579#L1044-1 assume !(0 == ~T5_E~0); 19997#L1049-1 assume !(0 == ~T6_E~0); 19998#L1054-1 assume !(0 == ~T7_E~0); 20234#L1059-1 assume !(0 == ~T8_E~0); 19699#L1064-1 assume !(0 == ~T9_E~0); 19700#L1069-1 assume !(0 == ~T10_E~0); 20438#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 20498#L1079-1 assume !(0 == ~E_1~0); 20471#L1084-1 assume !(0 == ~E_2~0); 20472#L1089-1 assume !(0 == ~E_3~0); 20516#L1094-1 assume !(0 == ~E_4~0); 20083#L1099-1 assume !(0 == ~E_5~0); 20084#L1104-1 assume !(0 == ~E_6~0); 20347#L1109-1 assume !(0 == ~E_7~0); 19866#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19867#L1119-1 assume !(0 == ~E_9~0); 19937#L1124-1 assume !(0 == ~E_10~0); 19353#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19354#L502 assume 1 == ~m_pc~0; 20232#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19479#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19480#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20285#L1273 assume !(0 != activate_threads_~tmp~1#1); 20286#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20609#L521 assume !(1 == ~t1_pc~0); 20544#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19404#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19369#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19370#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 19390#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19391#L540 assume 1 == ~t2_pc~0; 20482#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20194#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19864#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19865#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 20540#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19677#L559 assume 1 == ~t3_pc~0; 19678#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19955#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19306#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19307#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 19497#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19498#L578 assume !(1 == ~t4_pc~0); 19621#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 19620#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19437#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19438#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20266#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20267#L597 assume 1 == ~t5_pc~0; 20625#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19424#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19425#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20467#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 20215#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20216#L616 assume !(1 == ~t6_pc~0); 20231#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 20230#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19838#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19839#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 20073#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20074#L635 assume 1 == ~t7_pc~0; 20270#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19393#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19770#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20512#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 20207#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20208#L654 assume !(1 == ~t8_pc~0); 20024#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20025#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20400#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20401#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 20436#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19647#L673 assume 1 == ~t9_pc~0; 19648#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19344#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19919#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19920#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 20359#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20360#L692 assume !(1 == ~t10_pc~0); 20304#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20303#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20075#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20076#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 20087#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20415#L1142 assume !(1 == ~M_E~0); 19558#L1142-2 assume !(1 == ~T1_E~0); 19559#L1147-1 assume !(1 == ~T2_E~0); 20404#L1152-1 assume !(1 == ~T3_E~0); 19961#L1157-1 assume !(1 == ~T4_E~0); 19962#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20111#L1167-1 assume !(1 == ~T6_E~0); 20112#L1172-1 assume !(1 == ~T7_E~0); 20534#L1177-1 assume !(1 == ~T8_E~0); 20252#L1182-1 assume !(1 == ~T9_E~0); 20253#L1187-1 assume !(1 == ~T10_E~0); 20352#L1192-1 assume !(1 == ~E_M~0); 19818#L1197-1 assume !(1 == ~E_1~0); 19819#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20197#L1207-1 assume !(1 == ~E_3~0); 20172#L1212-1 assume !(1 == ~E_4~0); 19409#L1217-1 assume !(1 == ~E_5~0); 19410#L1222-1 assume !(1 == ~E_6~0); 20169#L1227-1 assume !(1 == ~E_7~0); 20170#L1232-1 assume !(1 == ~E_8~0); 19283#L1237-1 assume !(1 == ~E_9~0); 19284#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 20233#L1247-1 assume { :end_inline_reset_delta_events } true; 19454#L1553-2 [2023-11-29 05:59:25,502 INFO L750 eck$LassoCheckResult]: Loop: 19454#L1553-2 assume !false; 19455#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19594#L999-1 assume !false; 19735#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19542#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19427#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19899#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19900#L854 assume !(0 != eval_~tmp~0#1); 20309#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20096#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20097#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20569#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20069#L1029-3 assume !(0 == ~T2_E~0); 20037#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20038#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20380#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19643#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19644#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19405#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19406#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20007#L1069-3 assume !(0 == ~T10_E~0); 20008#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20354#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20245#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20130#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20131#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20056#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20057#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20378#L1109-3 assume !(0 == ~E_7~0); 20366#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20367#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20630#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20637#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20603#L502-36 assume !(1 == ~m_pc~0); 19786#L502-38 is_master_triggered_~__retres1~0#1 := 0; 19271#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19272#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19701#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19702#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19975#L521-36 assume 1 == ~t1_pc~0; 19976#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19991#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20161#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20555#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20440#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20441#L540-36 assume 1 == ~t2_pc~0; 20605#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19358#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19773#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20442#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20106#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19277#L559-36 assume !(1 == ~t3_pc~0); 19278#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 19739#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19914#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19915#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 20254#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20494#L578-36 assume !(1 == ~t4_pc~0); 20179#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 20180#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20118#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20119#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20015#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20016#L597-36 assume !(1 == ~t5_pc~0); 20242#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 20595#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20539#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20196#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19816#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19817#L616-36 assume !(1 == ~t6_pc~0); 20565#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 19349#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19350#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19894#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20066#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20395#L635-36 assume 1 == ~t7_pc~0; 20570#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20452#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20453#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20515#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20052#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20053#L654-36 assume 1 == ~t8_pc~0; 20633#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20576#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20219#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20220#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20610#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19727#L673-36 assume 1 == ~t9_pc~0; 19728#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20092#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19957#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19958#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19290#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19291#L692-36 assume !(1 == ~t10_pc~0); 19505#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 19506#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19800#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19694#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 19695#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20063#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20212#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20577#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20578#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20143#L1157-3 assume !(1 == ~T4_E~0); 20144#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20448#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20561#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20051#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19949#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19950#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19964#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19783#L1197-3 assume !(1 == ~E_1~0); 19784#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20034#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20152#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20376#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19687#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19374#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19375#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20477#L1237-3 assume !(1 == ~E_9~0); 20478#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20640#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20526#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19525#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19526#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 19790#L1572 assume !(0 == start_simulation_~tmp~3#1); 19821#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19983#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19304#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19362#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 19363#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19275#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19276#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 20123#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 19454#L1553-2 [2023-11-29 05:59:25,502 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:25,502 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2023-11-29 05:59:25,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:25,503 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027319110] [2023-11-29 05:59:25,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:25,503 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:25,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:25,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:25,554 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:25,554 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027319110] [2023-11-29 05:59:25,554 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2027319110] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:25,554 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:25,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:25,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [173741817] [2023-11-29 05:59:25,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:25,555 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:25,555 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:25,556 INFO L85 PathProgramCache]: Analyzing trace with hash 1738262043, now seen corresponding path program 1 times [2023-11-29 05:59:25,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:25,556 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984675369] [2023-11-29 05:59:25,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:25,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:25,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:25,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:25,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:25,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [984675369] [2023-11-29 05:59:25,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [984675369] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:25,620 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:25,620 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:25,620 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1516287634] [2023-11-29 05:59:25,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:25,620 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:25,621 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:25,621 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:25,621 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:25,621 INFO L87 Difference]: Start difference. First operand 1372 states and 2028 transitions. cyclomatic complexity: 657 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:25,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:25,656 INFO L93 Difference]: Finished difference Result 1372 states and 2027 transitions. [2023-11-29 05:59:25,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2027 transitions. [2023-11-29 05:59:25,664 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:25,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2027 transitions. [2023-11-29 05:59:25,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-29 05:59:25,677 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-29 05:59:25,677 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2027 transitions. [2023-11-29 05:59:25,679 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:25,679 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2027 transitions. [2023-11-29 05:59:25,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2027 transitions. [2023-11-29 05:59:25,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-29 05:59:25,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.477405247813411) internal successors, (2027), 1371 states have internal predecessors, (2027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:25,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2027 transitions. [2023-11-29 05:59:25,712 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2027 transitions. [2023-11-29 05:59:25,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 05:59:25,713 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2027 transitions. [2023-11-29 05:59:25,713 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-29 05:59:25,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2027 transitions. [2023-11-29 05:59:25,719 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:25,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:25,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:25,721 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:25,722 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:25,722 INFO L748 eck$LassoCheckResult]: Stem: 22404#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22405#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 23306#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23307#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22986#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 22674#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22675#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22956#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23126#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22843#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22844#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22726#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22727#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 23080#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 23040#L764-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22963#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22964#L1024 assume !(0 == ~M_E~0); 23220#L1024-2 assume !(0 == ~T1_E~0); 22400#L1029-1 assume !(0 == ~T2_E~0); 22401#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22503#L1039-1 assume !(0 == ~T4_E~0); 23330#L1044-1 assume !(0 == ~T5_E~0); 22746#L1049-1 assume !(0 == ~T6_E~0); 22747#L1054-1 assume !(0 == ~T7_E~0); 22985#L1059-1 assume !(0 == ~T8_E~0); 22450#L1064-1 assume !(0 == ~T9_E~0); 22451#L1069-1 assume !(0 == ~T10_E~0); 23189#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 23249#L1079-1 assume !(0 == ~E_1~0); 23222#L1084-1 assume !(0 == ~E_2~0); 23223#L1089-1 assume !(0 == ~E_3~0); 23267#L1094-1 assume !(0 == ~E_4~0); 22834#L1099-1 assume !(0 == ~E_5~0); 22835#L1104-1 assume !(0 == ~E_6~0); 23098#L1109-1 assume !(0 == ~E_7~0); 22617#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 22618#L1119-1 assume !(0 == ~E_9~0); 22684#L1124-1 assume !(0 == ~E_10~0); 22104#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22105#L502 assume 1 == ~m_pc~0; 22983#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22230#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22231#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23034#L1273 assume !(0 != activate_threads_~tmp~1#1); 23035#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23360#L521 assume !(1 == ~t1_pc~0); 23295#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22155#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22120#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22121#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 22141#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22142#L540 assume 1 == ~t2_pc~0; 23233#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22945#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22613#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22614#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 23291#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22428#L559 assume 1 == ~t3_pc~0; 22429#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22705#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22057#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22058#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 22248#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22249#L578 assume !(1 == ~t4_pc~0); 22367#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22366#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22187#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22188#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23015#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23016#L597 assume 1 == ~t5_pc~0; 23375#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22175#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22176#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23218#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 22965#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22966#L616 assume !(1 == ~t6_pc~0); 22980#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22979#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22589#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22590#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 22823#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22824#L635 assume 1 == ~t7_pc~0; 23020#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22144#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22519#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23263#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 22958#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22959#L654 assume !(1 == ~t8_pc~0); 22775#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22776#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23148#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23149#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 23187#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22398#L673 assume 1 == ~t9_pc~0; 22399#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22095#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22668#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22669#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 23110#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23111#L692 assume !(1 == ~t10_pc~0); 23055#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23054#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22826#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22827#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 22838#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23166#L1142 assume !(1 == ~M_E~0); 22309#L1142-2 assume !(1 == ~T1_E~0); 22310#L1147-1 assume !(1 == ~T2_E~0); 23155#L1152-1 assume !(1 == ~T3_E~0); 22712#L1157-1 assume !(1 == ~T4_E~0); 22713#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22862#L1167-1 assume !(1 == ~T6_E~0); 22863#L1172-1 assume !(1 == ~T7_E~0); 23284#L1177-1 assume !(1 == ~T8_E~0); 23003#L1182-1 assume !(1 == ~T9_E~0); 23004#L1187-1 assume !(1 == ~T10_E~0); 23103#L1192-1 assume !(1 == ~E_M~0); 22567#L1197-1 assume !(1 == ~E_1~0); 22568#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22947#L1207-1 assume !(1 == ~E_3~0); 22923#L1212-1 assume !(1 == ~E_4~0); 22160#L1217-1 assume !(1 == ~E_5~0); 22161#L1222-1 assume !(1 == ~E_6~0); 22920#L1227-1 assume !(1 == ~E_7~0); 22921#L1232-1 assume !(1 == ~E_8~0); 22034#L1237-1 assume !(1 == ~E_9~0); 22035#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22984#L1247-1 assume { :end_inline_reset_delta_events } true; 22205#L1553-2 [2023-11-29 05:59:25,722 INFO L750 eck$LassoCheckResult]: Loop: 22205#L1553-2 assume !false; 22206#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22345#L999-1 assume !false; 22486#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22293#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22178#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22650#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22651#L854 assume !(0 != eval_~tmp~0#1); 23060#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22847#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22848#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23320#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22820#L1029-3 assume !(0 == ~T2_E~0); 22788#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22789#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23131#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22394#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22395#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22156#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22157#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22758#L1069-3 assume !(0 == ~T10_E~0); 22759#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23105#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22995#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22881#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22882#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22807#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22808#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23129#L1109-3 assume !(0 == ~E_7~0); 23117#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23118#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23381#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23388#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23354#L502-36 assume !(1 == ~m_pc~0); 22537#L502-38 is_master_triggered_~__retres1~0#1 := 0; 22022#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22023#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22452#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22453#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22731#L521-36 assume 1 == ~t1_pc~0; 22732#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22742#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22912#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23308#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23191#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23192#L540-36 assume 1 == ~t2_pc~0; 23356#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22112#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22524#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23193#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22857#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22031#L559-36 assume !(1 == ~t3_pc~0); 22032#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 22490#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22665#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22666#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 23005#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23245#L578-36 assume !(1 == ~t4_pc~0); 22932#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 22933#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22869#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22870#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22766#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22767#L597-36 assume !(1 == ~t5_pc~0); 22993#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 23346#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23290#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22948#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22569#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22570#L616-36 assume !(1 == ~t6_pc~0); 23316#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 22100#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22101#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22645#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22817#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23146#L635-36 assume 1 == ~t7_pc~0; 23321#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23203#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23204#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23266#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22803#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22804#L654-36 assume 1 == ~t8_pc~0; 23384#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23327#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22970#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22971#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23361#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22478#L673-36 assume !(1 == ~t9_pc~0); 22480#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 22845#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22708#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22709#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22041#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22042#L692-36 assume !(1 == ~t10_pc~0); 22256#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 22257#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22551#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22445#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 22446#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22816#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22967#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23328#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23329#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22894#L1157-3 assume !(1 == ~T4_E~0); 22895#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23199#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23312#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22802#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22700#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22701#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22715#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22534#L1197-3 assume !(1 == ~E_1~0); 22535#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22785#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22903#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23127#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22438#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22125#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22126#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23228#L1237-3 assume !(1 == ~E_9~0); 23229#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23391#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23277#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22276#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22277#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 22541#L1572 assume !(0 == start_simulation_~tmp~3#1); 22572#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22734#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22055#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22113#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 22114#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22026#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22027#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 22874#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 22205#L1553-2 [2023-11-29 05:59:25,723 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:25,723 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2023-11-29 05:59:25,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:25,723 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613598716] [2023-11-29 05:59:25,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:25,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:25,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:25,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:25,782 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:25,782 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613598716] [2023-11-29 05:59:25,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [613598716] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:25,782 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:25,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:25,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1521043966] [2023-11-29 05:59:25,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:25,783 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:25,784 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:25,784 INFO L85 PathProgramCache]: Analyzing trace with hash -155180132, now seen corresponding path program 1 times [2023-11-29 05:59:25,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:25,784 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [980360608] [2023-11-29 05:59:25,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:25,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:25,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:25,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:25,847 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:25,847 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [980360608] [2023-11-29 05:59:25,847 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [980360608] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:25,848 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:25,848 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:25,848 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1794588697] [2023-11-29 05:59:25,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:25,848 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:25,848 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:25,849 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:25,849 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:25,849 INFO L87 Difference]: Start difference. First operand 1372 states and 2027 transitions. cyclomatic complexity: 656 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:25,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:25,883 INFO L93 Difference]: Finished difference Result 1372 states and 2026 transitions. [2023-11-29 05:59:25,883 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2026 transitions. [2023-11-29 05:59:25,891 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:25,901 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1372 states and 2026 transitions. [2023-11-29 05:59:25,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1372 [2023-11-29 05:59:25,903 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1372 [2023-11-29 05:59:25,903 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1372 states and 2026 transitions. [2023-11-29 05:59:25,905 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:25,906 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2026 transitions. [2023-11-29 05:59:25,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states and 2026 transitions. [2023-11-29 05:59:25,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1372. [2023-11-29 05:59:25,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1372 states, 1372 states have (on average 1.4766763848396502) internal successors, (2026), 1371 states have internal predecessors, (2026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:25,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1372 states to 1372 states and 2026 transitions. [2023-11-29 05:59:25,936 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1372 states and 2026 transitions. [2023-11-29 05:59:25,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 05:59:25,937 INFO L428 stractBuchiCegarLoop]: Abstraction has 1372 states and 2026 transitions. [2023-11-29 05:59:25,937 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-29 05:59:25,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1372 states and 2026 transitions. [2023-11-29 05:59:25,943 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1233 [2023-11-29 05:59:25,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:25,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:25,945 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:25,945 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:25,946 INFO L748 eck$LassoCheckResult]: Stem: 25155#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 26057#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26058#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25737#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 25425#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25426#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25707#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25877#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25595#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25596#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25477#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25478#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25831#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25791#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 25715#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25716#L1024 assume !(0 == ~M_E~0); 25971#L1024-2 assume !(0 == ~T1_E~0); 25151#L1029-1 assume !(0 == ~T2_E~0); 25152#L1034-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25254#L1039-1 assume !(0 == ~T4_E~0); 26081#L1044-1 assume !(0 == ~T5_E~0); 25497#L1049-1 assume !(0 == ~T6_E~0); 25498#L1054-1 assume !(0 == ~T7_E~0); 25736#L1059-1 assume !(0 == ~T8_E~0); 25201#L1064-1 assume !(0 == ~T9_E~0); 25202#L1069-1 assume !(0 == ~T10_E~0); 25940#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 26000#L1079-1 assume !(0 == ~E_1~0); 25973#L1084-1 assume !(0 == ~E_2~0); 25974#L1089-1 assume !(0 == ~E_3~0); 26018#L1094-1 assume !(0 == ~E_4~0); 25585#L1099-1 assume !(0 == ~E_5~0); 25586#L1104-1 assume !(0 == ~E_6~0); 25849#L1109-1 assume !(0 == ~E_7~0); 25368#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25369#L1119-1 assume !(0 == ~E_9~0); 25435#L1124-1 assume !(0 == ~E_10~0); 24855#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24856#L502 assume 1 == ~m_pc~0; 25734#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24981#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24982#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25785#L1273 assume !(0 != activate_threads_~tmp~1#1); 25786#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26111#L521 assume !(1 == ~t1_pc~0); 26046#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24906#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24871#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24872#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 24892#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24893#L540 assume 1 == ~t2_pc~0; 25984#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25696#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25364#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25365#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 26042#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25179#L559 assume 1 == ~t3_pc~0; 25180#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25456#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24808#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24809#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 24999#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25000#L578 assume !(1 == ~t4_pc~0); 25121#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25120#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24939#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24940#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25768#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25769#L597 assume 1 == ~t5_pc~0; 26126#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24926#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24927#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25969#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 25717#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25718#L616 assume !(1 == ~t6_pc~0); 25731#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25730#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25340#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25341#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 25574#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25575#L635 assume 1 == ~t7_pc~0; 25771#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24895#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25270#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26014#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 25709#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25710#L654 assume !(1 == ~t8_pc~0); 25526#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25527#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25901#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25902#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 25938#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25149#L673 assume 1 == ~t9_pc~0; 25150#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24846#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25421#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25422#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 25861#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25862#L692 assume !(1 == ~t10_pc~0); 25806#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25805#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25577#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25578#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 25589#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25917#L1142 assume !(1 == ~M_E~0); 25060#L1142-2 assume !(1 == ~T1_E~0); 25061#L1147-1 assume !(1 == ~T2_E~0); 25906#L1152-1 assume !(1 == ~T3_E~0); 25463#L1157-1 assume !(1 == ~T4_E~0); 25464#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25613#L1167-1 assume !(1 == ~T6_E~0); 25614#L1172-1 assume !(1 == ~T7_E~0); 26035#L1177-1 assume !(1 == ~T8_E~0); 25754#L1182-1 assume !(1 == ~T9_E~0); 25755#L1187-1 assume !(1 == ~T10_E~0); 25854#L1192-1 assume !(1 == ~E_M~0); 25318#L1197-1 assume !(1 == ~E_1~0); 25319#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25698#L1207-1 assume !(1 == ~E_3~0); 25674#L1212-1 assume !(1 == ~E_4~0); 24911#L1217-1 assume !(1 == ~E_5~0); 24912#L1222-1 assume !(1 == ~E_6~0); 25671#L1227-1 assume !(1 == ~E_7~0); 25672#L1232-1 assume !(1 == ~E_8~0); 24785#L1237-1 assume !(1 == ~E_9~0); 24786#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 25735#L1247-1 assume { :end_inline_reset_delta_events } true; 24956#L1553-2 [2023-11-29 05:59:25,946 INFO L750 eck$LassoCheckResult]: Loop: 24956#L1553-2 assume !false; 24957#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25096#L999-1 assume !false; 25237#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25044#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24929#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25401#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25402#L854 assume !(0 != eval_~tmp~0#1); 25811#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25598#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25599#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26071#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25571#L1029-3 assume !(0 == ~T2_E~0); 25539#L1034-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25540#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25882#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25145#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25146#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24907#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24908#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25509#L1069-3 assume !(0 == ~T10_E~0); 25510#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25856#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25747#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25632#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25633#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25558#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25559#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25880#L1109-3 assume !(0 == ~E_7~0); 25868#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25869#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26132#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26139#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26105#L502-36 assume !(1 == ~m_pc~0); 25288#L502-38 is_master_triggered_~__retres1~0#1 := 0; 24773#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24774#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25203#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25204#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25482#L521-36 assume 1 == ~t1_pc~0; 25483#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25493#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25663#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26059#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25942#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25943#L540-36 assume 1 == ~t2_pc~0; 26107#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24863#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25275#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25944#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25608#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24782#L559-36 assume 1 == ~t3_pc~0; 24784#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25241#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25416#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25417#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 25756#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25996#L578-36 assume !(1 == ~t4_pc~0); 25683#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 25684#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25620#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25621#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25517#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25518#L597-36 assume !(1 == ~t5_pc~0); 25744#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 26097#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26041#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25699#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25320#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25321#L616-36 assume !(1 == ~t6_pc~0); 26067#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 24851#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24852#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25396#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25568#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25897#L635-36 assume 1 == ~t7_pc~0; 26072#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25954#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25955#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26017#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25554#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25555#L654-36 assume 1 == ~t8_pc~0; 26135#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26080#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25721#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25722#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26112#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25226#L673-36 assume 1 == ~t9_pc~0; 25227#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25594#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25459#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25460#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24792#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24793#L692-36 assume 1 == ~t10_pc~0; 25746#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25005#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25302#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25194#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 25195#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25565#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25714#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26075#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26076#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25645#L1157-3 assume !(1 == ~T4_E~0); 25646#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25950#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26062#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25551#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25451#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25452#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25466#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25284#L1197-3 assume !(1 == ~E_1~0); 25285#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25532#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25653#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25878#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25189#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24876#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24877#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25979#L1237-3 assume !(1 == ~E_9~0); 25980#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26142#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 26028#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 25027#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25028#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 25292#L1572 assume !(0 == start_simulation_~tmp~3#1); 25323#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25485#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24806#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24864#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 24865#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24777#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24778#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25625#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 24956#L1553-2 [2023-11-29 05:59:25,947 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:25,947 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2023-11-29 05:59:25,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:25,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688166104] [2023-11-29 05:59:25,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:25,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:25,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:26,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:26,068 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:26,068 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688166104] [2023-11-29 05:59:26,068 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1688166104] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:26,068 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:26,069 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:26,069 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1723895976] [2023-11-29 05:59:26,069 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:26,069 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:26,070 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:26,070 INFO L85 PathProgramCache]: Analyzing trace with hash -671382823, now seen corresponding path program 1 times [2023-11-29 05:59:26,070 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:26,070 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65807035] [2023-11-29 05:59:26,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:26,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:26,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:26,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:26,140 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:26,140 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [65807035] [2023-11-29 05:59:26,140 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [65807035] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:26,140 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:26,141 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:26,141 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [417354290] [2023-11-29 05:59:26,141 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:26,141 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:26,142 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:26,142 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 05:59:26,142 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 05:59:26,142 INFO L87 Difference]: Start difference. First operand 1372 states and 2026 transitions. cyclomatic complexity: 655 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:26,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:26,315 INFO L93 Difference]: Finished difference Result 2526 states and 3716 transitions. [2023-11-29 05:59:26,315 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2526 states and 3716 transitions. [2023-11-29 05:59:26,333 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2365 [2023-11-29 05:59:26,353 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2526 states to 2526 states and 3716 transitions. [2023-11-29 05:59:26,354 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2526 [2023-11-29 05:59:26,357 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2526 [2023-11-29 05:59:26,357 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2526 states and 3716 transitions. [2023-11-29 05:59:26,361 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:26,361 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2526 states and 3716 transitions. [2023-11-29 05:59:26,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2526 states and 3716 transitions. [2023-11-29 05:59:26,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2526 to 2526. [2023-11-29 05:59:26,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2526 states, 2526 states have (on average 1.471100554235946) internal successors, (3716), 2525 states have internal predecessors, (3716), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:26,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2526 states to 2526 states and 3716 transitions. [2023-11-29 05:59:26,423 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2526 states and 3716 transitions. [2023-11-29 05:59:26,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 05:59:26,424 INFO L428 stractBuchiCegarLoop]: Abstraction has 2526 states and 3716 transitions. [2023-11-29 05:59:26,424 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-29 05:59:26,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2526 states and 3716 transitions. [2023-11-29 05:59:26,434 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2365 [2023-11-29 05:59:26,434 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:26,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:26,436 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:26,436 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:26,437 INFO L748 eck$LassoCheckResult]: Stem: 29063#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 29064#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 29983#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29984#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29654#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 29335#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29336#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29622#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29797#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29508#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29509#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29387#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29388#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29751#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29709#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 29629#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29630#L1024 assume !(0 == ~M_E~0); 29894#L1024-2 assume !(0 == ~T1_E~0); 29059#L1029-1 assume !(0 == ~T2_E~0); 29060#L1034-1 assume !(0 == ~T3_E~0); 29163#L1039-1 assume !(0 == ~T4_E~0); 30008#L1044-1 assume !(0 == ~T5_E~0); 29408#L1049-1 assume !(0 == ~T6_E~0); 29409#L1054-1 assume !(0 == ~T7_E~0); 29653#L1059-1 assume !(0 == ~T8_E~0); 29109#L1064-1 assume !(0 == ~T9_E~0); 29110#L1069-1 assume !(0 == ~T10_E~0); 29863#L1074-1 assume 0 == ~E_M~0;~E_M~0 := 1; 29924#L1079-1 assume !(0 == ~E_1~0); 29896#L1084-1 assume !(0 == ~E_2~0); 29897#L1089-1 assume !(0 == ~E_3~0); 29943#L1094-1 assume !(0 == ~E_4~0); 29499#L1099-1 assume !(0 == ~E_5~0); 29500#L1104-1 assume !(0 == ~E_6~0); 29769#L1109-1 assume !(0 == ~E_7~0); 29277#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 29278#L1119-1 assume !(0 == ~E_9~0); 29345#L1124-1 assume !(0 == ~E_10~0); 28763#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28764#L502 assume 1 == ~m_pc~0; 29651#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28889#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28890#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29703#L1273 assume !(0 != activate_threads_~tmp~1#1); 29704#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30054#L521 assume !(1 == ~t1_pc~0); 29972#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28814#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28779#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28780#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 28800#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28801#L540 assume 1 == ~t2_pc~0; 29908#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29611#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29273#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29274#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 29968#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29087#L559 assume 1 == ~t3_pc~0; 29088#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29366#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28716#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28717#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 28907#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28908#L578 assume !(1 == ~t4_pc~0); 29028#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29027#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28846#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28847#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29685#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29686#L597 assume 1 == ~t5_pc~0; 30071#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28834#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28835#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29892#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 29631#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29632#L616 assume !(1 == ~t6_pc~0); 29648#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29647#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29249#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29250#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 29488#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29489#L635 assume 1 == ~t7_pc~0; 29688#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28803#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29179#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29939#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 29624#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29625#L654 assume !(1 == ~t8_pc~0); 29439#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29440#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29820#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29821#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 29861#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29057#L673 assume 1 == ~t9_pc~0; 29058#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28754#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29329#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29330#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 29781#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29782#L692 assume !(1 == ~t10_pc~0); 29724#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29723#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29491#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29492#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 29503#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29839#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 30094#L1142-2 assume !(1 == ~T1_E~0); 30494#L1147-1 assume !(1 == ~T2_E~0); 30488#L1152-1 assume !(1 == ~T3_E~0); 30093#L1157-1 assume !(1 == ~T4_E~0); 30424#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30421#L1167-1 assume !(1 == ~T6_E~0); 30419#L1172-1 assume !(1 == ~T7_E~0); 30417#L1177-1 assume !(1 == ~T8_E~0); 30397#L1182-1 assume !(1 == ~T9_E~0); 30240#L1187-1 assume !(1 == ~T10_E~0); 30239#L1192-1 assume !(1 == ~E_M~0); 29227#L1197-1 assume !(1 == ~E_1~0); 29228#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 29613#L1207-1 assume !(1 == ~E_3~0); 29589#L1212-1 assume !(1 == ~E_4~0); 28819#L1217-1 assume !(1 == ~E_5~0); 28820#L1222-1 assume !(1 == ~E_6~0); 29586#L1227-1 assume !(1 == ~E_7~0); 29587#L1232-1 assume !(1 == ~E_8~0); 28693#L1237-1 assume !(1 == ~E_9~0); 28694#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30138#L1247-1 assume { :end_inline_reset_delta_events } true; 30131#L1553-2 [2023-11-29 05:59:26,437 INFO L750 eck$LassoCheckResult]: Loop: 30131#L1553-2 assume !false; 30125#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30121#L999-1 assume !false; 30120#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30119#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30108#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30107#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30105#L854 assume !(0 != eval_~tmp~0#1); 30104#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30103#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30101#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30102#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30962#L1029-3 assume !(0 == ~T2_E~0); 30961#L1034-3 assume !(0 == ~T3_E~0); 30960#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30959#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30958#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30957#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30956#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30955#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30954#L1069-3 assume !(0 == ~T10_E~0); 30953#L1074-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30952#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30951#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30950#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30949#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30948#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30947#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30031#L1109-3 assume !(0 == ~E_7~0); 29788#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29789#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30078#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30087#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30044#L502-36 assume 1 == ~m_pc~0; 29803#L503-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28681#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28682#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29111#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29112#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29392#L521-36 assume 1 == ~t1_pc~0; 29393#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29404#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29578#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29985#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29865#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29866#L540-36 assume 1 == ~t2_pc~0; 30048#L541-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28771#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29184#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29867#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29522#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28690#L559-36 assume !(1 == ~t3_pc~0); 28691#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 29150#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29326#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29327#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 29673#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29920#L578-36 assume 1 == ~t4_pc~0; 29641#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29599#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29534#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29535#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29428#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29429#L597-36 assume !(1 == ~t5_pc~0); 29661#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 30027#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29967#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29614#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29229#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29230#L616-36 assume 1 == ~t6_pc~0; 30049#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28759#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28760#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29305#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29482#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29817#L635-36 assume !(1 == ~t7_pc~0); 30097#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 30550#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30548#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30546#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30544#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30338#L654-36 assume 1 == ~t8_pc~0; 30334#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30332#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30330#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30328#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30326#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30324#L673-36 assume !(1 == ~t9_pc~0); 30320#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 30318#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30316#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30314#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30312#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30310#L692-36 assume 1 == ~t10_pc~0; 30306#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30304#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30302#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30300#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 30298#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30296#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29633#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30292#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30290#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30032#L1157-3 assume !(1 == ~T4_E~0); 30287#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30285#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30284#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30283#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30282#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30281#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30280#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30279#L1197-3 assume !(1 == ~E_1~0); 30278#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30277#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30276#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30275#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30274#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30273#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30272#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30271#L1237-3 assume !(1 == ~E_9~0); 30270#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30269#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30268#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30257#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30256#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 30255#L1572 assume !(0 == start_simulation_~tmp~3#1); 29232#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 30249#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30241#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30170#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 30157#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30150#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30143#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30139#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 30131#L1553-2 [2023-11-29 05:59:26,437 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:26,438 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2023-11-29 05:59:26,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:26,438 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [148083475] [2023-11-29 05:59:26,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:26,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:26,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:26,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:26,513 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:26,513 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [148083475] [2023-11-29 05:59:26,513 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [148083475] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:26,513 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:26,513 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:26,514 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061272950] [2023-11-29 05:59:26,514 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:26,514 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:26,514 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:26,514 INFO L85 PathProgramCache]: Analyzing trace with hash -2013593701, now seen corresponding path program 1 times [2023-11-29 05:59:26,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:26,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345985604] [2023-11-29 05:59:26,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:26,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:26,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:26,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:26,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:26,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345985604] [2023-11-29 05:59:26,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1345985604] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:26,572 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:26,572 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:26,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1457981145] [2023-11-29 05:59:26,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:26,572 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:26,573 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:26,573 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 05:59:26,573 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 05:59:26,573 INFO L87 Difference]: Start difference. First operand 2526 states and 3716 transitions. cyclomatic complexity: 1192 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:26,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:26,772 INFO L93 Difference]: Finished difference Result 4664 states and 6847 transitions. [2023-11-29 05:59:26,772 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4664 states and 6847 transitions. [2023-11-29 05:59:26,797 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4471 [2023-11-29 05:59:26,829 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4664 states to 4664 states and 6847 transitions. [2023-11-29 05:59:26,830 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4664 [2023-11-29 05:59:26,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4664 [2023-11-29 05:59:26,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4664 states and 6847 transitions. [2023-11-29 05:59:26,841 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:26,842 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4664 states and 6847 transitions. [2023-11-29 05:59:26,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4664 states and 6847 transitions. [2023-11-29 05:59:26,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4664 to 4662. [2023-11-29 05:59:26,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4662 states, 4662 states have (on average 1.4682539682539681) internal successors, (6845), 4661 states have internal predecessors, (6845), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:26,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4662 states to 4662 states and 6845 transitions. [2023-11-29 05:59:26,950 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4662 states and 6845 transitions. [2023-11-29 05:59:26,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 05:59:26,951 INFO L428 stractBuchiCegarLoop]: Abstraction has 4662 states and 6845 transitions. [2023-11-29 05:59:26,951 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-29 05:59:26,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4662 states and 6845 transitions. [2023-11-29 05:59:26,965 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4471 [2023-11-29 05:59:26,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:26,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:26,967 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:26,967 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:26,968 INFO L748 eck$LassoCheckResult]: Stem: 36263#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36264#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 37182#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37183#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36850#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 36535#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36536#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36819#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36992#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36705#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36706#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36589#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36590#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36945#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36905#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36827#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36828#L1024 assume !(0 == ~M_E~0); 37088#L1024-2 assume !(0 == ~T1_E~0); 36259#L1029-1 assume !(0 == ~T2_E~0); 36260#L1034-1 assume !(0 == ~T3_E~0); 36362#L1039-1 assume !(0 == ~T4_E~0); 37206#L1044-1 assume !(0 == ~T5_E~0); 36609#L1049-1 assume !(0 == ~T6_E~0); 36610#L1054-1 assume !(0 == ~T7_E~0); 36849#L1059-1 assume !(0 == ~T8_E~0); 36309#L1064-1 assume !(0 == ~T9_E~0); 36310#L1069-1 assume !(0 == ~T10_E~0); 37057#L1074-1 assume !(0 == ~E_M~0); 37118#L1079-1 assume !(0 == ~E_1~0); 37090#L1084-1 assume !(0 == ~E_2~0); 37091#L1089-1 assume !(0 == ~E_3~0); 37136#L1094-1 assume !(0 == ~E_4~0); 36695#L1099-1 assume !(0 == ~E_5~0); 36696#L1104-1 assume !(0 == ~E_6~0); 36963#L1109-1 assume !(0 == ~E_7~0); 36476#L1114-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36477#L1119-1 assume !(0 == ~E_9~0); 36550#L1124-1 assume !(0 == ~E_10~0); 35963#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35964#L502 assume 1 == ~m_pc~0; 36847#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36089#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36090#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36901#L1273 assume !(0 != activate_threads_~tmp~1#1); 36902#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37238#L521 assume !(1 == ~t1_pc~0); 37167#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36014#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35979#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35980#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 36000#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36001#L540 assume 1 == ~t2_pc~0; 37102#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36807#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36474#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36475#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 37163#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36287#L559 assume 1 == ~t3_pc~0; 36288#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36566#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35916#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35917#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 36107#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36108#L578 assume !(1 == ~t4_pc~0); 36231#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36230#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36047#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36048#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36881#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36882#L597 assume 1 == ~t5_pc~0; 37255#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36034#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36035#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37086#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 36829#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36830#L616 assume !(1 == ~t6_pc~0); 36846#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36845#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36448#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36449#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 36685#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36686#L635 assume 1 == ~t7_pc~0; 36885#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36003#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36380#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37132#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 36820#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36821#L654 assume !(1 == ~t8_pc~0); 36636#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36637#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37019#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37020#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 37055#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36257#L673 assume 1 == ~t9_pc~0; 36258#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35956#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36530#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36531#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 36976#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36977#L692 assume !(1 == ~t10_pc~0); 36922#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36921#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36687#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36688#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 36699#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37034#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 37275#L1142-2 assume !(1 == ~T1_E~0); 37560#L1147-1 assume !(1 == ~T2_E~0); 37273#L1152-1 assume !(1 == ~T3_E~0); 37274#L1157-1 assume !(1 == ~T4_E~0); 37490#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36723#L1167-1 assume !(1 == ~T6_E~0); 36724#L1172-1 assume !(1 == ~T7_E~0); 37169#L1177-1 assume !(1 == ~T8_E~0); 37170#L1182-1 assume !(1 == ~T9_E~0); 36968#L1187-1 assume !(1 == ~T10_E~0); 36969#L1192-1 assume !(1 == ~E_M~0); 37369#L1197-1 assume !(1 == ~E_1~0); 37367#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 37365#L1207-1 assume !(1 == ~E_3~0); 37364#L1212-1 assume !(1 == ~E_4~0); 37352#L1217-1 assume !(1 == ~E_5~0); 37350#L1222-1 assume !(1 == ~E_6~0); 37348#L1227-1 assume !(1 == ~E_7~0); 37336#L1232-1 assume !(1 == ~E_8~0); 37327#L1237-1 assume !(1 == ~E_9~0); 37319#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 37312#L1247-1 assume { :end_inline_reset_delta_events } true; 37308#L1553-2 [2023-11-29 05:59:26,968 INFO L750 eck$LassoCheckResult]: Loop: 37308#L1553-2 assume !false; 37302#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37298#L999-1 assume !false; 37297#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37296#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37285#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37284#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37282#L854 assume !(0 != eval_~tmp~0#1); 37281#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37280#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37278#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37279#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38470#L1029-3 assume !(0 == ~T2_E~0); 38467#L1034-3 assume !(0 == ~T3_E~0); 38464#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38461#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38458#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38455#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38452#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 38449#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38446#L1069-3 assume !(0 == ~T10_E~0); 38443#L1074-3 assume !(0 == ~E_M~0); 38439#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38434#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38429#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38423#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38418#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38413#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38408#L1109-3 assume !(0 == ~E_7~0); 38401#L1114-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38396#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38390#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38385#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38381#L502-36 assume !(1 == ~m_pc~0); 38353#L502-38 is_master_triggered_~__retres1~0#1 := 0; 38351#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38348#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38346#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38344#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38342#L521-36 assume 1 == ~t1_pc~0; 38340#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38337#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38335#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38333#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38331#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38329#L540-36 assume !(1 == ~t2_pc~0); 38326#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 38316#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38309#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38300#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38292#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38285#L559-36 assume 1 == ~t3_pc~0; 38278#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38269#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38261#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38252#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 38244#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38237#L578-36 assume 1 == ~t4_pc~0; 38229#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38220#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38212#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38203#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38195#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38189#L597-36 assume !(1 == ~t5_pc~0); 38182#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 38174#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38167#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38160#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38152#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38145#L616-36 assume 1 == ~t6_pc~0; 38138#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38131#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38124#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38117#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38110#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38105#L635-36 assume !(1 == ~t7_pc~0); 38065#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 38057#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38049#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38041#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38033#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38025#L654-36 assume 1 == ~t8_pc~0; 38016#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38008#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38000#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37992#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37984#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37976#L673-36 assume 1 == ~t9_pc~0; 37968#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37959#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37951#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37941#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37935#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37930#L692-36 assume 1 == ~t10_pc~0; 37820#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37817#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37815#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37813#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 37811#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37809#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36825#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37806#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37786#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37226#L1157-3 assume !(1 == ~T4_E~0); 37769#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37761#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37754#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37747#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37738#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37730#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37722#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37713#L1197-3 assume !(1 == ~E_1~0); 37707#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37701#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37693#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37686#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37679#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37672#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37666#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37661#L1237-3 assume !(1 == ~E_9~0); 37654#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37648#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37444#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37433#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37432#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 37431#L1572 assume !(0 == start_simulation_~tmp~3#1); 36431#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37359#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37351#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37349#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 37337#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37328#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37320#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 37313#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 37308#L1553-2 [2023-11-29 05:59:26,968 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:26,969 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2023-11-29 05:59:26,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:26,969 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830439296] [2023-11-29 05:59:26,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:26,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:26,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:27,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:27,029 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:27,029 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1830439296] [2023-11-29 05:59:27,029 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1830439296] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:27,029 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:27,029 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:27,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1096648002] [2023-11-29 05:59:27,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:27,030 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:27,030 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:27,030 INFO L85 PathProgramCache]: Analyzing trace with hash 590468125, now seen corresponding path program 1 times [2023-11-29 05:59:27,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:27,031 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699641789] [2023-11-29 05:59:27,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:27,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:27,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:27,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:27,074 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:27,074 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1699641789] [2023-11-29 05:59:27,074 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1699641789] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:27,074 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:27,074 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:27,074 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [703321277] [2023-11-29 05:59:27,074 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:27,075 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:27,075 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:27,075 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 05:59:27,075 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 05:59:27,076 INFO L87 Difference]: Start difference. First operand 4662 states and 6845 transitions. cyclomatic complexity: 2187 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:27,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:27,261 INFO L93 Difference]: Finished difference Result 8740 states and 12800 transitions. [2023-11-29 05:59:27,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8740 states and 12800 transitions. [2023-11-29 05:59:27,292 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8525 [2023-11-29 05:59:27,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8740 states to 8740 states and 12800 transitions. [2023-11-29 05:59:27,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8740 [2023-11-29 05:59:27,340 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8740 [2023-11-29 05:59:27,340 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8740 states and 12800 transitions. [2023-11-29 05:59:27,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:27,348 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8740 states and 12800 transitions. [2023-11-29 05:59:27,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8740 states and 12800 transitions. [2023-11-29 05:59:27,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8740 to 8736. [2023-11-29 05:59:27,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8736 states, 8736 states have (on average 1.4647435897435896) internal successors, (12796), 8735 states have internal predecessors, (12796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:27,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8736 states to 8736 states and 12796 transitions. [2023-11-29 05:59:27,557 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8736 states and 12796 transitions. [2023-11-29 05:59:27,557 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 05:59:27,558 INFO L428 stractBuchiCegarLoop]: Abstraction has 8736 states and 12796 transitions. [2023-11-29 05:59:27,558 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-29 05:59:27,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8736 states and 12796 transitions. [2023-11-29 05:59:27,581 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8525 [2023-11-29 05:59:27,581 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:27,582 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:27,583 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:27,583 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:27,584 INFO L748 eck$LassoCheckResult]: Stem: 49675#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 49676#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 50613#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50614#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50269#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 49948#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49949#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50238#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50418#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50123#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50124#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50000#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50001#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50370#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50327#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50245#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50246#L1024 assume !(0 == ~M_E~0); 50519#L1024-2 assume !(0 == ~T1_E~0); 49671#L1029-1 assume !(0 == ~T2_E~0); 49672#L1034-1 assume !(0 == ~T3_E~0); 49774#L1039-1 assume !(0 == ~T4_E~0); 50637#L1044-1 assume !(0 == ~T5_E~0); 50021#L1049-1 assume !(0 == ~T6_E~0); 50022#L1054-1 assume !(0 == ~T7_E~0); 50268#L1059-1 assume !(0 == ~T8_E~0); 49721#L1064-1 assume !(0 == ~T9_E~0); 49722#L1069-1 assume !(0 == ~T10_E~0); 50488#L1074-1 assume !(0 == ~E_M~0); 50550#L1079-1 assume !(0 == ~E_1~0); 50521#L1084-1 assume !(0 == ~E_2~0); 50522#L1089-1 assume !(0 == ~E_3~0); 50570#L1094-1 assume !(0 == ~E_4~0); 50114#L1099-1 assume !(0 == ~E_5~0); 50115#L1104-1 assume !(0 == ~E_6~0); 50388#L1109-1 assume !(0 == ~E_7~0); 49889#L1114-1 assume !(0 == ~E_8~0); 49890#L1119-1 assume !(0 == ~E_9~0); 49958#L1124-1 assume !(0 == ~E_10~0); 49375#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49376#L502 assume 1 == ~m_pc~0; 50266#L503 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49501#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49502#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50321#L1273 assume !(0 != activate_threads_~tmp~1#1); 50322#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50676#L521 assume !(1 == ~t1_pc~0); 50599#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49426#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49391#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49392#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 49412#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49413#L540 assume 1 == ~t2_pc~0; 50534#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50226#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49885#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49886#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 50595#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49699#L559 assume 1 == ~t3_pc~0; 49700#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49979#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49328#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49329#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 49519#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49520#L578 assume !(1 == ~t4_pc~0); 49641#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49640#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49459#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49460#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50303#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50304#L597 assume 1 == ~t5_pc~0; 50694#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49446#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49447#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50517#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 50247#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50248#L616 assume !(1 == ~t6_pc~0); 50263#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50262#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49861#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49862#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 50102#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50103#L635 assume 1 == ~t7_pc~0; 50306#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49415#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49790#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50566#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 50240#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50241#L654 assume !(1 == ~t8_pc~0); 50051#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50052#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50447#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50448#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 50486#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49669#L673 assume 1 == ~t9_pc~0; 49670#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49366#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49944#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49945#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 50402#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50403#L692 assume !(1 == ~t10_pc~0); 50342#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50341#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50105#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50106#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 50118#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50465#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 50720#L1142-2 assume !(1 == ~T1_E~0); 50452#L1147-1 assume !(1 == ~T2_E~0); 50453#L1152-1 assume !(1 == ~T3_E~0); 51084#L1157-1 assume !(1 == ~T4_E~0); 51081#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51077#L1167-1 assume !(1 == ~T6_E~0); 51074#L1172-1 assume !(1 == ~T7_E~0); 51071#L1177-1 assume !(1 == ~T8_E~0); 51068#L1182-1 assume !(1 == ~T9_E~0); 51064#L1187-1 assume !(1 == ~T10_E~0); 51061#L1192-1 assume !(1 == ~E_M~0); 51057#L1197-1 assume !(1 == ~E_1~0); 50866#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50864#L1207-1 assume !(1 == ~E_3~0); 50839#L1212-1 assume !(1 == ~E_4~0); 50827#L1217-1 assume !(1 == ~E_5~0); 50825#L1222-1 assume !(1 == ~E_6~0); 50804#L1227-1 assume !(1 == ~E_7~0); 50802#L1232-1 assume !(1 == ~E_8~0); 50786#L1237-1 assume !(1 == ~E_9~0); 50770#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 50761#L1247-1 assume { :end_inline_reset_delta_events } true; 50754#L1553-2 [2023-11-29 05:59:27,584 INFO L750 eck$LassoCheckResult]: Loop: 50754#L1553-2 assume !false; 50748#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50744#L999-1 assume !false; 50743#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50742#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50731#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50730#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50728#L854 assume !(0 != eval_~tmp~0#1); 50727#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50726#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50724#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50725#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52358#L1029-3 assume !(0 == ~T2_E~0); 52356#L1034-3 assume !(0 == ~T3_E~0); 52354#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52352#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52350#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52348#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52346#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52344#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 52342#L1069-3 assume !(0 == ~T10_E~0); 52340#L1074-3 assume !(0 == ~E_M~0); 52338#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52336#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52334#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52332#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52329#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 52327#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52325#L1109-3 assume !(0 == ~E_7~0); 52323#L1114-3 assume !(0 == ~E_8~0); 52321#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 52319#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52316#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52314#L502-36 assume !(1 == ~m_pc~0); 52284#L502-38 is_master_triggered_~__retres1~0#1 := 0; 52282#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52279#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52277#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52275#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52273#L521-36 assume 1 == ~t1_pc~0; 52270#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 52268#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52265#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 52263#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52261#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52259#L540-36 assume !(1 == ~t2_pc~0); 52256#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 52254#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52251#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52249#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52247#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52245#L559-36 assume 1 == ~t3_pc~0; 52242#L560-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 52240#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52237#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52235#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 52233#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52231#L578-36 assume 1 == ~t4_pc~0; 52228#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 52226#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52223#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51841#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51839#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50276#L597-36 assume !(1 == ~t5_pc~0); 50277#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 51694#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51691#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51689#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51687#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51685#L616-36 assume 1 == ~t6_pc~0; 51659#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 51644#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51642#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51640#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51637#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51635#L635-36 assume !(1 == ~t7_pc~0); 51632#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 51625#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51598#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51596#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 51593#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51592#L654-36 assume 1 == ~t8_pc~0; 51578#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51566#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51564#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51561#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51559#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51557#L673-36 assume !(1 == ~t9_pc~0); 51554#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 50125#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49982#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49983#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51504#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51502#L692-36 assume 1 == ~t10_pc~0; 51479#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51477#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51468#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51460#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 51452#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51444#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50249#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 51429#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51420#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50662#L1157-3 assume !(1 == ~T4_E~0); 51405#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51400#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 51395#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 51390#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 51384#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 51379#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51374#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 51367#L1197-3 assume !(1 == ~E_1~0); 51364#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51361#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 51357#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51354#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51351#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51348#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51345#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 51341#L1237-3 assume !(1 == ~E_9~0); 51338#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51336#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51334#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51322#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51177#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 50863#L1572 assume !(0 == start_simulation_~tmp~3#1); 49843#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50834#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50826#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50805#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 50788#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50774#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50771#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 50762#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 50754#L1553-2 [2023-11-29 05:59:27,584 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:27,585 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2023-11-29 05:59:27,585 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:27,585 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614321022] [2023-11-29 05:59:27,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:27,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:27,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:27,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:27,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:27,636 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [614321022] [2023-11-29 05:59:27,636 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [614321022] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:27,636 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:27,637 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 05:59:27,637 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674250504] [2023-11-29 05:59:27,637 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:27,637 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:27,638 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:27,638 INFO L85 PathProgramCache]: Analyzing trace with hash -1184532576, now seen corresponding path program 1 times [2023-11-29 05:59:27,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:27,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111419707] [2023-11-29 05:59:27,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:27,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:27,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:27,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:27,681 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:27,681 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111419707] [2023-11-29 05:59:27,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2111419707] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:27,681 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:27,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:27,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1852896078] [2023-11-29 05:59:27,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:27,682 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:27,682 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:27,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:27,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:27,683 INFO L87 Difference]: Start difference. First operand 8736 states and 12796 transitions. cyclomatic complexity: 4068 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:27,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:27,832 INFO L93 Difference]: Finished difference Result 17155 states and 24947 transitions. [2023-11-29 05:59:27,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17155 states and 24947 transitions. [2023-11-29 05:59:27,892 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16929 [2023-11-29 05:59:28,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17155 states to 17155 states and 24947 transitions. [2023-11-29 05:59:28,008 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17155 [2023-11-29 05:59:28,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17155 [2023-11-29 05:59:28,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17155 states and 24947 transitions. [2023-11-29 05:59:28,039 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:28,039 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17155 states and 24947 transitions. [2023-11-29 05:59:28,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17155 states and 24947 transitions. [2023-11-29 05:59:28,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17155 to 16547. [2023-11-29 05:59:28,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16547 states, 16547 states have (on average 1.455913458632985) internal successors, (24091), 16546 states have internal predecessors, (24091), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:28,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16547 states to 16547 states and 24091 transitions. [2023-11-29 05:59:28,407 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16547 states and 24091 transitions. [2023-11-29 05:59:28,407 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 05:59:28,408 INFO L428 stractBuchiCegarLoop]: Abstraction has 16547 states and 24091 transitions. [2023-11-29 05:59:28,408 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-29 05:59:28,408 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16547 states and 24091 transitions. [2023-11-29 05:59:28,478 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16321 [2023-11-29 05:59:28,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:28,479 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:28,481 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:28,482 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:28,482 INFO L748 eck$LassoCheckResult]: Stem: 75581#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 75582#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 76637#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76638#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76213#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 75869#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75870#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76181#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76378#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76053#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76054#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75928#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75929#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76324#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 76274#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76190#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76191#L1024 assume !(0 == ~M_E~0); 76509#L1024-2 assume !(0 == ~T1_E~0); 75576#L1029-1 assume !(0 == ~T2_E~0); 75577#L1034-1 assume !(0 == ~T3_E~0); 75685#L1039-1 assume !(0 == ~T4_E~0); 76671#L1044-1 assume !(0 == ~T5_E~0); 75947#L1049-1 assume !(0 == ~T6_E~0); 75948#L1054-1 assume !(0 == ~T7_E~0); 76212#L1059-1 assume !(0 == ~T8_E~0); 75632#L1064-1 assume !(0 == ~T9_E~0); 75633#L1069-1 assume !(0 == ~T10_E~0); 76472#L1074-1 assume !(0 == ~E_M~0); 76550#L1079-1 assume !(0 == ~E_1~0); 76514#L1084-1 assume !(0 == ~E_2~0); 76515#L1089-1 assume !(0 == ~E_3~0); 76582#L1094-1 assume !(0 == ~E_4~0); 76042#L1099-1 assume !(0 == ~E_5~0); 76043#L1104-1 assume !(0 == ~E_6~0); 76345#L1109-1 assume !(0 == ~E_7~0); 75807#L1114-1 assume !(0 == ~E_8~0); 75808#L1119-1 assume !(0 == ~E_9~0); 75884#L1124-1 assume !(0 == ~E_10~0); 75273#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75274#L502 assume !(1 == ~m_pc~0); 75474#L502-2 is_master_triggered_~__retres1~0#1 := 0; 75404#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75405#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76270#L1273 assume !(0 != activate_threads_~tmp~1#1); 76271#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76738#L521 assume !(1 == ~t1_pc~0); 76621#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75326#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75289#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 75290#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 75310#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75311#L540 assume 1 == ~t2_pc~0; 76529#L541 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 76164#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75805#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75806#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 76615#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75610#L559 assume 1 == ~t3_pc~0; 75611#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75900#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75226#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75227#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 75420#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75421#L578 assume !(1 == ~t4_pc~0); 75546#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 75545#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75358#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75359#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76248#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76249#L597 assume 1 == ~t5_pc~0; 76768#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75344#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75345#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76507#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 76192#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76193#L616 assume !(1 == ~t6_pc~0); 76210#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76209#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75778#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75779#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 76032#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76033#L635 assume 1 == ~t7_pc~0; 76251#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75313#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75702#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76577#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 76183#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76184#L654 assume !(1 == ~t8_pc~0); 75976#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75977#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76417#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76418#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 76469#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75574#L673 assume 1 == ~t9_pc~0; 75575#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75266#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75862#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75863#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 76357#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76358#L692 assume !(1 == ~t10_pc~0); 76293#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76292#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76034#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76035#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 76046#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76437#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 76820#L1142-2 assume !(1 == ~T1_E~0); 85261#L1147-1 assume !(1 == ~T2_E~0); 76819#L1152-1 assume !(1 == ~T3_E~0); 75906#L1157-1 assume !(1 == ~T4_E~0); 75907#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76521#L1167-1 assume !(1 == ~T6_E~0); 85966#L1172-1 assume !(1 == ~T7_E~0); 85964#L1177-1 assume !(1 == ~T8_E~0); 76231#L1182-1 assume !(1 == ~T9_E~0); 76232#L1187-1 assume !(1 == ~T10_E~0); 76350#L1192-1 assume !(1 == ~E_M~0); 76407#L1197-1 assume !(1 == ~E_1~0); 76422#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 76423#L1207-1 assume !(1 == ~E_3~0); 76142#L1212-1 assume !(1 == ~E_4~0); 76143#L1217-1 assume !(1 == ~E_5~0); 76839#L1222-1 assume !(1 == ~E_6~0); 76840#L1227-1 assume !(1 == ~E_7~0); 76228#L1232-1 assume !(1 == ~E_8~0); 75203#L1237-1 assume !(1 == ~E_9~0); 75204#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 76211#L1247-1 assume { :end_inline_reset_delta_events } true; 75379#L1553-2 [2023-11-29 05:59:28,483 INFO L750 eck$LassoCheckResult]: Loop: 75379#L1553-2 assume !false; 75380#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 75518#L999-1 assume !false; 75668#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 75466#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 75347#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 75841#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 75842#L854 assume !(0 != eval_~tmp~0#1); 76299#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 90685#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 90683#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 90684#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 91425#L1029-3 assume !(0 == ~T2_E~0); 91423#L1034-3 assume !(0 == ~T3_E~0); 91421#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 91419#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 91417#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 91416#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 91415#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 91414#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 91413#L1069-3 assume !(0 == ~T10_E~0); 91412#L1074-3 assume !(0 == ~E_M~0); 76639#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 76223#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 76093#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76094#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 76013#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 76014#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 76381#L1109-3 assume !(0 == ~E_7~0); 76365#L1114-3 assume !(0 == ~E_8~0); 76366#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 76775#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 76787#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76727#L502-36 assume !(1 == ~m_pc~0); 75720#L502-38 is_master_triggered_~__retres1~0#1 := 0; 75191#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75192#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75634#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 75635#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75925#L521-36 assume !(1 == ~t1_pc~0); 75927#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 75939#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76128#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76636#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 76474#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76475#L540-36 assume !(1 == ~t2_pc~0); 75280#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 75281#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75705#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76476#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 76068#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75200#L559-36 assume !(1 == ~t3_pc~0); 75201#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 75674#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75857#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75858#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 76233#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76546#L578-36 assume !(1 == ~t4_pc~0); 76151#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 76152#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76081#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76082#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75965#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75966#L597-36 assume 1 == ~t5_pc~0; 76221#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 76704#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76614#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76166#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 75751#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75752#L616-36 assume !(1 == ~t6_pc~0); 76648#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 75269#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75270#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75836#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76024#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 91298#L635-36 assume 1 == ~t7_pc~0; 91296#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 91292#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 91290#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 91288#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 91286#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 91284#L654-36 assume !(1 == ~t8_pc~0); 91243#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 91240#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 91238#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 91236#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 91233#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 91226#L673-36 assume 1 == ~t9_pc~0; 76519#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76052#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75902#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75903#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 91211#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 91206#L692-36 assume !(1 == ~t10_pc~0); 91201#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 91198#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 91197#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75625#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 75626#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76023#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76189#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 76666#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76667#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76107#L1157-3 assume !(1 == ~T4_E~0); 76108#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76482#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 76643#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 76003#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 75894#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 75895#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 75909#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 75714#L1197-3 assume !(1 == ~E_1~0); 75715#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 75985#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 90910#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 90908#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 90906#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 90904#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 90902#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 86234#L1237-3 assume !(1 == ~E_9~0); 90898#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 90896#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 90894#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 90882#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 90880#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 90878#L1572 assume !(0 == start_simulation_~tmp~3#1); 77473#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 90753#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 90745#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77459#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 76806#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 75195#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75196#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 76086#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 75379#L1553-2 [2023-11-29 05:59:28,483 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:28,483 INFO L85 PathProgramCache]: Analyzing trace with hash -2098669114, now seen corresponding path program 1 times [2023-11-29 05:59:28,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:28,484 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870447003] [2023-11-29 05:59:28,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:28,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:28,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:28,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:28,554 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:28,554 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870447003] [2023-11-29 05:59:28,554 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1870447003] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:28,554 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:28,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 05:59:28,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [185981699] [2023-11-29 05:59:28,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:28,555 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:28,555 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:28,556 INFO L85 PathProgramCache]: Analyzing trace with hash -55286749, now seen corresponding path program 1 times [2023-11-29 05:59:28,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:28,556 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [743629406] [2023-11-29 05:59:28,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:28,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:28,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:28,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:28,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:28,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [743629406] [2023-11-29 05:59:28,621 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [743629406] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:28,621 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:28,621 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:28,621 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1507779291] [2023-11-29 05:59:28,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:28,622 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:28,622 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:28,623 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:28,623 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:28,624 INFO L87 Difference]: Start difference. First operand 16547 states and 24091 transitions. cyclomatic complexity: 7560 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:28,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:28,873 INFO L93 Difference]: Finished difference Result 31457 states and 45569 transitions. [2023-11-29 05:59:28,873 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31457 states and 45569 transitions. [2023-11-29 05:59:29,148 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31184 [2023-11-29 05:59:29,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31457 states to 31457 states and 45569 transitions. [2023-11-29 05:59:29,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31457 [2023-11-29 05:59:29,279 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31457 [2023-11-29 05:59:29,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31457 states and 45569 transitions. [2023-11-29 05:59:29,303 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:29,303 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31457 states and 45569 transitions. [2023-11-29 05:59:29,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31457 states and 45569 transitions. [2023-11-29 05:59:29,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31457 to 31425. [2023-11-29 05:59:29,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31425 states, 31425 states have (on average 1.4490692124105011) internal successors, (45537), 31424 states have internal predecessors, (45537), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:29,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31425 states to 31425 states and 45537 transitions. [2023-11-29 05:59:29,826 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31425 states and 45537 transitions. [2023-11-29 05:59:29,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 05:59:29,827 INFO L428 stractBuchiCegarLoop]: Abstraction has 31425 states and 45537 transitions. [2023-11-29 05:59:29,827 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-29 05:59:29,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31425 states and 45537 transitions. [2023-11-29 05:59:29,919 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31152 [2023-11-29 05:59:29,919 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:29,919 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:29,922 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:29,922 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:29,922 INFO L748 eck$LassoCheckResult]: Stem: 123588#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 123589#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 124556#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 124557#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 124198#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 123871#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 123872#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 124158#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 124348#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 124041#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 124042#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 123922#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 123923#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 124299#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 124254#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 124170#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 124171#L1024 assume !(0 == ~M_E~0); 124461#L1024-2 assume !(0 == ~T1_E~0); 123584#L1029-1 assume !(0 == ~T2_E~0); 123585#L1034-1 assume !(0 == ~T3_E~0); 123693#L1039-1 assume !(0 == ~T4_E~0); 124583#L1044-1 assume !(0 == ~T5_E~0); 123942#L1049-1 assume !(0 == ~T6_E~0); 123943#L1054-1 assume !(0 == ~T7_E~0); 124197#L1059-1 assume !(0 == ~T8_E~0); 123639#L1064-1 assume !(0 == ~T9_E~0); 123640#L1069-1 assume !(0 == ~T10_E~0); 124428#L1074-1 assume !(0 == ~E_M~0); 124492#L1079-1 assume !(0 == ~E_1~0); 124463#L1084-1 assume !(0 == ~E_2~0); 124464#L1089-1 assume !(0 == ~E_3~0); 124512#L1094-1 assume !(0 == ~E_4~0); 124032#L1099-1 assume !(0 == ~E_5~0); 124033#L1104-1 assume !(0 == ~E_6~0); 124318#L1109-1 assume !(0 == ~E_7~0); 123810#L1114-1 assume !(0 == ~E_8~0); 123811#L1119-1 assume !(0 == ~E_9~0); 123881#L1124-1 assume !(0 == ~E_10~0); 123284#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123285#L502 assume !(1 == ~m_pc~0); 123479#L502-2 is_master_triggered_~__retres1~0#1 := 0; 123411#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123412#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 124248#L1273 assume !(0 != activate_threads_~tmp~1#1); 124249#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 124634#L521 assume !(1 == ~t1_pc~0); 124544#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 123335#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123300#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 123301#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 123321#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123322#L540 assume !(1 == ~t2_pc~0); 124145#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 124146#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123806#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 123807#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 124538#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123617#L559 assume 1 == ~t3_pc~0; 123618#L560 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 123901#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123237#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123238#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 123429#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123430#L578 assume !(1 == ~t4_pc~0); 123548#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 123547#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123368#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123369#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124228#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 124229#L597 assume 1 == ~t5_pc~0; 124653#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 123356#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123357#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 124459#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 124172#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124173#L616 assume !(1 == ~t6_pc~0); 124192#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 124191#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 123780#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 123781#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 124021#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124022#L635 assume 1 == ~t7_pc~0; 124233#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 123324#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 123709#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 124508#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 124163#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 124164#L654 assume !(1 == ~t8_pc~0); 123971#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 123972#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 124373#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 124374#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 124426#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 123582#L673 assume 1 == ~t9_pc~0; 123583#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 123275#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 123865#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 123866#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 124330#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 124331#L692 assume !(1 == ~t10_pc~0); 124270#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 124269#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 124024#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 124025#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 124036#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124402#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 123489#L1142-2 assume !(1 == ~T1_E~0); 123490#L1147-1 assume !(1 == ~T2_E~0); 124380#L1152-1 assume !(1 == ~T3_E~0); 123908#L1157-1 assume !(1 == ~T4_E~0); 123909#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 124061#L1167-1 assume !(1 == ~T6_E~0); 124062#L1172-1 assume !(1 == ~T7_E~0); 124530#L1177-1 assume !(1 == ~T8_E~0); 124216#L1182-1 assume !(1 == ~T9_E~0); 124217#L1187-1 assume !(1 == ~T10_E~0); 124323#L1192-1 assume !(1 == ~E_M~0); 123759#L1197-1 assume !(1 == ~E_1~0); 123760#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 124149#L1207-1 assume !(1 == ~E_3~0); 124124#L1212-1 assume !(1 == ~E_4~0); 123340#L1217-1 assume !(1 == ~E_5~0); 123341#L1222-1 assume !(1 == ~E_6~0); 124121#L1227-1 assume !(1 == ~E_7~0); 124122#L1232-1 assume !(1 == ~E_8~0); 124213#L1237-1 assume !(1 == ~E_9~0); 151883#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 151882#L1247-1 assume { :end_inline_reset_delta_events } true; 151881#L1553-2 [2023-11-29 05:59:29,922 INFO L750 eck$LassoCheckResult]: Loop: 151881#L1553-2 assume !false; 151880#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 151878#L999-1 assume !false; 151877#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 151274#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 151262#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 151260#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 151257#L854 assume !(0 != eval_~tmp~0#1); 151258#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 152761#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 152759#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 152757#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 152755#L1029-3 assume !(0 == ~T2_E~0); 152753#L1034-3 assume !(0 == ~T3_E~0); 152751#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 152749#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 152747#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 152745#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 152743#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 152741#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 152739#L1069-3 assume !(0 == ~T10_E~0); 152737#L1074-3 assume !(0 == ~E_M~0); 152735#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 152733#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 152731#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 152729#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 152727#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 152725#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 152723#L1109-3 assume !(0 == ~E_7~0); 152721#L1114-3 assume !(0 == ~E_8~0); 152719#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 152717#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 152715#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 152713#L502-36 assume !(1 == ~m_pc~0); 152711#L502-38 is_master_triggered_~__retres1~0#1 := 0; 152709#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 152707#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 152705#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 152703#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 152700#L521-36 assume !(1 == ~t1_pc~0); 152698#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 152695#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 152693#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 152691#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 152689#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 152687#L540-36 assume !(1 == ~t2_pc~0); 152685#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 152683#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 152681#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 152679#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 152677#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152674#L559-36 assume !(1 == ~t3_pc~0); 152672#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 152669#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152667#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 152665#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 152663#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 152660#L578-36 assume !(1 == ~t4_pc~0); 152658#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 152655#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 152653#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 152651#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 152649#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 152646#L597-36 assume !(1 == ~t5_pc~0); 152643#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 152641#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 152639#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 152637#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 152635#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 152632#L616-36 assume !(1 == ~t6_pc~0); 152630#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 152627#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 152625#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 152623#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 152621#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 152618#L635-36 assume !(1 == ~t7_pc~0); 152615#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 152613#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 152611#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 152609#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 152607#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 152604#L654-36 assume !(1 == ~t8_pc~0); 152602#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 152599#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 152597#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 152595#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 152593#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 152590#L673-36 assume !(1 == ~t9_pc~0); 152587#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 152585#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 152583#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 152581#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 152579#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 152578#L692-36 assume 1 == ~t10_pc~0; 152574#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 152572#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 152570#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 152568#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 152566#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152565#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 143198#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 152367#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 152362#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 145476#L1157-3 assume !(1 == ~T4_E~0); 152358#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 152356#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 152354#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 152352#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 152350#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 152347#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 152345#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 152311#L1197-3 assume !(1 == ~E_1~0); 152342#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 152340#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 152338#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 152335#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 152333#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 152330#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 152328#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 145773#L1237-3 assume !(1 == ~E_9~0); 151670#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 149128#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 149098#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 149072#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 125259#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 124182#L1572 assume !(0 == start_simulation_~tmp~3#1); 124183#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 153823#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 153816#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 153815#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 153814#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 153813#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 151453#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 151454#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 151881#L1553-2 [2023-11-29 05:59:29,923 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:29,923 INFO L85 PathProgramCache]: Analyzing trace with hash 353984391, now seen corresponding path program 1 times [2023-11-29 05:59:29,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:29,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971368175] [2023-11-29 05:59:29,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:29,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:29,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:30,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:30,072 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:30,072 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1971368175] [2023-11-29 05:59:30,073 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1971368175] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:30,073 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:30,073 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 05:59:30,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [532410759] [2023-11-29 05:59:30,073 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:30,074 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:30,074 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:30,075 INFO L85 PathProgramCache]: Analyzing trace with hash -155238939, now seen corresponding path program 1 times [2023-11-29 05:59:30,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:30,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143473517] [2023-11-29 05:59:30,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:30,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:30,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:30,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:30,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:30,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143473517] [2023-11-29 05:59:30,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [143473517] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:30,147 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:30,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:30,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1776229307] [2023-11-29 05:59:30,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:30,149 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:30,149 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:30,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:30,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:30,150 INFO L87 Difference]: Start difference. First operand 31425 states and 45537 transitions. cyclomatic complexity: 14144 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:30,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:30,509 INFO L93 Difference]: Finished difference Result 59788 states and 86234 transitions. [2023-11-29 05:59:30,510 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59788 states and 86234 transitions. [2023-11-29 05:59:30,891 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59420 [2023-11-29 05:59:31,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59788 states to 59788 states and 86234 transitions. [2023-11-29 05:59:31,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59788 [2023-11-29 05:59:31,096 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59788 [2023-11-29 05:59:31,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59788 states and 86234 transitions. [2023-11-29 05:59:31,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:31,139 INFO L218 hiAutomatonCegarLoop]: Abstraction has 59788 states and 86234 transitions. [2023-11-29 05:59:31,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59788 states and 86234 transitions. [2023-11-29 05:59:31,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59788 to 59724. [2023-11-29 05:59:31,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59724 states, 59724 states have (on average 1.4428035630567275) internal successors, (86170), 59723 states have internal predecessors, (86170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:31,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59724 states to 59724 states and 86170 transitions. [2023-11-29 05:59:31,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59724 states and 86170 transitions. [2023-11-29 05:59:31,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 05:59:31,766 INFO L428 stractBuchiCegarLoop]: Abstraction has 59724 states and 86170 transitions. [2023-11-29 05:59:31,766 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-29 05:59:31,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59724 states and 86170 transitions. [2023-11-29 05:59:32,109 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59356 [2023-11-29 05:59:32,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:32,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:32,111 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:32,112 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:32,112 INFO L748 eck$LassoCheckResult]: Stem: 214807#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 214808#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 215770#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 215771#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 215410#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 215089#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 215090#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 215378#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 215567#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 215259#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 215260#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 215141#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 215142#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 215514#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 215471#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 215385#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 215386#L1024 assume !(0 == ~M_E~0); 215678#L1024-2 assume !(0 == ~T1_E~0); 214803#L1029-1 assume !(0 == ~T2_E~0); 214804#L1034-1 assume !(0 == ~T3_E~0); 214910#L1039-1 assume !(0 == ~T4_E~0); 215797#L1044-1 assume !(0 == ~T5_E~0); 215162#L1049-1 assume !(0 == ~T6_E~0); 215163#L1054-1 assume !(0 == ~T7_E~0); 215409#L1059-1 assume !(0 == ~T8_E~0); 214855#L1064-1 assume !(0 == ~T9_E~0); 214856#L1069-1 assume !(0 == ~T10_E~0); 215645#L1074-1 assume !(0 == ~E_M~0); 215707#L1079-1 assume !(0 == ~E_1~0); 215680#L1084-1 assume !(0 == ~E_2~0); 215681#L1089-1 assume !(0 == ~E_3~0); 215726#L1094-1 assume !(0 == ~E_4~0); 215250#L1099-1 assume !(0 == ~E_5~0); 215251#L1104-1 assume !(0 == ~E_6~0); 215533#L1109-1 assume !(0 == ~E_7~0); 215030#L1114-1 assume !(0 == ~E_8~0); 215031#L1119-1 assume !(0 == ~E_9~0); 215099#L1124-1 assume !(0 == ~E_10~0); 214503#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 214504#L502 assume !(1 == ~m_pc~0); 214698#L502-2 is_master_triggered_~__retres1~0#1 := 0; 214628#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 214629#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 215465#L1273 assume !(0 != activate_threads_~tmp~1#1); 215466#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 215839#L521 assume !(1 == ~t1_pc~0); 215758#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 214553#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 214519#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 214520#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 214539#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 214540#L540 assume !(1 == ~t2_pc~0); 215364#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 215365#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 215026#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 215027#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 215753#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 214834#L559 assume !(1 == ~t3_pc~0); 214835#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 215120#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 214456#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 214457#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 214646#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 214647#L578 assume !(1 == ~t4_pc~0); 214770#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 214769#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 214585#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 214586#L1305 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 215444#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 215445#L597 assume 1 == ~t5_pc~0; 215861#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 214573#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 214574#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 215676#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 215387#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 215388#L616 assume !(1 == ~t6_pc~0); 215404#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 215403#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 215003#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 215004#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 215239#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 215240#L635 assume 1 == ~t7_pc~0; 215450#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 214542#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 214925#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 215722#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 215380#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 215381#L654 assume !(1 == ~t8_pc~0); 215191#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 215192#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 215598#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 215599#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 215643#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 214801#L673 assume 1 == ~t9_pc~0; 214802#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 214494#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 215083#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 215084#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 215548#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 215549#L692 assume !(1 == ~t10_pc~0); 215487#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 215486#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 215242#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 215243#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 215254#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 215618#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 214710#L1142-2 assume !(1 == ~T1_E~0); 214711#L1147-1 assume !(1 == ~T2_E~0); 215605#L1152-1 assume !(1 == ~T3_E~0); 215127#L1157-1 assume !(1 == ~T4_E~0); 215128#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 215278#L1167-1 assume !(1 == ~T6_E~0); 215279#L1172-1 assume !(1 == ~T7_E~0); 215744#L1177-1 assume !(1 == ~T8_E~0); 215430#L1182-1 assume !(1 == ~T9_E~0); 215431#L1187-1 assume !(1 == ~T10_E~0); 215541#L1192-1 assume !(1 == ~E_M~0); 215596#L1197-1 assume !(1 == ~E_1~0); 215608#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 215367#L1207-1 assume !(1 == ~E_3~0); 215344#L1212-1 assume !(1 == ~E_4~0); 214558#L1217-1 assume !(1 == ~E_5~0); 214559#L1222-1 assume !(1 == ~E_6~0); 215341#L1227-1 assume !(1 == ~E_7~0); 215342#L1232-1 assume !(1 == ~E_8~0); 215427#L1237-1 assume !(1 == ~E_9~0); 237427#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 237110#L1247-1 assume { :end_inline_reset_delta_events } true; 237108#L1553-2 [2023-11-29 05:59:32,112 INFO L750 eck$LassoCheckResult]: Loop: 237108#L1553-2 assume !false; 235933#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 235928#L999-1 assume !false; 235926#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 235924#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 235912#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 235911#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 235909#L854 assume !(0 != eval_~tmp~0#1); 235910#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 244368#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 244365#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 244362#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 244359#L1029-3 assume !(0 == ~T2_E~0); 244356#L1034-3 assume !(0 == ~T3_E~0); 244353#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 244350#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 244347#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 244343#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 244339#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 244336#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 244333#L1069-3 assume !(0 == ~T10_E~0); 244330#L1074-3 assume !(0 == ~E_M~0); 244327#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 244324#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 244320#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 244317#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 244314#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 244311#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 244308#L1109-3 assume !(0 == ~E_7~0); 244304#L1114-3 assume !(0 == ~E_8~0); 244300#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 244297#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 244294#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 244291#L502-36 assume !(1 == ~m_pc~0); 244288#L502-38 is_master_triggered_~__retres1~0#1 := 0; 244284#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 244280#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 244277#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 244273#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 244269#L521-36 assume !(1 == ~t1_pc~0); 244265#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 244259#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 244254#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 244249#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 244244#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 244238#L540-36 assume !(1 == ~t2_pc~0); 244233#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 244227#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 244221#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 216577#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 216578#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216565#L559-36 assume !(1 == ~t3_pc~0); 216566#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 216552#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 216553#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 216538#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 216539#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 216525#L578-36 assume !(1 == ~t4_pc~0); 216527#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 216510#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 216511#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 216498#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 216499#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 216484#L597-36 assume 1 == ~t5_pc~0; 216486#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 216470#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216471#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 216458#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 216459#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 216445#L616-36 assume !(1 == ~t6_pc~0); 216447#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 216429#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 216430#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 216416#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 216417#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 216402#L635-36 assume !(1 == ~t7_pc~0); 216403#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 216388#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 216389#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 216269#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 216270#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 216262#L654-36 assume 1 == ~t8_pc~0; 216263#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 216255#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 216256#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 216248#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 216249#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 216241#L673-36 assume !(1 == ~t9_pc~0); 216243#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 216232#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 216233#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 216225#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 216226#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 244044#L692-36 assume !(1 == ~t10_pc~0); 244043#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 244041#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 244040#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 244039#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 244038#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 244037#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 216139#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 244036#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 244035#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 241206#L1157-3 assume !(1 == ~T4_E~0); 244034#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 244033#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 244032#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 244031#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 216095#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 216096#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 216091#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 216092#L1197-3 assume !(1 == ~E_1~0); 216087#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 216088#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 216083#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 216084#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 216079#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 216080#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 216076#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 216074#L1237-3 assume !(1 == ~E_9~0); 216075#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 243449#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 243001#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 242989#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 242987#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 242983#L1572 assume !(0 == start_simulation_~tmp~3#1); 242980#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 242815#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 242807#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 242419#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 237118#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 237115#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 237113#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 237111#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 237108#L1553-2 [2023-11-29 05:59:32,113 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:32,113 INFO L85 PathProgramCache]: Analyzing trace with hash -1601336824, now seen corresponding path program 1 times [2023-11-29 05:59:32,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:32,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213641062] [2023-11-29 05:59:32,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:32,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:32,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:32,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:32,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:32,183 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [213641062] [2023-11-29 05:59:32,183 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [213641062] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:32,183 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:32,184 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 05:59:32,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [474011061] [2023-11-29 05:59:32,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:32,184 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:32,185 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:32,185 INFO L85 PathProgramCache]: Analyzing trace with hash 1588686052, now seen corresponding path program 1 times [2023-11-29 05:59:32,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:32,185 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619181510] [2023-11-29 05:59:32,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:32,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:32,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:32,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:32,231 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:32,231 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1619181510] [2023-11-29 05:59:32,231 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1619181510] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:32,232 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:32,232 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:32,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [713072737] [2023-11-29 05:59:32,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:32,232 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:32,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:32,233 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 05:59:32,233 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 05:59:32,234 INFO L87 Difference]: Start difference. First operand 59724 states and 86170 transitions. cyclomatic complexity: 26510 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:33,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:33,005 INFO L93 Difference]: Finished difference Result 144064 states and 206185 transitions. [2023-11-29 05:59:33,005 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 144064 states and 206185 transitions. [2023-11-29 05:59:33,656 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 143352 [2023-11-29 05:59:33,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 144064 states to 144064 states and 206185 transitions. [2023-11-29 05:59:33,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144064 [2023-11-29 05:59:33,973 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144064 [2023-11-29 05:59:33,973 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144064 states and 206185 transitions. [2023-11-29 05:59:34,318 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:34,318 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144064 states and 206185 transitions. [2023-11-29 05:59:34,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144064 states and 206185 transitions. [2023-11-29 05:59:35,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144064 to 61575. [2023-11-29 05:59:35,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61575 states, 61575 states have (on average 1.4294924888347544) internal successors, (88021), 61574 states have internal predecessors, (88021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:35,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61575 states to 61575 states and 88021 transitions. [2023-11-29 05:59:35,267 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61575 states and 88021 transitions. [2023-11-29 05:59:35,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 05:59:35,268 INFO L428 stractBuchiCegarLoop]: Abstraction has 61575 states and 88021 transitions. [2023-11-29 05:59:35,268 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-29 05:59:35,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61575 states and 88021 transitions. [2023-11-29 05:59:35,525 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 61204 [2023-11-29 05:59:35,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:35,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:35,527 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:35,527 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:35,527 INFO L748 eck$LassoCheckResult]: Stem: 418612#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 418613#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 419651#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 419652#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 419244#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 418895#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 418896#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 419208#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 419409#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 419082#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 419083#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 418948#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 418949#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 419353#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 419305#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 419217#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 419218#L1024 assume !(0 == ~M_E~0); 419531#L1024-2 assume !(0 == ~T1_E~0); 418608#L1029-1 assume !(0 == ~T2_E~0); 418609#L1034-1 assume !(0 == ~T3_E~0); 418715#L1039-1 assume !(0 == ~T4_E~0); 419683#L1044-1 assume !(0 == ~T5_E~0); 418971#L1049-1 assume !(0 == ~T6_E~0); 418972#L1054-1 assume !(0 == ~T7_E~0); 419243#L1059-1 assume !(0 == ~T8_E~0); 418661#L1064-1 assume !(0 == ~T9_E~0); 418662#L1069-1 assume !(0 == ~T10_E~0); 419495#L1074-1 assume !(0 == ~E_M~0); 419565#L1079-1 assume !(0 == ~E_1~0); 419534#L1084-1 assume !(0 == ~E_2~0); 419535#L1089-1 assume !(0 == ~E_3~0); 419596#L1094-1 assume !(0 == ~E_4~0); 419072#L1099-1 assume !(0 == ~E_5~0); 419073#L1104-1 assume !(0 == ~E_6~0); 419373#L1109-1 assume !(0 == ~E_7~0); 418837#L1114-1 assume !(0 == ~E_8~0); 418838#L1119-1 assume !(0 == ~E_9~0); 418905#L1124-1 assume !(0 == ~E_10~0); 418305#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 418306#L502 assume !(1 == ~m_pc~0); 418502#L502-2 is_master_triggered_~__retres1~0#1 := 0; 418434#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 418435#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 419299#L1273 assume !(0 != activate_threads_~tmp~1#1); 419300#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 419762#L521 assume !(1 == ~t1_pc~0); 419633#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 418356#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 418321#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 418322#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 418342#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 418343#L540 assume !(1 == ~t2_pc~0); 419193#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 419194#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 418833#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 418834#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 419626#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 418640#L559 assume !(1 == ~t3_pc~0); 418641#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 418926#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 418258#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 418259#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 418452#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 418453#L578 assume !(1 == ~t4_pc~0); 418572#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 419500#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 419528#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 419739#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 419278#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 419279#L597 assume 1 == ~t5_pc~0; 419793#L598 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 418376#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 418377#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 419529#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 419219#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 419220#L616 assume !(1 == ~t6_pc~0); 419238#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 419237#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 418809#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 418810#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 419060#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 419061#L635 assume 1 == ~t7_pc~0; 419283#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 418345#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 418731#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 419591#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 419210#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 419211#L654 assume !(1 == ~t8_pc~0); 419002#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 419003#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 419440#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 419441#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 419493#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 418606#L673 assume 1 == ~t9_pc~0; 418607#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 418296#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 418889#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 418890#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 419386#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 419387#L692 assume !(1 == ~t10_pc~0); 419323#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 419322#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 419063#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 419064#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 419076#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 419466#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 419867#L1142-2 assume !(1 == ~T1_E~0); 421242#L1147-1 assume !(1 == ~T2_E~0); 419866#L1152-1 assume !(1 == ~T3_E~0); 418933#L1157-1 assume !(1 == ~T4_E~0); 418934#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 421217#L1167-1 assume !(1 == ~T6_E~0); 421213#L1172-1 assume !(1 == ~T7_E~0); 421209#L1177-1 assume !(1 == ~T8_E~0); 421202#L1182-1 assume !(1 == ~T9_E~0); 421183#L1187-1 assume !(1 == ~T10_E~0); 421178#L1192-1 assume !(1 == ~E_M~0); 421171#L1197-1 assume !(1 == ~E_1~0); 421135#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 421133#L1207-1 assume !(1 == ~E_3~0); 421132#L1212-1 assume !(1 == ~E_4~0); 421131#L1217-1 assume !(1 == ~E_5~0); 421129#L1222-1 assume !(1 == ~E_6~0); 421128#L1227-1 assume !(1 == ~E_7~0); 421094#L1232-1 assume !(1 == ~E_8~0); 421090#L1237-1 assume !(1 == ~E_9~0); 421078#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 421069#L1247-1 assume { :end_inline_reset_delta_events } true; 421062#L1553-2 [2023-11-29 05:59:35,528 INFO L750 eck$LassoCheckResult]: Loop: 421062#L1553-2 assume !false; 421056#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 421052#L999-1 assume !false; 421051#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 421050#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 421039#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 421038#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 421036#L854 assume !(0 != eval_~tmp~0#1); 421037#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 432800#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 432799#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 432798#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 432797#L1029-3 assume !(0 == ~T2_E~0); 432796#L1034-3 assume !(0 == ~T3_E~0); 432795#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 432794#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 432793#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 432792#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 432791#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 432790#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 432789#L1069-3 assume !(0 == ~T10_E~0); 432788#L1074-3 assume !(0 == ~E_M~0); 432787#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 432786#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 432785#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 432784#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 432783#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 432782#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 432781#L1109-3 assume !(0 == ~E_7~0); 432780#L1114-3 assume !(0 == ~E_8~0); 432779#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 432778#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 432777#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 432776#L502-36 assume !(1 == ~m_pc~0); 432775#L502-38 is_master_triggered_~__retres1~0#1 := 0; 432774#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 432773#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 432772#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 432771#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 432770#L521-36 assume 1 == ~t1_pc~0; 432768#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 432767#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 432766#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 432765#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 432764#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 432763#L540-36 assume !(1 == ~t2_pc~0); 432762#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 432761#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 432760#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 432759#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 432758#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 432757#L559-36 assume !(1 == ~t3_pc~0); 432756#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 432755#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 432754#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 432753#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 432752#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 432751#L578-36 assume !(1 == ~t4_pc~0); 432750#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 432748#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 432746#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 432744#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 432739#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 432734#L597-36 assume 1 == ~t5_pc~0; 432730#L598-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 432725#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 432720#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 432715#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 432711#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 432706#L616-36 assume !(1 == ~t6_pc~0); 432702#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 432697#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 432692#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 432687#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 432683#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 432678#L635-36 assume 1 == ~t7_pc~0; 432674#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 432635#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 432629#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 432588#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 432547#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 432506#L654-36 assume !(1 == ~t8_pc~0); 432498#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 432456#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 432450#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 432414#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 432412#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 432411#L673-36 assume 1 == ~t9_pc~0; 432410#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 432408#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 432407#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 432400#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 432374#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 422870#L692-36 assume !(1 == ~t10_pc~0); 422868#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 422865#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 422862#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 422860#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 422317#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 422292#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 420232#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 422269#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 422262#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 422258#L1157-3 assume !(1 == ~T4_E~0); 422256#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 422255#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 422254#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 422253#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 422251#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 422236#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 422231#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 422222#L1197-3 assume !(1 == ~E_1~0); 422217#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 422212#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 422207#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 422201#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 422195#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 422190#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 421222#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 421215#L1237-3 assume !(1 == ~E_9~0); 421211#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 421207#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 421200#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 421181#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 421176#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 421169#L1572 assume !(0 == start_simulation_~tmp~3#1); 421166#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 421123#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 421097#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 421096#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 421095#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 421091#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 421079#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 421070#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 421062#L1553-2 [2023-11-29 05:59:35,528 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:35,528 INFO L85 PathProgramCache]: Analyzing trace with hash 360237834, now seen corresponding path program 1 times [2023-11-29 05:59:35,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:35,528 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433737832] [2023-11-29 05:59:35,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:35,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:35,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:35,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:35,568 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:35,568 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [433737832] [2023-11-29 05:59:35,568 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [433737832] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:35,568 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:35,568 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 05:59:35,569 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145964500] [2023-11-29 05:59:35,569 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:35,569 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:35,569 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:35,569 INFO L85 PathProgramCache]: Analyzing trace with hash -1839252828, now seen corresponding path program 1 times [2023-11-29 05:59:35,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:35,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1114722743] [2023-11-29 05:59:35,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:35,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:35,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:35,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:35,602 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:35,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1114722743] [2023-11-29 05:59:35,603 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1114722743] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:35,603 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:35,603 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:35,603 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1167310389] [2023-11-29 05:59:35,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:35,603 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:35,604 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:35,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:35,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:35,604 INFO L87 Difference]: Start difference. First operand 61575 states and 88021 transitions. cyclomatic complexity: 26510 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:36,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:36,065 INFO L93 Difference]: Finished difference Result 117170 states and 166838 transitions. [2023-11-29 05:59:36,065 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117170 states and 166838 transitions. [2023-11-29 05:59:36,407 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 116512 [2023-11-29 05:59:36,777 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117170 states to 117170 states and 166838 transitions. [2023-11-29 05:59:36,777 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117170 [2023-11-29 05:59:36,830 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117170 [2023-11-29 05:59:36,830 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117170 states and 166838 transitions. [2023-11-29 05:59:36,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:36,888 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117170 states and 166838 transitions. [2023-11-29 05:59:36,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117170 states and 166838 transitions. [2023-11-29 05:59:37,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117170 to 117042. [2023-11-29 05:59:37,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117042 states, 117042 states have (on average 1.424360485979392) internal successors, (166710), 117041 states have internal predecessors, (166710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:38,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117042 states to 117042 states and 166710 transitions. [2023-11-29 05:59:38,089 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117042 states and 166710 transitions. [2023-11-29 05:59:38,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 05:59:38,090 INFO L428 stractBuchiCegarLoop]: Abstraction has 117042 states and 166710 transitions. [2023-11-29 05:59:38,090 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-29 05:59:38,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117042 states and 166710 transitions. [2023-11-29 05:59:38,609 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 116384 [2023-11-29 05:59:38,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:38,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:38,611 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:38,611 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:38,612 INFO L748 eck$LassoCheckResult]: Stem: 597361#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 597362#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 598397#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 598398#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 597981#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 597639#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 597640#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 597947#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 598147#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 597822#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 597823#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 597698#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 597699#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 598090#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 598038#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 597955#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 597956#L1024 assume !(0 == ~M_E~0); 598280#L1024-2 assume !(0 == ~T1_E~0); 597356#L1029-1 assume !(0 == ~T2_E~0); 597357#L1034-1 assume !(0 == ~T3_E~0); 597462#L1039-1 assume !(0 == ~T4_E~0); 598430#L1044-1 assume !(0 == ~T5_E~0); 597716#L1049-1 assume !(0 == ~T6_E~0); 597717#L1054-1 assume !(0 == ~T7_E~0); 597980#L1059-1 assume !(0 == ~T8_E~0); 597407#L1064-1 assume !(0 == ~T9_E~0); 597408#L1069-1 assume !(0 == ~T10_E~0); 598240#L1074-1 assume !(0 == ~E_M~0); 598318#L1079-1 assume !(0 == ~E_1~0); 598282#L1084-1 assume !(0 == ~E_2~0); 598283#L1089-1 assume !(0 == ~E_3~0); 598341#L1094-1 assume !(0 == ~E_4~0); 597811#L1099-1 assume !(0 == ~E_5~0); 597812#L1104-1 assume !(0 == ~E_6~0); 598112#L1109-1 assume !(0 == ~E_7~0); 597580#L1114-1 assume !(0 == ~E_8~0); 597581#L1119-1 assume !(0 == ~E_9~0); 597655#L1124-1 assume !(0 == ~E_10~0); 597056#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 597057#L502 assume !(1 == ~m_pc~0); 597255#L502-2 is_master_triggered_~__retres1~0#1 := 0; 597185#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 597186#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 598034#L1273 assume !(0 != activate_threads_~tmp~1#1); 598035#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 598498#L521 assume !(1 == ~t1_pc~0); 598382#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 597109#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 597072#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 597073#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 597093#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 597094#L540 assume !(1 == ~t2_pc~0); 597932#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 597933#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 597578#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 597579#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 598371#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 597386#L559 assume !(1 == ~t3_pc~0); 597387#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 597671#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 597009#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 597010#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 597201#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 597202#L578 assume !(1 == ~t4_pc~0); 597328#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 598245#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 597141#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 597142#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 598015#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 598016#L597 assume !(1 == ~t5_pc~0); 597965#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 597128#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 597129#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 598278#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 597957#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 597958#L616 assume !(1 == ~t6_pc~0); 597977#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 597976#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 597552#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 597553#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 597800#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 597801#L635 assume 1 == ~t7_pc~0; 598018#L636 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 597096#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 597480#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 598336#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 597949#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 597950#L654 assume !(1 == ~t8_pc~0); 597744#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 597745#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 598188#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 598189#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 598238#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 597354#L673 assume 1 == ~t9_pc~0; 597355#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 597049#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 597633#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 597634#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 598127#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 598128#L692 assume !(1 == ~t10_pc~0); 598061#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 598060#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 597802#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 597803#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 597815#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 598214#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 598573#L1142-2 assume !(1 == ~T1_E~0); 603017#L1147-1 assume !(1 == ~T2_E~0); 598571#L1152-1 assume !(1 == ~T3_E~0); 598572#L1157-1 assume !(1 == ~T4_E~0); 602879#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 602877#L1167-1 assume !(1 == ~T6_E~0); 602875#L1172-1 assume !(1 == ~T7_E~0); 598385#L1177-1 assume !(1 == ~T8_E~0); 597998#L1182-1 assume !(1 == ~T9_E~0); 597999#L1187-1 assume !(1 == ~T10_E~0); 602189#L1192-1 assume !(1 == ~E_M~0); 602187#L1197-1 assume !(1 == ~E_1~0); 602185#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 601447#L1207-1 assume !(1 == ~E_3~0); 601445#L1212-1 assume !(1 == ~E_4~0); 601443#L1217-1 assume !(1 == ~E_5~0); 601441#L1222-1 assume !(1 == ~E_6~0); 600992#L1227-1 assume !(1 == ~E_7~0); 600989#L1232-1 assume !(1 == ~E_8~0); 600758#L1237-1 assume !(1 == ~E_9~0); 600755#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 600654#L1247-1 assume { :end_inline_reset_delta_events } true; 600650#L1553-2 [2023-11-29 05:59:38,612 INFO L750 eck$LassoCheckResult]: Loop: 600650#L1553-2 assume !false; 600649#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 600645#L999-1 assume !false; 600643#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 600486#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 600354#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 600344#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 600234#L854 assume !(0 != eval_~tmp~0#1); 600235#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 608988#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 608987#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 608986#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 608985#L1029-3 assume !(0 == ~T2_E~0); 608984#L1034-3 assume !(0 == ~T3_E~0); 608983#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 608981#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 608979#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 608977#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 608975#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 608973#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 608971#L1069-3 assume !(0 == ~T10_E~0); 608969#L1074-3 assume !(0 == ~E_M~0); 608966#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 608964#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 608962#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 608960#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 608958#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 608956#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 608954#L1109-3 assume !(0 == ~E_7~0); 608952#L1114-3 assume !(0 == ~E_8~0); 608950#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 608948#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 608946#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 608944#L502-36 assume !(1 == ~m_pc~0); 608942#L502-38 is_master_triggered_~__retres1~0#1 := 0; 608940#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 608938#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 608936#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 608934#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 608930#L521-36 assume 1 == ~t1_pc~0; 608927#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 608925#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 608923#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 608920#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 608918#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 608916#L540-36 assume !(1 == ~t2_pc~0); 608914#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 608912#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 608910#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 608908#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 608906#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 608904#L559-36 assume !(1 == ~t3_pc~0); 608901#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 608899#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 608897#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 608895#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 608893#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 608891#L578-36 assume 1 == ~t4_pc~0; 608889#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 608890#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 608990#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 608879#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 608877#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 608875#L597-36 assume !(1 == ~t5_pc~0); 608872#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 608870#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 608868#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 608867#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 608866#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 608865#L616-36 assume 1 == ~t6_pc~0; 608863#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 608862#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 608861#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 608860#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 608859#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 608858#L635-36 assume 1 == ~t7_pc~0; 608856#L636-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 608816#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 608790#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 608773#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 608769#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 608765#L654-36 assume !(1 == ~t8_pc~0); 608761#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 608759#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 608758#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 608757#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 608754#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 608752#L673-36 assume !(1 == ~t9_pc~0); 608749#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 608748#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 608745#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 608740#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 608728#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 608726#L692-36 assume 1 == ~t10_pc~0; 608723#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 608721#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 608719#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 608717#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 608715#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 608712#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 604018#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 604739#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 603894#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 603890#L1157-3 assume !(1 == ~T4_E~0); 603888#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 603886#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 603874#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 603872#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 603870#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 603868#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 603866#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 603862#L1197-3 assume !(1 == ~E_1~0); 603847#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 603837#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 603829#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 603823#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 603815#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 603807#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 603800#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 602989#L1237-3 assume !(1 == ~E_9~0); 603786#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 603782#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 602216#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 601461#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 601459#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 601004#L1572 assume !(0 == start_simulation_~tmp~3#1); 601002#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 600778#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 600770#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 600768#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 600766#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 600762#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 600659#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 600655#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 600650#L1553-2 [2023-11-29 05:59:38,613 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:38,613 INFO L85 PathProgramCache]: Analyzing trace with hash -671092981, now seen corresponding path program 1 times [2023-11-29 05:59:38,613 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:38,613 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [46689736] [2023-11-29 05:59:38,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:38,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:38,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:38,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:38,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:38,683 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [46689736] [2023-11-29 05:59:38,683 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [46689736] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:38,683 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:38,683 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:38,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1261835551] [2023-11-29 05:59:38,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:38,684 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:38,684 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:38,684 INFO L85 PathProgramCache]: Analyzing trace with hash -1827127967, now seen corresponding path program 1 times [2023-11-29 05:59:38,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:38,684 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977727441] [2023-11-29 05:59:38,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:38,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:38,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:38,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:38,751 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:38,752 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1977727441] [2023-11-29 05:59:38,752 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1977727441] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:38,752 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:38,752 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:38,752 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223844543] [2023-11-29 05:59:38,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:38,752 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:38,753 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:38,753 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 05:59:38,753 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 05:59:38,753 INFO L87 Difference]: Start difference. First operand 117042 states and 166710 transitions. cyclomatic complexity: 49796 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:39,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:39,849 INFO L93 Difference]: Finished difference Result 281557 states and 398399 transitions. [2023-11-29 05:59:39,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 281557 states and 398399 transitions. [2023-11-29 05:59:40,988 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 279812 [2023-11-29 05:59:41,605 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 281557 states to 281557 states and 398399 transitions. [2023-11-29 05:59:41,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281557 [2023-11-29 05:59:41,722 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281557 [2023-11-29 05:59:41,723 INFO L73 IsDeterministic]: Start isDeterministic. Operand 281557 states and 398399 transitions. [2023-11-29 05:59:41,848 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:41,848 INFO L218 hiAutomatonCegarLoop]: Abstraction has 281557 states and 398399 transitions. [2023-11-29 05:59:41,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281557 states and 398399 transitions. [2023-11-29 05:59:43,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281557 to 227265. [2023-11-29 05:59:43,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 227265 states, 227265 states have (on average 1.4180582139792752) internal successors, (322275), 227264 states have internal predecessors, (322275), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:44,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227265 states to 227265 states and 322275 transitions. [2023-11-29 05:59:44,732 INFO L240 hiAutomatonCegarLoop]: Abstraction has 227265 states and 322275 transitions. [2023-11-29 05:59:44,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 05:59:44,733 INFO L428 stractBuchiCegarLoop]: Abstraction has 227265 states and 322275 transitions. [2023-11-29 05:59:44,733 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-29 05:59:44,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 227265 states and 322275 transitions. [2023-11-29 05:59:45,190 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 226160 [2023-11-29 05:59:45,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:45,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:45,192 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:45,192 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:45,192 INFO L748 eck$LassoCheckResult]: Stem: 995974#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 995975#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 997049#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 997050#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 996621#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 996258#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 996259#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 996583#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 996790#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 996454#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 996455#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 996316#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 996317#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 996737#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 996685#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 996592#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 996593#L1024 assume !(0 == ~M_E~0); 996924#L1024-2 assume !(0 == ~T1_E~0); 995970#L1029-1 assume !(0 == ~T2_E~0); 995971#L1034-1 assume !(0 == ~T3_E~0); 996077#L1039-1 assume !(0 == ~T4_E~0); 997082#L1044-1 assume !(0 == ~T5_E~0); 996338#L1049-1 assume !(0 == ~T6_E~0); 996339#L1054-1 assume !(0 == ~T7_E~0); 996620#L1059-1 assume !(0 == ~T8_E~0); 996023#L1064-1 assume !(0 == ~T9_E~0); 996024#L1069-1 assume !(0 == ~T10_E~0); 996886#L1074-1 assume !(0 == ~E_M~0); 996967#L1079-1 assume !(0 == ~E_1~0); 996926#L1084-1 assume !(0 == ~E_2~0); 996927#L1089-1 assume !(0 == ~E_3~0); 996994#L1094-1 assume !(0 == ~E_4~0); 996442#L1099-1 assume !(0 == ~E_5~0); 996443#L1104-1 assume !(0 == ~E_6~0); 996757#L1109-1 assume !(0 == ~E_7~0); 996194#L1114-1 assume !(0 == ~E_8~0); 996195#L1119-1 assume !(0 == ~E_9~0); 996270#L1124-1 assume !(0 == ~E_10~0); 995666#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 995667#L502 assume !(1 == ~m_pc~0); 995863#L502-2 is_master_triggered_~__retres1~0#1 := 0; 995793#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 995794#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 996679#L1273 assume !(0 != activate_threads_~tmp~1#1); 996680#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 997138#L521 assume !(1 == ~t1_pc~0); 997033#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 995718#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 995682#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 995683#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 995704#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 995705#L540 assume !(1 == ~t2_pc~0); 996569#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 996570#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 996190#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 996191#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 997025#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 996002#L559 assume !(1 == ~t3_pc~0); 996003#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 996292#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 995619#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 995620#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 995811#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 995812#L578 assume !(1 == ~t4_pc~0); 995933#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 996892#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 996921#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 997124#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 996659#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 996660#L597 assume !(1 == ~t5_pc~0); 996603#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 995738#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 995739#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 996922#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 996594#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 996595#L616 assume !(1 == ~t6_pc~0); 996615#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 996614#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 996165#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 996166#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 996430#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 996431#L635 assume !(1 == ~t7_pc~0); 995706#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 995707#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 996093#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 996989#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 996586#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 996587#L654 assume !(1 == ~t8_pc~0); 996371#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 996372#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 996831#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 996832#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 996883#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 995968#L673 assume 1 == ~t9_pc~0; 995969#L674 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 995657#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 996252#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 996253#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 996773#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 996774#L692 assume !(1 == ~t10_pc~0); 996702#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 996701#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 996433#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 996434#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 996447#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 996856#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 995873#L1142-2 assume !(1 == ~T1_E~0); 995874#L1147-1 assume !(1 == ~T2_E~0); 997236#L1152-1 assume !(1 == ~T3_E~0); 997237#L1157-1 assume !(1 == ~T4_E~0); 996937#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 996938#L1167-1 assume !(1 == ~T6_E~0); 997014#L1172-1 assume !(1 == ~T7_E~0); 997015#L1177-1 assume !(1 == ~T8_E~0); 996642#L1182-1 assume !(1 == ~T9_E~0); 996643#L1187-1 assume !(1 == ~T10_E~0); 996824#L1192-1 assume !(1 == ~E_M~0); 996825#L1197-1 assume !(1 == ~E_1~0); 996843#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 996844#L1207-1 assume !(1 == ~E_3~0); 1032088#L1212-1 assume !(1 == ~E_4~0); 1032087#L1217-1 assume !(1 == ~E_5~0); 1032086#L1222-1 assume !(1 == ~E_6~0); 996543#L1227-1 assume !(1 == ~E_7~0); 996544#L1232-1 assume !(1 == ~E_8~0); 995596#L1237-1 assume !(1 == ~E_9~0); 995597#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 997108#L1247-1 assume { :end_inline_reset_delta_events } true; 1035965#L1553-2 [2023-11-29 05:59:45,193 INFO L750 eck$LassoCheckResult]: Loop: 1035965#L1553-2 assume !false; 1035963#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1035942#L999-1 assume !false; 1035938#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1035917#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1035905#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1035904#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1035886#L854 assume !(0 != eval_~tmp~0#1); 1035887#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1038668#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1038666#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1038664#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1038662#L1029-3 assume !(0 == ~T2_E~0); 1038660#L1034-3 assume !(0 == ~T3_E~0); 1038658#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1038656#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1038654#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1038652#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1038650#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1038648#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1038646#L1069-3 assume !(0 == ~T10_E~0); 1038644#L1074-3 assume !(0 == ~E_M~0); 1038642#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1038640#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1038638#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1038635#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1038633#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1038631#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1038629#L1109-3 assume !(0 == ~E_7~0); 1038627#L1114-3 assume !(0 == ~E_8~0); 1038625#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1038623#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1038621#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1038619#L502-36 assume !(1 == ~m_pc~0); 1038617#L502-38 is_master_triggered_~__retres1~0#1 := 0; 1038615#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1038613#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1038611#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1038609#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1038607#L521-36 assume !(1 == ~t1_pc~0); 1038605#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1038602#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1038598#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1038596#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1038594#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1038592#L540-36 assume !(1 == ~t2_pc~0); 1038589#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1038587#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1038585#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1038583#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1038581#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1038579#L559-36 assume !(1 == ~t3_pc~0); 1038577#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1038575#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1038573#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1038570#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 1038568#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1038566#L578-36 assume !(1 == ~t4_pc~0); 1038564#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1038782#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1038780#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1038482#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 1038479#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1038477#L597-36 assume !(1 == ~t5_pc~0); 1038475#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1038473#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1038470#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1038468#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1038466#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1038464#L616-36 assume !(1 == ~t6_pc~0); 1038462#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1038459#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1038457#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1038455#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1038453#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1038451#L635-36 assume !(1 == ~t7_pc~0); 1010428#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1038448#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1038445#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1038443#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1038441#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1038440#L654-36 assume !(1 == ~t8_pc~0); 1038439#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1038437#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1038435#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1038433#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1038401#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1037563#L673-36 assume 1 == ~t9_pc~0; 1037560#L674-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1037557#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1037555#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1037553#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1037551#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1037549#L692-36 assume !(1 == ~t10_pc~0); 1037546#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1037543#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1037541#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1037539#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 1037537#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1037535#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1027227#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1037530#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1037526#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1037522#L1157-3 assume !(1 == ~T4_E~0); 1037520#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1037518#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1037516#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1037514#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1037512#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1037510#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1037509#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1037506#L1197-3 assume !(1 == ~E_1~0); 1037505#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1037504#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1037492#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1037490#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1037488#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1037486#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1037484#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1031471#L1237-3 assume !(1 == ~E_9~0); 1037471#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1037463#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1037440#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1037427#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1036144#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1035995#L1572 assume !(0 == start_simulation_~tmp~3#1); 1035993#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1035985#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1035976#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1035974#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1035972#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1035970#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1035968#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1035966#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 1035965#L1553-2 [2023-11-29 05:59:45,193 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:45,193 INFO L85 PathProgramCache]: Analyzing trace with hash 1730432140, now seen corresponding path program 1 times [2023-11-29 05:59:45,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:45,194 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [196692738] [2023-11-29 05:59:45,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:45,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:45,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:45,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:45,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:45,238 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [196692738] [2023-11-29 05:59:45,238 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [196692738] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:45,238 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:45,238 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 05:59:45,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [712045467] [2023-11-29 05:59:45,238 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:45,239 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:45,239 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:45,239 INFO L85 PathProgramCache]: Analyzing trace with hash -658014041, now seen corresponding path program 1 times [2023-11-29 05:59:45,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:45,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1059412073] [2023-11-29 05:59:45,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:45,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:45,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:45,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:45,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:45,271 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1059412073] [2023-11-29 05:59:45,271 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1059412073] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:45,271 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:45,272 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:45,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1008373679] [2023-11-29 05:59:45,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:45,272 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:45,272 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:45,273 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:45,273 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:45,273 INFO L87 Difference]: Start difference. First operand 227265 states and 322275 transitions. cyclomatic complexity: 95138 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:46,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:46,943 INFO L93 Difference]: Finished difference Result 431696 states and 610128 transitions. [2023-11-29 05:59:46,943 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 431696 states and 610128 transitions. [2023-11-29 05:59:48,885 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 429184 [2023-11-29 05:59:50,130 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 431696 states to 431696 states and 610128 transitions. [2023-11-29 05:59:50,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 431696 [2023-11-29 05:59:50,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 431696 [2023-11-29 05:59:50,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 431696 states and 610128 transitions. [2023-11-29 05:59:50,442 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 05:59:50,442 INFO L218 hiAutomatonCegarLoop]: Abstraction has 431696 states and 610128 transitions. [2023-11-29 05:59:50,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431696 states and 610128 transitions. [2023-11-29 05:59:54,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431696 to 431184. [2023-11-29 05:59:54,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 431184 states, 431184 states have (on average 1.4138186945712272) internal successors, (609616), 431183 states have internal predecessors, (609616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:55,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 431184 states to 431184 states and 609616 transitions. [2023-11-29 05:59:55,735 INFO L240 hiAutomatonCegarLoop]: Abstraction has 431184 states and 609616 transitions. [2023-11-29 05:59:55,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 05:59:55,736 INFO L428 stractBuchiCegarLoop]: Abstraction has 431184 states and 609616 transitions. [2023-11-29 05:59:55,736 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-29 05:59:55,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 431184 states and 609616 transitions. [2023-11-29 05:59:57,100 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 428672 [2023-11-29 05:59:57,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 05:59:57,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 05:59:57,102 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:57,102 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 05:59:57,102 INFO L748 eck$LassoCheckResult]: Stem: 1654933#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1654934#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1655987#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1655988#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1655568#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 1655216#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1655217#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1655527#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1655739#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1655404#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1655405#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1655270#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1655271#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1655685#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1655627#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1655535#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1655536#L1024 assume !(0 == ~M_E~0); 1655875#L1024-2 assume !(0 == ~T1_E~0); 1654929#L1029-1 assume !(0 == ~T2_E~0); 1654930#L1034-1 assume !(0 == ~T3_E~0); 1655032#L1039-1 assume !(0 == ~T4_E~0); 1656021#L1044-1 assume !(0 == ~T5_E~0); 1655292#L1049-1 assume !(0 == ~T6_E~0); 1655293#L1054-1 assume !(0 == ~T7_E~0); 1655567#L1059-1 assume !(0 == ~T8_E~0); 1654980#L1064-1 assume !(0 == ~T9_E~0); 1654981#L1069-1 assume !(0 == ~T10_E~0); 1655836#L1074-1 assume !(0 == ~E_M~0); 1655914#L1079-1 assume !(0 == ~E_1~0); 1655879#L1084-1 assume !(0 == ~E_2~0); 1655880#L1089-1 assume !(0 == ~E_3~0); 1655939#L1094-1 assume !(0 == ~E_4~0); 1655393#L1099-1 assume !(0 == ~E_5~0); 1655394#L1104-1 assume !(0 == ~E_6~0); 1655705#L1109-1 assume !(0 == ~E_7~0); 1655153#L1114-1 assume !(0 == ~E_8~0); 1655154#L1119-1 assume !(0 == ~E_9~0); 1655227#L1124-1 assume !(0 == ~E_10~0); 1654632#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1654633#L502 assume !(1 == ~m_pc~0); 1654827#L502-2 is_master_triggered_~__retres1~0#1 := 0; 1654758#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1654759#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1655621#L1273 assume !(0 != activate_threads_~tmp~1#1); 1655622#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1656089#L521 assume !(1 == ~t1_pc~0); 1655974#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1654684#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1654648#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1654649#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 1654669#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1654670#L540 assume !(1 == ~t2_pc~0); 1655515#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1655516#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1655149#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1655150#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 1655969#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1654958#L559 assume !(1 == ~t3_pc~0); 1654959#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1655247#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1654585#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1654586#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 1654776#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1654777#L578 assume !(1 == ~t4_pc~0); 1654895#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1655841#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1655872#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1656071#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 1655600#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1655601#L597 assume !(1 == ~t5_pc~0); 1655550#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1654704#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1654705#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1655873#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 1655537#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1655538#L616 assume !(1 == ~t6_pc~0); 1655562#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1655561#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1655126#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1655127#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 1655381#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1655382#L635 assume !(1 == ~t7_pc~0); 1654671#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1654672#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1655049#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1655934#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 1655530#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1655531#L654 assume !(1 == ~t8_pc~0); 1655323#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1655324#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1655777#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1655778#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 1655834#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1654928#L673 assume !(1 == ~t9_pc~0); 1654622#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1654623#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1655210#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1655211#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 1655720#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1655721#L692 assume !(1 == ~t10_pc~0); 1655652#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1655651#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1655384#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1655385#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 1655398#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1655809#L1142 assume 1 == ~M_E~0;~M_E~0 := 2; 1654837#L1142-2 assume !(1 == ~T1_E~0); 1654838#L1147-1 assume !(1 == ~T2_E~0); 1655784#L1152-1 assume !(1 == ~T3_E~0); 1656182#L1157-1 assume !(1 == ~T4_E~0); 1770633#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1770632#L1167-1 assume !(1 == ~T6_E~0); 1770631#L1172-1 assume !(1 == ~T7_E~0); 1770630#L1177-1 assume !(1 == ~T8_E~0); 1770629#L1182-1 assume !(1 == ~T9_E~0); 1655711#L1187-1 assume !(1 == ~T10_E~0); 1655712#L1192-1 assume !(1 == ~E_M~0); 1655774#L1197-1 assume !(1 == ~E_1~0); 1781118#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1781116#L1207-1 assume !(1 == ~E_3~0); 1781114#L1212-1 assume !(1 == ~E_4~0); 1781112#L1217-1 assume !(1 == ~E_5~0); 1781111#L1222-1 assume !(1 == ~E_6~0); 1781110#L1227-1 assume !(1 == ~E_7~0); 1781108#L1232-1 assume !(1 == ~E_8~0); 1781104#L1237-1 assume !(1 == ~E_9~0); 1781102#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1776879#L1247-1 assume { :end_inline_reset_delta_events } true; 1776877#L1553-2 [2023-11-29 05:59:57,103 INFO L750 eck$LassoCheckResult]: Loop: 1776877#L1553-2 assume !false; 1776874#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1776870#L999-1 assume !false; 1776869#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1775256#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1775244#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1774579#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1774575#L854 assume !(0 != eval_~tmp~0#1); 1774576#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1826721#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1826717#L1024-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1826712#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1826706#L1029-3 assume !(0 == ~T2_E~0); 1826700#L1034-3 assume !(0 == ~T3_E~0); 1826695#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1826690#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1826686#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1826682#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1826676#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1826672#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1826668#L1069-3 assume !(0 == ~T10_E~0); 1826664#L1074-3 assume !(0 == ~E_M~0); 1826659#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1826655#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1826650#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1826646#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1826642#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1826639#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1826636#L1109-3 assume !(0 == ~E_7~0); 1826633#L1114-3 assume !(0 == ~E_8~0); 1826628#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1826625#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1826621#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1826618#L502-36 assume !(1 == ~m_pc~0); 1826615#L502-38 is_master_triggered_~__retres1~0#1 := 0; 1826612#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1826606#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1826601#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1826595#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1826590#L521-36 assume !(1 == ~t1_pc~0); 1826586#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1826581#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1826577#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1826573#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1826568#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1826564#L540-36 assume !(1 == ~t2_pc~0); 1826560#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1826556#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1826550#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1826546#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1826542#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1826538#L559-36 assume !(1 == ~t3_pc~0); 1826534#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1826531#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1826527#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1826523#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 1826518#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1826513#L578-36 assume !(1 == ~t4_pc~0); 1826509#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1826503#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1826497#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1826492#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 1826486#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1826481#L597-36 assume !(1 == ~t5_pc~0); 1826476#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1826470#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1826465#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1826461#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1826457#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1826453#L616-36 assume !(1 == ~t6_pc~0); 1826449#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1826445#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1826442#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1826439#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1826434#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1806749#L635-36 assume !(1 == ~t7_pc~0); 1806742#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1806736#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1806728#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1806722#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1806716#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1806709#L654-36 assume !(1 == ~t8_pc~0); 1806701#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1806692#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1806682#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1806674#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1806669#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1806664#L673-36 assume !(1 == ~t9_pc~0); 1806580#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1806579#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1806562#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1806555#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1806109#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1806106#L692-36 assume !(1 == ~t10_pc~0); 1806104#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1806101#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1806099#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1806097#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 1806096#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1806095#L1142-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1742305#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1806090#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1806088#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1804626#L1157-3 assume !(1 == ~T4_E~0); 1806085#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1806083#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1806081#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1806079#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1806077#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1806075#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1806073#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1803744#L1197-3 assume !(1 == ~E_1~0); 1806070#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1806068#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1806066#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1806064#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1806062#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1806060#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1806058#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1806054#L1237-3 assume !(1 == ~E_9~0); 1806052#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1806050#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1782222#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1782211#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1782210#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1776914#L1572 assume !(0 == start_simulation_~tmp~3#1); 1776912#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1776898#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1776890#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1776888#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 1776886#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1776884#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1776882#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1776880#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 1776877#L1553-2 [2023-11-29 05:59:57,103 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:57,103 INFO L85 PathProgramCache]: Analyzing trace with hash -1513086067, now seen corresponding path program 1 times [2023-11-29 05:59:57,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:57,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [518415300] [2023-11-29 05:59:57,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:57,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:57,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:57,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:57,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:57,153 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [518415300] [2023-11-29 05:59:57,153 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [518415300] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:57,153 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:57,153 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 05:59:57,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1050246643] [2023-11-29 05:59:57,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:57,154 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 05:59:57,154 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 05:59:57,155 INFO L85 PathProgramCache]: Analyzing trace with hash 1743511080, now seen corresponding path program 1 times [2023-11-29 05:59:57,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 05:59:57,155 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848312270] [2023-11-29 05:59:57,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 05:59:57,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 05:59:57,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 05:59:57,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 05:59:57,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 05:59:57,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848312270] [2023-11-29 05:59:57,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [848312270] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 05:59:57,188 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 05:59:57,188 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 05:59:57,188 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2022956986] [2023-11-29 05:59:57,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 05:59:57,189 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 05:59:57,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 05:59:57,189 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 05:59:57,189 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 05:59:57,189 INFO L87 Difference]: Start difference. First operand 431184 states and 609616 transitions. cyclomatic complexity: 178688 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 05:59:58,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 05:59:58,965 INFO L93 Difference]: Finished difference Result 489437 states and 691881 transitions. [2023-11-29 05:59:58,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 489437 states and 691881 transitions. [2023-11-29 06:00:01,206 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 486656 [2023-11-29 06:00:02,145 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 489437 states to 489437 states and 691881 transitions. [2023-11-29 06:00:02,145 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 489437 [2023-11-29 06:00:02,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 489437 [2023-11-29 06:00:02,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 489437 states and 691881 transitions. [2023-11-29 06:00:02,828 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 06:00:02,828 INFO L218 hiAutomatonCegarLoop]: Abstraction has 489437 states and 691881 transitions. [2023-11-29 06:00:03,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 489437 states and 691881 transitions. [2023-11-29 06:00:04,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 489437 to 121736. [2023-11-29 06:00:04,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121736 states, 121736 states have (on average 1.4184629033318) internal successors, (172678), 121735 states have internal predecessors, (172678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:05,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121736 states to 121736 states and 172678 transitions. [2023-11-29 06:00:05,097 INFO L240 hiAutomatonCegarLoop]: Abstraction has 121736 states and 172678 transitions. [2023-11-29 06:00:05,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 06:00:05,098 INFO L428 stractBuchiCegarLoop]: Abstraction has 121736 states and 172678 transitions. [2023-11-29 06:00:05,098 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-29 06:00:05,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121736 states and 172678 transitions. [2023-11-29 06:00:05,408 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 121024 [2023-11-29 06:00:05,409 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 06:00:05,409 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 06:00:05,410 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:05,410 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:05,411 INFO L748 eck$LassoCheckResult]: Stem: 2575568#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 2575569#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 2576591#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2576592#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2576196#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 2575850#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2575851#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2576161#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2576363#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2576037#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2576038#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2575908#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2575909#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2576304#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2576257#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2576169#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2576170#L1024 assume !(0 == ~M_E~0); 2576489#L1024-2 assume !(0 == ~T1_E~0); 2575563#L1029-1 assume !(0 == ~T2_E~0); 2575564#L1034-1 assume !(0 == ~T3_E~0); 2575667#L1039-1 assume !(0 == ~T4_E~0); 2576621#L1044-1 assume !(0 == ~T5_E~0); 2575928#L1049-1 assume !(0 == ~T6_E~0); 2575929#L1054-1 assume !(0 == ~T7_E~0); 2576195#L1059-1 assume !(0 == ~T8_E~0); 2575617#L1064-1 assume !(0 == ~T9_E~0); 2575618#L1069-1 assume !(0 == ~T10_E~0); 2576451#L1074-1 assume !(0 == ~E_M~0); 2576524#L1079-1 assume !(0 == ~E_1~0); 2576491#L1084-1 assume !(0 == ~E_2~0); 2576492#L1089-1 assume !(0 == ~E_3~0); 2576547#L1094-1 assume !(0 == ~E_4~0); 2576026#L1099-1 assume !(0 == ~E_5~0); 2576027#L1104-1 assume !(0 == ~E_6~0); 2576328#L1109-1 assume !(0 == ~E_7~0); 2575785#L1114-1 assume !(0 == ~E_8~0); 2575786#L1119-1 assume !(0 == ~E_9~0); 2575865#L1124-1 assume !(0 == ~E_10~0); 2575262#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2575263#L502 assume !(1 == ~m_pc~0); 2575460#L502-2 is_master_triggered_~__retres1~0#1 := 0; 2575391#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2575392#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2576253#L1273 assume !(0 != activate_threads_~tmp~1#1); 2576254#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2576695#L521 assume !(1 == ~t1_pc~0); 2576577#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2575314#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2575278#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2575279#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 2575298#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2575299#L540 assume !(1 == ~t2_pc~0); 2576147#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2576148#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2575783#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2575784#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 2576573#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2575595#L559 assume !(1 == ~t3_pc~0); 2575596#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2575881#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2575215#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2575216#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 2575407#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2575408#L578 assume !(1 == ~t4_pc~0); 2575533#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2576456#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2576486#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2576680#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 2576233#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2576234#L597 assume !(1 == ~t5_pc~0); 2576178#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2575332#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2575333#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2576487#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 2576171#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2576172#L616 assume !(1 == ~t6_pc~0); 2576192#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2576191#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2575758#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2575759#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 2576016#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2576017#L635 assume !(1 == ~t7_pc~0); 2575300#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2575301#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2575685#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2576543#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 2576163#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2576164#L654 assume !(1 == ~t8_pc~0); 2575957#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2575958#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2576400#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2576401#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 2576447#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2575562#L673 assume !(1 == ~t9_pc~0); 2575254#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2575255#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2575844#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2575845#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 2576341#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2576342#L692 assume !(1 == ~t10_pc~0); 2576279#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2576278#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2576018#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2576019#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 2576030#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2576422#L1142 assume !(1 == ~M_E~0); 2575468#L1142-2 assume !(1 == ~T1_E~0); 2575469#L1147-1 assume !(1 == ~T2_E~0); 2576405#L1152-1 assume !(1 == ~T3_E~0); 2575887#L1157-1 assume !(1 == ~T4_E~0); 2575888#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2576055#L1167-1 assume !(1 == ~T6_E~0); 2576056#L1172-1 assume !(1 == ~T7_E~0); 2576566#L1177-1 assume !(1 == ~T8_E~0); 2576212#L1182-1 assume !(1 == ~T9_E~0); 2576213#L1187-1 assume !(1 == ~T10_E~0); 2576334#L1192-1 assume !(1 == ~E_M~0); 2575736#L1197-1 assume !(1 == ~E_1~0); 2575737#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2576152#L1207-1 assume !(1 == ~E_3~0); 2576126#L1212-1 assume !(1 == ~E_4~0); 2575317#L1217-1 assume !(1 == ~E_5~0); 2575318#L1222-1 assume !(1 == ~E_6~0); 2576122#L1227-1 assume !(1 == ~E_7~0); 2576123#L1232-1 assume !(1 == ~E_8~0); 2575192#L1237-1 assume !(1 == ~E_9~0); 2575193#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2576193#L1247-1 assume { :end_inline_reset_delta_events } true; 2576194#L1553-2 [2023-11-29 06:00:05,411 INFO L750 eck$LassoCheckResult]: Loop: 2576194#L1553-2 assume !false; 2617611#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2617598#L999-1 assume !false; 2617534#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2617297#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2617286#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2617284#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2617282#L854 assume !(0 != eval_~tmp~0#1); 2617283#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2633705#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2633701#L1024-3 assume !(0 == ~M_E~0); 2633697#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2633692#L1029-3 assume !(0 == ~T2_E~0); 2633688#L1034-3 assume !(0 == ~T3_E~0); 2633683#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2633678#L1044-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2633673#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2633668#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2633663#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2633658#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2633653#L1069-3 assume !(0 == ~T10_E~0); 2633648#L1074-3 assume !(0 == ~E_M~0); 2633642#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2633637#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2633632#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2633627#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2633622#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2633617#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2633612#L1109-3 assume !(0 == ~E_7~0); 2633607#L1114-3 assume !(0 == ~E_8~0); 2633601#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2633595#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2633587#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2633580#L502-36 assume !(1 == ~m_pc~0); 2633573#L502-38 is_master_triggered_~__retres1~0#1 := 0; 2633567#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2633562#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2633557#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2633551#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2633545#L521-36 assume 1 == ~t1_pc~0; 2633537#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2633529#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2633521#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2633514#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2633507#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2633501#L540-36 assume !(1 == ~t2_pc~0); 2633495#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2633488#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2633483#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2633477#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2633471#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2633464#L559-36 assume !(1 == ~t3_pc~0); 2633456#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2633449#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2633442#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2633436#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 2633429#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2633423#L578-36 assume 1 == ~t4_pc~0; 2633417#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2633409#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2633401#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2633394#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2633385#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2633378#L597-36 assume !(1 == ~t5_pc~0); 2633370#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2633362#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2633353#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2633345#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2633335#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2633328#L616-36 assume !(1 == ~t6_pc~0); 2633320#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 2633310#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2632819#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2632814#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2632810#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2631926#L635-36 assume !(1 == ~t7_pc~0); 2631925#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2631924#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2631923#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2631922#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2631920#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2631918#L654-36 assume 1 == ~t8_pc~0; 2631915#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2631913#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2631911#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2631909#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2631907#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2631905#L673-36 assume !(1 == ~t9_pc~0); 2631903#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 2631901#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2631899#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2631897#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2631895#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2631893#L692-36 assume 1 == ~t10_pc~0; 2631890#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2631888#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2631886#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2631884#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 2631882#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2631880#L1142-3 assume !(1 == ~M_E~0); 2597453#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2631877#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2631875#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2631873#L1157-3 assume !(1 == ~T4_E~0); 2631871#L1162-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2631869#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2631867#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2631865#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2631863#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2631861#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2631859#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2631856#L1197-3 assume !(1 == ~E_1~0); 2631854#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2631852#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2631850#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2631848#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2631846#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2631844#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2631842#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2631840#L1237-3 assume !(1 == ~E_9~0); 2631839#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2631258#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2630949#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2630934#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2628965#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 2597574#L1572 assume !(0 == start_simulation_~tmp~3#1); 2597575#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2617767#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2617758#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2617756#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 2617754#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2617752#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2617750#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2617626#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 2576194#L1553-2 [2023-11-29 06:00:05,411 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:05,411 INFO L85 PathProgramCache]: Analyzing trace with hash 976442895, now seen corresponding path program 1 times [2023-11-29 06:00:05,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:05,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185596331] [2023-11-29 06:00:05,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:05,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:05,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:05,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:05,488 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:05,488 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [185596331] [2023-11-29 06:00:05,488 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [185596331] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:05,488 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:05,489 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:05,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [129257915] [2023-11-29 06:00:05,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:05,489 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 06:00:05,489 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:05,490 INFO L85 PathProgramCache]: Analyzing trace with hash -2104005086, now seen corresponding path program 1 times [2023-11-29 06:00:05,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:05,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823261624] [2023-11-29 06:00:05,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:05,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:05,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:05,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:05,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:05,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1823261624] [2023-11-29 06:00:05,532 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1823261624] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:05,532 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:05,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:05,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [899469297] [2023-11-29 06:00:05,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:05,532 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 06:00:05,532 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 06:00:05,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 06:00:05,533 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 06:00:05,533 INFO L87 Difference]: Start difference. First operand 121736 states and 172678 transitions. cyclomatic complexity: 50974 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:06,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 06:00:06,440 INFO L93 Difference]: Finished difference Result 191514 states and 271279 transitions. [2023-11-29 06:00:06,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191514 states and 271279 transitions. [2023-11-29 06:00:07,161 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 190400 [2023-11-29 06:00:07,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191514 states to 191514 states and 271279 transitions. [2023-11-29 06:00:07,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191514 [2023-11-29 06:00:07,571 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191514 [2023-11-29 06:00:07,571 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191514 states and 271279 transitions. [2023-11-29 06:00:07,639 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 06:00:07,640 INFO L218 hiAutomatonCegarLoop]: Abstraction has 191514 states and 271279 transitions. [2023-11-29 06:00:07,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191514 states and 271279 transitions. [2023-11-29 06:00:08,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191514 to 134633. [2023-11-29 06:00:09,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134633 states, 134633 states have (on average 1.420974055395037) internal successors, (191310), 134632 states have internal predecessors, (191310), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:09,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134633 states to 134633 states and 191310 transitions. [2023-11-29 06:00:09,245 INFO L240 hiAutomatonCegarLoop]: Abstraction has 134633 states and 191310 transitions. [2023-11-29 06:00:09,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 06:00:09,246 INFO L428 stractBuchiCegarLoop]: Abstraction has 134633 states and 191310 transitions. [2023-11-29 06:00:09,246 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-29 06:00:09,246 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134633 states and 191310 transitions. [2023-11-29 06:00:09,937 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 133824 [2023-11-29 06:00:09,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 06:00:09,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 06:00:09,940 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:09,940 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:09,940 INFO L748 eck$LassoCheckResult]: Stem: 2888824#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 2888825#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 2889849#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2889850#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2889440#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 2889100#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2889101#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2889401#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2889610#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2889279#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2889280#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2889154#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2889155#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2889551#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2889497#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2889413#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2889414#L1024 assume !(0 == ~M_E~0); 2889737#L1024-2 assume !(0 == ~T1_E~0); 2888820#L1029-1 assume !(0 == ~T2_E~0); 2888821#L1034-1 assume !(0 == ~T3_E~0); 2888922#L1039-1 assume !(0 == ~T4_E~0); 2889880#L1044-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2889881#L1049-1 assume !(0 == ~T6_E~0); 2890039#L1054-1 assume !(0 == ~T7_E~0); 2890040#L1059-1 assume !(0 == ~T8_E~0); 2888872#L1064-1 assume !(0 == ~T9_E~0); 2888873#L1069-1 assume !(0 == ~T10_E~0); 2889993#L1074-1 assume !(0 == ~E_M~0); 2889994#L1079-1 assume !(0 == ~E_1~0); 2889739#L1084-1 assume !(0 == ~E_2~0); 2889740#L1089-1 assume !(0 == ~E_3~0); 2889802#L1094-1 assume !(0 == ~E_4~0); 2889803#L1099-1 assume !(0 == ~E_5~0); 2889908#L1104-1 assume !(0 == ~E_6~0); 2889909#L1109-1 assume !(0 == ~E_7~0); 2889040#L1114-1 assume !(0 == ~E_8~0); 2889041#L1119-1 assume !(0 == ~E_9~0); 2889110#L1124-1 assume !(0 == ~E_10~0); 2889111#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2889598#L502 assume !(1 == ~m_pc~0); 2889599#L502-2 is_master_triggered_~__retres1~0#1 := 0; 2888647#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2888648#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2889491#L1273 assume !(0 != activate_threads_~tmp~1#1); 2889492#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2889943#L521 assume !(1 == ~t1_pc~0); 2889944#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2890064#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2888536#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2888537#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 2888557#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2888558#L540 assume !(1 == ~t2_pc~0); 2889388#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2889389#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2889036#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2889037#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 2889832#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2889833#L559 assume !(1 == ~t3_pc~0); 2889255#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2889256#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2888473#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2888474#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 2888665#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2888666#L578 assume !(1 == ~t4_pc~0); 2888785#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2889704#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2890055#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2890056#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 2889469#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2889470#L597 assume !(1 == ~t5_pc~0); 2889422#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2889423#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2889734#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2889735#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 2889415#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2889416#L616 assume !(1 == ~t6_pc~0); 2889433#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2889432#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2889013#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2889014#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 2889326#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2889568#L635 assume !(1 == ~t7_pc~0); 2889569#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2890062#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2890014#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2890015#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 2889407#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2889408#L654 assume !(1 == ~t8_pc~0); 2889205#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2889206#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2889834#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2889693#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 2889694#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2889865#L673 assume !(1 == ~t9_pc~0); 2888510#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2888511#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2889093#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2889094#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 2889587#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2889588#L692 assume !(1 == ~t10_pc~0); 2889518#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2889517#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2889869#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2889272#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 2889273#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2890030#L1142 assume !(1 == ~M_E~0); 2890031#L1142-2 assume !(1 == ~T1_E~0); 2889645#L1147-1 assume !(1 == ~T2_E~0); 2889646#L1152-1 assume !(1 == ~T3_E~0); 2889140#L1157-1 assume !(1 == ~T4_E~0); 2889141#L1162-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2889299#L1167-1 assume !(1 == ~T6_E~0); 2889300#L1172-1 assume !(1 == ~T7_E~0); 2889824#L1177-1 assume !(1 == ~T8_E~0); 2889455#L1182-1 assume !(1 == ~T9_E~0); 2889456#L1187-1 assume !(1 == ~T10_E~0); 2889580#L1192-1 assume !(1 == ~E_M~0); 2888991#L1197-1 assume !(1 == ~E_1~0); 2888992#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2889392#L1207-1 assume !(1 == ~E_3~0); 2889366#L1212-1 assume !(1 == ~E_4~0); 2888577#L1217-1 assume !(1 == ~E_5~0); 2888578#L1222-1 assume !(1 == ~E_6~0); 2889363#L1227-1 assume !(1 == ~E_7~0); 2889364#L1232-1 assume !(1 == ~E_8~0); 2888451#L1237-1 assume !(1 == ~E_9~0); 2888452#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2889436#L1247-1 assume { :end_inline_reset_delta_events } true; 2889437#L1553-2 [2023-11-29 06:00:09,941 INFO L750 eck$LassoCheckResult]: Loop: 2889437#L1553-2 assume !false; 2959643#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2959636#L999-1 assume !false; 2959633#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2959596#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2959584#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2959581#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2959579#L854 assume !(0 != eval_~tmp~0#1); 2889656#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2889282#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2889283#L1024-3 assume !(0 == ~M_E~0); 2889868#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2889252#L1029-3 assume !(0 == ~T2_E~0); 2889218#L1034-3 assume !(0 == ~T3_E~0); 2889219#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2889615#L1044-3 assume !(0 == ~T5_E~0); 2888814#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2888815#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2888573#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2888574#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2889187#L1069-3 assume !(0 == ~T10_E~0); 2889188#L1074-3 assume !(0 == ~E_M~0); 2889582#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2889448#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2889320#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2889321#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2889238#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2889239#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2889613#L1109-3 assume !(0 == ~E_7~0); 2889595#L1114-3 assume !(0 == ~E_8~0); 2889596#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2889977#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2889992#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2889930#L502-36 assume !(1 == ~m_pc~0); 2889931#L502-38 is_master_triggered_~__retres1~0#1 := 0; 3023053#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3023052#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3023051#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3023050#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2889159#L521-36 assume 1 == ~t1_pc~0; 2889160#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2889170#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3023015#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2889979#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2889701#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2889702#L540-36 assume !(1 == ~t2_pc~0); 2888525#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2888526#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2888943#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2889703#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2889294#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2888449#L559-36 assume !(1 == ~t3_pc~0); 2888450#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2888911#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2889089#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2889090#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 2889457#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2889777#L578-36 assume !(1 == ~t4_pc~0); 2889375#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 2889376#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2889309#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2889310#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 2889193#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2889194#L597-36 assume !(1 == ~t5_pc~0); 2889443#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2889913#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2889831#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2889391#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2888989#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2888990#L616-36 assume !(1 == ~t6_pc~0); 2889859#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 2888516#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2888517#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2889068#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2889249#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2889633#L635-36 assume !(1 == ~t7_pc~0); 3021551#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3021545#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3021539#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3021533#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3021525#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3021517#L654-36 assume !(1 == ~t8_pc~0); 3021510#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 3021502#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3021497#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3021492#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3021485#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3021476#L673-36 assume !(1 == ~t9_pc~0); 3021468#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3021460#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3021452#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3021444#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3021435#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3021425#L692-36 assume 1 == ~t10_pc~0; 3021416#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3021409#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3021403#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3021396#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 3021387#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3021378#L1142-3 assume !(1 == ~M_E~0); 2912743#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3021368#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3021361#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3021355#L1157-3 assume !(1 == ~T4_E~0); 3021300#L1162-3 assume !(1 == ~T5_E~0); 3021297#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3021294#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3021292#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3021290#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3021289#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3021286#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3021284#L1197-3 assume !(1 == ~E_1~0); 3021282#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3021279#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3021277#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3021275#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3021273#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3021271#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3021269#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3021266#L1237-3 assume !(1 == ~E_9~0); 3021264#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3021262#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3019602#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3015859#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3015856#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 2912905#L1572 assume !(0 == start_simulation_~tmp~3#1); 2912906#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2959667#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2959659#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2959657#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 2959655#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2959653#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2959651#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2959646#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 2889437#L1553-2 [2023-11-29 06:00:09,941 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:09,941 INFO L85 PathProgramCache]: Analyzing trace with hash -1176663923, now seen corresponding path program 1 times [2023-11-29 06:00:09,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:09,941 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090876168] [2023-11-29 06:00:09,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:09,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:09,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:09,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:09,988 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:09,988 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090876168] [2023-11-29 06:00:09,988 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1090876168] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:09,988 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:09,988 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:09,988 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1352347189] [2023-11-29 06:00:09,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:09,989 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 06:00:09,989 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:09,989 INFO L85 PathProgramCache]: Analyzing trace with hash 1199254630, now seen corresponding path program 1 times [2023-11-29 06:00:09,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:09,990 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911138804] [2023-11-29 06:00:09,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:09,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:09,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:10,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:10,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:10,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911138804] [2023-11-29 06:00:10,020 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [911138804] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:10,020 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:10,020 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:10,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1522774556] [2023-11-29 06:00:10,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:10,020 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 06:00:10,020 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 06:00:10,021 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 06:00:10,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 06:00:10,021 INFO L87 Difference]: Start difference. First operand 134633 states and 191310 transitions. cyclomatic complexity: 56709 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:10,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 06:00:10,449 INFO L93 Difference]: Finished difference Result 178600 states and 252164 transitions. [2023-11-29 06:00:10,449 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178600 states and 252164 transitions. [2023-11-29 06:00:11,421 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 177600 [2023-11-29 06:00:11,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178600 states to 178600 states and 252164 transitions. [2023-11-29 06:00:11,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178600 [2023-11-29 06:00:11,739 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178600 [2023-11-29 06:00:11,739 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178600 states and 252164 transitions. [2023-11-29 06:00:11,791 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 06:00:11,791 INFO L218 hiAutomatonCegarLoop]: Abstraction has 178600 states and 252164 transitions. [2023-11-29 06:00:11,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178600 states and 252164 transitions. [2023-11-29 06:00:12,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178600 to 121736. [2023-11-29 06:00:13,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121736 states, 121736 states have (on average 1.415292107511336) internal successors, (172292), 121735 states have internal predecessors, (172292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:13,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121736 states to 121736 states and 172292 transitions. [2023-11-29 06:00:13,309 INFO L240 hiAutomatonCegarLoop]: Abstraction has 121736 states and 172292 transitions. [2023-11-29 06:00:13,310 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 06:00:13,310 INFO L428 stractBuchiCegarLoop]: Abstraction has 121736 states and 172292 transitions. [2023-11-29 06:00:13,310 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-29 06:00:13,310 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121736 states and 172292 transitions. [2023-11-29 06:00:13,661 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 121024 [2023-11-29 06:00:13,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 06:00:13,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 06:00:13,663 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:13,663 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:13,664 INFO L748 eck$LassoCheckResult]: Stem: 3202066#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3202067#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3203052#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3203053#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3202677#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3202343#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3202344#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3202642#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3202839#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3202523#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3202524#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3202400#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3202401#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3202787#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3202736#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3202649#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3202650#L1024 assume !(0 == ~M_E~0); 3202950#L1024-2 assume !(0 == ~T1_E~0); 3202060#L1029-1 assume !(0 == ~T2_E~0); 3202061#L1034-1 assume !(0 == ~T3_E~0); 3202162#L1039-1 assume !(0 == ~T4_E~0); 3203081#L1044-1 assume !(0 == ~T5_E~0); 3202419#L1049-1 assume !(0 == ~T6_E~0); 3202420#L1054-1 assume !(0 == ~T7_E~0); 3202676#L1059-1 assume !(0 == ~T8_E~0); 3202111#L1064-1 assume !(0 == ~T9_E~0); 3202112#L1069-1 assume !(0 == ~T10_E~0); 3202914#L1074-1 assume !(0 == ~E_M~0); 3202987#L1079-1 assume !(0 == ~E_1~0); 3202953#L1084-1 assume !(0 == ~E_2~0); 3202954#L1089-1 assume !(0 == ~E_3~0); 3203009#L1094-1 assume !(0 == ~E_4~0); 3202511#L1099-1 assume !(0 == ~E_5~0); 3202512#L1104-1 assume !(0 == ~E_6~0); 3202806#L1109-1 assume !(0 == ~E_7~0); 3202278#L1114-1 assume !(0 == ~E_8~0); 3202279#L1119-1 assume !(0 == ~E_9~0); 3202356#L1124-1 assume !(0 == ~E_10~0); 3201762#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3201763#L502 assume !(1 == ~m_pc~0); 3201962#L502-2 is_master_triggered_~__retres1~0#1 := 0; 3201893#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3201894#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3202732#L1273 assume !(0 != activate_threads_~tmp~1#1); 3202733#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3203131#L521 assume !(1 == ~t1_pc~0); 3203038#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3201815#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3201778#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3201779#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 3201799#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3201800#L540 assume !(1 == ~t2_pc~0); 3202629#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3202630#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3202276#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3202277#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 3203034#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3202090#L559 assume !(1 == ~t3_pc~0); 3202091#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3202374#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3201715#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3201716#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 3201909#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3201910#L578 assume !(1 == ~t4_pc~0); 3202029#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3202920#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3202947#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3203115#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 3202710#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3202711#L597 assume !(1 == ~t5_pc~0); 3202661#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3201833#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3201834#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3202948#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3202651#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3202652#L616 assume !(1 == ~t6_pc~0); 3202673#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3202672#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3202252#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3202253#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3202501#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3202502#L635 assume !(1 == ~t7_pc~0); 3201801#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3201802#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3202179#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3203004#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3202644#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3202645#L654 assume !(1 == ~t8_pc~0); 3202446#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3202447#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3202867#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3202868#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3202910#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3202059#L673 assume !(1 == ~t9_pc~0); 3201754#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3201755#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3202336#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3202337#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3202820#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3202821#L692 assume !(1 == ~t10_pc~0); 3202756#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3202755#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3202503#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3202504#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3202516#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3202887#L1142 assume !(1 == ~M_E~0); 3201970#L1142-2 assume !(1 == ~T1_E~0); 3201971#L1147-1 assume !(1 == ~T2_E~0); 3202872#L1152-1 assume !(1 == ~T3_E~0); 3202380#L1157-1 assume !(1 == ~T4_E~0); 3202381#L1162-1 assume !(1 == ~T5_E~0); 3202541#L1167-1 assume !(1 == ~T6_E~0); 3202542#L1172-1 assume !(1 == ~T7_E~0); 3203027#L1177-1 assume !(1 == ~T8_E~0); 3202694#L1182-1 assume !(1 == ~T9_E~0); 3202695#L1187-1 assume !(1 == ~T10_E~0); 3202812#L1192-1 assume !(1 == ~E_M~0); 3202231#L1197-1 assume !(1 == ~E_1~0); 3202232#L1202-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3202633#L1207-1 assume !(1 == ~E_3~0); 3202606#L1212-1 assume !(1 == ~E_4~0); 3201818#L1217-1 assume !(1 == ~E_5~0); 3201819#L1222-1 assume !(1 == ~E_6~0); 3202603#L1227-1 assume !(1 == ~E_7~0); 3202604#L1232-1 assume !(1 == ~E_8~0); 3201694#L1237-1 assume !(1 == ~E_9~0); 3201695#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3202674#L1247-1 assume { :end_inline_reset_delta_events } true; 3202675#L1553-2 [2023-11-29 06:00:13,664 INFO L750 eck$LassoCheckResult]: Loop: 3202675#L1553-2 assume !false; 3274474#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3274469#L999-1 assume !false; 3274468#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3274464#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3274452#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3274450#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3274448#L854 assume !(0 != eval_~tmp~0#1); 3274449#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3323235#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3323234#L1024-3 assume !(0 == ~M_E~0); 3323232#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3323230#L1029-3 assume !(0 == ~T2_E~0); 3323228#L1034-3 assume !(0 == ~T3_E~0); 3323226#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3323224#L1044-3 assume !(0 == ~T5_E~0); 3323222#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3323220#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3323217#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3323213#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3323209#L1069-3 assume !(0 == ~T10_E~0); 3323205#L1074-3 assume !(0 == ~E_M~0); 3323201#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3323197#L1084-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3323193#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3323189#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3323185#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3323181#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3323177#L1109-3 assume !(0 == ~E_7~0); 3323173#L1114-3 assume !(0 == ~E_8~0); 3323169#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3323165#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3323161#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3323157#L502-36 assume !(1 == ~m_pc~0); 3323153#L502-38 is_master_triggered_~__retres1~0#1 := 0; 3323149#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3323145#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3323141#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3323137#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3323133#L521-36 assume 1 == ~t1_pc~0; 3323128#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3323124#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3323119#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3323115#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3323110#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3323106#L540-36 assume !(1 == ~t2_pc~0); 3323102#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3323098#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3202918#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3202919#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3202536#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3201692#L559-36 assume !(1 == ~t3_pc~0); 3201693#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3323356#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3323354#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3323352#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 3202982#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3202983#L578-36 assume !(1 == ~t4_pc~0); 3202616#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3202617#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3202550#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3202551#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 3202437#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3202438#L597-36 assume !(1 == ~t5_pc~0); 3202683#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3203104#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3203033#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3202632#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3202229#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3202230#L616-36 assume 1 == ~t6_pc~0; 3203124#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3201758#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3201759#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3202309#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3202493#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3202860#L635-36 assume !(1 == ~t7_pc~0); 3296311#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3296309#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3296307#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3296306#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3296304#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3296302#L654-36 assume 1 == ~t8_pc~0; 3296299#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3296297#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3296295#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3296293#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3296291#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3296289#L673-36 assume !(1 == ~t9_pc~0); 3296287#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3296285#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3296283#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3296281#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3296279#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3296277#L692-36 assume !(1 == ~t10_pc~0); 3296274#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3295700#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3277410#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3276972#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 3276969#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3276964#L1142-3 assume !(1 == ~M_E~0); 3219434#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3276920#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3276917#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3276915#L1157-3 assume !(1 == ~T4_E~0); 3276913#L1162-3 assume !(1 == ~T5_E~0); 3276911#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3276909#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3276907#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3276883#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3276877#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3276871#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3276865#L1197-3 assume !(1 == ~E_1~0); 3276860#L1202-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3276855#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3276850#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3276845#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3276841#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3276838#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3276834#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3276829#L1237-3 assume !(1 == ~E_9~0); 3276825#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3276821#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3276802#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3276787#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3276783#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3219423#L1572 assume !(0 == start_simulation_~tmp~3#1); 3219424#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3274496#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3274488#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3274486#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 3274484#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3274482#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3274479#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3274477#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 3202675#L1553-2 [2023-11-29 06:00:13,664 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:13,664 INFO L85 PathProgramCache]: Analyzing trace with hash -1017701811, now seen corresponding path program 1 times [2023-11-29 06:00:13,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:13,665 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863709252] [2023-11-29 06:00:13,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:13,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:13,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:13,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:13,727 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:13,727 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1863709252] [2023-11-29 06:00:13,727 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1863709252] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:13,727 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:13,727 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 06:00:13,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1034850025] [2023-11-29 06:00:13,728 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:13,728 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 06:00:13,728 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:13,728 INFO L85 PathProgramCache]: Analyzing trace with hash 610215589, now seen corresponding path program 1 times [2023-11-29 06:00:13,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:13,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276454454] [2023-11-29 06:00:13,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:13,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:13,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:13,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:13,771 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:13,771 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276454454] [2023-11-29 06:00:13,771 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1276454454] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:13,771 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:13,771 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:13,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [610961164] [2023-11-29 06:00:13,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:13,772 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 06:00:13,772 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 06:00:13,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 06:00:13,772 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 06:00:13,772 INFO L87 Difference]: Start difference. First operand 121736 states and 172292 transitions. cyclomatic complexity: 50588 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:14,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 06:00:14,108 INFO L93 Difference]: Finished difference Result 121736 states and 171330 transitions. [2023-11-29 06:00:14,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121736 states and 171330 transitions. [2023-11-29 06:00:14,955 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 121024 [2023-11-29 06:00:15,200 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121736 states to 121736 states and 171330 transitions. [2023-11-29 06:00:15,200 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 121736 [2023-11-29 06:00:15,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 121736 [2023-11-29 06:00:15,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 121736 states and 171330 transitions. [2023-11-29 06:00:15,312 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 06:00:15,312 INFO L218 hiAutomatonCegarLoop]: Abstraction has 121736 states and 171330 transitions. [2023-11-29 06:00:15,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121736 states and 171330 transitions. [2023-11-29 06:00:16,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121736 to 121736. [2023-11-29 06:00:16,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121736 states, 121736 states have (on average 1.4073897614510087) internal successors, (171330), 121735 states have internal predecessors, (171330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:16,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121736 states to 121736 states and 171330 transitions. [2023-11-29 06:00:16,693 INFO L240 hiAutomatonCegarLoop]: Abstraction has 121736 states and 171330 transitions. [2023-11-29 06:00:16,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 06:00:16,694 INFO L428 stractBuchiCegarLoop]: Abstraction has 121736 states and 171330 transitions. [2023-11-29 06:00:16,694 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-29 06:00:16,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121736 states and 171330 transitions. [2023-11-29 06:00:16,971 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 121024 [2023-11-29 06:00:16,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 06:00:16,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 06:00:16,972 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:16,972 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:16,973 INFO L748 eck$LassoCheckResult]: Stem: 3445547#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3445548#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3446522#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3446523#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3446151#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3445823#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3445824#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3446117#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3446307#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3445998#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3445999#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3445881#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3445882#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3446258#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3446209#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3446124#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3446125#L1024 assume !(0 == ~M_E~0); 3446419#L1024-2 assume !(0 == ~T1_E~0); 3445542#L1029-1 assume !(0 == ~T2_E~0); 3445543#L1034-1 assume !(0 == ~T3_E~0); 3445643#L1039-1 assume !(0 == ~T4_E~0); 3446552#L1044-1 assume !(0 == ~T5_E~0); 3445898#L1049-1 assume !(0 == ~T6_E~0); 3445899#L1054-1 assume !(0 == ~T7_E~0); 3446149#L1059-1 assume !(0 == ~T8_E~0); 3445592#L1064-1 assume !(0 == ~T9_E~0); 3445593#L1069-1 assume !(0 == ~T10_E~0); 3446381#L1074-1 assume !(0 == ~E_M~0); 3446454#L1079-1 assume !(0 == ~E_1~0); 3446423#L1084-1 assume !(0 == ~E_2~0); 3446424#L1089-1 assume !(0 == ~E_3~0); 3446475#L1094-1 assume !(0 == ~E_4~0); 3445988#L1099-1 assume !(0 == ~E_5~0); 3445989#L1104-1 assume !(0 == ~E_6~0); 3446277#L1109-1 assume !(0 == ~E_7~0); 3445761#L1114-1 assume !(0 == ~E_8~0); 3445762#L1119-1 assume !(0 == ~E_9~0); 3445837#L1124-1 assume !(0 == ~E_10~0); 3445244#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3445245#L502 assume !(1 == ~m_pc~0); 3445439#L502-2 is_master_triggered_~__retres1~0#1 := 0; 3445370#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3445371#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3446205#L1273 assume !(0 != activate_threads_~tmp~1#1); 3446206#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3446602#L521 assume !(1 == ~t1_pc~0); 3446508#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3445295#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3445259#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3445260#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 3445279#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3445280#L540 assume !(1 == ~t2_pc~0); 3446102#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3446103#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3445759#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3445760#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 3446501#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3445571#L559 assume !(1 == ~t3_pc~0); 3445572#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3445854#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3445197#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3445198#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 3445386#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3445387#L578 assume !(1 == ~t4_pc~0); 3445512#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3446387#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3446416#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3446589#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 3446187#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3446188#L597 assume !(1 == ~t5_pc~0); 3446135#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3445314#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3445315#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3446417#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3446126#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3446127#L616 assume !(1 == ~t6_pc~0); 3446146#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3446145#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3445735#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3445736#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3445978#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3445979#L635 assume !(1 == ~t7_pc~0); 3445281#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3445282#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3445661#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3446471#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3446119#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3446120#L654 assume !(1 == ~t8_pc~0); 3445925#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3445926#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3446339#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3446340#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3446379#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3445541#L673 assume !(1 == ~t9_pc~0); 3445236#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3445237#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3445815#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3445816#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3446290#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3446291#L692 assume !(1 == ~t10_pc~0); 3446228#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3446227#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3445980#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3445981#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3445992#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3446356#L1142 assume !(1 == ~M_E~0); 3445447#L1142-2 assume !(1 == ~T1_E~0); 3445448#L1147-1 assume !(1 == ~T2_E~0); 3446344#L1152-1 assume !(1 == ~T3_E~0); 3445860#L1157-1 assume !(1 == ~T4_E~0); 3445861#L1162-1 assume !(1 == ~T5_E~0); 3446016#L1167-1 assume !(1 == ~T6_E~0); 3446017#L1172-1 assume !(1 == ~T7_E~0); 3446493#L1177-1 assume !(1 == ~T8_E~0); 3446168#L1182-1 assume !(1 == ~T9_E~0); 3446169#L1187-1 assume !(1 == ~T10_E~0); 3446283#L1192-1 assume !(1 == ~E_M~0); 3445712#L1197-1 assume !(1 == ~E_1~0); 3445713#L1202-1 assume !(1 == ~E_2~0); 3446106#L1207-1 assume !(1 == ~E_3~0); 3446080#L1212-1 assume !(1 == ~E_4~0); 3445298#L1217-1 assume !(1 == ~E_5~0); 3445299#L1222-1 assume !(1 == ~E_6~0); 3446077#L1227-1 assume !(1 == ~E_7~0); 3446078#L1232-1 assume !(1 == ~E_8~0); 3445174#L1237-1 assume !(1 == ~E_9~0); 3445175#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3446147#L1247-1 assume { :end_inline_reset_delta_events } true; 3446148#L1553-2 [2023-11-29 06:00:16,973 INFO L750 eck$LassoCheckResult]: Loop: 3446148#L1553-2 assume !false; 3460830#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3460825#L999-1 assume !false; 3460823#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3460821#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3460809#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3460807#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3460804#L854 assume !(0 != eval_~tmp~0#1); 3460805#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3461957#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3461955#L1024-3 assume !(0 == ~M_E~0); 3461953#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3461951#L1029-3 assume !(0 == ~T2_E~0); 3461949#L1034-3 assume !(0 == ~T3_E~0); 3461947#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3461945#L1044-3 assume !(0 == ~T5_E~0); 3461943#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3461941#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3461939#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3461937#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3461935#L1069-3 assume !(0 == ~T10_E~0); 3461933#L1074-3 assume !(0 == ~E_M~0); 3461931#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3461929#L1084-3 assume !(0 == ~E_2~0); 3461927#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3461925#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3461923#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3461921#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3461909#L1109-3 assume !(0 == ~E_7~0); 3461907#L1114-3 assume !(0 == ~E_8~0); 3461905#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3461902#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3461901#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3461899#L502-36 assume !(1 == ~m_pc~0); 3461897#L502-38 is_master_triggered_~__retres1~0#1 := 0; 3461895#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3461893#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3461891#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3461889#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3461887#L521-36 assume !(1 == ~t1_pc~0); 3461884#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 3461881#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3461879#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3461877#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3461875#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3461873#L540-36 assume !(1 == ~t2_pc~0); 3461871#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3461869#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3461867#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3461865#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3461863#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3461861#L559-36 assume !(1 == ~t3_pc~0); 3461859#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3461857#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3461855#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3461853#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 3461851#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3461850#L578-36 assume !(1 == ~t4_pc~0); 3461848#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3461846#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3461844#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3461843#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 3461838#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3461836#L597-36 assume !(1 == ~t5_pc~0); 3461834#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3461832#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3461829#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3461827#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3461825#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3461823#L616-36 assume 1 == ~t6_pc~0; 3461820#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3461818#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3461816#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3461814#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3461812#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3461809#L635-36 assume !(1 == ~t7_pc~0); 3454135#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3461806#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3461804#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3461802#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3461800#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3461799#L654-36 assume 1 == ~t8_pc~0; 3461796#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3461794#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3461792#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3461790#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3461788#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3461785#L673-36 assume !(1 == ~t9_pc~0); 3461783#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3461781#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3461779#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3461777#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3461775#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3461773#L692-36 assume 1 == ~t10_pc~0; 3461770#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3461768#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3461766#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3461764#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 3461762#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3461759#L1142-3 assume !(1 == ~M_E~0); 3461755#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3461753#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3461751#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3461749#L1157-3 assume !(1 == ~T4_E~0); 3461746#L1162-3 assume !(1 == ~T5_E~0); 3461744#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3461742#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3461740#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3461738#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3461736#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3461734#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3461732#L1197-3 assume !(1 == ~E_1~0); 3461730#L1202-3 assume !(1 == ~E_2~0); 3461728#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3461726#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3461724#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3461722#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3461720#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3461718#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3461716#L1237-3 assume !(1 == ~E_9~0); 3461714#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3461712#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3461710#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3461698#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3461696#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3461692#L1572 assume !(0 == start_simulation_~tmp~3#1); 3461691#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3460852#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3460844#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3460842#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 3460839#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3460837#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3460835#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3460833#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 3446148#L1553-2 [2023-11-29 06:00:16,974 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:16,974 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728821, now seen corresponding path program 1 times [2023-11-29 06:00:16,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:16,974 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1075772043] [2023-11-29 06:00:16,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:16,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:16,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:17,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:17,034 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:17,034 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1075772043] [2023-11-29 06:00:17,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1075772043] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:17,034 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:17,035 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:17,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1611654223] [2023-11-29 06:00:17,035 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:17,035 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 06:00:17,035 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:17,035 INFO L85 PathProgramCache]: Analyzing trace with hash -460194395, now seen corresponding path program 1 times [2023-11-29 06:00:17,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:17,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665941123] [2023-11-29 06:00:17,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:17,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:17,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:17,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:17,069 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:17,069 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [665941123] [2023-11-29 06:00:17,069 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [665941123] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:17,069 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:17,069 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:17,069 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1774786934] [2023-11-29 06:00:17,070 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:17,070 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 06:00:17,070 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 06:00:17,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 06:00:17,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 06:00:17,071 INFO L87 Difference]: Start difference. First operand 121736 states and 171330 transitions. cyclomatic complexity: 49626 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:17,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 06:00:17,631 INFO L93 Difference]: Finished difference Result 189397 states and 264712 transitions. [2023-11-29 06:00:17,631 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 189397 states and 264712 transitions. [2023-11-29 06:00:18,611 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 188240 [2023-11-29 06:00:18,905 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 189397 states to 189397 states and 264712 transitions. [2023-11-29 06:00:18,905 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 189397 [2023-11-29 06:00:18,964 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 189397 [2023-11-29 06:00:18,964 INFO L73 IsDeterministic]: Start isDeterministic. Operand 189397 states and 264712 transitions. [2023-11-29 06:00:19,024 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 06:00:19,024 INFO L218 hiAutomatonCegarLoop]: Abstraction has 189397 states and 264712 transitions. [2023-11-29 06:00:19,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189397 states and 264712 transitions. [2023-11-29 06:00:20,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189397 to 134633. [2023-11-29 06:00:20,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134633 states, 134633 states have (on average 1.4019222627439039) internal successors, (188745), 134632 states have internal predecessors, (188745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:20,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134633 states to 134633 states and 188745 transitions. [2023-11-29 06:00:20,689 INFO L240 hiAutomatonCegarLoop]: Abstraction has 134633 states and 188745 transitions. [2023-11-29 06:00:20,690 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 06:00:20,690 INFO L428 stractBuchiCegarLoop]: Abstraction has 134633 states and 188745 transitions. [2023-11-29 06:00:20,690 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-29 06:00:20,690 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134633 states and 188745 transitions. [2023-11-29 06:00:21,028 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 133824 [2023-11-29 06:00:21,028 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 06:00:21,028 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 06:00:21,030 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:21,030 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:21,031 INFO L748 eck$LassoCheckResult]: Stem: 3756686#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3756687#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3757697#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3757698#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3757311#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 3756967#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3756968#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3757279#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3757474#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3757150#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3757151#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3757028#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3757029#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3757419#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3757368#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3757286#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3757287#L1024 assume !(0 == ~M_E~0); 3757590#L1024-2 assume !(0 == ~T1_E~0); 3756681#L1029-1 assume !(0 == ~T2_E~0); 3756682#L1034-1 assume !(0 == ~T3_E~0); 3756784#L1039-1 assume !(0 == ~T4_E~0); 3757729#L1044-1 assume !(0 == ~T5_E~0); 3757044#L1049-1 assume !(0 == ~T6_E~0); 3757045#L1054-1 assume !(0 == ~T7_E~0); 3757310#L1059-1 assume !(0 == ~T8_E~0); 3756733#L1064-1 assume !(0 == ~T9_E~0); 3756734#L1069-1 assume !(0 == ~T10_E~0); 3757550#L1074-1 assume !(0 == ~E_M~0); 3757626#L1079-1 assume !(0 == ~E_1~0); 3757592#L1084-1 assume !(0 == ~E_2~0); 3757593#L1089-1 assume !(0 == ~E_3~0); 3757650#L1094-1 assume !(0 == ~E_4~0); 3757138#L1099-1 assume !(0 == ~E_5~0); 3757139#L1104-1 assume !(0 == ~E_6~0); 3757441#L1109-1 assume !(0 == ~E_7~0); 3756903#L1114-1 assume !(0 == ~E_8~0); 3756904#L1119-1 assume !(0 == ~E_9~0); 3756981#L1124-1 assume 0 == ~E_10~0;~E_10~0 := 1; 3756385#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3756386#L502 assume !(1 == ~m_pc~0); 3756579#L502-2 is_master_triggered_~__retres1~0#1 := 0; 3756511#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3756512#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3757586#L1273 assume !(0 != activate_threads_~tmp~1#1); 3757893#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3757894#L521 assume !(1 == ~t1_pc~0); 3757685#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3756436#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3756400#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3756401#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 3757957#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3757956#L540 assume !(1 == ~t2_pc~0); 3757263#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3757264#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3757609#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3757848#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 3757677#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3756710#L559 assume !(1 == ~t3_pc~0); 3756711#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3757000#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3756338#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3756339#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 3757949#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3757864#L578 assume !(1 == ~t4_pc~0); 3757556#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3757557#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3757587#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3757774#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 3757775#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3757813#L597 assume !(1 == ~t5_pc~0); 3757814#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3756455#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3756456#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3757588#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 3757288#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3757289#L616 assume !(1 == ~t6_pc~0); 3757307#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3757306#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3756875#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3756876#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 3757128#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3757129#L635 assume !(1 == ~t7_pc~0); 3756422#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3756423#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3756803#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3757941#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 3757281#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3757282#L654 assume !(1 == ~t8_pc~0); 3757071#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3757072#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3757507#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3757508#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 3757548#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3756680#L673 assume !(1 == ~t9_pc~0); 3756377#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3756378#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3757926#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3757925#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 3757924#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3757923#L692 assume !(1 == ~t10_pc~0); 3757921#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3757920#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3757919#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3757918#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 3757917#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3757916#L1142 assume !(1 == ~M_E~0); 3757915#L1142-2 assume !(1 == ~T1_E~0); 3757914#L1147-1 assume !(1 == ~T2_E~0); 3757913#L1152-1 assume !(1 == ~T3_E~0); 3757912#L1157-1 assume !(1 == ~T4_E~0); 3757911#L1162-1 assume !(1 == ~T5_E~0); 3757910#L1167-1 assume !(1 == ~T6_E~0); 3757909#L1172-1 assume !(1 == ~T7_E~0); 3757908#L1177-1 assume !(1 == ~T8_E~0); 3757907#L1182-1 assume !(1 == ~T9_E~0); 3757906#L1187-1 assume !(1 == ~T10_E~0); 3757905#L1192-1 assume !(1 == ~E_M~0); 3757904#L1197-1 assume !(1 == ~E_1~0); 3757903#L1202-1 assume !(1 == ~E_2~0); 3757902#L1207-1 assume !(1 == ~E_3~0); 3757901#L1212-1 assume !(1 == ~E_4~0); 3757900#L1217-1 assume !(1 == ~E_5~0); 3757899#L1222-1 assume !(1 == ~E_6~0); 3757898#L1227-1 assume !(1 == ~E_7~0); 3757897#L1232-1 assume !(1 == ~E_8~0); 3757896#L1237-1 assume !(1 == ~E_9~0); 3757895#L1242-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3757308#L1247-1 assume { :end_inline_reset_delta_events } true; 3757309#L1553-2 [2023-11-29 06:00:21,031 INFO L750 eck$LassoCheckResult]: Loop: 3757309#L1553-2 assume !false; 3784488#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3784365#L999-1 assume !false; 3784362#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3784360#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3784343#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3784333#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3784324#L854 assume !(0 != eval_~tmp~0#1); 3784325#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3789102#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3789096#L1024-3 assume !(0 == ~M_E~0); 3789089#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3789084#L1029-3 assume !(0 == ~T2_E~0); 3789077#L1034-3 assume !(0 == ~T3_E~0); 3789071#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3789064#L1044-3 assume !(0 == ~T5_E~0); 3789057#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3789051#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3789045#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3789039#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3789033#L1069-3 assume !(0 == ~T10_E~0); 3789026#L1074-3 assume !(0 == ~E_M~0); 3789020#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3789014#L1084-3 assume !(0 == ~E_2~0); 3789007#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3789002#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3788996#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3788990#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3788984#L1109-3 assume !(0 == ~E_7~0); 3788977#L1114-3 assume !(0 == ~E_8~0); 3788970#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3788963#L1124-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3788962#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3788961#L502-36 assume !(1 == ~m_pc~0); 3788960#L502-38 is_master_triggered_~__retres1~0#1 := 0; 3788959#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3788958#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3788957#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3788956#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3788955#L521-36 assume 1 == ~t1_pc~0; 3788953#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3788952#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3788951#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3788950#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3788949#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3788948#L540-36 assume !(1 == ~t2_pc~0); 3788947#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 3788946#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3788945#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3788944#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3788943#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3788942#L559-36 assume !(1 == ~t3_pc~0); 3788941#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3788940#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3788939#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3788938#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 3788937#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3788936#L578-36 assume !(1 == ~t4_pc~0); 3788935#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3788933#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3788931#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3788929#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 3788927#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3788926#L597-36 assume !(1 == ~t5_pc~0); 3788925#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 3788924#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3788923#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3788922#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3788921#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3788920#L616-36 assume !(1 == ~t6_pc~0); 3788919#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 3788917#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3788916#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3788915#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3788914#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3788913#L635-36 assume !(1 == ~t7_pc~0); 3778189#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 3788912#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3788911#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3788910#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3788909#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3788908#L654-36 assume !(1 == ~t8_pc~0); 3788907#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 3788905#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3788904#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3788903#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3788902#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3788901#L673-36 assume !(1 == ~t9_pc~0); 3788900#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 3788899#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3788898#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3788897#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3788896#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3788895#L692-36 assume 1 == ~t10_pc~0; 3788892#L693-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3788891#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3788890#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3788889#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 3788888#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3788887#L1142-3 assume !(1 == ~M_E~0); 3775288#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3788886#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3788885#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3788884#L1157-3 assume !(1 == ~T4_E~0); 3788883#L1162-3 assume !(1 == ~T5_E~0); 3788882#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3788881#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3788880#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3788879#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3788878#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3788877#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3788876#L1197-3 assume !(1 == ~E_1~0); 3788875#L1202-3 assume !(1 == ~E_2~0); 3788874#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3788873#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3788872#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3788871#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3788870#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3788869#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3788868#L1237-3 assume !(1 == ~E_9~0); 3788866#L1242-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3788858#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3788795#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3788639#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3788633#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3775241#L1572 assume !(0 == start_simulation_~tmp~3#1); 3775242#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3784569#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3784554#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3784547#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 3784537#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3784529#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3784518#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3784508#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 3757309#L1553-2 [2023-11-29 06:00:21,031 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:21,032 INFO L85 PathProgramCache]: Analyzing trace with hash 529853193, now seen corresponding path program 1 times [2023-11-29 06:00:21,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:21,032 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649723215] [2023-11-29 06:00:21,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:21,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:21,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:21,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:21,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:21,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1649723215] [2023-11-29 06:00:21,091 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1649723215] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:21,091 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:21,091 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:21,091 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [497216102] [2023-11-29 06:00:21,091 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:21,091 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 06:00:21,092 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:21,092 INFO L85 PathProgramCache]: Analyzing trace with hash -229253594, now seen corresponding path program 1 times [2023-11-29 06:00:21,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:21,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1226260184] [2023-11-29 06:00:21,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:21,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:21,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:21,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:21,131 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:21,131 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1226260184] [2023-11-29 06:00:21,131 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1226260184] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:21,131 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:21,131 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:21,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [881450162] [2023-11-29 06:00:21,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:21,132 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 06:00:21,132 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 06:00:21,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 06:00:21,132 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 06:00:21,133 INFO L87 Difference]: Start difference. First operand 134633 states and 188745 transitions. cyclomatic complexity: 54144 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:22,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 06:00:22,050 INFO L93 Difference]: Finished difference Result 176088 states and 245199 transitions. [2023-11-29 06:00:22,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176088 states and 245199 transitions. [2023-11-29 06:00:22,641 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 175056 [2023-11-29 06:00:22,988 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176088 states to 176088 states and 245199 transitions. [2023-11-29 06:00:22,989 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176088 [2023-11-29 06:00:23,074 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176088 [2023-11-29 06:00:23,074 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176088 states and 245199 transitions. [2023-11-29 06:00:23,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 06:00:23,543 INFO L218 hiAutomatonCegarLoop]: Abstraction has 176088 states and 245199 transitions. [2023-11-29 06:00:23,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176088 states and 245199 transitions. [2023-11-29 06:00:24,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176088 to 121736. [2023-11-29 06:00:24,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121736 states, 121736 states have (on average 1.3947476506538738) internal successors, (169791), 121735 states have internal predecessors, (169791), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:24,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121736 states to 121736 states and 169791 transitions. [2023-11-29 06:00:24,711 INFO L240 hiAutomatonCegarLoop]: Abstraction has 121736 states and 169791 transitions. [2023-11-29 06:00:24,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 06:00:24,712 INFO L428 stractBuchiCegarLoop]: Abstraction has 121736 states and 169791 transitions. [2023-11-29 06:00:24,712 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-29 06:00:24,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121736 states and 169791 transitions. [2023-11-29 06:00:25,331 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 121024 [2023-11-29 06:00:25,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 06:00:25,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 06:00:25,332 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:25,332 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:25,333 INFO L748 eck$LassoCheckResult]: Stem: 4067418#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 4067419#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4068436#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4068437#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4068044#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 4067704#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4067705#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4068008#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4068207#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4067884#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4067885#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4067762#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4067763#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4068151#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4068106#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4068016#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4068017#L1024 assume !(0 == ~M_E~0); 4068331#L1024-2 assume !(0 == ~T1_E~0); 4067413#L1029-1 assume !(0 == ~T2_E~0); 4067414#L1034-1 assume !(0 == ~T3_E~0); 4067519#L1039-1 assume !(0 == ~T4_E~0); 4068468#L1044-1 assume !(0 == ~T5_E~0); 4067778#L1049-1 assume !(0 == ~T6_E~0); 4067779#L1054-1 assume !(0 == ~T7_E~0); 4068043#L1059-1 assume !(0 == ~T8_E~0); 4067466#L1064-1 assume !(0 == ~T9_E~0); 4067467#L1069-1 assume !(0 == ~T10_E~0); 4068296#L1074-1 assume !(0 == ~E_M~0); 4068368#L1079-1 assume !(0 == ~E_1~0); 4068334#L1084-1 assume !(0 == ~E_2~0); 4068335#L1089-1 assume !(0 == ~E_3~0); 4068394#L1094-1 assume !(0 == ~E_4~0); 4067874#L1099-1 assume !(0 == ~E_5~0); 4067875#L1104-1 assume !(0 == ~E_6~0); 4068176#L1109-1 assume !(0 == ~E_7~0); 4067637#L1114-1 assume !(0 == ~E_8~0); 4067638#L1119-1 assume !(0 == ~E_9~0); 4067718#L1124-1 assume !(0 == ~E_10~0); 4067116#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4067117#L502 assume !(1 == ~m_pc~0); 4067311#L502-2 is_master_triggered_~__retres1~0#1 := 0; 4067243#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4067244#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4068102#L1273 assume !(0 != activate_threads_~tmp~1#1); 4068103#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4068535#L521 assume !(1 == ~t1_pc~0); 4068425#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4067167#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4067131#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4067132#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 4067151#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4067152#L540 assume !(1 == ~t2_pc~0); 4067991#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4067992#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4067635#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4067636#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 4068419#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4067444#L559 assume !(1 == ~t3_pc~0); 4067445#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4067734#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4067069#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4067070#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 4067260#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4067261#L578 assume !(1 == ~t4_pc~0); 4067385#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4068301#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4068328#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4068521#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 4068083#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4068084#L597 assume !(1 == ~t5_pc~0); 4068028#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4067186#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4067187#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4068329#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 4068018#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4068019#L616 assume !(1 == ~t6_pc~0); 4068040#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4068039#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4067610#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4067611#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 4067864#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4067865#L635 assume !(1 == ~t7_pc~0); 4067153#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4067154#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4067539#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4068389#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 4068010#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4068011#L654 assume !(1 == ~t8_pc~0); 4067805#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4067806#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4068246#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4068247#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 4068294#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4067412#L673 assume !(1 == ~t9_pc~0); 4067108#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4067109#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4067698#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4067699#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 4068189#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4068190#L692 assume !(1 == ~t10_pc~0); 4068125#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4068175#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4067866#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4067867#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 4067878#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4068266#L1142 assume !(1 == ~M_E~0); 4067319#L1142-2 assume !(1 == ~T1_E~0); 4067320#L1147-1 assume !(1 == ~T2_E~0); 4068249#L1152-1 assume !(1 == ~T3_E~0); 4067740#L1157-1 assume !(1 == ~T4_E~0); 4067741#L1162-1 assume !(1 == ~T5_E~0); 4067901#L1167-1 assume !(1 == ~T6_E~0); 4067902#L1172-1 assume !(1 == ~T7_E~0); 4068412#L1177-1 assume !(1 == ~T8_E~0); 4068064#L1182-1 assume !(1 == ~T9_E~0); 4068065#L1187-1 assume !(1 == ~T10_E~0); 4068182#L1192-1 assume !(1 == ~E_M~0); 4067588#L1197-1 assume !(1 == ~E_1~0); 4067589#L1202-1 assume !(1 == ~E_2~0); 4067996#L1207-1 assume !(1 == ~E_3~0); 4067968#L1212-1 assume !(1 == ~E_4~0); 4067170#L1217-1 assume !(1 == ~E_5~0); 4067171#L1222-1 assume !(1 == ~E_6~0); 4067965#L1227-1 assume !(1 == ~E_7~0); 4067966#L1232-1 assume !(1 == ~E_8~0); 4067047#L1237-1 assume !(1 == ~E_9~0); 4067048#L1242-1 assume !(1 == ~E_10~0); 4068041#L1247-1 assume { :end_inline_reset_delta_events } true; 4068042#L1553-2 [2023-11-29 06:00:25,333 INFO L750 eck$LassoCheckResult]: Loop: 4068042#L1553-2 assume !false; 4138542#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4138537#L999-1 assume !false; 4138536#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4138532#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4138520#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4138518#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4138516#L854 assume !(0 != eval_~tmp~0#1); 4138517#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4188331#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4188330#L1024-3 assume !(0 == ~M_E~0); 4188329#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4188328#L1029-3 assume !(0 == ~T2_E~0); 4188327#L1034-3 assume !(0 == ~T3_E~0); 4188326#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4188325#L1044-3 assume !(0 == ~T5_E~0); 4188324#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4188323#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4187852#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4187848#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4187846#L1069-3 assume !(0 == ~T10_E~0); 4187844#L1074-3 assume !(0 == ~E_M~0); 4187842#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4187839#L1084-3 assume !(0 == ~E_2~0); 4187837#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4187835#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4187833#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4187831#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4187829#L1109-3 assume !(0 == ~E_7~0); 4187255#L1114-3 assume !(0 == ~E_8~0); 4186844#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4185613#L1124-3 assume !(0 == ~E_10~0); 4184510#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4183814#L502-36 assume !(1 == ~m_pc~0); 4183811#L502-38 is_master_triggered_~__retres1~0#1 := 0; 4183809#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4183807#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4183805#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4183803#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4183801#L521-36 assume !(1 == ~t1_pc~0); 4183798#L521-38 is_transmit1_triggered_~__retres1~1#1 := 0; 4183795#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4183793#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4183791#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4183789#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4183786#L540-36 assume !(1 == ~t2_pc~0); 4183784#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 4183782#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4183780#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4183778#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4183776#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4183774#L559-36 assume !(1 == ~t3_pc~0); 4183773#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 4183771#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4183769#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4183767#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 4183765#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4183763#L578-36 assume !(1 == ~t4_pc~0); 4183759#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 4183757#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4183755#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4183753#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 4183750#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4183748#L597-36 assume !(1 == ~t5_pc~0); 4183746#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4183744#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4183742#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4183740#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4183738#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4183736#L616-36 assume !(1 == ~t6_pc~0); 4183734#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 4183731#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4183729#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4183727#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4183715#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4138715#L635-36 assume !(1 == ~t7_pc~0); 4138714#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 4138713#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4138712#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4138711#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4138710#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4138709#L654-36 assume !(1 == ~t8_pc~0); 4138708#L654-38 is_transmit8_triggered_~__retres1~8#1 := 0; 4138706#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4138704#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4138703#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4138702#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4138701#L673-36 assume !(1 == ~t9_pc~0); 4138700#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 4138699#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4138697#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4138695#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4138693#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4138691#L692-36 assume !(1 == ~t10_pc~0); 4138688#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 4138686#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4138684#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4138681#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 4138679#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4138677#L1142-3 assume !(1 == ~M_E~0); 4079827#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4138674#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4138672#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4138670#L1157-3 assume !(1 == ~T4_E~0); 4138668#L1162-3 assume !(1 == ~T5_E~0); 4138666#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4138664#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4138662#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4138660#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4138658#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4138656#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4138654#L1197-3 assume !(1 == ~E_1~0); 4138652#L1202-3 assume !(1 == ~E_2~0); 4138650#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4138646#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4138644#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4138642#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4138640#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4138637#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4138635#L1237-3 assume !(1 == ~E_9~0); 4138633#L1242-3 assume !(1 == ~E_10~0); 4138631#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4138629#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4138617#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4138615#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 4138580#L1572 assume !(0 == start_simulation_~tmp~3#1); 4138578#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4138564#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4138556#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4138554#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 4138552#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4138549#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4138547#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4138545#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 4068042#L1553-2 [2023-11-29 06:00:25,334 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:25,334 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 1 times [2023-11-29 06:00:25,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:25,334 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1279793249] [2023-11-29 06:00:25,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:25,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:25,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 06:00:25,348 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 06:00:25,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 06:00:25,437 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 06:00:25,437 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:25,437 INFO L85 PathProgramCache]: Analyzing trace with hash 408951208, now seen corresponding path program 1 times [2023-11-29 06:00:25,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:25,438 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006518571] [2023-11-29 06:00:25,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:25,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:25,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:25,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:25,477 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:25,477 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2006518571] [2023-11-29 06:00:25,478 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2006518571] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:25,478 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:25,478 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:25,478 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [343645587] [2023-11-29 06:00:25,478 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:25,478 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 06:00:25,478 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 06:00:25,479 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 06:00:25,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 06:00:25,479 INFO L87 Difference]: Start difference. First operand 121736 states and 169791 transitions. cyclomatic complexity: 48087 Second operand has 3 states, 3 states have (on average 44.666666666666664) internal successors, (134), 3 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:25,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 06:00:25,789 INFO L93 Difference]: Finished difference Result 134633 states and 187971 transitions. [2023-11-29 06:00:25,789 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 134633 states and 187971 transitions. [2023-11-29 06:00:26,248 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 133824 [2023-11-29 06:00:26,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 134633 states to 134633 states and 187971 transitions. [2023-11-29 06:00:26,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134633 [2023-11-29 06:00:26,570 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134633 [2023-11-29 06:00:26,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134633 states and 187971 transitions. [2023-11-29 06:00:27,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 06:00:27,036 INFO L218 hiAutomatonCegarLoop]: Abstraction has 134633 states and 187971 transitions. [2023-11-29 06:00:27,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134633 states and 187971 transitions. [2023-11-29 06:00:27,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134633 to 134633. [2023-11-29 06:00:27,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134633 states, 134633 states have (on average 1.3961733007509303) internal successors, (187971), 134632 states have internal predecessors, (187971), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:28,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134633 states to 134633 states and 187971 transitions. [2023-11-29 06:00:28,186 INFO L240 hiAutomatonCegarLoop]: Abstraction has 134633 states and 187971 transitions. [2023-11-29 06:00:28,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 06:00:28,186 INFO L428 stractBuchiCegarLoop]: Abstraction has 134633 states and 187971 transitions. [2023-11-29 06:00:28,186 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-29 06:00:28,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134633 states and 187971 transitions. [2023-11-29 06:00:28,875 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 133824 [2023-11-29 06:00:28,876 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 06:00:28,876 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 06:00:28,877 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:28,878 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:28,878 INFO L748 eck$LassoCheckResult]: Stem: 4323793#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 4323794#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4324841#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4324842#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4324419#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 4324071#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4324072#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4324384#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4324593#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4324254#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4324255#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4324133#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4324134#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4324539#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4324476#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4324391#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4324392#L1024 assume !(0 == ~M_E~0); 4324732#L1024-2 assume !(0 == ~T1_E~0); 4323788#L1029-1 assume !(0 == ~T2_E~0); 4323789#L1034-1 assume !(0 == ~T3_E~0); 4323890#L1039-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4325027#L1044-1 assume !(0 == ~T5_E~0); 4325105#L1049-1 assume !(0 == ~T6_E~0); 4325040#L1054-1 assume !(0 == ~T7_E~0); 4325041#L1059-1 assume !(0 == ~T8_E~0); 4325104#L1064-1 assume !(0 == ~T9_E~0); 4325103#L1069-1 assume !(0 == ~T10_E~0); 4324987#L1074-1 assume !(0 == ~E_M~0); 4324768#L1079-1 assume !(0 == ~E_1~0); 4324735#L1084-1 assume !(0 == ~E_2~0); 4324736#L1089-1 assume !(0 == ~E_3~0); 4325100#L1094-1 assume !(0 == ~E_4~0); 4325099#L1099-1 assume !(0 == ~E_5~0); 4324894#L1104-1 assume !(0 == ~E_6~0); 4324895#L1109-1 assume !(0 == ~E_7~0); 4324008#L1114-1 assume !(0 == ~E_8~0); 4324009#L1119-1 assume !(0 == ~E_9~0); 4324086#L1124-1 assume !(0 == ~E_10~0); 4324087#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4324582#L502 assume !(1 == ~m_pc~0); 4324583#L502-2 is_master_triggered_~__retres1~0#1 := 0; 4325098#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4325097#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4324472#L1273 assume !(0 != activate_threads_~tmp~1#1); 4324473#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4324931#L521 assume !(1 == ~t1_pc~0); 4324932#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4325096#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4323506#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4323507#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 4325095#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4325094#L540 assume !(1 == ~t2_pc~0); 4324368#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4324369#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4324754#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4324990#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 4324818#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4323816#L559 assume !(1 == ~t3_pc~0); 4323817#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4324104#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4323444#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4323445#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 4325087#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4325001#L578 assume !(1 == ~t4_pc~0); 4324694#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4324695#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4324729#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4324914#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 4324915#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4324959#L597 assume !(1 == ~t5_pc~0); 4324960#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4323563#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4323564#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4324730#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 4324393#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4324394#L616 assume !(1 == ~t6_pc~0); 4324415#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4324414#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4323981#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4323982#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 4324234#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4324235#L635 assume !(1 == ~t7_pc~0); 4325082#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4325081#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4325006#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4324783#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 4324784#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4325079#L654 assume !(1 == ~t8_pc~0); 4325077#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4325076#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4325075#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4325074#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 4325073#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4325072#L673 assume !(1 == ~t9_pc~0); 4323483#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4323484#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4325071#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4325070#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 4325069#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4325067#L692 assume !(1 == ~t10_pc~0); 4325066#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4325065#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4325064#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4325063#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 4325062#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4325022#L1142 assume !(1 == ~M_E~0); 4325023#L1142-2 assume !(1 == ~T1_E~0); 4325061#L1147-1 assume !(1 == ~T2_E~0); 4325021#L1152-1 assume !(1 == ~T3_E~0); 4324110#L1157-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4324111#L1162-1 assume !(1 == ~T5_E~0); 4324276#L1167-1 assume !(1 == ~T6_E~0); 4324277#L1172-1 assume !(1 == ~T7_E~0); 4324810#L1177-1 assume !(1 == ~T8_E~0); 4324436#L1182-1 assume !(1 == ~T9_E~0); 4324437#L1187-1 assume !(1 == ~T10_E~0); 4324564#L1192-1 assume !(1 == ~E_M~0); 4323959#L1197-1 assume !(1 == ~E_1~0); 4323960#L1202-1 assume !(1 == ~E_2~0); 4324373#L1207-1 assume !(1 == ~E_3~0); 4324347#L1212-1 assume !(1 == ~E_4~0); 4323547#L1217-1 assume !(1 == ~E_5~0); 4323548#L1222-1 assume !(1 == ~E_6~0); 4324341#L1227-1 assume !(1 == ~E_7~0); 4324342#L1232-1 assume !(1 == ~E_8~0); 4323422#L1237-1 assume !(1 == ~E_9~0); 4323423#L1242-1 assume !(1 == ~E_10~0); 4324416#L1247-1 assume { :end_inline_reset_delta_events } true; 4324417#L1553-2 [2023-11-29 06:00:28,878 INFO L750 eck$LassoCheckResult]: Loop: 4324417#L1553-2 assume !false; 4330860#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4330856#L999-1 assume !false; 4330855#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4330854#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4330843#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4330841#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4330839#L854 assume !(0 != eval_~tmp~0#1); 4330840#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4385619#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4385615#L1024-3 assume !(0 == ~M_E~0); 4382142#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4382141#L1029-3 assume !(0 == ~T2_E~0); 4382140#L1034-3 assume !(0 == ~T3_E~0); 4382012#L1039-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4382011#L1044-3 assume !(0 == ~T5_E~0); 4382009#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4382007#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4382006#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4382005#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4382003#L1069-3 assume !(0 == ~T10_E~0); 4382001#L1074-3 assume !(0 == ~E_M~0); 4382000#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4381841#L1084-3 assume !(0 == ~E_2~0); 4381838#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4381836#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4381834#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4381832#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4381830#L1109-3 assume !(0 == ~E_7~0); 4381828#L1114-3 assume !(0 == ~E_8~0); 4381826#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4381824#L1124-3 assume !(0 == ~E_10~0); 4381822#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4381819#L502-36 assume !(1 == ~m_pc~0); 4381817#L502-38 is_master_triggered_~__retres1~0#1 := 0; 4381815#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4381814#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4381803#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4381797#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4381790#L521-36 assume 1 == ~t1_pc~0; 4381783#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4381778#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4381772#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4381741#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4381734#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4381727#L540-36 assume !(1 == ~t2_pc~0); 4381721#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 4381715#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4381709#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4381702#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4381695#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4381688#L559-36 assume !(1 == ~t3_pc~0); 4381681#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 4381674#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4381664#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4381656#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 4381649#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4381642#L578-36 assume 1 == ~t4_pc~0; 4381634#L579-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4381625#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4381592#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4381582#L1305-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4381575#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4381568#L597-36 assume !(1 == ~t5_pc~0); 4381560#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4381554#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4381548#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4381540#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4381534#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4381530#L616-36 assume !(1 == ~t6_pc~0); 4381418#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 4381409#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4381402#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4381395#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4381389#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4344382#L635-36 assume !(1 == ~t7_pc~0); 4344378#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 4344375#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4344372#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4344369#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4344366#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4344361#L654-36 assume 1 == ~t8_pc~0; 4344356#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4344352#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4344348#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4344343#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4344339#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4344336#L673-36 assume !(1 == ~t9_pc~0); 4344331#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 4344327#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4344323#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4344318#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4344314#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4344309#L692-36 assume !(1 == ~t10_pc~0); 4344304#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 4344300#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4344296#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4344290#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 4344284#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4344226#L1142-3 assume !(1 == ~M_E~0); 4344222#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4344220#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4344218#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4344216#L1157-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4344212#L1162-3 assume !(1 == ~T5_E~0); 4344210#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4344208#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4344206#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4344204#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4344202#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4344199#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4344171#L1197-3 assume !(1 == ~E_1~0); 4344165#L1202-3 assume !(1 == ~E_2~0); 4344157#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4344151#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4344144#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4344138#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4344131#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4344124#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4344121#L1237-3 assume !(1 == ~E_9~0); 4344118#L1242-3 assume !(1 == ~E_10~0); 4344116#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4343983#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4343967#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4343959#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 4343952#L1572 assume !(0 == start_simulation_~tmp~3#1); 4343948#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4343895#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4343885#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4343881#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 4330876#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4330872#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4330868#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4330864#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 4324417#L1553-2 [2023-11-29 06:00:28,879 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:28,879 INFO L85 PathProgramCache]: Analyzing trace with hash -2043586935, now seen corresponding path program 1 times [2023-11-29 06:00:28,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:28,879 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143936414] [2023-11-29 06:00:28,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:28,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:28,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:28,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:28,926 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:28,926 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143936414] [2023-11-29 06:00:28,927 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [143936414] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:28,927 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:28,927 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:28,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1553063212] [2023-11-29 06:00:28,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:28,927 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 06:00:28,927 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:28,928 INFO L85 PathProgramCache]: Analyzing trace with hash -433404639, now seen corresponding path program 1 times [2023-11-29 06:00:28,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:28,928 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411466147] [2023-11-29 06:00:28,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:28,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:28,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:28,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:28,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:28,957 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1411466147] [2023-11-29 06:00:28,957 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1411466147] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:28,957 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:28,957 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:28,957 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2070073369] [2023-11-29 06:00:28,957 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:28,958 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 06:00:28,958 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 06:00:28,958 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 06:00:28,958 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 06:00:28,958 INFO L87 Difference]: Start difference. First operand 134633 states and 187971 transitions. cyclomatic complexity: 53370 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:29,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 06:00:29,367 INFO L93 Difference]: Finished difference Result 178618 states and 248430 transitions. [2023-11-29 06:00:29,367 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178618 states and 248430 transitions. [2023-11-29 06:00:30,366 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 177600 [2023-11-29 06:00:30,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178618 states to 178618 states and 248430 transitions. [2023-11-29 06:00:30,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178618 [2023-11-29 06:00:30,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178618 [2023-11-29 06:00:30,686 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178618 states and 248430 transitions. [2023-11-29 06:00:30,744 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 06:00:30,744 INFO L218 hiAutomatonCegarLoop]: Abstraction has 178618 states and 248430 transitions. [2023-11-29 06:00:30,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178618 states and 248430 transitions. [2023-11-29 06:00:31,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178618 to 121736. [2023-11-29 06:00:32,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121736 states, 121736 states have (on average 1.3936879805480713) internal successors, (169662), 121735 states have internal predecessors, (169662), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:32,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121736 states to 121736 states and 169662 transitions. [2023-11-29 06:00:32,241 INFO L240 hiAutomatonCegarLoop]: Abstraction has 121736 states and 169662 transitions. [2023-11-29 06:00:32,241 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 06:00:32,242 INFO L428 stractBuchiCegarLoop]: Abstraction has 121736 states and 169662 transitions. [2023-11-29 06:00:32,242 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-29 06:00:32,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121736 states and 169662 transitions. [2023-11-29 06:00:32,526 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 121024 [2023-11-29 06:00:32,526 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 06:00:32,526 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 06:00:32,528 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:32,528 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:32,528 INFO L748 eck$LassoCheckResult]: Stem: 4637050#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 4637051#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4638084#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4638085#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4637688#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 4637335#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4637336#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4637646#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4637851#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4637522#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4637523#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4637392#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4637393#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4637794#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4637747#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4637656#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4637657#L1024 assume !(0 == ~M_E~0); 4637972#L1024-2 assume !(0 == ~T1_E~0); 4637046#L1029-1 assume !(0 == ~T2_E~0); 4637047#L1034-1 assume !(0 == ~T3_E~0); 4637149#L1039-1 assume !(0 == ~T4_E~0); 4638117#L1044-1 assume !(0 == ~T5_E~0); 4637413#L1049-1 assume !(0 == ~T6_E~0); 4637414#L1054-1 assume !(0 == ~T7_E~0); 4637687#L1059-1 assume !(0 == ~T8_E~0); 4637098#L1064-1 assume !(0 == ~T9_E~0); 4637099#L1069-1 assume !(0 == ~T10_E~0); 4637937#L1074-1 assume !(0 == ~E_M~0); 4638009#L1079-1 assume !(0 == ~E_1~0); 4637974#L1084-1 assume !(0 == ~E_2~0); 4637975#L1089-1 assume !(0 == ~E_3~0); 4638032#L1094-1 assume !(0 == ~E_4~0); 4637511#L1099-1 assume !(0 == ~E_5~0); 4637512#L1104-1 assume !(0 == ~E_6~0); 4637817#L1109-1 assume !(0 == ~E_7~0); 4637272#L1114-1 assume !(0 == ~E_8~0); 4637273#L1119-1 assume !(0 == ~E_9~0); 4637346#L1124-1 assume !(0 == ~E_10~0); 4636751#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4636752#L502 assume !(1 == ~m_pc~0); 4636942#L502-2 is_master_triggered_~__retres1~0#1 := 0; 4636874#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4636875#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4637741#L1273 assume !(0 != activate_threads_~tmp~1#1); 4637742#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4638176#L521 assume !(1 == ~t1_pc~0); 4638071#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4636800#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4636766#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4636767#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 4636786#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4636787#L540 assume !(1 == ~t2_pc~0); 4637632#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4637633#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4637268#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4637269#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 4638064#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4637077#L559 assume !(1 == ~t3_pc~0); 4637078#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4637367#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4636704#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4636705#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 4636892#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4636893#L578 assume !(1 == ~t4_pc~0); 4637012#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4637943#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4636833#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4636834#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 4637721#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4637722#L597 assume !(1 == ~t5_pc~0); 4637671#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4636821#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4636822#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4637970#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 4637658#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4637659#L616 assume !(1 == ~t6_pc~0); 4637682#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4637681#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4637244#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4637245#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 4637499#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4637500#L635 assume !(1 == ~t7_pc~0); 4636788#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4636789#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4637166#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4638027#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 4637652#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4637653#L654 assume !(1 == ~t8_pc~0); 4637442#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4637443#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4637881#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4637882#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 4637933#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4637045#L673 assume !(1 == ~t9_pc~0); 4636741#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4636742#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4637329#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4637330#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 4637830#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4637831#L692 assume !(1 == ~t10_pc~0); 4637767#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4637816#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4637502#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4637503#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 4637516#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4637905#L1142 assume !(1 == ~M_E~0); 4636952#L1142-2 assume !(1 == ~T1_E~0); 4636953#L1147-1 assume !(1 == ~T2_E~0); 4637889#L1152-1 assume !(1 == ~T3_E~0); 4637374#L1157-1 assume !(1 == ~T4_E~0); 4637375#L1162-1 assume !(1 == ~T5_E~0); 4637541#L1167-1 assume !(1 == ~T6_E~0); 4637542#L1172-1 assume !(1 == ~T7_E~0); 4638050#L1177-1 assume !(1 == ~T8_E~0); 4637706#L1182-1 assume !(1 == ~T9_E~0); 4637707#L1187-1 assume !(1 == ~T10_E~0); 4637823#L1192-1 assume !(1 == ~E_M~0); 4637216#L1197-1 assume !(1 == ~E_1~0); 4637217#L1202-1 assume !(1 == ~E_2~0); 4637636#L1207-1 assume !(1 == ~E_3~0); 4637609#L1212-1 assume !(1 == ~E_4~0); 4636805#L1217-1 assume !(1 == ~E_5~0); 4636806#L1222-1 assume !(1 == ~E_6~0); 4637606#L1227-1 assume !(1 == ~E_7~0); 4637607#L1232-1 assume !(1 == ~E_8~0); 4636683#L1237-1 assume !(1 == ~E_9~0); 4636684#L1242-1 assume !(1 == ~E_10~0); 4637685#L1247-1 assume { :end_inline_reset_delta_events } true; 4637686#L1553-2 [2023-11-29 06:00:32,528 INFO L750 eck$LassoCheckResult]: Loop: 4637686#L1553-2 assume !false; 4701860#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4701854#L999-1 assume !false; 4701852#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4701850#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4701838#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4701836#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4701833#L854 assume !(0 != eval_~tmp~0#1); 4701834#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4752070#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4752068#L1024-3 assume !(0 == ~M_E~0); 4752066#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4752064#L1029-3 assume !(0 == ~T2_E~0); 4752062#L1034-3 assume !(0 == ~T3_E~0); 4752060#L1039-3 assume !(0 == ~T4_E~0); 4752058#L1044-3 assume !(0 == ~T5_E~0); 4752054#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4752052#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4752050#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4752048#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4752045#L1069-3 assume !(0 == ~T10_E~0); 4752043#L1074-3 assume !(0 == ~E_M~0); 4752041#L1079-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4752039#L1084-3 assume !(0 == ~E_2~0); 4752037#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4752035#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4752033#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4752031#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4752029#L1109-3 assume !(0 == ~E_7~0); 4752026#L1114-3 assume !(0 == ~E_8~0); 4752024#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4752022#L1124-3 assume !(0 == ~E_10~0); 4752020#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4752018#L502-36 assume !(1 == ~m_pc~0); 4748228#L502-38 is_master_triggered_~__retres1~0#1 := 0; 4748227#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4748226#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4748225#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4748224#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4748223#L521-36 assume 1 == ~t1_pc~0; 4748221#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4748220#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4748219#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4748218#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4748217#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4748216#L540-36 assume !(1 == ~t2_pc~0); 4748215#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 4748214#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4748213#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4748211#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4748210#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4748209#L559-36 assume !(1 == ~t3_pc~0); 4748208#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 4748207#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4748206#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4748205#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 4748204#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4748203#L578-36 assume !(1 == ~t4_pc~0); 4748201#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 4748199#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4748197#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4748196#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 4748194#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4748192#L597-36 assume !(1 == ~t5_pc~0); 4748190#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 4748188#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4748186#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4748184#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4748182#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4748180#L616-36 assume 1 == ~t6_pc~0; 4748177#L617-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4748175#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4748173#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4748171#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4748169#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4748167#L635-36 assume !(1 == ~t7_pc~0); 4720653#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 4748164#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4748162#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4748160#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4748158#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4748156#L654-36 assume 1 == ~t8_pc~0; 4748153#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4748151#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4748149#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4748147#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4748145#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4748143#L673-36 assume !(1 == ~t9_pc~0); 4748140#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 4748138#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4748136#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4748134#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4748132#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4748130#L692-36 assume !(1 == ~t10_pc~0); 4748126#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 4748124#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4748122#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4748120#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 4748118#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4748115#L1142-3 assume !(1 == ~M_E~0); 4653237#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4748112#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4748110#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4748108#L1157-3 assume !(1 == ~T4_E~0); 4748106#L1162-3 assume !(1 == ~T5_E~0); 4748104#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4748102#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4748100#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4748098#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4748096#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4748094#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4748090#L1197-3 assume !(1 == ~E_1~0); 4748088#L1202-3 assume !(1 == ~E_2~0); 4748086#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4748084#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4748081#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4748079#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4748077#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4748075#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4748073#L1237-3 assume !(1 == ~E_9~0); 4748071#L1242-3 assume !(1 == ~E_10~0); 4748069#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4748067#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4747824#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4691067#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 4664455#L1572 assume !(0 == start_simulation_~tmp~3#1); 4664456#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4701881#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4701873#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4701871#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 4701869#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4701867#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4701865#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4701863#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 4637686#L1553-2 [2023-11-29 06:00:32,529 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:32,529 INFO L85 PathProgramCache]: Analyzing trace with hash -1410728759, now seen corresponding path program 2 times [2023-11-29 06:00:32,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:32,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821465273] [2023-11-29 06:00:32,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:32,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:32,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 06:00:32,540 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 06:00:32,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 06:00:32,588 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 06:00:32,588 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:32,589 INFO L85 PathProgramCache]: Analyzing trace with hash -660471837, now seen corresponding path program 1 times [2023-11-29 06:00:32,589 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:32,589 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1630970306] [2023-11-29 06:00:32,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:32,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:32,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:32,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:32,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:32,627 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1630970306] [2023-11-29 06:00:32,627 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1630970306] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:32,627 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:32,628 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:32,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79120851] [2023-11-29 06:00:32,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:32,628 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 06:00:32,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 06:00:32,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 06:00:32,629 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 06:00:32,629 INFO L87 Difference]: Start difference. First operand 121736 states and 169662 transitions. cyclomatic complexity: 47958 Second operand has 3 states, 3 states have (on average 44.666666666666664) internal successors, (134), 3 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:33,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 06:00:33,177 INFO L93 Difference]: Finished difference Result 230697 states and 318178 transitions. [2023-11-29 06:00:33,177 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230697 states and 318178 transitions. [2023-11-29 06:00:34,484 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 229312 [2023-11-29 06:00:34,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230697 states to 230697 states and 318178 transitions. [2023-11-29 06:00:34,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 230697 [2023-11-29 06:00:35,057 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 230697 [2023-11-29 06:00:35,057 INFO L73 IsDeterministic]: Start isDeterministic. Operand 230697 states and 318178 transitions. [2023-11-29 06:00:35,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 06:00:35,146 INFO L218 hiAutomatonCegarLoop]: Abstraction has 230697 states and 318178 transitions. [2023-11-29 06:00:35,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230697 states and 318178 transitions. [2023-11-29 06:00:37,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230697 to 230121. [2023-11-29 06:00:37,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 230121 states, 230121 states have (on average 1.3793178371378536) internal successors, (317410), 230120 states have internal predecessors, (317410), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:37,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230121 states to 230121 states and 317410 transitions. [2023-11-29 06:00:37,687 INFO L240 hiAutomatonCegarLoop]: Abstraction has 230121 states and 317410 transitions. [2023-11-29 06:00:37,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 06:00:37,688 INFO L428 stractBuchiCegarLoop]: Abstraction has 230121 states and 317410 transitions. [2023-11-29 06:00:37,688 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-29 06:00:37,688 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 230121 states and 317410 transitions. [2023-11-29 06:00:38,260 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 228864 [2023-11-29 06:00:38,260 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 06:00:38,260 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 06:00:38,262 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:38,262 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 06:00:38,262 INFO L748 eck$LassoCheckResult]: Stem: 4989495#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 4989496#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4990583#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret29#1, start_simulation_#t~ret30#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4990584#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4990146#L719 assume 1 == ~m_i~0;~m_st~0 := 0; 4989787#L719-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4989788#L724-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4990109#L729-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4990322#L734-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4989977#L739-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4989978#L744-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4989843#L749-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4989844#L754-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4990262#L759-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4990215#L764-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4990119#L769-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4990120#L1024 assume !(0 == ~M_E~0); 4990466#L1024-2 assume !(0 == ~T1_E~0); 4989491#L1029-1 assume !(0 == ~T2_E~0); 4989492#L1034-1 assume !(0 == ~T3_E~0); 4989598#L1039-1 assume !(0 == ~T4_E~0); 4990614#L1044-1 assume !(0 == ~T5_E~0); 4989865#L1049-1 assume !(0 == ~T6_E~0); 4989866#L1054-1 assume !(0 == ~T7_E~0); 4990145#L1059-1 assume !(0 == ~T8_E~0); 4989544#L1064-1 assume !(0 == ~T9_E~0); 4989545#L1069-1 assume !(0 == ~T10_E~0); 4990420#L1074-1 assume !(0 == ~E_M~0); 4990508#L1079-1 assume 0 == ~E_1~0;~E_1~0 := 1; 4990509#L1084-1 assume !(0 == ~E_2~0); 4990634#L1089-1 assume !(0 == ~E_3~0); 4990533#L1094-1 assume !(0 == ~E_4~0); 4989967#L1099-1 assume !(0 == ~E_5~0); 4989968#L1104-1 assume !(0 == ~E_6~0); 4990285#L1109-1 assume !(0 == ~E_7~0); 4990286#L1114-1 assume !(0 == ~E_8~0); 4990793#L1119-1 assume !(0 == ~E_9~0); 4989797#L1124-1 assume !(0 == ~E_10~0); 4989798#L1129-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4990893#L502 assume !(1 == ~m_pc~0); 4989382#L502-2 is_master_triggered_~__retres1~0#1 := 0; 4989383#L513 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4990891#is_master_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4990209#L1273 assume !(0 != activate_threads_~tmp~1#1); 4990210#L1273-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4990689#L521 assume !(1 == ~t1_pc~0); 4990690#L521-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4990571#L532 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4990898#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4990229#L1281 assume !(0 != activate_threads_~tmp___0~0#1); 4989226#L1281-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4989227#L540 assume !(1 == ~t2_pc~0); 4990482#L540-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4990894#L551 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4989717#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4989718#L1289 assume !(0 != activate_threads_~tmp___1~0#1); 4990892#L1289-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4990890#L559 assume !(1 == ~t3_pc~0); 4990889#L559-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4990888#L570 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4990887#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4990244#L1297 assume !(0 != activate_threads_~tmp___2~0#1); 4989331#L1297-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4989332#L578 assume !(1 == ~t4_pc~0); 4989454#L578-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4990884#L589 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4990863#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4990864#L1305 assume !(0 != activate_threads_~tmp___3~0#1); 4990183#L1305-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4990184#L597 assume !(1 == ~t5_pc~0); 4990129#L597-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4990130#L608 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4990883#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4990882#L1313 assume !(0 != activate_threads_~tmp___4~0#1); 4990121#L1313-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4990122#L616 assume !(1 == ~t6_pc~0); 4990140#L616-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4990139#L627 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4990881#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4990880#L1321 assume !(0 != activate_threads_~tmp___5~0#1); 4990879#L1321-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4990878#L635 assume !(1 == ~t7_pc~0); 4990877#L635-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4990876#L646 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4990788#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4990528#L1329 assume !(0 != activate_threads_~tmp___6~0#1); 4990529#L1329-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4990874#L654 assume !(1 == ~t8_pc~0); 4990872#L654-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4990871#L665 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4990870#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4990869#L1337 assume !(0 != activate_threads_~tmp___7~0#1); 4990868#L1337-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4990867#L673 assume !(1 == ~t9_pc~0); 4989180#L673-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4989181#L684 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4990861#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4990860#L1345 assume !(0 != activate_threads_~tmp___8~0#1); 4990859#L1345-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4990857#L692 assume !(1 == ~t10_pc~0); 4990856#L692-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4990855#L703 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4990854#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4990853#L1353 assume !(0 != activate_threads_~tmp___9~0#1); 4990852#L1353-2 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4990851#L1142 assume !(1 == ~M_E~0); 4989393#L1142-2 assume !(1 == ~T1_E~0); 4989394#L1147-1 assume !(1 == ~T2_E~0); 4990361#L1152-1 assume !(1 == ~T3_E~0); 4989827#L1157-1 assume !(1 == ~T4_E~0); 4989828#L1162-1 assume !(1 == ~T5_E~0); 4989995#L1167-1 assume !(1 == ~T6_E~0); 4989996#L1172-1 assume !(1 == ~T7_E~0); 4990551#L1177-1 assume !(1 == ~T8_E~0); 4990163#L1182-1 assume !(1 == ~T9_E~0); 4990164#L1187-1 assume !(1 == ~T10_E~0); 4990292#L1192-1 assume !(1 == ~E_M~0); 4989668#L1197-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4989669#L1202-1 assume !(1 == ~E_2~0); 4990097#L1207-1 assume !(1 == ~E_3~0); 4990069#L1212-1 assume !(1 == ~E_4~0); 4989245#L1217-1 assume !(1 == ~E_5~0); 4989246#L1222-1 assume !(1 == ~E_6~0); 4990064#L1227-1 assume !(1 == ~E_7~0); 4990065#L1232-1 assume !(1 == ~E_8~0); 4989122#L1237-1 assume !(1 == ~E_9~0); 4989123#L1242-1 assume !(1 == ~E_10~0); 4990143#L1247-1 assume { :end_inline_reset_delta_events } true; 4990144#L1553-2 [2023-11-29 06:00:38,263 INFO L750 eck$LassoCheckResult]: Loop: 4990144#L1553-2 assume !false; 5018056#L1554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5018051#L999-1 assume !false; 5018049#L850 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5018047#L782 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5018034#L839 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5018032#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5018029#L854 assume !(0 != eval_~tmp~0#1); 5018027#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5018025#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5018023#L1024-3 assume !(0 == ~M_E~0); 5018021#L1024-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5018019#L1029-3 assume !(0 == ~T2_E~0); 5018017#L1034-3 assume !(0 == ~T3_E~0); 5018014#L1039-3 assume !(0 == ~T4_E~0); 5018012#L1044-3 assume !(0 == ~T5_E~0); 5018010#L1049-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5018008#L1054-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5018006#L1059-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5018004#L1064-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5018001#L1069-3 assume !(0 == ~T10_E~0); 5018000#L1074-3 assume !(0 == ~E_M~0); 5017996#L1079-3 assume !(0 == ~E_1~0); 5017997#L1084-3 assume !(0 == ~E_2~0); 5018360#L1089-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5018358#L1094-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5018356#L1099-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5018354#L1104-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5018352#L1109-3 assume !(0 == ~E_7~0); 5018350#L1114-3 assume !(0 == ~E_8~0); 5018348#L1119-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5018346#L1124-3 assume !(0 == ~E_10~0); 5018344#L1129-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5018342#L502-36 assume !(1 == ~m_pc~0); 5018340#L502-38 is_master_triggered_~__retres1~0#1 := 0; 5018338#L513-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5018336#is_master_triggered_returnLabel#13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5018333#L1273-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5018331#L1273-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5018329#L521-36 assume 1 == ~t1_pc~0; 5018328#L522-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5017956#L532-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5017954#is_transmit1_triggered_returnLabel#13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5017952#L1281-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5017950#L1281-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5017948#L540-36 assume !(1 == ~t2_pc~0); 5017946#L540-38 is_transmit2_triggered_~__retres1~2#1 := 0; 5017942#L551-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5017940#is_transmit2_triggered_returnLabel#13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5017938#L1289-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5017936#L1289-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5017933#L559-36 assume !(1 == ~t3_pc~0); 5017931#L559-38 is_transmit3_triggered_~__retres1~3#1 := 0; 5017929#L570-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5017927#is_transmit3_triggered_returnLabel#13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5017925#L1297-36 assume !(0 != activate_threads_~tmp___2~0#1); 5017923#L1297-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5017921#L578-36 assume !(1 == ~t4_pc~0); 5017917#L578-38 is_transmit4_triggered_~__retres1~4#1 := 0; 5017915#L589-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5017912#is_transmit4_triggered_returnLabel#13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5017910#L1305-36 assume !(0 != activate_threads_~tmp___3~0#1); 5017907#L1305-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5017905#L597-36 assume !(1 == ~t5_pc~0); 5017903#L597-38 is_transmit5_triggered_~__retres1~5#1 := 0; 5017901#L608-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5017900#is_transmit5_triggered_returnLabel#13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5017898#L1313-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5017896#L1313-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5017894#L616-36 assume !(1 == ~t6_pc~0); 5017892#L616-38 is_transmit6_triggered_~__retres1~6#1 := 0; 5017889#L627-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5017886#is_transmit6_triggered_returnLabel#13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5017884#L1321-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5017882#L1321-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5017880#L635-36 assume !(1 == ~t7_pc~0); 5014481#L635-38 is_transmit7_triggered_~__retres1~7#1 := 0; 5017877#L646-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5017875#is_transmit7_triggered_returnLabel#13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5017873#L1329-36 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5017871#L1329-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5017869#L654-36 assume 1 == ~t8_pc~0; 5017866#L655-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5017863#L665-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5017861#is_transmit8_triggered_returnLabel#13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5017859#L1337-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5017857#L1337-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5017855#L673-36 assume !(1 == ~t9_pc~0); 5017853#L673-38 is_transmit9_triggered_~__retres1~9#1 := 0; 5017852#L684-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5017851#is_transmit9_triggered_returnLabel#13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5017850#L1345-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5017848#L1345-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5017846#L692-36 assume !(1 == ~t10_pc~0); 5017843#L692-38 is_transmit10_triggered_~__retres1~10#1 := 0; 5017841#L703-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5017839#is_transmit10_triggered_returnLabel#13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5017837#L1353-36 assume !(0 != activate_threads_~tmp___9~0#1); 5017835#L1353-38 havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5017833#L1142-3 assume !(1 == ~M_E~0); 5017829#L1142-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5017827#L1147-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5017825#L1152-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5017823#L1157-3 assume !(1 == ~T4_E~0); 5017821#L1162-3 assume !(1 == ~T5_E~0); 5017819#L1167-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5017817#L1172-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5017816#L1177-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5017812#L1182-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5017810#L1187-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5017808#L1192-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5017806#L1197-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5017802#L1202-3 assume !(1 == ~E_2~0); 5017800#L1207-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5017798#L1212-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5017796#L1217-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5017794#L1222-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5017792#L1227-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5017790#L1232-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5017788#L1237-3 assume !(1 == ~E_9~0); 5017786#L1242-3 assume !(1 == ~E_10~0); 5017783#L1247-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5017781#L782-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5017769#L839-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5017767#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5017764#L1572 assume !(0 == start_simulation_~tmp~3#1); 5017765#L1572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5025726#L782-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5025718#L839-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5025716#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret28#1;havoc stop_simulation_#t~ret28#1; 5025714#L1527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5025712#L1534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5025710#stop_simulation_returnLabel#1 start_simulation_#t~ret30#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret28#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 5025708#L1585 assume !(0 != start_simulation_~tmp___0~1#1); 4990144#L1553-2 [2023-11-29 06:00:38,263 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:38,263 INFO L85 PathProgramCache]: Analyzing trace with hash 285677193, now seen corresponding path program 1 times [2023-11-29 06:00:38,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:38,263 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [237251120] [2023-11-29 06:00:38,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:38,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:38,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:38,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:38,319 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:38,320 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [237251120] [2023-11-29 06:00:38,320 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [237251120] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:38,320 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:38,320 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:38,320 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [38921235] [2023-11-29 06:00:38,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:38,320 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 06:00:38,321 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 06:00:38,321 INFO L85 PathProgramCache]: Analyzing trace with hash 1993965664, now seen corresponding path program 1 times [2023-11-29 06:00:38,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 06:00:38,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1451596308] [2023-11-29 06:00:38,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 06:00:38,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 06:00:38,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 06:00:38,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 06:00:38,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 06:00:38,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1451596308] [2023-11-29 06:00:38,352 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1451596308] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 06:00:38,352 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 06:00:38,352 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 06:00:38,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [984961930] [2023-11-29 06:00:38,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 06:00:38,353 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 06:00:38,353 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 06:00:38,353 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 06:00:38,354 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 06:00:38,354 INFO L87 Difference]: Start difference. First operand 230121 states and 317410 transitions. cyclomatic complexity: 87321 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 06:00:39,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 06:00:39,453 INFO L93 Difference]: Finished difference Result 282560 states and 388775 transitions. [2023-11-29 06:00:39,453 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 282560 states and 388775 transitions. [2023-11-29 06:00:40,408 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 277296 [2023-11-29 06:00:41,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 282560 states to 282560 states and 388775 transitions. [2023-11-29 06:00:41,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 282560 [2023-11-29 06:00:41,452 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 282560 [2023-11-29 06:00:41,452 INFO L73 IsDeterministic]: Start isDeterministic. Operand 282560 states and 388775 transitions. [2023-11-29 06:00:41,542 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 06:00:41,542 INFO L218 hiAutomatonCegarLoop]: Abstraction has 282560 states and 388775 transitions. [2023-11-29 06:00:41,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282560 states and 388775 transitions. [2023-11-29 06:00:43,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282560 to 230102. [2023-11-29 06:00:43,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 230102 states, 230102 states have (on average 1.3787537700671877) internal successors, (317254), 230101 states have internal predecessors, (317254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)